TW201411999A - Power converter and operating method thereof - Google Patents

Abstract

A power converter including a zero-current detection unit, a ramp generation unit, an amplifying unit, and a comparing unit is disclosed. The zero-current detecting unit provides a zero-current detection signal. The ramp generation unit receives the zero-current detection signal and a first switch signal and generates a ramp signal according to the zero-current detection signal. The ramp signal has a first default voltage and a second default voltage, and the first default voltage is higher than the second default voltage. The amplifying unit provides an error amplifying signal according to an output voltage of the power converter. The comparing unit compares the ramp signal with the error amplifying signal to generate a PWM control signal. When the ramp signal reaches the second default voltage, if the zero-current detection signal is high, the ramp generation unit will stop generating the ramp signal until the first switch signal is high.

Description

Power converter and its operating method

The present invention relates to a DC-DC converter, and more particularly to a power converter having a faster transient response speed when entering a heavy load state from a light load state and a method of operating the same.

In recent years, power supply circuits have been widely used in various electronic products, such as portable electronic products and computer products. The power supply circuit can provide voltage or current conversion or provide power with a fixed voltage or current for use in electronic products. In the power supply circuit, a power integrated circuit (Power IC) is one of the necessary active components.

Generally speaking, in the current operation configuration of the fixed-frequency DC-to-DC converter, when the DC-to-DC converter enters the light load state from the heavy load state, the operation mode of the system will enter the discontinuous mode from the continuous conduction mode. The conduction mode, and its conduction period will be gradually shortened from the heavy load state to the light load state. At this time, as shown in FIG. 1, the error amplification signal Comp output by the error amplifier is likely to be lower than the bottom of the ramp signal Ramp generated by the ramp generator, and cannot intersect with the ramp signal Ramp. That is, even when the ramp signal Ramp has dropped from its top T2 to its bottom B2, the relatively low error amplification signal Comp is still below the bottom B2 and cannot intersect the ramp signal Ramp.

Since the conventional ramp generator still generates the ramp signal Ramp continuously, when the error amplification signal Comp intersects the bottom B3 of the ramp signal Ramp again, the ramp signal Ramp will rise from the bottom B3 to a higher position. The ramp signal Ramp is far away from the error amplification signal Comp, thus causing the conduction period to be slower. Out, it is impossible to provide sufficient energy for the system and needs to be improved.

Similarly, in the transient response, if the system enters the heavy load state from the light load state at this time, the traditional ramp generator will continue to generate the ramp signal Ramp, so that the error amplification signal Comp has to be ramped again. When the signal Ramp intersects, the ramp signal Ramp has risen from the bottom to the higher position, and the ramp signal Ramp is far away from the error amplification signal Comp, thus causing the bridge switch to be turned on slowly at the output stage, so the transient state The response is slow and needs to be improved.

Accordingly, the present invention provides a power converter and method of operating the same to address the above-discussed problems encountered in the prior art.

One aspect of the invention is to propose a power converter. In a preferred embodiment, the power converter includes a zero current detecting unit, a ramp generating unit, an amplifying unit, and a comparing unit. The zero current detection unit provides a zero current detection signal. The ramp generating unit receives the zero current detecting signal and the first switching signal, and generates a ramp signal according to the zero current detecting signal. The ramp signal has a first preset voltage value and a second preset voltage value, and the first preset voltage value is higher than the second preset voltage value. The amplifying unit provides an error amplification signal according to an output voltage of one of the power converters. The comparing unit compares the ramp signal with the error amplifying signal to generate a pulse width modulation control signal. When the ramp signal reaches the second preset voltage value, if the zero current detection signal is at the high level, the ramp wave generating unit stops generating the ramp signal until the first switch signal is at the high level.

In one embodiment, the power converter is a fixed frequency DC-DC power converter.

In an embodiment, when the power converter enters the discontinuous conduction mode from the continuous conduction mode, if the ramp signal is higher than the error amplification signal, the ramp generating unit stops production. Raw ramp signal.

In an embodiment, when the power converter enters the heavy load state from the light load state, if the ramp signal is higher than the error amplification signal, the ramp generating unit stops generating the ramp signal.

In an embodiment, the ramp wave generating unit includes a reset unit and a ramp generating circuit. The reset unit is configured to receive the zero current detection signal and the first switching signal, and output a control signal. The ramp generating circuit is coupled to the reset unit for stopping or continuing to generate the ramp signal according to the control signal.

In an embodiment, when the ramp signal generated by the ramp generating circuit reaches the second preset voltage value, the reset unit determines whether the zero current detecting signal received by the signal is at a high level, and if so, resets the unit. The output control signal controls the ramp generating unit to stop generating the ramp signal.

In an embodiment, when the ramp generating unit stops generating the ramp signal, the reset unit determines whether the first switching signal received by the ramping unit is at a high level, and if so, the reset unit outputs a control signal to control the ramp generating unit to continue. Generate a ramp signal.

Another aspect of the present invention is to provide a method of operating a power converter. In one embodiment, the power converter operating method is for operating a power converter. The method comprises the steps of: (a) providing an error amplification signal according to an output voltage of one of the power converters; (b) receiving a zero current detection signal and a first switching signal; (c) generating a zero current detection signal a ramp signal, wherein the ramp signal has a first preset voltage value and a second preset voltage value, and the first preset voltage value is higher than the second preset voltage value, when the ramp signal reaches the second preset voltage When the value is zero, if the zero current detection signal is at the high level, the ramp signal is stopped until the first switching signal is at the high level; (d) the ramp signal and the error amplification signal are compared to generate a pulse width modulation control. Signal.

Compared with the prior art, when the power converter of the present invention enters the discontinuous conduction mode from the continuous conduction mode and enters the heavy load state from the light load state, the oblique wave signal When the number is higher than the error amplification signal so that the two cannot intersect, the power converter will control the ramp generating unit to stop generating the ramp signal, thereby improving the power converter under the light load condition by changing the waveform of the ramp signal. System efficiency, and the transient response speed of the power converter when it enters the heavy load state from light load state.

The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.

A preferred embodiment of the invention is a power converter. In fact, the power converter proposed by the present invention is applied to a fixed frequency DC-DC power converter, but is not limited thereto. The invention can also be applied to the architecture of a power conversion circuit such as an alternating current to direct current converter or a direct current to alternating current converter.

Please refer to FIG. 2. FIG. 2 is a schematic diagram showing the circuit architecture of the power converter of this embodiment. As shown in FIG. 2, the power converter 1 includes a zero current detecting unit 10, a ramp generating unit 12, an amplifying unit 14, a comparing unit 16, a first input terminal 17, a pulse width modulation unit 18, and a second input terminal. 19 and output stage 20. In this embodiment, the output stage 20 includes a first switch 201, a second switch 202, a voltage input terminal 203, a voltage output terminal 204, an output inductor L, a first resistor R1, a second resistor R2, and a first capacitor C1. The second capacitor C2. The first switch 201 and the second switch 202 are respectively an upper bridge switch and a lower bridge switch; the voltage input terminal 203 and the voltage output terminal 204 are respectively configured to receive the input voltage Vin.

The amplifying unit 14 receives the reference voltage V _REF and the output voltage V _out through the first input terminal 17 and the second input terminal 19 respectively, and the amplifying unit 14 outputs the error amplification signal Comp to the positive input terminal + of the comparing unit 16. In fact, the amplifying unit 14 can subtract and amplify the reference voltage V _REF and the output voltage V _out into an error amplification signal Comp, and output the output voltage V _out as an output voltage outputted by the output stage 20 of the power converter 1; V _REF can be a preset voltage value, but not limited to this.

In this embodiment, the zero current detecting unit 10 is configured to detect whether the output current I _L flowing through the output inductor L in the output stage 20 is zero. When the zero current detecting unit 10 detects that the output current I _L is zero, the zero current detecting unit 10 outputs the zero current detecting signal ZC to the ramp generating unit 12 and the pulse width modulation unit 18, respectively. When the first switch 201 is in the off state and the second switch 202 is in the on state, when the pulse width modulation unit 18 receives the zero current detection signal ZC, the pulse width modulation unit 18 will output the second switching signal LG to the first The second switch 202 turns off the second switch 202 that is originally in the on state, while the first switch 201 is still in the off state.

As shown in FIG. 3, the ramp generating unit 12 may include a reset unit 120 and a ramp generating circuit 122. In fact, the ramp generating circuit may include components such as an oscillator, a charging capacitor, and a comparator. The reset unit 120 receives the zero current detection signal ZC and the first switching signal UG, and outputs a control signal RST. The ramp generating circuit 122 is coupled to the reset unit 120 for stopping or continuing to generate the ramp signal Ramp according to the control signal RST. For example, when the ramp current generating unit 12 receives the zero current detecting signal ZC, the ramp generating circuit 122 of the ramp generating unit 12 generates the ramp signal Ramp according to the zero current detecting signal ZC to the comparing unit 16. Negative input -. In fact, the ramp signal Ramp has a first preset voltage value and a second preset voltage value, and the first preset voltage value is higher than the second preset voltage value.

When the comparison unit 16 receives the error amplification signal Comp and the ramp signal Ramp through its positive input terminal + negative input terminal, the comparison unit 16 compares the magnitude of the error amplification signal Comp and the ramp signal Ramp to generate a pulse. The variable control signal CTL is widely modulated to the pulse width modulation unit 18.

If the ramp wave generating circuit 122 generates the ramp signal Ramp, the charging power is passed through The charging method pulls the ramp signal Ramp to the first preset voltage value (that is, the top of the ramp signal Ramp), and then pulls down the charging capacitor to the second preset voltage value (ie, the ramp signal) Ramp bottom). When the ramp signal Ramp generated by the ramp generating circuit 122 reaches the second preset voltage value, the reset unit 120 determines whether the received zero current detecting signal ZC is at a high level. If so, the reset unit 120 outputs the control signal RST to control the ramp generating circuit 122 to stop generating the ramp signal Ramp.

For example, as shown in FIG. 4, when the power converter 1 enters the light load state from the heavy load state, the load current I _Load gradually becomes smaller with time, and the conduction period length of the first switch 201 is also gradually shortened with time. The error amplification signal Comp will also gradually decrease with time, and the output current I _L will gradually decrease with time. During the period t4~t5, when the zero current detecting unit 10 detects that the output current I _L is zero, the zero current detecting unit 10 starts to generate the zero current detecting signal ZC until the time t5, the output current I _L starts again. When the rise is not zero, the zero current detecting unit 10 stops generating the zero current detecting signal ZC.

When the first switch 201 is in the off state and the second switch 202 is in the on state, when the pulse width modulation unit 18 receives the zero current detection signal ZC, the pulse width modulation unit 18 will output the second switch of the low level. The signal LG is sent to the second switch 202 to turn off the second switch 202, while the first switch 201 is still in the off state. At time t5, the pulse width modulation unit 18 will output the high level first switching signal UG to the first switch 201 to turn on the first switch 201. The pulse width modulation unit 18 outputs the low-level first switching signal UG and the high-level second switching signal LG to the first switch 201 and the second switch 202 respectively until the end period of the first switch 201 is completed. To turn off the first switch 201 and simultaneously turn on the second switch 202. It should be noted that, at this time, the error amplification signal Comp gradually decreases with time, but since the error amplification signal Comp is still higher than the bottom of the ramp signal Ramp, the reset unit 120 does not output the control signal RST to control the ramp wave. The generating circuit 122 stops generating the ramp signal Ramp.

Until time t10, the ramp signal Ramp is reduced from the top T10 to the bottom B10. Since the error amplification signal Comp is lower than the bottom B10 of the ramp signal Ramp, the reset unit 120 starts to send the control signal RST to the ramp generating circuit 122. The ramp signal generating circuit 122 stops generating the ramp signal Ramp. Since the ramp wave generating circuit 122 stops generating the ramp signal Ramp in the first period of time ΔK1 from the time t10, the ramp signal Ramp will be maintained at the bottom during the first period of time ΔK1, so that the ramp signal is The waveform of the Ramp is changed, so that the short circuit of the ramp signal Ramp and the error amplification signal Comp is caused in the prior art, and the conduction period is slow to open, which cannot provide sufficient energy of the system.

It should be noted that, at time t10, the pulse width modulation unit 18 does not output the high level first switching signal UG to turn on the first switch 201. Until the error amplification signal Comp rises again to intersect with the ramp signal Ramp, the pulse width modulation unit 18 outputs the high level first switching signal UG to turn on the first switch 201. At this time, the reset unit 120 will judge that the first switching signal UG received by it is at a high level, so the reset unit UG output control signal RST controls the ramp generating circuit 122 to continue to generate the ramp signal 122.

At time t11, the ramp signal Ramp is lowered from the top T11 to the bottom B11. Since the error amplification signal Comp is lower than the bottom B11 of the ramp signal Ramp, the reset unit 120 starts to send the control signal RST to the ramp generating circuit 122 to The control ramp generating circuit 122 stops generating the ramp signal Ramp during the second period of time ΔK2. The difference is that the second period of time ΔK2 at which the ramp generating circuit 122 stops generating the ramp signal Ramp will be longer than the first period ΔK1. This phenomenon is mainly caused by the fact that the output current I _L is zero for a longer period of time, and the time for the zero current detecting unit 10 to generate the zero current detecting signal ZC is longer and longer.

Similarly, at time t12, the ramp signal Ramp is lowered from the top T12 to the bottom. B12, since the error amplification signal Comp is lower than the bottom B12 of the ramp signal Ramp, the reset unit 120 starts to send the control signal RST to the ramp generating circuit 122 to control the ramp generating circuit 122 for the third period of time ΔK3. Stop generating the ramp signal Ramp. At time t13, the ramp signal Ramp is lowered from the top T13 to the bottom B13. Since the error amplification signal Comp is lower than the bottom B13 of the ramp signal Ramp, the reset unit 120 starts to send the control signal RST to the ramp generating circuit 122 to The control ramp generating circuit 122 stops generating the ramp signal Ramp during the fourth period of time ΔK4.

The difference is that the third period of time ΔK3 is longer than the second period of time ΔK2, and the fourth period of time ΔK4 is longer than the third period of time ΔK3. This phenomenon is mainly because the longer the output current I _L is zero, the longer the zero current detecting unit 10 generates the zero current detecting signal ZC, so that the reset unit 120 sends the control signal RST to control the ramp generating circuit. 122 The longer the time to stop generating the ramp signal Ramp.

In addition, the present invention can also improve the transient response speed of the power converter 1 when entering the heavy load state from the light load state by changing the waveform of the ramp signal. Please refer to FIG. 5. FIG. 5 shows that when the power converter 1 of the present invention enters the heavy load state from the light load state, the error amplification signal Comp rises and intersects the bottom of the ramp signal Ramp, and immediately turns on the first switch 201. A schematic diagram of increasing the transient response speed.

As shown in FIG. 5, the load current I _Load changes from the original low level to the high level at time t4, indicating that the power converter 1 starts to enter the heavy load state from the original light load state at time t4, and the output current I _L also As the power converter 1 enters the heavy load state from the light load state, it becomes large. During the period t2~t3, when the zero current detecting unit 10 detects that the output current I _L is zero, the zero current detecting unit 10 starts to generate the zero current detecting signal ZC until the time t4, the output current I _L starts again. When the rise is not zero, the zero current detecting unit 10 stops generating the zero current detecting signal ZC.

When the first switch 201 is in the off state and the second switch 202 is in the on state, when the pulse width modulation unit 18 receives the zero current detection signal ZC, the pulse width modulation unit 18 will output the second switch of the low level. The signal LG is sent to the second switch 202 to turn off the second switch 202, while the first switch 201 is still in the off state. At time t5, the pulse width modulation unit 18 will output the high level first switching signal UG to the first switch 201 to turn on the first switch 201.

At time t3, the ramp signal Ramp is lowered from the top T3 to the bottom B3. Since the error amplification signal Comp is lower than the bottom B3 of the ramp signal Ramp, the reset unit 120 starts to send the control signal RST to the ramp generating circuit 122 to The control ramp generating circuit 122 stops generating the ramp signal Ramp so that the waveform of the ramp signal Ramp is maintained at the bottom without continuing to rise to the top immediately as in the prior art.

Then, at time t4, the power converter 1 starts to enter the heavy load state from the light load state, the load current I _{Load changes} from the original low level to the high level, and the output current I _L also becomes larger, and the error amplification is performed at this time. The signal Comp will also rise from the bottom of the ramp signal Ramp to intersect the ramp signal Ramp. Since the error amplification signal Comp has intersected the ramp signal Ramp, the reset unit 120 outputs the control signal RST to control the ramp generating circuit 122 to continue to generate the ramp signal Ramp, so that the waveform of the ramp signal Ramp starts to rise to the top.

In the transient response, when the prior art power converter enters the heavy load state from the light load state, since the conventional ramp generator still continuously generates the ramp signal Ramp, when the error amplification signal Comp wants to be again and obliquely When the wave signal Ramp intersects, the ramp signal Ramp has risen from the bottom to the higher position, so that the ramp signal Ramp is far away from the error amplification signal Comp, so that the first switch takes a long time to be turned on. Therefore, its transient response speed is slower. In contrast, the power converter 1 of the present invention starts to issue control due to the reset unit 120. The signal RST control ramp generating circuit 122 stops generating the ramp signal Ramp, so that the waveform of the ramp signal Ramp is maintained at the bottom for a period of time, and does not rise to the top immediately as in the prior art. Therefore, when the error amplification signal Comp wants to be again When intersecting with the ramp signal Ramp, the error amplification signal Comp can intersect the bottom of the ramp signal Ramp at time t4, and the pulse width modulation unit 18 can immediately output the high-level first switching signal UG to turn on the first switch 201. Therefore, the transient response speed is relatively fast, effectively improving the transient response speed of the power converter 1 from the light load state to the heavy load state.

Another embodiment of the present invention is a method of operating a power converter. In this embodiment, the power converter operating method is used to operate the power converter. Please refer to FIG. 6. FIG. 6 is a flow chart showing the operation method of the power converter. As shown in FIG. 6, in step S10, the method provides an error amplification signal according to an output voltage of one of the power converters. In step S12, the method receives a zero current detection signal and a first switching signal. In step S14, the method generates a ramp signal based on the zero current detection signal. The ramp signal has a first preset voltage value and a second preset voltage value, and the first preset voltage value is higher than the second preset voltage value. Next, the method compares the ramp signal with the error amplification signal to generate a pulse width modulation control signal.

The method performs step S16 to determine whether the ramp signal reaches the second preset voltage value. If the result of the determination in step S16 is YES, the method proceeds to step S18 to determine whether the zero current detection signal is at a high level. If the result of the determination in step S18 is YES, the method proceeds to step S20 to stop generating the ramp signal until the first switching signal is at the high level.

Compared with the prior art, when the power converter of the present invention enters the discontinuous conduction mode from the continuous conduction mode and enters the heavy load state from the light load state, the oblique wave signal is higher than the error amplification signal so that the two cannot intersect. Next, the power converter will control the ramp generating unit to stop generating the ramp signal, thereby changing the ramp signal The waveform mode enhances the system efficiency of the power converter under light load conditions and improves the transient response speed of the power converter from a light load state to a heavy load state.

The features and spirits of the present invention are more apparent from the detailed description of the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed.

S10~S20‧‧‧ Process steps

RST‧‧‧ control signal

B1~B14‧‧‧Bottom of the ramp signal

Top of the T1~T14‧‧‧ ramp signal

1‧‧‧Power Converter

10‧‧‧Zero current detection unit

12‧‧‧ ramp generation unit

14‧‧‧Amplification unit

16‧‧‧Comparative unit

17‧‧‧ first input

18‧‧‧ Pulse width modulation unit

19‧‧‧second input

20‧‧‧Output level

201‧‧‧First switch

202‧‧‧Second switch

203‧‧‧Voltage input

204‧‧‧voltage output

120‧‧‧Reset unit

122‧‧‧ ramp generation circuit

L‧‧‧Output inductor

R1‧‧‧first resistance

R2‧‧‧second resistance

C1‧‧‧first capacitor

C2‧‧‧second capacitor

V _in ‧‧‧ input voltage

V _out ‧‧‧output voltage

V _REF ‧‧‧reference voltage

ZC‧‧‧ zero current detection signal

Comp‧‧‧Error amplification signal

Ramp‧‧‧ ramp signal

UG‧‧‧First switch signal

LG‧‧‧Second switch signal

CTL‧‧‧ control signal

I _load ‧‧‧Load current

+‧‧‧正Input

-‧‧‧negative input

I _L ‧‧‧Output current

T1~t14‧‧‧Time

△K1~△K4‧‧‧The time when the ramp signal stops outputting

FIG. 1 is a schematic diagram showing that when a conventional power converter enters a heavy load state from a light load state, the ramp wave generator continuously generates a ramp signal, thereby causing the oblique wave signal to be far apart from the error amplification signal.

2 is a schematic diagram showing the circuit architecture of a power converter according to an embodiment of the present invention.

3 is a functional block diagram of the ramp generating unit of FIG. 2 including a reset unit and a ramp generating circuit.

4 shows that when the power converter of the present invention enters the light load state from the heavy load state, once the error amplification signal is lower than the bottom of the ramp signal, the ramp generator stops generating the ramp signal, so that the ramp signal and the error A schematic diagram in which the amplified signals are closer together.

FIG. 5 is a schematic diagram showing when the power converter of the present invention enters the heavy load state from the light load state, the error amplification signal rises to intersect the bottom of the ramp signal, and immediately turns on the first switch to increase the transient response speed.

6 is a flow chart showing a method of operating a power converter in accordance with another embodiment of the present invention.

1‧‧‧Power Converter

10‧‧‧Zero current detection unit

12‧‧‧ ramp generation unit

14‧‧‧Amplification unit

16‧‧‧Comparative unit

17‧‧‧ first input

18‧‧‧ Pulse width modulation unit

19‧‧‧second input

20‧‧‧Output level

201‧‧‧First switch

202‧‧‧Second switch

203‧‧‧Voltage input

204‧‧‧voltage output

L‧‧‧Output inductor

R1‧‧‧first resistance

R2‧‧‧second resistance

C1‧‧‧first capacitor

C2‧‧‧second capacitor

Vin‧‧‧Input voltage

Vout‧‧‧ output voltage

V _REF ‧‧‧reference voltage

ZC‧‧‧ zero current detection signal

Comp‧‧‧Error amplification signal

Ramp‧‧‧ ramp signal

UG‧‧‧First switch signal

LG‧‧‧Second switch signal

Claims (10)

A power converter includes a zero current detecting unit for providing a zero current detecting signal, and a ramp generating unit coupled to the zero current detecting unit for receiving the zero current detecting signal and a a first switching signal, and generating a ramp signal according to the zero current detecting signal, wherein the ramp signal has a first preset voltage value and a second preset voltage value, and the first preset voltage value is high And at the second preset voltage value, when the ramp signal reaches the second preset voltage value, if the zero current detection signal received by the ramp generating unit is at a high level, the ramp generating unit Stop generating the ramp signal until the first switching signal received by the ramp generating unit is at a high level; an amplifying unit configured to provide an error amplification signal according to an output voltage of the power converter; A comparison unit is coupled to the ramp generating unit and the amplifying unit for comparing the ramp signal with the error amplification signal to generate a pulse width modulation control signal. The power converter of claim 1, wherein the power converter is a frequency-frequency DC-DC power converter. The power converter of claim 1, wherein when the power converter enters a discontinuous conduction mode from a continuous conduction mode, if the ramp signal is higher than the error amplification signal, the ramp generation unit Stop generating the ramp signal. The power converter of claim 1, wherein when the power converter enters a heavy load state from a light load state, if the ramp signal is higher than the error Amplifying the signal, the ramp generating unit stops generating the ramp signal. The power converter of claim 1, wherein the ramp generating unit comprises: a reset unit for receiving the zero current detecting signal and the first switching signal, and outputting a control signal; The ramp generating circuit is coupled to the reset unit for stopping or continuing to generate the ramp signal according to the control signal. The power converter of claim 5, wherein when the ramp signal generated by the ramp generating circuit reaches the second preset voltage value, the reset unit determines the zero current received The detection signal is at a high level. If yes, the reset unit outputs the control signal to control the ramp generating circuit to stop generating the ramp signal. The power converter of claim 6, wherein when the ramp generating unit stops generating the ramp signal, the reset unit determines whether the first switching signal received by the resetting signal is at a high level, if The reset unit outputs the control signal to control the ramp generating circuit to continue generating the ramp signal. A power converter operating method for operating a power converter, the power converter operating method comprising the steps of: (a) providing an error amplification signal according to an output voltage of the power converter; (b) receiving a zero current Detecting a signal and a first switching signal; (c) generating a ramp signal according to the zero current detecting signal, wherein the ramp signal has a first predetermined voltage value and a second predetermined voltage value, and the The first preset voltage value is higher than the second preset voltage value, and when the ramp signal reaches the second preset voltage value, if the zero current detection signal is at a high level, stop The ramp signal is generated until the first switching signal is at a high level; and (d) the ramp signal is compared with the error amplification signal to generate a pulse width modulation control signal. The power converter operating method of claim 8, further comprising the step of: stopping the ramp signal when the power converter is switched from the continuous conduction mode to the discontinuous conduction mode, if the ramp signal is higher than the error amplification signal, stopping The ramp signal is generated. The power converter operating method according to claim 8 , further comprising the following steps: when the power converter enters a heavy load state from a light load state, if the ramp signal is higher than the error amplification signal, the generation stops. The ramp signal.