TW201407739A - Conductive line of semiconductor device - Google Patents

Abstract

A conductive line of a semiconductor device includes a conductive layer disposed on a semiconductor substrate. A thickness of the conductive layer is substantially larger than 10000 angstrom ( Å ), and at least a side of the conductive layer has at least two different values of curvature.

Description

Conductor wire

The present invention relates to a wire for a semiconductor device and a method of fabricating the same, and more particularly to a wire of a semiconductor device having at least two sides of different curvatures and a method of fabricating the same.

An integrated circuit (IC) is constructed by a device device and an interconnect structure formed by patterned features formed on a substrate or different film layers. As the degree of integration of the integrated circuit component device increases, the interconnect structure process between the component device and the component device becomes more important. The interconnect structure generally comprises alternating dielectric layers and metal layers. Generally, the fabrication process of the multi-level interconnects includes: depositing a layer of a patterned metal wire layer on the substrate a dielectric layer of the metal wiring layer, and then a plurality of contact plugs electrically connected to the metal wiring layers are formed in the dielectric layer, and then the contact plug is formed on the dielectric layer. The next layer of metal wire is connected, and finally a layer of protective layer is selectively covered to complete the fabrication of the metal interconnect.

The dielectric layer and the protective layer are mainly used to provide functions such as insulation and protection, and the materials of the dielectric layer and the protective layer must be selected in consideration of the dielectric constant, the structural strength, and the stress problem of the dielectric layer itself and other materials. Wait. Generally, the material of the dielectric layer and the protective layer mainly includes yttrium oxide and tantalum nitride, and the tantalum nitride is generally used as a protective layer of a semiconductor device device because of its dense material structure. With the needs of semiconductor manufacturing Diversification, when the thickness of the metal wire layer is too thick and/or the degree of accumulation is too high, the dielectric layer or the protective layer over the metal wire layer may have poor step coverage effect, so that the dielectric layer or protection The phenomenon of overhang occurs when the layer fills the space between the two metal wire layers, or the dielectric layer or the protective layer cracks due to stress concentration at the corners of the metal wire layer.

Therefore, how to avoid the damage of the dielectric layer or the protective layer caused by the excessively thick metal wire layer to improve the electrical performance of the semiconductor device is a problem that the related art desires to improve.

It is an object of the present invention to provide a wire for a semiconductor device and a method of fabricating the same that avoids the damage of the dielectric layer disposed over the wire layer by the contour of the wire layer.

A preferred embodiment of the present invention provides a wire for a semiconductor device including a conductive layer and a semiconductor substrate. The conductive layer is disposed on the semiconductor substrate, wherein the conductive layer has a thickness system substantially greater than 10,000 angstroms (Åstrom), and at least one side of the conductive layer includes at least two different curvatures.

Another preferred embodiment of the present invention provides a method of fabricating a wire for a semiconductor device comprising the following steps. First, a layer of conductive material and a mask layer are sequentially formed on a semiconductor substrate, and the thickness of the layer of conductive material is substantially greater than 10,000 angstroms. Then, a first etching process is performed to remove a portion of the conductive material layer to form at least one upper side, and then a second etching process is performed to remove a portion of the conductive material layer to form The side edges are less, wherein one of the curvatures of the upper side is substantially different from the curvature of one of the lower sides.

The present invention adjusts the profile of at least one side of the conductive layer by performing a multi-stage etching process such that at least one side of the formed wire has at least two different curvatures, including a concave arc-shaped upper side and a line The lower side, according to which the wire can have a concave arc profile provided by the upper side instead of the common vertical profile, avoiding excessive stress concentration on the corner of the wire when the dielectric layer covers the wire, and the damage is The electrical layer helps to improve the insulation and protection of the dielectric layer to further improve the electrical performance of the semiconductor device.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

Please refer to Figure 1. 1 is a schematic view showing a wire of a semiconductor device in accordance with a preferred embodiment of the present invention. As shown in FIG. 1, the wire includes a patterned conductive layer 104 disposed on a semiconductor substrate 100. The semiconductor substrate 100 can comprise, for example, a substrate composed of germanium, gallium arsenide, a germanium-on-insulator (SOI) layer, an epitaxial layer, a germanium layer, or other semiconductor material. The semiconductor substrate 100 may be provided with at least one conductive portion 102 and/or other semiconductor components (not shown), wherein the conductive portion 102 may be a gate, a drain, a source, a contact plug, and a via plug. Various types of conductive elements such as via plugs and wires, or metal contacts, etc., may include materials such as doped semiconductors, metal tellurides or metals. In addition, the conductive portion 102 can be disposed on the semiconductor base according to actual needs. The bottom 100 surface or a dielectric layer (not shown) on the semiconductor substrate 100. The conductive layer 104 is composed of a conductive material and is electrically connected to the at least one conductive portion 102 and/or other semiconductor elements, wherein the conductive material may include an opaque metal such as aluminum, molybdenum, chromium, tungsten, copper or the above metal. Combination, or other suitable transparent conductive material. In the preferred embodiment, the conductive layer 104 is a metal interconnect or a connection pad for output/input, usually composed of an aluminum metal material, and the thickness H of the conductive layer 104 is substantially greater than 10,000 angstroms. Preferably, it is between 30,000 angstroms and 90,000 angstroms. In addition, a dielectric layer 106 is disposed on the conductive layer 104 to provide an insulating effect, or used as a protective layer. The dielectric layer 106 may include a dielectric material commonly used in a semiconductor process, and a low dielectric constant (dielectric constant). k) material (dielectric constant value less than 3.9), ultra low dielectric constant (ULL) material (dielectric constant value less than 2.6), or porous ultra low dielectric constant (porous ULK) The material may be, for example, ruthenium oxide or tantalum nitride. In addition, a barrier layer 108 is selectively disposed between the conductive layer 104 and the semiconductor substrate 100, and can be used to prevent metal atoms of the conductive layer 104 from diffusing to the conductive portion 102. The barrier layer 108 includes titanium, titanium nitride or other suitable A single layer structure or a multilayer structure composed of materials.

It should be noted that, in the preferred embodiment, at least one side S of the conductive layer 104 includes at least two different curvatures, that is, the side edges S of the conductive layer 104 are not only composed of the same line segment, but may be different. The sides of the inclined or different shapes are formed together. In more detail, the side S of the conductive layer 104 may include at least one upper side S1 and at least one lower side S2, and the upper side S1 is located on the lower side S2. The upper side S1 and the lower side S2 have different shapes, such that the intersection of the upper side S1 and the lower side S2 is a turning point P, wherein a curvature of the upper side S1 is preferably substantially larger than the lower side. A curvature of the edge S2. In this embodiment, the curvature of the upper side S1 is substantially close to 1, and the curvature of the lower side S2 is substantially close to 0, that is, the shape of the upper side S1 is similar to that of the quarter arc. That is, an arc-shaped side, and the shape of the lower side S2 is close to a straight line, that is, a linear side, and the projection length W _S1 of the upper side S1 in the horizontal direction D1 of the bottom surface B of the conductive layer 104 is substantially The upper side is larger than the lower side S2 in the horizontal direction D1 of the bottom surface B of the conductive layer 104 in the horizontal direction D1 (close to 0), wherein the upper side S1 preferably has a concave arc-shaped side, that is, the upper side S1 is an arcuate side having a concave direction D2 toward the semiconductor substrate 100.

In addition, a top surface width W1 of the conductive layer 104 will be substantially smaller than a bottom surface width W2 of the conductive layer 104, such that the conductive layer 104 has an approximately convex-shaped cross section, and the top surface width W1 is preferably substantially greater than or equal to conductive. The bottom surface of layer 104 has a width of one third of W2. In the present embodiment, the top surface width W1 of the conductive layer 104 is substantially about 40,000 angstroms, the bottom surface width W2 is substantially about 120,000 angstroms, and the thickness H is substantially about 60,000 angstroms, that is, the conductive layer. The ratio of the thickness H to the maximum width of 104 is substantially 0.5. Also, the portion of the conductive layer 104 that is in contact with the dielectric layer 106 has a half Y-shaped profile, that is, the upper side S1 of the conductive layer 104 provides a concave arc profile instead of the common vertical profile. The dielectric layer 106 overlying the conductive layer 104 is prevented from being cracked due to excessive stress concentration on the corners of the conductive layer 104.

The present invention also provides a method of fabricating a wire of a semiconductor device to form the above-described wire structure. Please refer to Figures 2 to 6. 2 to 6 illustrate the present invention A schematic diagram of a method of fabricating a wire for a semiconductor device in a preferred embodiment. As shown in FIG. 2, first, a semiconductor substrate 200 is provided. A plurality of conductive portions 202 and/or other semiconductor elements (not shown) may be disposed in the semiconductor substrate 200. The semiconductor substrate 200 may comprise, for example, a substrate composed of germanium, gallium arsenide, a germanium-on-insulator (SOI) layer, an epitaxial layer, a germanium layer or other semiconductor material, and the conductive portion 202 may be a gate or a drain. Various types of conductive elements or metal contacts of sources, contact plugs, via plugs, wires, and the like. The method of forming the conductive portion 202 and other semiconductor elements is well known to those skilled in the art and the general knowledge, and the actual position of the material and the arrangement of the conductive portion 202 is as shown in FIG. 1 and 102, and thus will not be further described herein.

Next, a barrier layer 203, a layer of conductive material 204, and a patterned mask layer 206 are sequentially formed on the semiconductor substrate 200. The barrier layer 203 comprises a single layer structure or a multilayer structure composed of titanium, titanium nitride or other suitable material, which may be formed by sputtering or other thin film deposition techniques. The conductive material layer 204 is composed of a conductive material, including an opaque metal such as aluminum, molybdenum, chromium, tungsten, copper or a combination of the above metals, but not limited thereto, or other suitable transparent conductive materials. The method of forming the conductive material layer 204 may include forming a thickness system substantially on the semiconductor substrate 200 by physical vapor deposition such as sputtering, evaporation, or chemical vapor deposition or other thin film deposition techniques. The conductive material layer 204 is greater than 10,000 angstroms, and the thickness of the conductive material layer 204 is preferably between 30,000 angstroms and 90,000 angstroms. In the present embodiment, the conductive material layer 204 is composed of an aluminum metal material, and the conductive material layer 204 has a thickness of substantially 60,000 angstroms. In addition, the mask layer 206 may comprise a patterned photoresist layer or have a single layer structure composed of other materials or at least two materials. The hard mask layer of the composite film structure, the method of forming the mask layer 206 is well known to those skilled in the art and will not be further described herein. In the present embodiment, the width W3 of the mask layer 206 is substantially about 120,000 angstroms.

Then, as shown in FIG. 3, using the mask layer 206 as a patterned mask, a first etching process is performed to remove a portion of the conductive material layer 204 to form at least one upper side S3, and the mask layer 206 is still exposed. A portion of the remaining conductive material layer 204'. The first etching process is an isotropic etching process. Additionally, a time mode can be employed to adjust operating conditions of the first etch process, such as processing time, to determine a portion of the thickness of the removed conductive material layer 204 without etching through the conductive material layer 204. In this embodiment, the first etching process is a wet etching process, and the etching liquid is preferably a mixed solution containing nitri acid, phosphoric acid, and acetic acid in an appropriate ratio, and partially remaining The conductive material layer 204' remains on the semiconductor substrate 200 where the mask layer 206 is not overlapped, leaving the semiconductor substrate 200 of this portion unexposed.

It should be noted that, because the first etching process is an isotropic etching process, in addition to the conductive material layer 204 not covered by the mask layer 206, the conductive material layer 204 partially covered by the mask layer 206 may also be removed. Because of the lateral etching, the top surface width W4 of the remaining conductive material layer 204' will be substantially smaller than the width W3 of the mask layer 206 after forming the first etching process, and the arcuate upper side S3 is formed. Between the semiconductor substrate 200 in which the mask layer 206 overlaps the mask layer 206. In this embodiment, after the first etching process is performed, the width W5 of the conductive layer removed under the mask layer 206 is substantially opposite to the thickness H1 of the removed conductive layer before the subsequent second etching process is performed. The width W5 of the conductive layer removed under the mask layer 206 is substantially equal to one third of the width W3 of the mask layer 206, and the thickness H1 of the removed conductive layer is equal to the original thickness of the conductive material layer 204. Two-thirds. That is, when the width W3 of the mask layer 206 is substantially about 120,000 angstroms, and the original thickness of the conductive material layer 204 is substantially 60,000 angstroms, the width W5 of the removed conductive layer is substantially equal to the remaining conductive material layer. The top surface width W4 of 204', that is, is substantially 40,000 angstroms. The thickness H1 of the removed conductive layer is also substantially 40,000 angstroms. In addition, the curvature of the formed upper side S3 will be substantially close to 1, that is, the shape of the upper side S3 is similar to the arc of a quarter of the lower left side or the lower right side of a circle, and this The center of the circle is not located in the remaining conductive material layer 204'. Therefore, the upper side S3 has a concave direction D3 toward the semiconductor substrate 200, but is not limited thereto. The upper side S3 may have other curvatures at different process generations or at different points of consideration, and the width ratio and thickness ratio described above may be changed accordingly.

Next, as shown in FIG. 4, after performing the first etching process, performing a second etching process to further remove a portion of the barrier layer 203 and a portion of the remaining conductive material layer 204' to form at least the lower side S4, and Preferably, the barrier layer 203 exposed by the mask layer 206 and the remaining conductive material layer 204 ′ exposed by the mask layer 206 are completely removed. At this time, since the second etching process is different from the second etching process and is preferred It is an anisotropic etching process, so that the curvature of one of the lower sides S4 formed will be substantially different from the curvature of the upper side S3. In addition, the second etching process may also adopt an end point mode, or stop between the semiconductor substrate 200 under the remaining conductive material layer 204' or the remaining conductive material layer 204' and the semiconductor substrate 200. An etch stop layer (not shown) is used to achieve a better etching effect. In this embodiment, the second etching process is a dry etching process, and the etchant is preferably a mixed gas containing chlorine (Cl ₂ ) and boron trichloride (BCl ₃ ) in an appropriate ratio. The second etching process can completely remove the barrier layer 203 exposed by the mask layer 206 and the remaining conductive material layer 204' exposed by the mask layer 206 in the vertical direction. Thereafter, as shown in FIG. 5, the mask layer 206 is removed and combined with a suitable cleaning process to complete the wires 208 of at least one semiconductor device, the wires 208 being connectable to the at least one conductive portion 202 and/or at least one other semiconductor device. Electrical connection, in addition, the number and relative position of the wires 208 are not limited thereto. As shown in FIG. 6, a dielectric layer 210 can be formed to cover the wires 208. Since the upper side S3 of the wires 208 provides a concave arc profile instead of the common vertical profile, the dielectric layer 210 can be prevented from covering the wires. At 208, damage to the dielectric layer 210 is caused by excessive stress concentration on the corners of the wires 208.

It should be noted that since the second etching process is an anisotropic etching process, only the remaining conductive material layer 204' not covered by the mask layer 206 is removed, and therefore, after the second etching process is performed, the remaining One of the bottom surface widths W6 of the conductive material layer 204" will be substantially equal to the width W3 of the mask layer 206, and the linear lower side S4 is formed between the semiconductor layer 200 in which the mask layer 206 overlaps the mask layer 206. The width of the remaining barrier layer 203' is also substantially equal to the width W3 of the mask layer 206. The curvature of the upper side S3 can be adjusted substantially by the process characteristics of the first etching process and the second etching process. The upper surface is larger than the curvature of the formed lower side S4. In this embodiment, after the second etching process, the bottom surface width W6 of the remaining conductive material layer 204" is substantially 120,000 angstroms, that is, the top of the wire 208. The width of the face is substantially smaller than the bottom surface of the wire 208 width. In addition, the shape of the lower side S4 is similar to the straight line, that is, the curvature of the lower side is substantially close to 0, but is not limited thereto.

In summary, the present invention adjusts the profile of at least one side of the conductive layer by performing a multi-stage etching process such that at least one side of the formed wire has at least two different curvatures, including a concave arc-shaped upper surface. The side edges and the lower side of the line, according to which the wire can have a concave arc profile provided by the upper side instead of the common vertical profile, avoiding excessive stress concentration on the side of the wire when the dielectric layer covers the wire. The corners, which damage the dielectric layer, help to improve the insulation and protection of the dielectric layer to further improve the electrical performance of the semiconductor device.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100,200‧‧‧Semiconductor substrate

102,202‧‧‧Electrical Department

104‧‧‧ Conductive layer

106,210‧‧‧ dielectric layer

108,203,203'‧‧‧ barrier layer

204,204',204"‧‧‧ Conductive material layer

206‧‧‧mask layer

208‧‧‧ wire

B‧‧‧ bottom

D1‧‧‧ horizontal direction

D2, D3‧‧‧ concave direction

H, H1‧‧‧ thickness

P‧‧‧ turning point

S‧‧‧ side

S1, S3‧‧‧ upper side

S2, S4‧‧‧ lower side

W _S1 ‧‧‧projection length

W1, W2, W3, W4, W5, W6‧‧ Width

1 is a schematic view showing a wire of a semiconductor device in accordance with a preferred embodiment of the present invention.

2 to 6 are schematic views showing a method of fabricating a wire of a semiconductor device in accordance with a preferred embodiment of the present invention.

100‧‧‧Semiconductor substrate

102‧‧‧Electrical Department

104‧‧‧ Conductive layer

106‧‧‧Dielectric layer

108‧‧‧Barrier layer

B‧‧‧ bottom

D1‧‧‧ horizontal direction

D2‧‧‧ concave direction

H‧‧‧thickness

P‧‧‧ turning point

S‧‧‧ side

S1‧‧‧ upper side

S2‧‧‧ lower side

W1, W2‧‧‧ width

W _S1 ‧‧‧projection length

Claims (20)

A wire of a semiconductor device comprising: a conductive layer disposed on a semiconductor substrate, the conductive layer having a thickness substantially greater than 10,000 angstroms (Åstrom), and at least one side of the conductive layer comprising at least two different Curvature. The wire of the semiconductor device of claim 1, wherein the side of the conductive layer comprises at least one upper side and at least one lower side, and the upper side is located on the lower side. The wire of the semiconductor device of claim 2, wherein a curvature of the upper side is substantially greater than a curvature of the lower side. The wire of the semiconductor device of claim 2, wherein a curvature of the upper side is substantially close to 1, and a curvature of the lower side is substantially close to zero. The wire of the semiconductor device of claim 2, wherein the upper side includes a concave arcuate side and the lower side includes a linear side. The wire of the semiconductor device of claim 1, wherein a width of a top surface of the conductive layer is substantially smaller than a width of a bottom surface of the conductive layer. The wire of the semiconductor device of claim 1, wherein a top surface of the conductive layer is wide The degree is substantially greater than or equal to one third of the width of a bottom surface of the conductive layer. The wire of the semiconductor device of claim 1, wherein the material of the conductive layer comprises aluminum. The lead wire of the semiconductor device of claim 1, further comprising a barrier layer disposed between the conductive layer and the semiconductor substrate. A method of fabricating a wire of a semiconductor device, comprising: sequentially forming a conductive material layer and a mask layer on a semiconductor substrate, and the conductive material layer has a thickness substantially greater than 10,000 angstroms (Åstrom); The first etching process removes a portion of the conductive material layer to form at least one upper side; and performs a second etching process to remove a portion of the conductive material layer to form at least a lower side, wherein the upper side has a curvature The system is substantially different from the curvature of one of the lower sides. The method of fabricating a wire of a semiconductor device according to claim 10, wherein the first etching process comprises an isotropic etching process, and the second etching process comprises an anisotropic etching process. The method of fabricating a wire of a semiconductor device according to claim 10, wherein the second etching process is performed after the first etching process. A method of fabricating a wire of a semiconductor device according to claim 10, wherein the curvature of the upper side is substantially greater than the curvature of the lower side. A method of fabricating a wire of a semiconductor device according to claim 10, wherein the curvature of the upper side is substantially close to 1, and the curvature of the lower side is substantially close to zero. A method of fabricating a wire for a semiconductor device according to claim 10, wherein the upper side includes a concave arcuate side and the lower side includes a linear side. The method of fabricating a wire of a semiconductor device according to claim 10, wherein after the first etching process, a top surface width of the conductive material layer is substantially smaller than a width of the mask layer. A method of fabricating a wire of a semiconductor device according to claim 10, wherein after the second etching process, a bottom surface of the conductive material layer has a width substantially equal to a width of the mask layer. A method of fabricating a wire of a semiconductor device according to claim 10, wherein the material of the layer of conductive material comprises aluminum. The method of fabricating a wire of a semiconductor device according to claim 10, further comprising forming a barrier layer between the conductive material layer and the semiconductor substrate. The method of fabricating a wire of a semiconductor device according to claim 19, further comprising performing the second etching process to remove a portion of the barrier layer.