TW201405664A - Silicon dioxide layer fabricating process - Google Patents
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本發明是有關於一種矽氧化物層的形成方法,且特別是有關於一種緻密矽氧化物層的形成方法。 The present invention relates to a method of forming a tantalum oxide layer, and more particularly to a method of forming a dense tantalum oxide layer.
在半導體領域,矽氧化層廣泛地作為絕緣結構。例如,在金屬-氧化層-半導體-場效電晶體(Metal-Oxide-Semiconductor Field-Effect Transistor,MOSFET)就使用閘極介電層阻隔閘極與基板。 In the field of semiconductors, tantalum oxide layers are widely used as insulating structures. For example, in a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a gate dielectric layer is used to block the gate and the substrate.
然而,若閘極介電層的結構鬆散,易使不必要的粒子擴散進入半導體基板,造成電晶體電性的漂移。 However, if the structure of the gate dielectric layer is loose, unnecessary particles are easily diffused into the semiconductor substrate, causing the electrical drift of the transistor.
本發明係有關於一種矽氧化物層的形成方法,所形成的矽氧化物層可阻隔或減少不必要的粒子進入到半導體基板內。 The present invention is directed to a method of forming a tantalum oxide layer that blocks or reduces unwanted particles from entering the semiconductor substrate.
根據本發明之一實施例,提出一種矽氧化物層的形成方法。矽氧化物層的形成方法包括以下步驟。提供一半導體基板;使用含有過氧化氫溶液清洗半導體基板,以形成一化學氧化層於半導體基板上;無氧加熱化學氧化層,使化學氧化層形成一緻密層;以及,於氧氣環境下,加熱半導體基板,形成一矽氧化物層於半導體基板與緻密層之間。 According to an embodiment of the present invention, a method of forming a tantalum oxide layer is proposed. The method of forming the tantalum oxide layer includes the following steps. Providing a semiconductor substrate; cleaning the semiconductor substrate with a hydrogen peroxide solution to form a chemical oxide layer on the semiconductor substrate; heating the chemical oxide layer without oxygen to form a uniform layer of the chemical oxide layer; and heating in an oxygen atmosphere The semiconductor substrate forms a tantalum oxide layer between the semiconductor substrate and the dense layer.
根據本發明之一實施例,提出一種矽氧化物層的形成 方法。矽氧化物層的形成方法包括以下步驟。提供一半導體基板;使用一臭氧水溶液清洗半導體基板,以形成一化學氧化層於半導體基板上;無氧加熱化學氧化層,使化學氧化層形成一緻密層;以及,於氧氣環境下,加熱半導體基板,形成一矽氧化物層於半導體基板與緻密層之間。 According to an embodiment of the invention, a formation of a tantalum oxide layer is proposed method. The method of forming the tantalum oxide layer includes the following steps. Providing a semiconductor substrate; cleaning the semiconductor substrate with an aqueous ozone solution to form a chemical oxide layer on the semiconductor substrate; heating the chemical oxide layer without oxygen to form a uniform dense layer of the chemical oxide layer; and heating the semiconductor substrate in an oxygen atmosphere Forming a tantalum oxide layer between the semiconductor substrate and the dense layer.
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉實施例,並配合所附圖式,作詳細說明如下: In order to provide a better understanding of the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings
請參照第1A至1D圖,其繪示依照本發明一實施例之矽氧化物層的形成過程圖。 Please refer to FIGS. 1A to 1D for illustrating a process of forming a tantalum oxide layer according to an embodiment of the present invention.
如第1A圖所示,提供半導體基板110,其中半導體基板110係一矽基板,如P型矽基板。 As shown in FIG. 1A, a semiconductor substrate 110 is provided, wherein the semiconductor substrate 110 is a germanium substrate such as a P-type germanium substrate.
如第1B圖所示,使用含有高濃度過氧化氫的SC1溶液清洗半導體基板110,以形成一化學氧化層120’於半導體基板110上。上述高濃度過氧化氫溶液例如是SC1(standard clean 1)溶液,其中SC1溶液的成份包括氨、過氧化氫及去離子水,其可去除殘留於半導體基板110上的粒子。本實施例中,SC1溶液的過氧化氫、氨及去離子水的比例分別為2~10:1:50。 As shown in Fig. 1B, the semiconductor substrate 110 is cleaned using an SC1 solution containing a high concentration of hydrogen peroxide to form a chemical oxide layer 120' on the semiconductor substrate 110. The high-concentration hydrogen peroxide solution is, for example, a SC1 (standard clean 1) solution in which the components of the SC1 solution include ammonia, hydrogen peroxide, and deionized water, which remove particles remaining on the semiconductor substrate 110. In this embodiment, the ratio of hydrogen peroxide, ammonia, and deionized water of the SC1 solution is 2 to 10:1:50, respectively.
另一實施例中,亦可使用臭氧水溶液(O3/DIW)清洗半導體基板110。臭氧水溶液的組成包含臭氧及去離子水,其中臭氧的濃度介於約60至110 ppm之間。 In another embodiment, the semiconductor substrate 110 may also be cleaned using an aqueous ozone solution (O 3 /DIW). The composition of the aqueous ozone solution comprises ozone and deionized water, wherein the concentration of ozone is between about 60 and 110 ppm.
如第1C圖所示,加熱化學氧化層120’,使化學氧化層120’(第1B圖)形成一緻密層120。本加熱步驟可於無 氧氣環境(例如氮氣)中完成、且加熱溫度例如是介於攝氏950至1050度之間,而加熱時間例如是介於約30至60秒之間。 As shown in Fig. 1C, the chemical oxide layer 120' is heated to form the chemically-etched layer 120' (Fig. 1B) into the uniform dense layer 120. This heating step can be used without This is done in an oxygen environment, such as nitrogen, and the heating temperature is, for example, between 950 and 1050 degrees Celsius, and the heating time is, for example, between about 30 and 60 seconds.
由於本加熱步驟使化學氧化層120’(第1B圖)中的懸空鍵(Dangling Bond)交連鍵結成更多的氧與矽鍵結,而形成緻密的緻密層120。就密度來說,緻密層120的密度大於化學氧化層120’的密度。就厚度來說,緻密層120的厚度小於化學氧化層120’,例如,化學氧化層120’的厚度約5埃,而其形成緻密層120後密實為2至3埃。 Since the heating step causes the dangling bond in the chemical oxide layer 120' (Fig. 1B) to be bonded to bond more oxygen and helium bonds, a dense dense layer 120 is formed. In terms of density, the density of the dense layer 120 is greater than the density of the chemical oxide layer 120'. In terms of thickness, the dense layer 120 has a thickness smaller than that of the chemical oxide layer 120'. For example, the chemical oxide layer 120' has a thickness of about 5 angstroms, and the dense layer 120 is formed to have a density of 2 to 3 angstroms.
由於本實施例使用含有高濃度過氧化氫的SC1溶液或臭氧水溶液清洗半導體基板110,故可增加緻密層120中氧原子數量,使後續形成之矽氧化物130(第1D圖)中氧與矽(二氧化矽)的比例接近理想比例(即2比1),此接近理想比例的矽氧化物130在後續氮化處理中形成對氮原子的阻力,避免氮原子擴散進入半導體基板110。關於矽氧化物130的氧矽比例關係容後說明。 Since the semiconductor substrate 110 is cleaned using the SC1 solution or the ozone aqueous solution containing a high concentration of hydrogen peroxide in the present embodiment, the number of oxygen atoms in the dense layer 120 can be increased to cause oxygen and ruthenium in the subsequently formed tantalum oxide 130 (Fig. 1D). The ratio of (cerium oxide) is close to the ideal ratio (i.e., 2 to 1), and the nearly ideal ratio of the tantalum oxide 130 forms a resistance to nitrogen atoms in the subsequent nitriding treatment, preventing the nitrogen atoms from diffusing into the semiconductor substrate 110. The relationship between the oxygen ratio of the cerium oxide 130 is described later.
如第1D圖所示,可採用例如是臨場蒸汽產生器(in-situ stream generator,ISSG)方法或其它氧化製程,加熱半導體基板110,使部分半導體基板110形成矽氧化物130,並位於半導體基板110與緻密層120之間,其中矽氧化物130的厚度介於約7至8埃之間。本ISSG步驟係於氧氣氛下完成,且加熱溫度大約是攝氏900度。 As shown in FIG. 1D, the semiconductor substrate 110 may be heated by, for example, an in-situ stream generator (ISSG) method or another oxidation process to form a portion of the semiconductor substrate 110 to form a tantalum oxide 130 and be located on the semiconductor substrate. Between 110 and dense layer 120, the thickness of tantalum oxide 130 is between about 7 and 8 angstroms. This ISSG step is done under an oxygen atmosphere and the heating temperature is approximately 900 degrees Celsius.
矽氧化物130中氧矽比例可由上述清洗步驟中採用的清洗液決定。例如,當採用含高濃度過氧化氫的SC1溶液清洗半導體基板時,矽氧化物130中氧矽比例約為0.96比 1;而當採用臭氧水溶液清洗半導體基板110時,矽氧化物130中氧矽比例約為1.43比1。當矽氧化物130中氧與矽的比例愈接近理想比例時,矽氧化物130愈緻密、其品質愈好,與半導體基板110的結合性也愈佳。 The proportion of oxonium in the cerium oxide 130 can be determined by the cleaning liquid used in the above washing step. For example, when the semiconductor substrate is cleaned with an SC1 solution containing a high concentration of hydrogen peroxide, the proportion of oxonium oxide in the lanthanum oxide 130 is about 0.96. 1; When the semiconductor substrate 110 is cleaned with an aqueous ozone solution, the proportion of oxygen oxide in the tantalum oxide 130 is about 1.43 to 1. When the ratio of oxygen to cerium in the cerium oxide 130 is closer to a desired ratio, the cerium oxide 130 becomes denser and the quality thereof is better, and the bonding with the semiconductor substrate 110 is also better.
相較於以低濃度過氧化氫的SC1溶液清洗半導體基板110所獲得的矽氧化物,由於本實施例的矽氧化物130中氧矽比例較接近理想比例,故矽氧化物130與半導體基板110的結合性佳。此外,矽氧化物130在後續氮化處理中形成對氮原子的阻力,避免氮原子的擴散。依據實驗數據,以低濃度過氧化氫的SC1溶液清洗半導體基板110所獲得的矽氧化物,氮原子對此矽氧化物的擴散深度深達35埃;相對地,氮原子對本實施例的矽氧化物130的擴散深度僅約25埃。由此可知,本實施例的矽氧化物130對氮產生有效擴散阻力,避免在氮化處理中氮擴散進入半導體基板110。 The tantalum oxide obtained by cleaning the semiconductor substrate 110 with the SC1 solution having a low concentration of hydrogen peroxide has a ratio of oxygen to germanium in the tantalum oxide 130 of the present embodiment closer to a desired ratio, so that the tantalum oxide 130 and the semiconductor substrate 110 are used. The combination is good. Further, the cerium oxide 130 forms a resistance to nitrogen atoms in the subsequent nitriding treatment, avoiding diffusion of nitrogen atoms. According to the experimental data, the cerium oxide obtained by cleaning the semiconductor substrate 110 with a low concentration of hydrogen peroxide in the SC1 solution, the diffusion depth of the nitrogen atom to the cerium oxide is as deep as 35 angstroms; in contrast, the nitrogen atom oxidizes the cerium in this embodiment. The diffusion depth of the object 130 is only about 25 angstroms. From this, it is understood that the tantalum oxide 130 of the present embodiment has an effective diffusion resistance against nitrogen, and nitrogen diffusion into the semiconductor substrate 110 during the nitriding treatment is prevented.
上述矽氧化物層的形成方法可應用於許多半導體元件上,例如是主動元件。以下係以MOSFET為例說明應用上述矽氧化物層形成方法形成主動元件的其中幾種方法。 The above-described method of forming a tantalum oxide layer can be applied to many semiconductor elements, such as active elements. Hereinafter, several methods of forming an active device using the above-described tantalum oxide layer forming method will be described using a MOSFET as an example.
請參照第2A至2B圖,其繪示依照本發明一實施例之主動元件的形成過程圖。 Please refer to FIGS. 2A-2B, which illustrate a process of forming an active device in accordance with an embodiment of the present invention.
如第2A圖所示,形成一MOSFET結構200’,其包括緻密層120、矽氧化物130、閘介電層240、閘極250、第一摻雜區域260及第二摻雜區域265於半導體基板110上,其中閘介電層240形成於半導體基板110與閘極250之間。第一摻雜區域260及第二摻雜區域265分別位於閘 介電層240之相對二側邊的半導體基板110內。其中,第一摻雜區域260及第二摻雜區域265例如是n型輕摻雜區域,且可分別作為汲極及源極。 As shown in FIG. 2A, a MOSFET structure 200' is formed, which includes a dense layer 120, a germanium oxide 130, a gate dielectric layer 240, a gate 250, a first doped region 260, and a second doped region 265 in a semiconductor. On the substrate 110, a gate dielectric layer 240 is formed between the semiconductor substrate 110 and the gate 250. The first doped region 260 and the second doped region 265 are respectively located at the gate The dielectric layer 240 is in the opposite side of the semiconductor substrate 110. The first doped region 260 and the second doped region 265 are, for example, n-type lightly doped regions, and can serve as drains and sources, respectively.
由於本實施例的矽氧化物130與半導體基板110的結合性佳,故可提高元件中通道的電子遷移率。依據實驗數據,相較於習知結構鬆散的矽氧化物,本實施例結構較緻密的矽氧化物層130使元件中通道的電子遷移率提升約14%。 Since the germanium oxide 130 of the present embodiment has good bonding property with the semiconductor substrate 110, the electron mobility of the channel in the device can be improved. According to the experimental data, the denser tantalum oxide layer 130 of this embodiment improves the electron mobility of the channels in the element by about 14% compared to the conventional structure of the tantalum oxide.
此外,由於本實施例矽氧化物130與半導體基板110的結合性佳,使元件的開啟電流提升。依據實驗數據,以相同的關閉電流(如10-8 A/μm)作為比較基準下,相較於習知結構鬆散的矽氧化物,本實施例結構較緻密的矽氧化物層130使元件的開啟電流提升約5.3%。 In addition, since the bonding property of the tantalum oxide 130 and the semiconductor substrate 110 is good in the present embodiment, the turn-on current of the element is increased. According to the experimental data, with the same shutdown current (such as 10 -8 A/μm) as a comparison, the denser tantalum oxide layer 130 of the present embodiment makes the component more compact than the conventional structure of the tantalum oxide. The turn-on current boost is about 5.3%.
如第2A圖所示,形成介電層270於包覆MOSFET結構200’。 As shown in FIG. 2A, a dielectric layer 270 is formed over the MOSFET structure 200'.
前述之閘介電層240可以是高介電常數材料,閘極250可以是金屬閘極,金屬閘極更由功函數材料層及低阻值金屬層(或阻障層)來構成。製程上可以採金屬閘極後製高介電常數材料後製、或金屬閘極後製高介電常數材料前製來形成。當採金屬閘極後製高介電常數材料後製時,矽氧化物130與緻密層120可以是前製或後製。以下詳細說明矽氧化物130與緻密層120前製、金屬閘極後製、高介電常數材料後製之製程,磨削如第2A圖所示之介電層270以露出虛置閘極250。然後,可採用例如是蝕刻製程,去除虛置閘介電層240及虛置閘極250,以形 成凹部271。 The gate dielectric layer 240 may be a high dielectric constant material, the gate 250 may be a metal gate, and the metal gate is further composed of a work function material layer and a low resistance metal layer (or barrier layer). The process can be formed by using a metal gate after the high dielectric constant material is formed, or a metal gate is used to form a high dielectric constant material. When the high dielectric constant material is formed after the metal gate is formed, the tantalum oxide 130 and the dense layer 120 may be pre-made or post-made. Hereinafter, the process of preparing the tantalum oxide 130 and the dense layer 120, the metal gate post-production, and the high dielectric constant material is described in detail, and the dielectric layer 270 as shown in FIG. 2A is ground to expose the dummy gate 250. . Then, for example, an etch process can be used to remove the dummy gate dielectric layer 240 and the dummy gate 250 to form A recess 271 is formed.
如第2B圖所示,可採用例如是化學氣相沈積法(CVD)或物理氣相沈積法(PVD),形成高介電常數閘介電層240於緻密層120上,其中高介電常數閘介電層240順應緻密層120的上表面輪廓及凹部271的側壁輪廓而形成。此外,閘介電層240具有高介電常數,其厚度約為30埃。 As shown in FIG. 2B, a high dielectric constant gate dielectric layer 240 may be formed on the dense layer 120 by, for example, chemical vapor deposition (CVD) or physical vapor deposition (PVD), wherein the high dielectric constant is high. The gate dielectric layer 240 is formed in conformity with the contour of the upper surface of the dense layer 120 and the sidewall profile of the recess 271. In addition, gate dielectric layer 240 has a high dielectric constant and a thickness of about 30 angstroms.
為了提升元件的可靠度,高介電常數閘介電層240形成後,可於高介電常數閘介電層240上執行氮化處理。 In order to improve the reliability of the device, after the high dielectric constant gate dielectric layer 240 is formed, the nitridation process can be performed on the high dielectric constant gate dielectric layer 240.
如第2B圖所示,可採用例如是沉積方法,形成一導電層290於閘介電層240上,其中導電層290順應閘介電層240的結構而形成。本實施例中,導電層290是功函數導電層,例如是氮化鈦(TiN)或鋁化鈦(TiAl)。 As shown in FIG. 2B, a conductive layer 290 can be formed on the gate dielectric layer 240 by, for example, a deposition method, wherein the conductive layer 290 is formed in conformity with the structure of the gate dielectric layer 240. In this embodiment, the conductive layer 290 is a work function conductive layer, such as titanium nitride (TiN) or titanium aluminide (TiAl).
第2B圖中,可採用例如是沉積方法,形成一導電層295於導電層290上,其中導電層295填滿上述凹部271。導電層295例如是低阻值的導電層,如鋁金屬。導電層295與導電層290構成MOSFET結構的閘極250。 In FIG. 2B, a conductive layer 295 may be formed on the conductive layer 290 by, for example, a deposition method, wherein the conductive layer 295 fills the recess 271. Conductive layer 295 is, for example, a low resistance conductive layer such as aluminum metal. Conductive layer 295 and conductive layer 290 form a gate 250 of the MOSFET structure.
如第2B圖所示,形成介電層170覆蓋閘極250及介電層270,而形成MOSFET結構200。 As shown in FIG. 2B, the dielectric layer 170 is formed to cover the gate 250 and the dielectric layer 270 to form the MOSFET structure 200.
雖然上述實施例之主動元件的形成方法係以”矽氧化物先製、閘介電層後製且閘極後製”的製程為例說明,然此非用以限制本發明實施例,以下係說明另一種”矽氧化物先製、閘介電層先製而閘極後製”的製程。 Although the method for forming the active device of the above embodiment is described by taking the process of “pre-manganese oxide first, gate dielectric layer post-production and gate post-production” as an example, it is not intended to limit the embodiments of the present invention. Explain another process of “pre-manufacturing of tantalum oxide, first implementation of gate dielectric layer and post-gate fabrication”.
請參照第2C圖,其繪示依照本發明另一實施例之主動元件的形成過程圖。在此實施例中,蝕刻第2A圖之閘極250,但保留具有高介電常數的閘介電層240。然後,形 成導電層290於閘介電層240上。然後,形成導電層295填滿凹部271,其中導電層295與導電層290構成MOSFET結構的閘極250。然後,形成介電層170覆蓋閘極250及介電層270,而形成第2C圖之MOSFET結構300。 Please refer to FIG. 2C, which illustrates a process of forming an active device according to another embodiment of the present invention. In this embodiment, the gate 250 of FIG. 2A is etched, but the gate dielectric layer 240 having a high dielectric constant is retained. Then, shape A conductive layer 290 is formed on the gate dielectric layer 240. Then, a conductive layer 295 is formed to fill the recess 271, wherein the conductive layer 295 and the conductive layer 290 constitute the gate 250 of the MOSFET structure. Then, the dielectric layer 170 is formed to cover the gate 250 and the dielectric layer 270 to form the MOSFET structure 300 of FIG.
綜上所述,雖然本發明已以實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。 In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
110‧‧‧半導體基板 110‧‧‧Semiconductor substrate
120'‧‧‧化學氧化層 120'‧‧‧Chemical Oxide
120‧‧‧緻密層 120‧‧‧Dense layer
130‧‧‧矽氧化物 130‧‧‧矽Oxide
170、270‧‧‧介電層 170, 270‧‧‧ dielectric layer
200、300‧‧‧主動元件 200, 300‧‧‧ active components
240‧‧‧閘介電層 240‧‧‧gate dielectric layer
250‧‧‧閘極 250‧‧‧ gate
260‧‧‧第一摻雜區域 260‧‧‧First doped region
265‧‧‧第二摻雜區域 265‧‧‧Second doped region
271‧‧‧凹部 271‧‧‧ recess
290、295‧‧‧導電層 290, 295‧‧‧ conductive layer
第1A至1D圖繪示依照本發明一實施例之矽氧化物層的形成過程圖。 1A to 1D are views showing a process of forming a tantalum oxide layer according to an embodiment of the present invention.
第2A至2B圖繪示依照本發明一實施例之主動元件的形成過程圖。 2A-2B are diagrams showing a process of forming an active device in accordance with an embodiment of the present invention.
第2C圖繪示依照本發明另一實施例之主動元件的形成過程圖。 FIG. 2C is a diagram showing a process of forming an active device according to another embodiment of the present invention.
110‧‧‧半導體基板 110‧‧‧Semiconductor substrate
120‧‧‧緻密層 120‧‧‧Dense layer
130‧‧‧矽氧化物 130‧‧‧矽Oxide
Claims (16)
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US7402480B2 (en) * | 2004-07-01 | 2008-07-22 | Linear Technology Corporation | Method of fabricating a semiconductor device with multiple gate oxide thicknesses |
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US7910467B2 (en) * | 2009-01-16 | 2011-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for treating layers of a gate stack |
US8313994B2 (en) * | 2009-03-26 | 2012-11-20 | Tokyo Electron Limited | Method for forming a high-K gate stack with reduced effective oxide thickness |
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