TW201403818A - Structure of vertical type dual gates transistors - Google Patents

Abstract

A structure of vertical type dual gates transistors comprises a substrate, at least a signaling wire, a plurality of columns spaced at intervals and arranged on the signaling wire, a plurality of receiving slots corresponding to the columns, a dielectric layer and a plurality of gates respectively formed in the receiving slots. The columns respectively have a connection part adjacent to the signaling wire, a top far away from the connection part and a sensing part disposed between the connection part and the top. The width of the sensing part is smaller than the widths of the connection part and the top. The gate corresponds to the location of the sensing part. The voltage operational sensitivity of the gate switch can be enhanced by utilizing the thinner sensing parts on the columns, and further the contrast ratio of the output current can be enhanced while turning on or off the gates, and the maximum current outputted by the columns can be retained as well.

Description

Vertical double gate transistor structure

The present invention relates to a transistor structure, and more particularly to a structure of a vertical double gate transistor.

The continuous improvement of semiconductor process technology has greatly reduced the size of electronic components on the one hand, and greatly reduced the manufacturing cost of electronic components on the other hand. The semiconductor process technology used in the past years is limited to the formation of planar semiconductor structures by etching, ion cloth values, wiring, etc. on the substrate, and the minimum wafer size can reach 6F2. However, at present, such technologies tend to be flattened with the miniaturization of the feature size, and the area occupied by the semiconductor on the wafer cannot be significantly reduced. Thus, vertical (or three-dimensional) semiconductor process technology is gradually evolving, which reduces the area occupied by the transistor on the wafer surface by vertically growing the semiconductor on the wafer, and further The chip size is reduced to 4F2. DRAM arrays, vertical transistor structures and methods of forming transistor structure and DRAM Array, and "Folded bit line DRAM with vertical ultra thin body transistors", respectively, which are disclosed in U.S. Patent Publication No. 7,266,061, respectively. A vertical columnar transistor structure and a manufacturing method and process thereof, wherein a gate material is formed beside the columnar body to control the conduction of the columnar body used as the transistor No, it is usually to form a gate which is not in contact with each other and attached to the columnar body by etching the metal wire. However, as the feature size has dropped below 40 nanometers (nm), the way in which the metal lines are etched to form gates on both sides of the column is greatly challenged because of its thickness control. .

Therefore, "SEMICONDUCTOR DEVICE HAVING VERTICAL PILLAR TRANSISTORS AND METHOD FOR MANUFACTURING THE SAME", which is disclosed in the U.S. Patent Publication No. 20090256187, discloses a gate which is provided only on one side of the columnar body, and is formed by etching the columnar body. a recess, and then a metal is formed in the recess to form a gate. Although it discloses a different manufacturing method from the prior art, it is difficult to control the thickness of the metal line by etching the metal line, but the same The gate must be etched to complete the gate arrangement, and the manner in which the pillars are etched to form the recesses is equally difficult.

The main object of the present invention is to solve the problem that the gate of the transistor is difficult to manufacture in the process technology in which the feature size is gradually reduced.

In order to achieve the above object, the present invention provides a structure of a vertical double-gate transistor, comprising a substrate, at least one signal line disposed on a surface of the substrate, a plurality of columnar bodies disposed on the signal line, and a plurality of a receiving recess between two adjacent columns, a dielectric layer, and a plurality of gates respectively formed in the receiving recesses. Each of the columnar bodies has a connecting portion adjacent to the signal line, a top portion away from the connecting portion, and a sensing portion disposed between the connecting portion and the top portion, the sensing portion having a width smaller than the connecting portion And the width of the top portion, the dielectric layer is formed on the surface of the accommodating recesses, and each of the gates is disposed at a position corresponding to the sensing portion, between the gate and the column body and the signal line The dielectric layer is spaced apart and the gates are not connected.

As can be seen from the above description, the present invention has the following features:

1. With the structure of the present invention, the etching separation of the gate is not required, the process steps of the gate are simplified, and it can be applied to the current transistor process and the process technology of the minimum line width shrinking in the future.

Second, the columnar body has a shorter distance between adjacent gates by the arrangement of the sensing portion, thereby having better corresponding control sensitivity, and the contrast of the current output when the gate switch is improved.

3. The width of the connecting portion and the top portion is greater than the width of the sensing portion, thereby avoiding reducing the maximum current value of the output of the column to maintain the circuit characteristics and quality of the transistor.

It should be noted that the structure of the double-gate transistor and the operation mode of the present invention have been described in the "Vertical Non-Dynamic Random Access Memory Structure" of the Taiwan Patent Application No. 100131047 previously filed by the applicant of the present application. "VERTICAL NON-DYNAMIC RAM STRUCTURE" of U.S. Patent Application Serial No. 13/282,948, the disclosure of which is incorporated herein incorporated by its entirety in its entirety in its entirety in its entirety the disclosure the disclosure the the the the the the the Etching problems. In addition, the applicant of the present application has further proposed a method for controlling the vertical mode of the dual gate active random access memory (Taiwan Patent Application No. 100138249) and the copending U.S. Patent Application No. 13/312,074. "METHOD OF CONTROLLING A VERTICAL DUAL-GATE DYNAMIC RANDOM ACCESS MEMORY", which discloses a control method for turning on and off the above-mentioned double gate transistor, and discloses a short circuit state, a false open state, and a fully open state The crystal control method and a setting of the clear state are explained, and the leakage current problem between the transistor states can be avoided.

The vertical transistor structure includes a plurality of columnar bodies 10, a plurality of trenches 20 formed between any two adjacent columnar bodies 10, and formed in the trenches 20, as shown in FIG. The gates 30 each have a corresponding two side walls 11 , and the adjacent two gates 30 respectively correspond to the two side walls 11 , and a gap between the gates 30 and the side walls 11 is provided Electrical layer 15. Please refer to "Figure 2" for the operation of the transistor including a short circuit condition, an open path and a false open state. For example, a first gate 31 and a second gate 32 adjacent to the first column 12 are connected to a conduction voltage V _on , and the first column 12 is electrically connected. In the short-circuit state, if the third gate 33 and the fourth gate 34 adjacent to the third column 14 are both connected to a cutoff voltage V _off , the third column 14 is in an open state. If the second gate 32 next to the second columnar body 13 is connected to the on-voltage V _on and the third gate 33 is turned on by the off-voltage V _off , it is called a pseudo-open state, and the conduction current is seen. The turn-on voltage V _on and the magnitude of the cutoff voltage V _off , and the amount of current will be between the short-circuit state and the open state.

Please refer to "FIG. 3A" and "FIG. 3B" for the implementation of the first transistor, wherein "FIG. 3A" is the columnar body 10a corresponding to "FIG. 1" and the adjacent sides. A first gate 31a and a second gate 32a are simplified and the drawing is simplified for enhanced feature description. As shown in the figure, when the width of the columnar body 10a is large, for example, 30 nm, the current conduction state is as shown in FIG. 3B, and includes a synchronization curve 41a, a variation curve 42a, and a contrast curve. 43a, the synchronization curve 41a represents that the first gate 31a and the second gate 32a are set to have the same voltage, so that the current is also increased from 1×10 ^-18 (μA/μm) as the voltage is from a low voltage to a high voltage. 1 × 10 ^-3 (μA / μm), in other words, when the first gate 31a and the second gate 32a are simultaneously supplied with a low voltage, the columnar body 10a is not electrically conductive, and thus the conduction current is equivalent. When the first gate 31a and the second gate 32a are simultaneously energized with a high voltage, the columnar body 10a is electrically turned on to increase the on current. The change curve 42a is a curve obtained by fixing the first gate 31 a to a low voltage and controlling the voltage of the second gate 32 a to change from a low voltage to a high voltage, wherein the current value represented by the change curve 42 a is smaller than The synchronization curve 41a is because the voltage of the first gate 31a is fixed to a low voltage, so the current is lower than the synchronization curve 41a, and the voltage and current curves in the pseudo open state are obtained by the indication of the variation curve 42. As a judgment as to whether or not the transistor is turned on. The comparison curve 43a represents the division of the synchronization curve 41a by the variation curve 42a, thereby determining the difference between the synchronization curve 41a and the variation curve 42a. If the difference is larger, it is easier to distinguish between the pseudo open state and the short circuit state. It should also be noted that the value of the contrast curve 43a corresponds to the number of the right vertical coordinate.

Please refer to FIG. 4A and FIG. 4B, which are schematic diagrams showing the structure of the columnar body 10b of the second transistor and the first gate 31b and the second gate 32b on the adjacent sides. The width of the columnar body 10b was thinned to 10 nm. From "Fig. 4B" versus "Fig. 3B", the thinned contrast curve 43b is much larger than the contrast curve 43b before thinning. In other words, the difference between the thinned synchronization curve 41b and the variation curve 42b is much thinner before the thinning, so that the transistor switch judgment is better and the judgment error is reduced. However, the on-currents of the synchronization curve 41b and the variation curve 42b in "FIG. 4B" are smaller than the on-currents of the synchronization curve 41a and the variation curve 42a of "FIG. 3B" because the columnar body 10b changes with the width. The thinness makes the cross-sectional area smaller, and also increases the resistance of the columnar body 10b, thereby lowering the on-current and reducing the circuit characteristics and quality of the transistor. Therefore, the width of the columnar bodies 10a, 10b controls the magnitudes of the contrast curves 43a, 43b and the amount of current, and the contrast curves 43a, 43b have a trade off condition with the amount of current, and cannot simultaneously reach the high contrast curve 43a. , 43b and high current characteristics.

Therefore, the present invention discloses a structure of a vertical double gate transistor to solve the above situation. The detailed description and technical content of the present invention will now be described as follows:

Referring to FIG. 5, the structure of the present invention comprises a substrate 50, at least one signal line 51 disposed on the surface of the substrate 50, and a plurality of columnar bodies 60 disposed on the signal line 51 at a plurality of intervals. A receiving recess 70 between the two adjacent columns 60, a dielectric layer 52, and a plurality of gates 80 respectively formed in the receiving recesses 70. The substrate 50 may be made of 矽 or 锗. The columnar bodies 60 respectively have a connecting portion 61 adjacent to the signal line 51, a top portion 62 away from the connecting portion 61, and a connecting portion 61 disposed thereon. The width of the sensing portion 63 between the top portions 62 is smaller than the width of the connecting portion 61 and the top portion 62. In this embodiment, the width of the connecting portion 61 and the top portion 62 are away from the sensing portion 63. One of the sides tapers in the direction of the sensing portion 63. The dielectric layer 52 is formed on the surface of the accommodating recesses 70. The material of the dielectric layer 52 can be, for example, yttrium oxide, hafnium oxide, tantalum nitride or a high-k material. Each of the gates 80 is disposed at a position corresponding to the sensing portion 63. The gate electrode 80 is spaced apart from the columnar body 60 and the signal line 51 by the dielectric layer 52, and between the gates 80. Not connected. The present invention further has an insulating layer 53 disposed on a side of the gate 80 adjacent to the signal line 51, whereby the position of the gate 80 can correspond to the position of the sensing portion 63.

In this embodiment, the memory is taken as an example. Therefore, the signal line 51 has a plurality of signals, and is spaced apart from each other and used as a bit line. The bit line can be fabricated by embedding a metal wire. The bit line can be formed by ion doping. The gates 80 are perpendicular to the signal lines 51 and arranged in a matrix, and a plurality of storage elements 90 are formed on the top 62 of the columns 60 to be connected to the columns 60. The storage elements 90 can be dynamic storage elements or static storage elements, depending on the needs of use and the choice of operation mode. In more detail, the top portion 62 and the connecting portion 61 of the columnar body 60 may be respectively doped with a doping element to form a source/drain electrode at the top portion 62, and a contact portion 61 is formed at the connecting portion 61. The drain/source, the doping element is a crystal structure derived from an element of Group 2A, 3A, 5A or 6A to form an NPN or PNP. In addition to this, it is also possible to dope the same doping element so that the entire columnar region forms a junctionless semiconductor to form an N-type or P-type junction-less transistor. Therefore, the columnar bodies 60 determine the electrical conduction state of the columnar body 60 by the voltage of the gates 80 provided on the adjacent sides.

Please refer to "FIG. 6A" and "FIG. 6B". "FIG. 6A" is a columnar body 60 corresponding to "FIG. 5" and gates 80 on the adjacent sides, which are simplified for enhanced feature description. FIG. 6B also shows a synchronization curve 41c, a variation curve 42c, and a comparison curve 43c measured by the structure of the present invention, and the present invention is utilized in the same manner and under the conditions as the first transistor and the second transistor. The contrast curve 43c of the structure is significantly higher than the contrast curve 43c of the first transistor and the second transistor, and the on current can still maintain the same condition as the first transistor, so that the structure of the present invention can be simultaneously displayed Both the high current output and the high contrast curve 43c are taken into consideration.

In addition, it was confirmed by experiments that in the short circuit state, the current obtained through the first transistor is 459 (μA/μm), and the current obtained by the second transistor is 259 (μA/μm). The current obtained by the present invention is 471 (μA/μm). Therefore, the structure disclosed in the present invention has the same or better performance as the first transistor in the short-circuit current, and the second transistor has a thinness reduction. And the current is lower. In addition, in the open state, the current obtained by the first transistor is 3050 (fA/μm), the second transistor is 12 (fA/μm), and the current obtained by the structure of the present invention is 16 (fA). /μm), therefore, in the performance of the open circuit, the present invention can also effectively avoid the occurrence of leakage current, and has better transistor characteristics and quality.

In summary, the present invention has the following features:

1. With the structure of the present invention, the etching separation of the gate is not required, the process steps of the gate are simplified, and it can be applied to the current transistor process and the process technology of the minimum line width shrinking in the future.

Second, the columnar body has a shorter distance between adjacent gates by the arrangement of the sensing portion, thereby having better corresponding control sensitivity, and the contrast of the current output when the gate switch is improved.

3. The width of the connecting portion and the top portion is larger than the width of the sensing portion, thereby avoiding the thinning of the transistor and reducing the cross-sectional area, thereby causing a problem of increasing resistance, thereby avoiding lowering the maximum current value of the column output and maintaining the transistor. Circuit characteristics and quality.

Therefore, the present invention is highly progressive and conforms to the requirements of the invention patent application, and the application is filed according to law, and the praying office grants the patent as soon as possible.

The present invention has been described in detail above, but the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the scope of the invention. That is, the equivalent changes and modifications made by the scope of the present application should remain within the scope of the patent of the present invention.

10, 10a, 10b, 60. . . Columnar body

11. . . Side wall

12. . . First column

13. . . Second column

14. . . Third column

15, 52. . . Dielectric layer

20. . . ditch

30, 80. . . Gate

31, 31a, 31b. . . First gate

32, 32a, 32b. . . Second gate

33. . . Third gate

34. . . Fourth gate

41a, 41b, 41c. . . Synchronization curve

42a, 42b, 42c. . . Curve

43a, 43b, 43c. . . Contrast curve

50. . . Base

51. . . Signal line

53. . . Insulation

61. . . Connection

62. . . top

63. . . Induction unit

70. . . Locating groove

90. . . Storage element

Figure 1 is a schematic diagram of the structure of the associated transistor.

Figure 2 is a schematic diagram of the operational state of the associated transistor.

3A is a schematic view showing the structure of a first transistor.

FIG. 3B is a schematic diagram of electrical characteristics of the first transistor.

4A is a schematic view showing the structure of a second transistor.

FIG. 4B is a schematic diagram showing electrical characteristics of the second transistor.

Figure 5 is a schematic view showing the structure of the present invention.

Fig. 6A is a schematic structural view of a transistor of the present invention.

Fig. 6B is a schematic view showing the electrical characteristic curve of the transistor of the present invention.

50. . . Base

51. . . Signal line

52. . . Dielectric layer

53. . . Insulation

60. . . Columnar body

61. . . Connection

62. . . top

63. . . Induction unit

70. . . Locating groove

80. . . Gate

90. . . Storage element

Claims (9)

A vertical double gate transistor structure comprising:
a substrate;
At least one signal line disposed on a surface of the substrate;
a plurality of columnar bodies disposed on the signal line, the columnar bodies respectively having a connecting portion adjacent to the signal line, a top portion away from the connecting portion, and a portion disposed between the connecting portion and the top portion a sensing portion, the width of the sensing portion is smaller than a width of the connecting portion and the top portion;
a plurality of receiving grooves formed between any two adjacent columns;
a dielectric layer formed on the surface of the accommodating recesses; and a plurality of gates respectively formed in the accommodating recesses, each of the gates corresponding to the position of the sensing portion, the gate and the gate The dielectric layer is spaced between the column and the signal line, and the gates are not connected. The structure of the vertical double gate transistor according to claim 1, wherein an insulating layer is formed on a side of the gate adjacent to the signal line. The structure of the vertical double-gate transistor according to claim 1, wherein the signal line has a plurality of lines spaced apart from each other, and the gates are perpendicular to the signal lines and form a matrix arrangement. The structure of the vertical double gate transistor according to claim 3, further comprising a plurality of storage elements formed on top of the columns. The structure of the vertical double gate transistor according to claim 4, wherein the signal line is a bit line. The structure of the vertical double-gate transistor according to claim 1, wherein the top portion and the connecting portion are respectively doped with a doping element to form a source/drain at the top, and The connection forms a drain/source. The structure of the vertical double gate transistor according to claim 6, wherein the doping element is derived from a group consisting of 2A, 3A, 5A and 6A elements. The structure of the vertical double gate transistor according to claim 1, wherein the substrate is selected from the group consisting of ruthenium and osmium. The structure of the vertical double-gate transistor according to claim 1, wherein the width of the connecting portion and the top portion is tapered from a side away from the sensing portion toward the sensing portion.