TW201403677A - Methods of forming semiconductor devices with metal silicide using pre-amorphization implants and devices so formed - Google Patents

Methods of forming semiconductor devices with metal silicide using pre-amorphization implants and devices so formed Download PDF

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TW201403677A
TW201403677A TW102117973A TW102117973A TW201403677A TW 201403677 A TW201403677 A TW 201403677A TW 102117973 A TW102117973 A TW 102117973A TW 102117973 A TW102117973 A TW 102117973A TW 201403677 A TW201403677 A TW 201403677A
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Taiwan
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forming
semiconductor device
metal
drain region
elevated source
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TW102117973A
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TWI591690B (en
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Chung-Hwan Shin
Sang-Bom Kang
Dae-Yong Kim
Jeong-Ik Kim
Chul-Sung Kim
Je-Hyung Ryu
Sang-Woo Lee
Hyo-Seok Choi
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Samsung Electronics Co Ltd
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Abstract

A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.

Description

使用預非晶化佈植的具有金屬矽化物的半導體元件的形成方法及由其形成的元件 Method for forming a semiconductor element having a metal germanide using pre-amorphization implantation and components formed therefrom 【相關申請案互相參照】[Related application cross-referencing]

本申請案主張在2012年5月24日於韓國智慧財產局提申的韓國專利申請案第10-2012-0055543號的優先權，其所揭露的內容完整地以引用方式併入本文。 The present application claims priority to Korean Patent Application No. 10-2012-0055543, filed on May 24, 2012, the disclosure of which is hereby incorporated by reference.

本發明是有關於一種半導體元件，且特別是有關於一種利用金屬矽化物的元件及其製造方法。 The present invention relates to a semiconductor device, and more particularly to an element utilizing a metal telluride and a method of fabricating the same.

當將半導體元件的積體密度定在20 nm或以下時，可減小金屬矽化物與矽之間的界面電阻。此是由於金屬矽化物與矽之間的界面電阻可作為半導體元件的寄生電阻(parasitic resistance)的支配要素。 When the bulk density of the semiconductor element is set to 20 nm or less, the interface resistance between the metal telluride and the tantalum can be reduced. This is because the interface resistance between the metal telluride and the germanium can be used as a dominant element of the parasitic resistance of the semiconductor element.

例如，藉由增加源極/汲極的摻雜濃度或減小蕭基能障 (Schottky Barrier)的高度可減小界面電阻。而且，藉由增加金屬矽化物與矽之間的界面面積可減小界面電阻。 For example, by increasing the doping concentration of the source/drain or reducing the base energy barrier The height of (Schottky Barrier) reduces the interface resistance. Moreover, the interface resistance can be reduced by increasing the interface area between the metal telluride and the germanium.

根據本發明的實施例可提供使用預非晶化佈植(pre-amorphization implants,PAI)的具有金屬矽化物的半導體元件的形成方法及由其形成的元件。依照此些實施例，可藉由形成露出升高的源極/汲極區的表面的開口來提供半導體元件的形成方法。可縮小開口的大小，且可通過開口施行預非晶化佈植至升高的源極/汲極區內，以形成升高的源極/汲極區的非晶化部分。可由金屬與非晶化部分形成金屬矽化物。 Embodiments of the present invention may provide a method of forming a metal germanide-containing semiconductor element using pre-amorphization implants (PAI) and an element formed therefrom. In accordance with such embodiments, a method of forming a semiconductor device can be provided by forming an opening that exposes a surface of the elevated source/drain region. The size of the opening can be reduced and pre-amorphized through the opening to the elevated source/drain regions to form an amorphized portion of the elevated source/drain regions. The metal telluride can be formed from the metal and the amorphized portion.

在本發明的一些實施例中，施行PAI的方法可包括形成包括與表面遠離的PAI的下輪廓的非晶化部分，PAI的下輪廓具有曲面剖面。在本發明的一些實施例中，曲面剖面的中心部分呈曲面。 In some embodiments of the invention, a method of performing a PAI can include forming an amorphized portion comprising a lower profile of a PAI that is remote from the surface, the lower profile of the PAI having a curved profile. In some embodiments of the invention, the central portion of the curved section is curved.

在本發明的一些實施例中，藉由形成包括與表面遠離的矽化物的下輪廓的金屬矽化物可提供形成金屬矽化物的方法，矽化物的下輪廓具有曲面剖面。在本發明的一些實施例中，曲面剖面的中心部分呈曲面。 In some embodiments of the invention, a method of forming a metal telluride can be provided by forming a metal halide comprising a lower profile of a telluride remote from the surface, the lower profile of the telluride having a curved profile. In some embodiments of the invention, the central portion of the curved section is curved.

在本發明的一些實施例中，藉由在與閘極氧化層相同或更高的高度形成矽化物的下輪廓可提供形成金屬矽化物的方法，其中閘極氧化層包含於直接與升高的源極/汲極區鄰接的閘極結構中。在本發明的一些實施例中，所述高度為約15 nm或以下。 In some embodiments of the invention, a method of forming a metal telluride can be provided by forming a lower profile of the telluride at the same or higher height as the gate oxide layer, wherein the gate oxide layer is included directly and elevated The source/drain region is adjacent to the gate structure. In some embodiments of the invention, the height is about 15 nm or less.

在本發明的一些實施例中，藉由在高於通道區的高度形成矽化物的下輪廓可提供形成金屬矽化物的方法，其中通道區與至少一個直接鄰接 的閘極結構連接。在本發明的一些實施例中，在升高的源極/汲極區中的矽化物的下輪廓的深度比升高的源極/汲極區的全部厚度的一半更大。 In some embodiments of the invention, a method of forming a metal telluride can be provided by forming a lower profile of the telluride at a height above the channel region, wherein the channel region is directly adjacent to at least one The gate structure is connected. In some embodiments of the invention, the lower profile of the germanide in the elevated source/drain regions is greater than half the total thickness of the elevated source/drain regions.

在本發明的一些實施例中，藉由縮小開口的底部的開口大小可提供縮小開口的大小的方法。在本發明的一些實施例中，藉由改變開口的底部的形狀以造成曲面側壁可提供縮小開口的大小的方法，曲面側壁於底部朝向升高的源極/汲極區的表面呈曲面。 In some embodiments of the invention, a method of reducing the size of the opening can be provided by reducing the size of the opening at the bottom of the opening. In some embodiments of the invention, the curved sidewalls may provide a method of reducing the size of the opening by varying the shape of the bottom of the opening, the curved sidewall being curved toward the surface of the raised source/drain region at the bottom.

在本發明的一些實施例中，藉由蝕刻升高的源極/汲極區的表面使表面的高度凹陷可提供縮小開口的大小的方法。在本發明的一些實施例中，藉由對升高的源極/汲極區與開口的側壁進行射頻蝕刻可提供縮小開口的大小的方法。 In some embodiments of the invention, recessing the height of the surface by etching the raised surface of the source/drain regions provides a way to reduce the size of the opening. In some embodiments of the invention, a method of reducing the size of the opening can be provided by radio frequency etching the raised source/drain regions and the sidewalls of the opening.

在本發明的一些實施例中，藉由形成包括與表面遠離的PAI的下輪廓的非晶化部分可提供施行PAI的方法，其中PAI的下輪廓具有曲面剖面。在本發明的一些實施例中，金屬矽化物可包括具有底部與側壁的上凹部，其中底部與矽化物的下輪廓的底部分開的距離比凹部的側壁與矽化物的下輪廓的側壁分開的距離更大。 In some embodiments of the invention, a method of performing a PAI can be provided by forming an amorphized portion comprising a lower profile of a PAI remote from the surface, wherein the lower profile of the PAI has a curved profile. In some embodiments of the invention, the metal halide may comprise an upper recess having a bottom and a side wall, wherein the bottom is separated from the bottom of the lower profile of the telluride by a distance separating the sidewall of the recess from the sidewall of the lower profile of the telluride Bigger.

在本發明的一些實施例中，金屬矽化物更包括相對於矽化物的下輪廓的凸面狀頂部。在本發明的一些實施例中，藉由將氙佈植至升高的源極/汲極區內以形成具有PAI的下輪廓的非晶化部分可提供施行PAI的方法，非晶化部分的總厚度為至少約100埃。 In some embodiments of the invention, the metal telluride further includes a convex top with respect to a lower profile of the telluride. In some embodiments of the invention, a method of performing PAI, amorphized portion, can be provided by implanting germanium into an elevated source/drain region to form an amorphized portion having a lower profile of PAI The total thickness is at least about 100 angstroms.

在本發明的一些實施例中，藉由將矽佈植至升高的源極/汲極區內以形成具有PAI的下輪廓的非晶化部分可提供施行PAI的方法，非晶化部分的總厚度為至少約100埃。 In some embodiments of the invention, a method of performing PAI, amorphized portion, can be provided by implanting germanium into an elevated source/drain region to form an amorphized portion having a lower profile of PAI The total thickness is at least about 100 angstroms.

在本發明的一些實施例中，藉由形成露出升高的源極/汲極區的表面的開口可提供一種半導體元件的形成方法。可通過開口施行PAI至升高的源極/汲極區內，以形成升高的源極/汲極區的非晶化部分。由金屬與非晶化部分形成金屬矽化物。 In some embodiments of the invention, a method of forming a semiconductor device can be provided by forming an opening that exposes a surface of the elevated source/drain region. The PAI can be applied through the opening to the elevated source/drain regions to form an amorphized portion of the elevated source/drain regions. A metal halide is formed from the metal and the amorphized portion.

在本發明的一些實施例中，一種半導體元件可包括：包括PMOS區以及NMOS區的基板；可位於絕緣層內的第一接觸窗孔洞，其露出PMOS區內的第一升高的源極/汲極區；可位於第一升高的源極/汲極區上的第一接觸窗孔洞內的第一金屬接觸窗；可位於第一升高的源極/汲極區內並與第一金屬接觸窗接觸的第一金屬矽化物，第一金屬矽化物包括與第一升高的源極/汲極區的表面遠離的第一矽化物的下輪廓，第一矽化物的下輪廓具有曲面剖面，且第一金屬矽化物包括相對於第一矽化物的下輪廓的平面頂部；可位於絕緣層內的第二接觸窗孔洞，其露出NMOS區內的第二升高的源極/汲極區，以及可位於第二升高的源極/汲極區上的第二接觸窗孔洞內的第二金屬接觸窗；可位於第二升高的源極/汲極區內並與第二金屬接觸窗接觸的第二金屬矽化物，第二金屬矽化物包括與第二升高的源極/汲極區的表面遠離的第二矽化物的下輪廓，第二矽化物的下輪廓具有曲面剖面，且第二金屬矽化物包括相對於第二矽化物的下輪廓的凸面頂部 In some embodiments of the present invention, a semiconductor device may include: a substrate including a PMOS region and an NMOS region; a first contact hole that may be located in the insulating layer, exposing the first elevated source in the PMOS region/ a first metal contact window in the first contact window hole on the first elevated source/drain region; may be located in the first elevated source/drain region and first a first metal telluride contacted by the metal contact window, the first metal halide comprising a lower profile of the first germanide away from the surface of the first elevated source/drain region, the lower contour of the first germanide having a curved surface a cross section, and the first metal germanide includes a planar top portion with respect to a lower contour of the first germanide; a second contact hole may be located within the insulating layer, exposing a second elevated source/drain of the NMOS region a second metal contact window in the second contact window hole that may be located on the second elevated source/drain region; may be located in the second elevated source/drain region and with the second metal a second metal halide contacting the contact window, the second metal halide comprising and the second High surface of the source / drain regions away from the lower profile of the second silicide and the second silicide lower profile cross section has a curved surface, and the second metal silicide having a convex surface with respect to the top profile of the second silicide

根據本發明的一些實施例，藉由形成露出升高的源極/汲極區的表面的開口可提供一種半導體元件的形成方法。升高的源極/汲極區可經處理以在升高的源極/汲極區內提供非均向金屬擴散速率，且可根據非均向金屬擴散速率由金屬與非晶化部分形成金屬矽化物，以提供包括與表面遠離的矽化物的下輪廓的金屬矽化物，矽化物的下輪廓具有曲面剖面。 According to some embodiments of the present invention, a method of forming a semiconductor element can be provided by forming an opening that exposes a surface of the raised source/drain region. The elevated source/drain regions can be treated to provide a non-uniform metal diffusion rate in the elevated source/drain regions and metal can be formed from the metal and amorphized portions according to the non-uniform metal diffusion rate A telluride to provide a metal halide comprising a lower profile of the telluride away from the surface, the lower profile of the telluride having a curved profile.

1、2、3、4、5、6‧‧‧半導體元件 1, 2, 3, 4, 5, 6‧‧‧ semiconductor components

100‧‧‧基板 100‧‧‧Substrate

101‧‧‧摻雜區 101‧‧‧Doped area

110‧‧‧第二金屬層 110‧‧‧Second metal layer

111a、111b‧‧‧電晶體 111a, 111b‧‧‧O crystal

115‧‧‧第一金屬層 115‧‧‧First metal layer

116‧‧‧閘極 116‧‧‧ gate

102、103、117‧‧‧升高的源極/汲極 102, 103, 117‧‧‧ raised source/drain

120‧‧‧閘極氧化層 120‧‧‧ gate oxide layer

121‧‧‧第一層間絕緣膜 121‧‧‧First interlayer insulating film

122‧‧‧第二層間絕緣膜 122‧‧‧Second interlayer insulating film

126‧‧‧孔隙 126‧‧‧ pores

141、143、341‧‧‧磊晶層 141, 143, 341‧‧ ‧ epitaxial layer

141a‧‧‧突出部 141a‧‧‧Protruding

141b‧‧‧表面 141b‧‧‧ surface

142‧‧‧矽鍺層 142‧‧‧矽锗

151‧‧‧金屬矽化物 151‧‧‧Metal Telluride

151a‧‧‧上凹部 151a‧‧‧Upper recess

151b‧‧‧凸面狀頂部 151b‧‧‧ convex top

152‧‧‧下輪廓 152‧‧‧Under contour

152a、195‧‧‧部分 Section 152a, 195‧‧‧

156‧‧‧上表面、水平面 156‧‧‧Upper surface, horizontal

158‧‧‧側表面 158‧‧‧ side surface

159‧‧‧頂端區 159‧‧‧top area

160‧‧‧金屬接觸窗 160‧‧‧Metal contact window

161、161a、161b‧‧‧接觸窗孔洞 161, 161a, 161b‧‧‧ contact window holes

165‧‧‧阻障層 165‧‧‧Barrier layer

198‧‧‧射頻蝕刻處理 198‧‧‧RF etching

199‧‧‧非晶化處理 199‧‧‧ Amorphization

201‧‧‧第二升高的源極/汲極 201‧‧‧Second elevated source/drain

210‧‧‧第四金屬層 210‧‧‧Fourth metal layer

211‧‧‧第二閘極 211‧‧‧second gate

215‧‧‧第三金屬層 215‧‧‧ Third metal layer

226‧‧‧第二孔隙 226‧‧‧second pore

251‧‧‧第二矽化物 251‧‧‧Second Telluride

301‧‧‧第三升高的源極/汲極 301‧‧‧ third elevated source/dip

311‧‧‧第三閘極 311‧‧‧third gate

351‧‧‧第三金屬矽化物 351‧‧‧ Third metal telluride

410、412‧‧‧PMOS電晶體的主動區 410, 412‧‧‧ active area of PMOS transistor

414、416‧‧‧NMOS電晶體的主動區 414, 416‧‧‧ active area of NMOS transistor

420‧‧‧第一驅動電晶體T3的閘電極 420‧‧‧The gate electrode of the first drive transistor T3

422‧‧‧第二驅動電晶體T4的閘電極 422‧‧‧The gate electrode of the second drive transistor T4

430‧‧‧第一傳輸電晶體T1與第二傳輸電晶體T2的閘電極 430‧‧‧The gate electrode of the first transmission transistor T1 and the second transmission transistor T2

440‧‧‧電源線 440‧‧‧Power cord

450‧‧‧接地線 450‧‧‧ Grounding wire

460‧‧‧位元線BL與互補位元線/BL 460‧‧‧ bit line BL and complementary bit line/BL

490‧‧‧金屬接觸窗 490‧‧‧Metal contact window

BL‧‧‧位元線 BL‧‧‧ bit line

/BL‧‧‧互補位元線 /BL‧‧‧Complementary bit line

INV1、INV2‧‧‧反相器 INV1, INV2‧‧‧ inverter

L1‧‧‧垂直長度 L1‧‧‧ vertical length

L2‧‧‧水平長度 L2‧‧‧ horizontal length

NC1、NC2‧‧‧節點 NC1, NC2‧‧‧ nodes

T1‧‧‧第一傳輸電晶體 T1‧‧‧ first transmission transistor

T2‧‧‧第二傳輸電晶體 T2‧‧‧second transmission transistor

T3‧‧‧第一驅動電晶體 T3‧‧‧First drive transistor

T4‧‧‧第二驅動電晶體 T4‧‧‧Second drive transistor

T5‧‧‧第一負載電晶體 T5‧‧‧First load transistor

T6‧‧‧第二負載電晶體 T6‧‧‧second load transistor

Vcc‧‧‧電源節點 Vcc‧‧‧ power node

Vss‧‧‧接地節點 Vss‧‧‧ Grounding node

WL1、WL2‧‧‧字元線 WL1, WL2‧‧‧ character line

θ‧‧‧預定角度 Θ‧‧‧predetermined angle

θ1、θ2‧‧‧角度 Θ1, θ2‧‧‧ angle

圖1為本發明的一些實施例的半導體元件的剖面示意圖。 1 is a schematic cross-sectional view of a semiconductor device in accordance with some embodiments of the present invention.

圖2A為圖1所示的金屬矽化物的透視圖。 2A is a perspective view of the metal telluride shown in FIG. 1.

圖2B為圖2A所示的金屬矽化物的剖面示意圖。 2B is a schematic cross-sectional view of the metal telluride shown in FIG. 2A.

圖3為本發明的一些實施例的半導體元件的剖面示意圖。 3 is a cross-sectional view of a semiconductor device in accordance with some embodiments of the present invention.

圖4A為圖3所示的金屬矽化物的透視圖。 4A is a perspective view of the metal telluride shown in FIG. 3.

圖4B為圖4A所示的金屬矽化物的剖面示意圖。 4B is a schematic cross-sectional view of the metal halide shown in FIG. 4A.

圖5為本發明的一些實施例的半導體元件的剖面示意圖。 Figure 5 is a cross-sectional view of a semiconductor device in accordance with some embodiments of the present invention.

圖6A為圖5所示的金屬矽化物的透視圖。 Figure 6A is a perspective view of the metal telluride shown in Figure 5.

圖6B為圖6A所示的金屬矽化物的剖面示意圖。 Figure 6B is a schematic cross-sectional view of the metal halide shown in Figure 6A.

圖7為本發明的一些實施例的半導體元件的剖面示意圖。 Figure 7 is a cross-sectional view of a semiconductor device in accordance with some embodiments of the present invention.

圖8為本發明的一些實施例的半導體元件的剖面示意圖。 Figure 8 is a cross-sectional view of a semiconductor device in accordance with some embodiments of the present invention.

圖9與圖10分別為本發明的一些實施例的半導體元件的電路圖以及佈局圖。 9 and 10 are respectively a circuit diagram and a layout view of a semiconductor device according to some embodiments of the present invention.

圖11至圖16B繪示本發明的一些實施例的半導體元件的製造方法的剖面示意圖。 11 to 16B are schematic cross-sectional views showing a method of fabricating a semiconductor device according to some embodiments of the present invention.

圖17繪示不同佈植的非晶矽的厚度對金屬矽化物的厚度的關係圖。 Figure 17 is a graph showing the relationship between the thickness of differently implanted amorphous germanium and the thickness of the metal telluride.

以下將參考繪示本發明的較佳實施例的隨附圖式更加完整地敘 述本發明。然而，本發明可以不同的方式實現，且不應解釋為受限於此處提出的實施例。當然，這些實施例提供的揭露將是詳盡與完備的，並能全面傳遞本發明的範圍給熟習此技術的人員。說明書中相同的元件符號代表相同的元件。在圖式中，為了清楚起見，會誇大各層及各區的厚度。 The following is a more complete description of the preferred embodiment of the present invention with reference to the accompanying drawings. The invention is described. However, the invention may be embodied in different ways and should not be construed as being limited to the embodiments set forth herein. The disclosure provided by these embodiments will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. The same component symbols in the specification denote the same components. In the drawings, the thickness of the various layers and the various regions are exaggerated for clarity.

應當理解，當膜層涉及在其他膜層或基板「上」時，該膜層可直接在其他膜層或基板上，或亦可存在介入其中的膜層。相較之下，當元件涉及直接在其他元件上時，則不存在介入其中的元件。 It should be understood that when the film layer is referred to as being "on" another film layer or substrate, the film layer may be directly on the other film layer or substrate, or there may be a film layer intervening therein. In contrast, when an element is referred to directly on another element, there is no element intervening.

諸如「下方」、「下」、「下部」、「上」、「上部」等相對空間用語，在此可用於簡化說明如圖所示的一構件或特徵對於另一構件或特徵的關係。應當理解的是，除了在附圖中顯示的方向之外，相對空間用語意在涵括使用中或操作中不同的元件方向。例如，如果在附圖中的元件翻轉，則說明為在其它構件或特徵「下」或「下部」的構件在其他構件或特徵「上」。因此，示範性用語「下」可包括上和下兩個方向。元件可朝向其它方向(旋轉90度或在其它方向上)且相應地解釋此處所用的相對空間描述。 Relative spatial terms such as "lower", "lower", "lower", "upper", "upper", etc., may be used to simplify the relationship of one component or feature to another component or feature as illustrated. It will be understood that the relative spatial terms are intended to encompass different orientations of the elements in use or operation. For example, elements in the "following" or "lower" of the other components or features are "on" other components or features. Therefore, the exemplary term "lower" can include both the upper and lower directions. The elements may be oriented in other directions (rotated 90 degrees or in other directions) and the relative spatial description used herein interpreted accordingly.

本發明所述的上下文(尤其在以下申請專利範圍的內文)中所用的詞彙「一」及「所述」以及相似的用語被解釋為涵蓋單數與多數兩者。除非另外註明，「包括」等用語被解釋為開放式的語言(即意指「包括，但不限於此」)。 The terms "a", "an" and "the" are used in the context of the invention, and the terms of Terms such as "include" are interpreted as open-ended languages (ie, "including, but not limited to," unless otherwise noted).

除了另外定義以外，所有此處所用的技術及科學用語具有與本發明所屬技術領域中具有通常知識者一般所能理解的意義相同。顯然地，任何及所有的實例的使用或此處所用的示範性用語僅用以更詳細闡述本發明，且除了另外說明以外，不以本發明的範圍為限。此外，除了另外定義 以外，一般利用字典所定義的所有用語可不用過度解釋。 All of the technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention pertains, unless otherwise defined. It is apparent that the use of any and all examples, or exemplary terms used herein, are merely intended to illustrate the invention in more detail, and are not to be construed as limiting the scope of the invention. In addition, in addition to the definition In addition, all terms defined by the dictionary are generally not to be over-interpreted.

將參考本發明的較佳實施例所繪示的透視圖、剖面圖、及/或平面圖來描述本發明。因此，可根據製造技術及/或容許度來修改示例圖的外觀。也就是說，不意圖將發明的實施例用以限制本發明的範圍，而是涵括由於製程的變化所造成的所有變更及修改。因此，圖中所繪示的區域以示意性的方式繪示，此區域的形狀以圖式方式簡單地呈現且不成為限制。 The invention will be described with reference to a perspective, cross-sectional, and/or plan view of a preferred embodiment of the invention. Thus, the appearance of the example figures can be modified in accordance with manufacturing techniques and/or tolerances. That is, the embodiments of the invention are not intended to limit the scope of the invention, but all changes and modifications due to variations in the process are included. Therefore, the regions illustrated in the figures are illustrated in a schematic manner, and the shapes of the regions are simply presented in a schematic manner and are not limiting.

進而，此處所用的「圓錐形」或「倒圓錐形」描述與諸如非晶化區域以及由非晶化區域形成的金屬矽化物區域有關的一般形狀。然而，應當理解的是，「圓錐形」不限於明確的圓錐形的數學或幾何定義，而是常用以形容預非晶化佈植區域及金屬矽化物區域的整體形狀，以致實際形成的結構及區域可不必符合精確的圓錐形的數學或幾何定義。此外，應當理解的是，被形容為圓錐形的該區域(諸如升高的源極/汲極區的非晶化區域或由其所形成的金屬矽化物)可具有形成此區域的區域的表面遠離的下輪廓，導致下輪廓具有曲面剖面。 Further, "conical" or "inverted conical" as used herein describes a general shape associated with, for example, an amorphized region and a metal halide region formed by the amorphized region. However, it should be understood that the "conical shape" is not limited to the mathematical or geometric definition of a clear conical shape, but is generally used to describe the overall shape of the pre-amorphized implanted region and the metal telluride region, so that the actually formed structure and The area may not necessarily conform to a mathematical or geometric definition of a precise conical shape. Furthermore, it should be understood that this region, which is described as being conical, such as an amorphized region of the elevated source/drain region or a metal halide formed therefrom, may have a surface that forms the region of this region. A far lower profile, resulting in a lower profile with a curved profile.

圖1為根據本發明實施例的半導體元件1的剖面圖。圖2A及圖2B為圖1所示的金屬矽化物151的透視圖及剖面圖。參考圖1，半導體元件1可包括基板100、閘極116、升高的源極/汲極117、第一層間絕緣膜121、第二層間絕緣膜122、金屬矽化物151、以及金屬接觸窗160。 1 is a cross-sectional view of a semiconductor device 1 in accordance with an embodiment of the present invention. 2A and 2B are a perspective view and a cross-sectional view of the metal telluride 151 shown in Fig. 1. Referring to FIG. 1, the semiconductor element 1 may include a substrate 100, a gate 116, a raised source/drain 117, a first interlayer insulating film 121, a second interlayer insulating film 122, a metal germanide 151, and a metal contact window. 160.

基板100可為矽基板、砷化鎵基板、矽鍺基板、陶瓷基板、石英基板或用於顯示器的玻璃基板，或可為矽覆絕緣層(Semiconductor on insulator,SOI)基板。以下敘述使用矽基板為例。 The substrate 100 may be a germanium substrate, a gallium arsenide substrate, a germanium substrate, a ceramic substrate, a quartz substrate, or a glass substrate for a display, or may be a semiconductor on insulator (SOI) substrate. The following describes an example using a tantalum substrate.

在基板100上形成閘極116。N通道金屬氧化物半導體(NMOS) 電晶體或P通道金屬氧化物半導體(PMOS)電晶體可包括閘極116。閘極116可具有後形成閘極(gate last)結構或取代閘極(replacement gate)結構。特別的是，第一層間絕緣膜121包括孔隙126，且閘極116位於孔隙126中。 A gate 116 is formed on the substrate 100. N-channel metal oxide semiconductor (NMOS) A transistor or P-channel metal oxide semiconductor (PMOS) transistor can include a gate 116. Gate 116 may have a post-last gate structure or a replacement gate structure. In particular, the first interlayer insulating film 121 includes the holes 126, and the gate 116 is located in the holes 126.

閘極116可包括例如第一金屬層115與第二金屬層110的堆疊。可沿著孔隙126的側壁與底面共形地形成第一金屬層115，且於第一金屬層115上可形成第二金屬層110以填滿孔隙126。第一金屬層115可包含如氮化鈦，且第二金屬層110可包含如鋁。此外，當閘極116有後形成閘極結構時，第一層間絕緣膜121可低於閘極116。 Gate 116 may include, for example, a stack of first metal layer 115 and second metal layer 110. The first metal layer 115 may be conformally formed along the sidewalls of the aperture 126 and the bottom surface, and the second metal layer 110 may be formed on the first metal layer 115 to fill the voids 126. The first metal layer 115 may include, for example, titanium nitride, and the second metal layer 110 may include, for example, aluminum. In addition, the first interlayer insulating film 121 may be lower than the gate 116 when the gate 116 has a gate structure.

可於閘極116之間形成升高的源極/汲極117。升高的源極/汲極117可包括形成於基板100與磊晶層141內的摻雜區101，其中磊晶層141與摻雜區101接觸。磊晶層141可為藉由利用基板100為基底的磊晶方法而成長的膜層。 An elevated source/drain 117 can be formed between the gates 116. The elevated source/drain 117 may include a doped region 101 formed in the substrate 100 and the epitaxial layer 141, wherein the epitaxial layer 141 is in contact with the doped region 101. The epitaxial layer 141 may be a film layer grown by an epitaxial method using the substrate 100 as a substrate.

可於升高的源極/汲極117上形成金屬矽化物151。亦即，升高的源極/汲極117的一部分(尤其是磊晶層141)可包括金屬矽化物151。用於金屬矽化物151的金屬可包括鎳、鈷、鉑、鈦、鎢、鉿、鐿、鋱、鏑、鉺、鈀及其合金的至少一者。接觸窗孔洞161通過第一層間絕緣膜121與第二層間絕緣膜122而露出至少一部分的金屬矽化物151。阻障層165可沿著接觸窗孔洞161的側面及底面共形地形成，且金屬接觸窗160可形成在阻障層165上以填滿接觸窗孔洞161。 A metal telluride 151 can be formed on the elevated source/drain 117. That is, a portion of the elevated source/drain 117 (especially the epitaxial layer 141) may include a metal telluride 151. The metal for the metal telluride 151 may include at least one of nickel, cobalt, platinum, titanium, tungsten, rhenium, ruthenium, osmium, iridium, iridium, palladium, and alloys thereof. The contact window hole 161 exposes at least a part of the metal telluride 151 through the first interlayer insulating film 121 and the second interlayer insulating film 122. The barrier layer 165 may be conformally formed along the side and bottom surfaces of the contact via 161, and a metal contact window 160 may be formed on the barrier layer 165 to fill the contact via 161.

參考圖1、圖2A、及圖2B，升高的源極/汲極117可包括突出部141a，其比基板100的表面更突出，並覆蓋金屬矽化物151的兩側。如圖所示，突出部141a可隨著與基板100表面的距離增加而變窄。此外，突出 部141a可覆蓋多於金屬矽化物151的垂直長度(即高度)的一半。圖1中，突出部141a覆蓋金屬矽化物151的整個側表面158。然而，本發明不限於此。 Referring to FIGS. 1, 2A, and 2B, the elevated source/drain 117 may include a protrusion 141a that protrudes more than the surface of the substrate 100 and covers both sides of the metal telluride 151. As shown, the protrusion 141a may become narrower as the distance from the surface of the substrate 100 increases. In addition, highlight The portion 141a may cover more than half of the vertical length (ie, height) of the metal telluride 151. In FIG. 1, the protrusion 141a covers the entire side surface 158 of the metal halide 151. However, the invention is not limited thereto.

金屬矽化物151可不形成於至少部分的升高的源極/汲極117的表面141b中。亦即參考圖1，升高的源極/汲極117在金屬矽化物151與閘極116之間的區域可具有未矽化的表面。 The metal telluride 151 may not be formed in the surface 141b of at least a portion of the elevated source/drain 117. That is, referring to FIG. 1, the raised source/drain 117 may have an undeuterated surface in the region between the metal telluride 151 and the gate 116.

如圖2A所示，金屬矽化物151可包括頂端區159、側表面158以及上表面156。如圖所示，金屬矽化物151可具有倒圓錐形。因此，頂端區159可朝向下(朝向基板100)，且上表面156可朝向上(遠離基板100)。此外，因為金屬矽化物151從底部到頂部漸漸變寬，側表面158可以預定角度θ傾斜。預定角度θ可約為30°至約70°，但不限於此。更具體地，預定角度θ可約為40°至約60°，但不限於此。金屬矽化物151的頂端區159亦可位於比基板100的表面更高處。在一些實施例中，頂端區159可高於閘極氧化層120。在一些實施例中，頂端區159位於閘極氧化層120之上約15 nm或以下。 As shown in FIG. 2A, the metal telluride 151 can include a tip region 159, a side surface 158, and an upper surface 156. As shown, the metal telluride 151 can have an inverted conical shape. Thus, the tip region 159 can face downward (toward the substrate 100) and the upper surface 156 can face upward (away from the substrate 100). Further, since the metal telluride 151 is gradually widened from the bottom to the top, the side surface 158 may be inclined at a predetermined angle θ. The predetermined angle θ may be about 30° to about 70°, but is not limited thereto. More specifically, the predetermined angle θ may be about 40° to about 60°, but is not limited thereto. The top end region 159 of the metal telluride 151 may also be located higher than the surface of the substrate 100. In some embodiments, the tip region 159 can be higher than the gate oxide layer 120. In some embodiments, the tip region 159 is located about 15 nm or less above the gate oxide layer 120.

如圖2A與圖2B進一步所示，金屬矽化物151的剖面可定義與上表面156遠離的下輪廓152。而且如圖2B所示，圖2A中的金屬矽化物151強調金屬矽化物151的下輪廓152具有曲面剖面，且更表現曲面剖面的中心部分可為曲面。 As further shown in FIGS. 2A and 2B, the cross section of the metal telluride 151 can define a lower profile 152 that is remote from the upper surface 156. Moreover, as shown in FIG. 2B, the metal telluride 151 of FIG. 2A emphasizes that the lower profile 152 of the metal telluride 151 has a curved cross section, and the central portion of the curved surface profile may be a curved surface.

如圖1進一步所示，在升高的源極/汲極117內，金屬矽化物的下輪廓位於高於與直接鄰接的閘極116連接的通道區的高度以上。在本發明的一些實施例中，金屬矽化物的下輪廓152位於高於包含於直接鄰接的閘 極116中的閘極氧化層120的高度以上。在本發明的其他實施例中，在升高的源極/汲極區117內的金屬矽化物的下輪廓152的深度比升高的源極/汲極區117的全部厚度的一半大。在本發明的其他實施例中，金屬矽化物的下輪廓152比包含於直接鄰接的閘極116中的閘極氧化層高出約15 nm或以下。 As further shown in FIG. 1, within the elevated source/drain 117, the lower profile of the metal telluride is above the height of the channel region that is connected to the directly adjacent gate 116. In some embodiments of the invention, the lower profile 152 of the metal telluride is located above the gates that are directly adjacent The height of the gate oxide layer 120 in the pole 116 is greater than or equal to. In other embodiments of the invention, the lower profile 152 of the metal telluride in the elevated source/drain region 117 is greater than half the full thickness of the raised source/drain region 117. In other embodiments of the invention, the lower profile 152 of the metal telluride is about 15 nm or less above the gate oxide layer included in the directly adjacent gate 116.

使用參考圖11至圖16所述的製程可形成金屬矽化物151與升高的源極/汲極117。應當理解的是，至少部分的升高的源極/汲極117可為非晶化的，且非晶化的升高的源極/汲極117可轉換成金屬矽化物151。經由此些處理，金屬矽化物151可呈現倒圓錐形的大致形狀(以提供具有曲面剖面的下輪廓)，且金屬矽化物151的側表面158可以預定角度θ傾斜。 The metal telluride 151 and the elevated source/drain 117 can be formed using the process described with reference to FIGS. 11-16. It should be understood that at least a portion of the elevated source/drain 117 may be amorphized and the amorphized elevated source/drain 117 may be converted to a metal telluride 151. Through such processing, the metal telluride 151 may assume an inverted conical shape (to provide a lower profile having a curved cross section), and the side surface 158 of the metal telluride 151 may be inclined at a predetermined angle θ.

可藉由PAI來提供非晶化處理。具體來說，如圖17所示，非晶化處理可為佈值矽、鍺、氙、及碳之至少一者的處理。因此，金屬矽化物151可包含矽、鍺、氙、及碳之至少一者。例如，半導體元件1可為NMOS電晶體，磊晶層141可為矽，而氙可用於非晶化處理。在此情形下，金屬矽化物151可包含矽與氙。在其他實例中，半導體元件1可為PMOS電晶體，磊晶層141可為矽鍺，而碳可用於非晶化處理。在此情形下，金屬矽化物151可包含矽、鍺、及碳。 Amorphization can be provided by PAI. Specifically, as shown in FIG. 17, the amorphization treatment may be a treatment of at least one of cloth values 锗, 锗, 氙, and carbon. Thus, the metal telluride 151 can comprise at least one of ruthenium, osmium, iridium, and carbon. For example, the semiconductor element 1 may be an NMOS transistor, the epitaxial layer 141 may be germanium, and germanium may be used for amorphization. In this case, the metal telluride 151 may contain ruthenium and osmium. In other examples, the semiconductor component 1 can be a PMOS transistor, the epitaxial layer 141 can be germanium, and carbon can be used for amorphization. In this case, the metal telluride 151 may contain ruthenium, osmium, and carbon.

在本發明的一些實施例中，半導體元件1可減小升高的源極/汲極117與金屬矽化物151之間的界面電阻。原因在於，金屬矽化物151的倒圓錐形形狀可在金屬矽化物151與升高的源極/汲極117之間提供寬廣的接觸面積。例如，當倒圓錐形的金屬矽化物151與一般平的(柱狀)金屬矽化物比較時，可看出由於金屬矽化物151的下輪廓具有曲面剖面，倒圓錐形 的金屬矽化物151與升高的源極/汲極117之間的接觸面積比平面的金屬矽化物與升高的源極/汲極之間的接觸面積更寬。而且，金屬矽化物151的倒圓錐形形狀可促進電流流動。 In some embodiments of the invention, the semiconductor component 1 can reduce the interfacial resistance between the elevated source/drain 117 and the metal telluride 151. The reason is that the inverted conical shape of the metal telluride 151 can provide a wide contact area between the metal telluride 151 and the raised source/drain 117. For example, when the inverted conical metal telluride 151 is compared with a generally flat (columnar) metal telluride, it can be seen that since the lower profile of the metal telluride 151 has a curved cross section, the inverted conical shape The contact area between the metal telluride 151 and the raised source/drain 117 is wider than the contact area between the planar metal halide and the raised source/drain. Moreover, the inverted conical shape of the metal telluride 151 promotes current flow.

圖3為本發明的一些實施例的半導體元件的剖面圖。圖4A與圖4B分別為圖2所示的金屬矽化物151的透視圖與剖面示意圖。參考圖3、圖4A、及圖4B，在本發明的一些實施例中，金屬矽化物151可具有倒圓錐形形狀，其包括從倒圓錐形形狀的上表面156向頂端區159凹陷的上凹部151a。如剖面所見，金屬矽化物151的下輪廓的形狀可呈現曲面。 3 is a cross-sectional view of a semiconductor device in accordance with some embodiments of the present invention. 4A and 4B are a perspective view and a cross-sectional view, respectively, of the metal telluride 151 shown in Fig. 2. Referring to FIGS. 3, 4A, and 4B, in some embodiments of the present invention, the metal telluride 151 may have an inverted conical shape including an upper recess recessed from the upper surface 156 of the inverted conical shape toward the top end region 159. 151a. As seen in the cross section, the shape of the lower profile of the metal telluride 151 can assume a curved surface.

從上凹部151a的底部至頂端區159的垂直長度L1可比從上凹部151a的側壁至側表面158的水平長度L2更大。此處，垂直長度L1及水平長度L2之每一者皆為到上凹部151a的邊界的距離。因為金屬矽化物151在垂直方向上延伸，因此從上凹部151a的底部至頂端區159的垂直長度L1可比水平長度L2長。如圖4B所示，金屬矽化物151的頂端區159的中心部分可具有曲面的輪廓。 The vertical length L1 from the bottom of the upper recess 151a to the tip end region 159 may be larger than the horizontal length L2 from the side wall of the upper recess 151a to the side surface 158. Here, each of the vertical length L1 and the horizontal length L2 is a distance to the boundary of the upper concave portion 151a. Since the metal telluride 151 extends in the vertical direction, the vertical length L1 from the bottom of the upper concave portion 151a to the tip end region 159 may be longer than the horizontal length L2. As shown in FIG. 4B, the central portion of the tip end region 159 of the metal telluride 151 may have a curved contour.

半導體元件2可為PMOS電晶體。升高的源極/汲極102可包含矽鍺。可在形成於基板100中的溝渠中形成矽鍺層142。矽鍺層142可為西格瑪(sigma，Σ)狀。矽鍺層142會對PMOS電晶體造成壓縮壓力(compressive stress)，從而增加PMOS電晶體的載子(電洞)的移動率(mobility)。藉由磊晶方法可形成矽鍺層142，以提供含有矽鍺的磊晶層。 The semiconductor component 2 can be a PMOS transistor. The elevated source/drain 102 can comprise germanium. The ruthenium layer 142 may be formed in a trench formed in the substrate 100. The ruthenium layer 142 may be in the form of a sigma. The germanium layer 142 causes compressive stress on the PMOS transistor, thereby increasing the mobility of carriers (holes) of the PMOS transistor. The germanium layer 142 can be formed by an epitaxial method to provide an epitaxial layer containing germanium.

當氙與碳之至少一者用於非晶化處理時，金屬矽化物152可不僅包含矽與鍺，亦包含氙與碳之至少一者。在金屬矽化物151上形成阻障層165，且在阻障層165上形成金屬接觸窗160。金屬矽化物151可包圍部分 的阻障層165。因為金屬矽化物151包括上凹部151a，因此在上凹部151a中可形成阻障層165。 When at least one of niobium and carbon is used for the amorphization treatment, the metal telluride 152 may include not only tantalum and niobium but also at least one of niobium and carbon. A barrier layer 165 is formed on the metal telluride 151, and a metal contact window 160 is formed on the barrier layer 165. Metal telluride 151 can surround part Barrier layer 165. Since the metal telluride 151 includes the upper concave portion 151a, the barrier layer 165 can be formed in the upper concave portion 151a.

如圖4A與圖4B所示，金屬矽化物151可具有倒圓錐形形狀，其包括從倒圓錐形形狀的上表面156向頂端區159凹陷的上凹部151a。如剖面所見，金屬矽化物151的下輪廓的形狀可為曲面。 As shown in FIGS. 4A and 4B, the metal telluride 151 may have an inverted conical shape including an upper concave portion 151a recessed from the upper surface 156 of the inverted conical shape toward the tip end region 159. As seen in the cross section, the shape of the lower contour of the metal telluride 151 may be a curved surface.

圖5為本發明的一些實施例的半導體元件3的剖面示意圖。圖6A與圖6B分別為圖5所示的金屬矽化物151的透視圖與剖面示意圖。 Figure 5 is a schematic cross-sectional view of a semiconductor device 3 in accordance with some embodiments of the present invention. 6A and 6B are a perspective view and a cross-sectional view, respectively, of the metal telluride 151 shown in Fig. 5.

參考圖5、圖6A、及圖6B，金屬矽化物151可具有倒圓錐形形狀151a。尤其，金屬矽化物151可包括從倒圓錐形形狀151a的水平面156向上突出的凸面狀頂部151b。如圖所示，凸面狀頂部151b可比水平面156處的寬度更窄。凸面狀頂部151b可從底部至頂部漸漸變窄。 Referring to FIGS. 5, 6A, and 6B, the metal telluride 151 may have an inverted conical shape 151a. In particular, the metal telluride 151 may include a convex top portion 151b that protrudes upward from a horizontal plane 156 of the inverted conical shape 151a. As shown, the convex top 151b can be narrower than the width at the horizontal plane 156. The convex top portion 151b can be tapered from the bottom to the top.

升高的源極/汲極103可包含形成於基板100中的溝渠中的碳化矽層143。碳化矽層143會對NMOS電晶體施加拉伸應力(tensile stress)，從而增加NMOS電晶體的載子(電子)的移動率。藉由磊晶方法可形成碳化矽層143。當鍺與氙之至少一者用於非晶化處理時，金屬矽化物151不僅包含矽與碳，亦包含鍺與氙之至少一者。 The elevated source/drain 103 may include a tantalum carbide layer 143 formed in a trench in the substrate 100. The tantalum carbide layer 143 applies tensile stress to the NMOS transistor, thereby increasing the mobility of carriers (electrons) of the NMOS transistor. The tantalum carbide layer 143 can be formed by an epitaxial method. When at least one of tantalum and niobium is used for the amorphization treatment, the metal telluride 151 contains not only tantalum and carbon but also at least one of tantalum and niobium.

如圖6A與圖6B所示，金屬矽化物151可具有倒圓錐形形狀151a，其包括從倒圓錐形形狀151a的水平面156向上突出的的凸面狀頂部151b。如剖面所見，金屬矽化物151的下輪廓的形狀可為曲面。 As shown in FIGS. 6A and 6B, the metal telluride 151 may have an inverted conical shape 151a including a convex top portion 151b that protrudes upward from a horizontal plane 156 of the inverted conical shape 151a. As seen in the cross section, the shape of the lower contour of the metal telluride 151 may be a curved surface.

圖7為本發明的一些實施例的半導體元件4的剖面示意圖。在圖7中，繪示同時形成NMOS電晶體與PMOS電晶體的情形。參考圖7，在基板100中定義第一區域I與第二區域II。 Figure 7 is a cross-sectional view of a semiconductor device 4 in accordance with some embodiments of the present invention. In FIG. 7, a case where an NMOS transistor and a PMOS transistor are simultaneously formed is illustrated. Referring to FIG. 7, a first region I and a second region II are defined in the substrate 100.

可在第一區域I內形成PMOS電晶體。PMOS電晶體可包括第一閘極111、形成在第一閘極111兩側的第一升高的源極/汲極102、以及形成在第一升高的源極/汲極102上的第一金屬矽化物151，且第一金屬矽化物151具有倒圓錐形形狀。 A PMOS transistor can be formed in the first region I. The PMOS transistor may include a first gate 111, a first raised source/drain 102 formed on both sides of the first gate 111, and a first formed on the first raised source/drain 102 A metal telluride 151, and the first metal telluride 151 has an inverted conical shape.

可在第二區域II內形成NMOS電晶體。NMOS電晶體包括第二閘極211、形成在第二閘極211兩側的第二升高的源極/汲極201、以及形成在第二升高的源極/汲極201上的第二金屬矽化物251，且第二金屬矽化物251具有倒圓錐形形狀。第一金屬矽化物151與第二金屬矽化物251可含有相同的材料。此處，所述相同的材料可包括鍺、氙、及碳之至少一者。 An NMOS transistor can be formed in the second region II. The NMOS transistor includes a second gate 211, a second elevated source/drain 201 formed on both sides of the second gate 211, and a second formed on the second elevated source/drain 201 The metal halide 251, and the second metal halide 251 has an inverted conical shape. The first metal halide 151 and the second metal halide 251 may contain the same material. Here, the same material may include at least one of ruthenium, osmium, and carbon.

例如，第一升高的源極/汲極102可含有矽鍺，且第二升高的源極/汲極201可含有矽。在此情形下，若鍺用於非晶化處理，則不僅在第一金屬矽化物151中可發現鍺，亦可在第二金屬矽化物251中發現鍺。或者，若氙用於非晶化處理，則第一金屬矽化物151與第二金屬矽化物251可含有氙。 For example, the first elevated source/drain 102 can contain germanium and the second elevated source/drain 201 can contain germanium. In this case, if ruthenium is used for the amorphization treatment, not only ruthenium may be found in the first metal ruthenium 151, but also ruthenium may be found in the second metal ruthenium 251. Alternatively, if the ruthenium is used for the amorphization treatment, the first metal ruthenide 151 and the second metal ruthenium 251 may contain ruthenium.

如以上所述，第一金屬矽化物151在倒圓錐形形狀的上表面進一步包括凹向頂端區的上凹部。此外，第二金屬矽化物251可進一步包括從倒圓錐形形狀的水平面向上突出的凸面狀頂部，且凸面狀頂部可比底面更窄。凸面狀頂部可從底部至頂部漸漸變窄。 As described above, the first metal telluride 151 further includes an upper concave portion of the concave tip end region on the upper surface of the inverted conical shape. Further, the second metal halide 251 may further include a convex top portion that protrudes upward from a horizontal surface of the inverted conical shape, and the convex top portion may be narrower than the bottom surface. The convex top can be tapered from the bottom to the top.

第一金屬矽化物151的側表面可具有比第二金屬矽化物251的側表面的角度θ2更大的角度θ1。亦即，PMOS電晶體的第一金屬矽化物151的側表面比NMOS電晶體的第二金屬矽化物251的側表面更陡。 The side surface of the first metal telluride 151 may have an angle θ1 larger than the angle θ2 of the side surface of the second metal halide 251. That is, the side surface of the first metal telluride 151 of the PMOS transistor is steeper than the side surface of the second metal germanide 251 of the NMOS transistor.

如以上所述，第一升高的源極/汲極102可包括突出部，其比基板 100的表面更突出，並覆蓋第一金屬矽化物151的兩側。突出部可隨著與基板100的表面的距離增加而變窄。第一金屬矽化物151可不形成於至少部分的第一升高的源極/汲極102的表面中。第一金屬矽化物152的倒圓錐形形狀的頂端區比第一閘極111的通道區更高。 As described above, the first elevated source/drain 102 can include a protrusion that is larger than the substrate The surface of 100 is more prominent and covers both sides of the first metal halide 151. The protrusion may become narrower as the distance from the surface of the substrate 100 increases. The first metal telluride 151 may not be formed in at least a portion of the surface of the first elevated source/drain 102. The tip region of the inverted metal shape of the first metal telluride 152 is higher than the channel region of the first gate 111.

第二金屬矽化物251的倒圓錐形形狀的頂端區亦可比第二閘極211的通道區更高，但不限於此。基於製程，第二金屬矽化物251的頂端區可與通道區約為相同的高度或更低。 The tip end region of the inverted metal shape of the second metal halide 251 may also be higher than the channel region of the second gate 211, but is not limited thereto. Based on the process, the top end region of the second metal halide 251 can be about the same height or lower than the channel region.

進一步將包括第一孔隙126與第二孔隙226的第一層間絕緣膜121供應至基板100上。在第一孔隙126中形成第一閘極111，且在第二孔隙226中形成第二閘極211。此外，第一閘極111包括沿著第一孔隙126的側壁與底面共形地形成的第一金屬層115，以及形成於第一孔隙126中的第一金屬層115上的第二金屬層110，以填滿第一孔隙126。第二閘極211包括沿著第二孔隙226的側壁與底面共形地形成的第三金屬層215，以及形成於第二孔隙226中的第三金屬層215上的第四金屬層210，以填滿第二孔隙226。如圖所示，第一層間絕緣膜121可低於第一閘極111與第二閘極211。可在第二區域II中形成圖5、圖6A、及圖6B所示的NMOS電晶體。亦即，可形成具有包括碳化矽磊晶層143的升高的源極/汲極103的NMOS電晶體。 The first interlayer insulating film 121 including the first and second pores 126 and 226 is further supplied onto the substrate 100. A first gate 111 is formed in the first aperture 126 and a second gate 211 is formed in the second aperture 226. In addition, the first gate 111 includes a first metal layer 115 conformally formed along sidewalls and a bottom surface of the first aperture 126, and a second metal layer 110 formed on the first metal layer 115 in the first aperture 126. To fill the first aperture 126. The second gate 211 includes a third metal layer 215 formed conformally along the sidewall and the bottom surface of the second aperture 226, and a fourth metal layer 210 formed on the third metal layer 215 in the second aperture 226 to The second aperture 226 is filled. As shown, the first interlayer insulating film 121 may be lower than the first gate 111 and the second gate 211. The NMOS transistor shown in FIGS. 5, 6A, and 6B can be formed in the second region II. That is, an NMOS transistor having the elevated source/drain 103 including the tantalum carbide epitaxial layer 143 can be formed.

圖8為本發明的一些實施例的半導體元件5的剖面示意圖。參考圖8，基板100包括第一區域I、第二區域II、以及第三區域III。第一區域I與第二區域II可分別為記憶區及邏輯區，且第三區域III可為周圍區。周圍區可包括例如輸入/輸出(I/O)區。第三區域III於構件之間可具有比第一區 域I與第二區域II更低的密度及更寬的間隙。 Figure 8 is a schematic cross-sectional view of a semiconductor device 5 in accordance with some embodiments of the present invention. Referring to FIG. 8, the substrate 100 includes a first region I, a second region II, and a third region III. The first area I and the second area II may be a memory area and a logic area, respectively, and the third area III may be a surrounding area. The surrounding area may include, for example, an input/output (I/O) area. The third region III may have a first region between the members Domain I has a lower density and a wider gap than the second region II.

在第一區域I與第二區域II中分別形成PMOS電晶體與NMOS電晶體。可於第二區域II中形成圖5、圖6A、及圖6B所示的NMOS電晶體。亦即，可形成具有包括碳化矽磊晶層143的升高的源極/汲極103的NMOS電晶體。 A PMOS transistor and an NMOS transistor are formed in the first region I and the second region II, respectively. The NMOS transistor shown in FIGS. 5, 6A, and 6B can be formed in the second region II. That is, an NMOS transistor having the elevated source/drain 103 including the tantalum carbide epitaxial layer 143 can be formed.

可於第三區域III的基板100上形成磊晶層341，且可於磊晶層341上形成具有倒圓錐形形狀的第三金屬矽化物351。第三金屬矽化物351可位於相鄰的第三閘極311之間。第三升高的源極/汲極301可比第一升高的源極/汲極102與第二升高的源極/汲極201相對較寬。此外，第三金屬矽化物351可比第一金屬矽化物151與第二金屬矽化物251相對較寬。 An epitaxial layer 341 may be formed on the substrate 100 of the third region III, and a third metal germanide 351 having an inverted conical shape may be formed on the epitaxial layer 341. The third metal halide 351 may be located between adjacent third gates 311. The third elevated source/drain 301 may be relatively wider than the first elevated source/drain 102 and the second elevated source/drain 201. Further, the third metal telluride 351 may be relatively wider than the first metal telluride 151 and the second metal telluride 251.

圖9與圖10分別為本發明的一些實施例的半導體元件6的電路圖以及佈局圖。根據本發明的實施例的半導體元件1至8可應用於所有使用金屬矽化物的元件。然而，圖9與圖10繪示靜態隨機存取記憶體(SRAM)作為實例。 9 and 10 are respectively a circuit diagram and a layout view of a semiconductor device 6 according to some embodiments of the present invention. The semiconductor elements 1 to 8 according to the embodiments of the present invention are applicable to all elements using metal telluride. However, FIG. 9 and FIG. 10 illustrate a static random access memory (SRAM) as an example.

參考圖9，半導體元件6可包括一對在電源節點Vcc與接地節點Vss之間並聯連接的反相器INV1與反相器INV2，以及分別連接至反相器INV1與反相器INV2的輸出節點的第一傳輸電晶體T1與第二傳輸電晶體T2。第一傳輸電晶體T1與第二傳輸電晶體T2可分別連接至位元線BL與互補位元線/BL。第一傳輸電晶體T1與第二傳輸電晶體T2的閘極可分別連接至字元線WL1與字元線WL2。 Referring to FIG. 9, the semiconductor element 6 may include a pair of inverters INV1 and INV2 connected in parallel between the power supply node Vcc and the ground node Vss, and output nodes connected to the inverter INV1 and the inverter INV2, respectively. The first transmission transistor T1 and the second transmission transistor T2. The first transfer transistor T1 and the second transfer transistor T2 may be connected to the bit line BL and the complementary bit line /BL, respectively. The gates of the first transfer transistor T1 and the second transfer transistor T2 may be connected to the word line WL1 and the word line WL2, respectively.

第一反相器INV1包括串聯連接的第一負載電晶體T5與第一驅動電晶體T3，且第二反相器INV2包括串聯連接的第二負載電晶體T6與第 二驅動電晶體T4。第一負載電晶體T5與第二負載電晶體T6可為PMOS電晶體，且第一驅動電晶體T3與第二驅動電晶體T4可為NMOS電晶體。 The first inverter INV1 includes a first load transistor T5 and a first drive transistor T3 connected in series, and the second inverter INV2 includes a second load transistor T6 and a series connected in series. Two drive transistor T4. The first load transistor T5 and the second load transistor T6 may be PMOS transistors, and the first drive transistor T3 and the second drive transistor T4 may be NMOS transistors.

此外，第一反相器INV1的輸入節點連接至第二反相器INV2的輸出節點(見節點NC2)，且第二反相器INV2的輸入節點連接至第一反相器INV1的輸出節點(見節點NC1)，從而第一反相器INV1與第二反相器INV2可構成一鎖存電路(latch circuit)。 Further, an input node of the first inverter INV1 is connected to an output node of the second inverter INV2 (see node NC2), and an input node of the second inverter INV2 is connected to an output node of the first inverter INV1 ( See node NC1), so that the first inverter INV1 and the second inverter INV2 can constitute a latch circuit.

參考圖9與圖10，元件符號410與412代表PMOS電晶體的主動區，且元件符號414與416代表NMOS電晶體的主動區。元件符號420與422代表第一驅動電晶體T3與第二驅動電晶體T4的閘電極，且元件符號430代表第一傳輸電晶體T1與第二傳輸電晶體T2的閘電極。元件符號440代表電源線(Vcc線)，元件符號450代表接地線(Vss線)，且元件符號460代表位元線BL與互補位元線/BL。此處，元件符號490代表金屬接觸窗。可使用根據參考以上圖1至圖8所描述的實施例半導體元件1至8的金屬矽化物與金屬接觸窗。 Referring to Figures 9 and 10, component symbols 410 and 412 represent active regions of a PMOS transistor, and component symbols 414 and 416 represent active regions of an NMOS transistor. The component symbols 420 and 422 represent the gate electrodes of the first driving transistor T3 and the second driving transistor T4, and the component symbol 430 represents the gate electrodes of the first transmission transistor T1 and the second transmission transistor T2. The component symbol 440 represents a power supply line (Vcc line), the component symbol 450 represents a ground line (Vss line), and the component symbol 460 represents a bit line BL and a complementary bit line /BL. Here, the symbol 490 represents a metal contact window. A metal telluride and metal contact window of the semiconductor elements 1 to 8 according to the embodiments described with reference to FIGS. 1 to 8 above may be used.

圖11至圖16B繪示本發明的一些實施例的半導體元件2的製造方法的剖面示意圖。圖13B至圖15B為圖13A至圖15B的放大剖面示意圖。參考圖11，一對電晶體位於基板100上。在，電晶體各自包括閘極115/110以及位於此對電晶體111a/111b之間的升高的源極/汲極102。第一層間絕緣膜121覆蓋升高的源極/汲極102。形成第二層間絕緣膜122以覆蓋升高的源極/汲極102與第一層間絕緣膜121。 11 to 16B are schematic cross-sectional views showing a method of fabricating the semiconductor device 2 of some embodiments of the present invention. 13B to 15B are enlarged cross-sectional views of Figs. 13A to 15B. Referring to FIG. 11, a pair of transistors are located on the substrate 100. The transistors each include a gate 115/110 and an elevated source/drain 102 between the pair of transistors 111a/111b. The first interlayer insulating film 121 covers the elevated source/drain 102. A second interlayer insulating film 122 is formed to cover the elevated source/drain 102 and the first interlayer insulating film 121.

參考圖12，藉由蝕刻第一層間絕緣膜121與第二層間絕緣膜122來形成接觸窗孔洞(或開口)161a，以露出升高的源極/汲極102的表面。 在本發明的一些實施例中，在第二層間絕緣膜122上形成罩幕圖案，接著進行乾蝕刻而形成接觸窗孔洞161a。 Referring to FIG. 12, a contact hole (or opening) 161a is formed by etching the first interlayer insulating film 121 and the second interlayer insulating film 122 to expose the surface of the raised source/drain 102. In some embodiments of the present invention, a mask pattern is formed on the second interlayer insulating film 122, followed by dry etching to form a contact hole 161a.

參考圖13A與圖13B，進行射頻(RF)蝕刻處理198，以縮小接觸窗孔洞161b的大小。射頻蝕刻處理198可使用例如氬(Ar+)。射頻蝕刻處理198可移除形成於升高的源極/汲極102上的原生氧化膜。此外，射頻蝕刻處理198可縮小接觸窗孔洞161b的底面的臨界尺寸(critical dimension,CD)。此是因為射頻蝕刻處理198會造成由升高的源極/汲極102產生的蝕刻副產物，且於第一層間絕緣膜121與第二層間絕緣膜122的側壁上再沈積第一層間絕緣膜121與第二層間絕緣膜122。因此，接觸窗孔洞161b內的射頻蝕刻可改變接觸窗孔洞161b的底部的形狀，以造成曲面側壁，其於接觸窗孔洞161b的底部朝向露出的升高的源極/汲極區102的表面呈曲面，以促成例如圖13B所示的形狀。 Referring to FIGS. 13A and 13B, a radio frequency (RF) etching process 198 is performed to reduce the size of the contact hole 161b. The RF etching process 198 can use, for example, argon (Ar+). The RF etch process 198 removes the native oxide film formed on the elevated source/drain 102. In addition, the RF etching process 198 can reduce the critical dimension (CD) of the bottom surface of the contact window hole 161b. This is because the RF etching process 198 causes etching by-products generated by the raised source/drain 102, and redeposits the first layer on the sidewalls of the first interlayer insulating film 121 and the second interlayer insulating film 122. The insulating film 121 and the second interlayer insulating film 122. Thus, the RF etching in the contact aperture 161b can change the shape of the bottom of the contact aperture 161b to create a curved sidewall that is oriented toward the exposed raised source/drain region 102 at the bottom of the contact aperture 161b. The curved surface is to promote a shape such as that shown in Fig. 13B.

參考圖14A與圖14B，藉由非晶化處理199對升高的源極/汲極102的至少一部分152a進行非晶化。尤其，可藉由PAI來提供升高的源極/汲極102的至少一部分195的非晶化處理199。非晶化處理199可包括佈植矽、鍺、氙、及碳之至少一者的處理。如圖14B所示的實例，PAI可促進非結晶部分152a的形成，以具有呈曲面的下輪廓。應當理解的是，PAI的下輪廓與直接鄰接的升高的源極/汲極區的表面遠離。 Referring to FIGS. 14A and 14B, at least a portion 152a of the elevated source/drain 102 is amorphized by amorphization process 199. In particular, the amorphization process 199 of the at least a portion 195 of the elevated source/drain 102 can be provided by PAI. The amorphization process 199 can include the treatment of implanting at least one of ruthenium, osmium, iridium, and carbon. As in the example shown in Fig. 14B, the PAI can promote the formation of the amorphous portion 152a to have a lower profile that is curved. It should be understood that the lower profile of the PAI is remote from the surface of the immediately adjacent raised source/drain region.

圖17繪示示例的形成於升高的源極/汲極區中的非晶矽層的厚度對在此處形成的金屬矽化物區域的厚度的關係圖。根據圖17，使用矽或氙比使用碳等雜質更能促進形成較厚的金屬矽化物。 17 is a graph showing the relationship of the thickness of an exemplary amorphous germanium layer formed in an elevated source/drain region to the thickness of a metal germanide region formed therein. According to Fig. 17, the use of ruthenium or osmium promotes the formation of a thicker metal ruthenium than the use of impurities such as carbon.

參考圖15A與圖15B，可進行清除處理。尤其，可臨場(in-situ) 進行清除處理。清除處理可移除形成於升高的源極/汲極102上的原生氧化膜，並調整接觸窗孔洞161的形狀。清除處理可省略。 Referring to Figures 15A and 15B, a clearing process can be performed. In particular, in-situ Perform the removal process. The cleaning process removes the native oxide film formed on the elevated source/drain 102 and adjusts the shape of the contact aperture 161. The clearing process can be omitted.

參考圖16A與圖16B，非晶化的升高的源極/汲極102與金屬矽化後而形成金屬矽化物151。非晶化部分使得金屬矽化物151在矽化處理期間於垂直方向上成長較多(見圖16B)。也就是說，非晶化部分可促進金屬矽化物151的形成，以產生與非晶化部分相同的大致倒圓錐形形狀，使得倒圓錐形形狀的下輪廓可具有曲面剖面。金屬矽化物151從底部至頂部漸漸變寬。亦即，非晶化的升高的源極/汲極102的部份151a使得金屬矽化物151在垂直方向比在水平方向成長更多。 Referring to FIGS. 16A and 16B, the amorphized raised source/drain 102 is deuterated with a metal to form a metal telluride 151. The amorphized portion causes the metal telluride 151 to grow more in the vertical direction during the deuteration treatment (see Fig. 16B). That is, the amorphized portion may promote the formation of the metal telluride 151 to produce the same substantially inverted conical shape as the amorphized portion, such that the lower profile of the inverted conical shape may have a curved cross-section. The metal telluride 151 is gradually widened from the bottom to the top. That is, the portion 151a of the amorphized raised source/drain 102 causes the metal telluride 151 to grow more in the vertical direction than in the horizontal direction.

可於非晶化的升高的源極/汲極102上形成金屬層。例如，金屬層可包含鎳、鈷、鉑、鈦、鎢、鉿、鐿、鋱、鏑、鉺、鈀及其合金之至少一種。金屬層與非晶化的升高的源極/汲極102製成後藉由第一熱處理而反應。例如，可在溫度約200℃至約540℃下進行第一熱處理。此外，第一熱處理可利用快速熱退火(rapid thermal annealing,RTA)。將金屬層的未反應部分移除。繼而，在高於第一熱處理的溫度下進行第二熱處理。例如，可在溫度約540℃至約800℃下進行第二熱處理。第二熱處理亦可使用RTA。 A metal layer can be formed on the amorphized raised source/drain 102. For example, the metal layer may comprise at least one of nickel, cobalt, platinum, titanium, tungsten, rhenium, ruthenium, osmium, iridium, iridium, palladium, and alloys thereof. The metal layer is reacted with the amorphized elevated source/drain 102 after the first heat treatment. For example, the first heat treatment can be performed at a temperature of about 200 ° C to about 540 ° C. In addition, the first heat treatment may utilize rapid thermal annealing (RTA). The unreacted portion of the metal layer is removed. Then, the second heat treatment is performed at a temperature higher than the first heat treatment. For example, the second heat treatment can be performed at a temperature of about 540 ° C to about 800 ° C. The second heat treatment can also use RTA.

如圖16A與圖16B所示，非晶化層的矽化可促進金屬矽化物的生成而具有下輪廓(與升高的源極/汲極的表面遠離)，其在下輪廓的中心部分呈現曲面。因此，在本發明的一些實施例中，改變接觸窗孔洞的底部的形狀可促進非結晶層的形成(對於PAI的反應)，該非結晶層具有呈曲面的下輪廓，可促進金屬矽化物的形成，尤其在金屬矽化物的中心部分亦具有曲面的剖面輪廓。 As shown in FIGS. 16A and 16B, the deuteration of the amorphized layer promotes the formation of metal telluride with a lower profile (away from the surface of the elevated source/drain), which presents a curved surface at the central portion of the lower profile. Thus, in some embodiments of the invention, changing the shape of the bottom of the contact opening can promote the formation of an amorphous layer (reaction to PAI) having a curved lower profile that promotes the formation of metal telluride In particular, the central portion of the metal telluride also has a curved profile.

回去參考圖3，沿著接觸窗孔洞161的側面及底面共形地形成阻障層165。再者，在阻障層165上形成金屬接觸窗160，以填滿接觸窗孔洞161。 Referring back to FIG. 3, a barrier layer 165 is conformally formed along the side and bottom surfaces of the contact via 161. Further, a metal contact window 160 is formed on the barrier layer 165 to fill the contact hole 161.

當已參考示範的實施例描述本發明概念後，所屬領域的通常知識者將理解在不違背本發明概念的精神與範圍下，可做各種改變與修改。因此，應當理解僅說明上述實施例而不限於此。從而，本發明概念的範圍由以下申請專利範圍及其等同者的最廣容許的解釋來定義，且不應限制或受限於前文所述。 Various changes and modifications can be made without departing from the spirit and scope of the inventions. Therefore, it should be understood that only the above embodiments are explained and are not limited thereto. Accordingly, the scope of the present invention is defined by the scope of the appended claims and the

1‧‧‧半導體元件 1‧‧‧Semiconductor components

100‧‧‧基板 100‧‧‧Substrate

101‧‧‧摻雜區 101‧‧‧Doped area

110‧‧‧第二金屬層 110‧‧‧Second metal layer

115‧‧‧第一金屬層 115‧‧‧First metal layer

116‧‧‧閘極 116‧‧‧ gate

117‧‧‧升高的源極/汲極 117‧‧‧ Elevated source/bungee

120‧‧‧閘極氧化層 120‧‧‧ gate oxide layer

121‧‧‧第一層間絕緣膜 121‧‧‧First interlayer insulating film

122‧‧‧第二層間絕緣膜 122‧‧‧Second interlayer insulating film

126‧‧‧孔隙 126‧‧‧ pores

141‧‧‧磊晶層 141‧‧‧Elevation layer

141a‧‧‧突出部 141a‧‧‧Protruding

141b‧‧‧表面 141b‧‧‧ surface

160‧‧‧金屬接觸窗 160‧‧‧Metal contact window

161‧‧‧接觸窗孔洞 161‧‧‧Contact window hole

165‧‧‧阻障層 165‧‧‧Barrier layer

Claims (30)

一種半導體元件的形成方法，包括：形成開口，所述開口露出升高的源極/汲極區的表面；縮小所述開口的大小；通過所述開口施行預非晶化佈植至所述升高的源極/汲極區內，以形成所述升高的源極/汲極區的非晶化部分；以及由金屬與所述非晶化部分形成金屬矽化物。 A method of forming a semiconductor device, comprising: forming an opening exposing a surface of an elevated source/drain region; reducing a size of the opening; performing pre-amorphization implantation through the opening to the liter a high source/drain region to form an amorphized portion of the elevated source/drain region; and a metal telluride formed from a metal and the amorphized portion. 如申請專利範圍第1項所述之半導體元件的形成方法，其中施行所述預非晶化佈植包括形成包括與所述表面遠離的預非晶化佈植的下輪廓的所述非晶化部分，其中所述預非晶化佈植的下輪廓具有曲面剖面。 The method of forming a semiconductor device according to claim 1, wherein the performing the pre-amorphization implant comprises forming the amorphization including a lower profile of a pre-amorphized implant away from the surface Part, wherein the lower profile of the pre-amorphized implant has a curved profile. 如申請專利範圍第2項所述之半導體元件的形成方法，其中所述曲面剖面的中心部分呈曲面。 The method of forming a semiconductor device according to claim 2, wherein the central portion of the curved surface section has a curved surface. 如申請專利範圍第1項所述之半導體元件的形成方法，其中形成所述金屬矽化物包括形成包括與所述表面遠離的矽化物的下輪廓的所述金屬矽化物，其中所述矽化物的下輪廓具有曲面剖面。 The method of forming a semiconductor device according to claim 1, wherein the forming the metal halide includes forming the metal halide including a lower profile of a telluride away from the surface, wherein the germanide The lower profile has a curved profile. 如申請專利範圍第4項所述之半導體元件的形成方法，其中所述曲面剖面的中心部分呈曲面。 The method of forming a semiconductor device according to claim 4, wherein a central portion of the curved surface section has a curved surface. 如申請專利範圍第4項所述之半導體元件的形成方法，其中形成所述金屬矽化物包括在與閘極氧化層相同或更高的高度形 成所述矽化物的下輪廓，其中所述閘極氧化層包含於直接與所述升高的源極/汲極區鄰接的閘極結構中。 The method of forming a semiconductor device according to claim 4, wherein the forming of the metal halide includes a height of the same or higher than that of the gate oxide layer. Forming a lower profile of the telluride, wherein the gate oxide layer is included in a gate structure directly adjacent the elevated source/drain region. 如申請專利範圍第6項所述之半導體元件的形成方法，其中所述高度為15 nm或以下。 The method of forming a semiconductor device according to claim 6, wherein the height is 15 nm or less. 如申請專利範圍第4項所述之半導體元件的形成方法，其中形成所述金屬矽化物包括在高於通道區的高度形成所述矽化物的下輪廓，其中所述通道區與至少一個直接鄰接的閘極結構連接。 The method of forming a semiconductor device according to claim 4, wherein the forming the metal halide comprises forming a lower profile of the germanide at a height higher than a channel region, wherein the channel region is directly adjacent to at least one The gate structure is connected. 申請專利範圍第4項所述之半導體元件的形成方法，其中在所述升高的源極/汲極區中的所述矽化物的下輪廓的深度比所述升高的源極/汲極區的全部厚度的一半更大。 The method of forming a semiconductor device according to claim 4, wherein a depth of a lower profile of the germanide in the elevated source/drain region is greater than the raised source/drain Half of the total thickness of the zone is greater. 如申請專利範圍第1項所述之半導體元件的形成方法，其中縮小所述開口的大小包括縮小所述開口的底部的開口大小。 The method of forming a semiconductor device according to claim 1, wherein reducing the size of the opening comprises reducing an opening size of a bottom of the opening. 如申請專利範圍第1項所述之半導體元件的形成方法，其中縮小所述開口的大小包括改變所述開口的底部的形狀以造成曲面側壁，所述曲面側壁於所述底部朝向所述升高的源極/汲極區的所述表面呈曲面。 The method of forming a semiconductor device according to claim 1, wherein reducing the size of the opening comprises changing a shape of a bottom of the opening to cause a curved sidewall, the curved sidewall being elevated toward the bottom toward the bottom The surface of the source/drain region is curved. 如申請專利範圍第1項所述之半導體元件的形成方法，其中縮小所述開口的大小包括蝕刻所述升高的源極/汲極區的所述表面，使所述表面的高度凹陷。 The method of forming a semiconductor device according to claim 1, wherein reducing the size of the opening comprises etching the surface of the elevated source/drain region to recess the height of the surface. 如申請專利範圍第1項所述之半導體元件的形成方法，其中縮小所述開口的大小包括對所述升高的源極/汲極區與所述開口的側壁進行射頻蝕刻。 The method of forming a semiconductor device according to claim 1, wherein reducing the size of the opening comprises radio-etching the elevated source/drain regions and sidewalls of the openings. 如申請專利範圍第13項所述之半導體元件的形成方法，其中施行所述預非晶化佈植包括形成包括與所述表面遠離的預非晶化佈植的下輪廓的所述非晶化部分，其中所述預非晶化佈植的下輪廓具有曲面剖面。 The method of forming a semiconductor device according to claim 13, wherein the performing the pre-amorphization implant comprises forming the amorphization including a lower profile of a pre-amorphized implant away from the surface Part, wherein the lower profile of the pre-amorphized implant has a curved profile. 如申請專利範圍第4項所述之半導體元件的形成方法，其中所述金屬矽化物包括具有底部與側壁的上凹部，其中所述底部與所述矽化物的下輪廓的底部分開的距離比所述上凹部的側壁與所述矽化物的下輪廓的側壁分開的距離更大。 The method of forming a semiconductor device according to claim 4, wherein the metal halide includes an upper recess having a bottom portion and a sidewall, wherein the bottom portion is separated from a bottom portion of the lower contour of the telluride by a distance ratio The side walls of the recess are separated from the side walls of the lower profile of the telluride by a greater distance. 如申請專利範圍第4項所述之半導體元件的形成方法，其中所述金屬矽化物更包括相對於所述矽化物的下輪廓的凸面狀頂部。 The method of forming a semiconductor device according to claim 4, wherein the metal halide further comprises a convex top portion with respect to a lower contour of the germanide. 如申請專利範圍第2項所述之半導體元件的形成方法，其中施行所述預非晶化佈植包括將氙佈植至所述升高的源極/汲極區內，以形成包括所述預非晶化佈植的下輪廓的所述非晶化部分，所述非晶化部分的總厚度為至少100埃。 The method of forming a semiconductor device according to claim 2, wherein the performing the pre-amorphization implant comprises implanting a germanium into the elevated source/drain region to form the The amorphized portion of the lower profile of the pre-amorphized implant, the amorphized portion having a total thickness of at least 100 angstroms. 如申請專利範圍第2項所述之半導體元件的形成方法，其中施行所述預非晶化佈植包括將矽佈植至所述升高的源極/汲極區內，以形成包括所述預非晶化佈植的下輪廓的所述非晶化部分，所述非晶化部分的總厚度為至少100埃。 The method of forming a semiconductor device according to claim 2, wherein the performing the pre-amorphization implant comprises implanting a germanium into the elevated source/drain region to form the The amorphized portion of the lower profile of the pre-amorphized implant, the amorphized portion having a total thickness of at least 100 angstroms. 一種半導體元件的形成方法，包括：形成開口，所述開口露出升高的源極/汲極區的表面；通過所述開口施行預非晶化佈植至所述升高的源極/汲極區 內，以形成所述升高的源極/汲極區的非晶化部分；以及由金屬與所述非晶化部分形成金屬矽化物。 A method of forming a semiconductor device, comprising: forming an opening that exposes a surface of an elevated source/drain region; performing pre-amorphization implantation through the opening to the elevated source/drain Area Internally forming an amorphized portion of the elevated source/drain region; and forming a metal telluride from the metal and the amorphized portion. 如申請專利範圍第19項所述之半導體元件的形成方法，更包括：在施行所述預非晶化佈植之前，縮小所述開口的大小。 The method of forming a semiconductor device according to claim 19, further comprising: reducing a size of the opening before performing the pre-amorphization implant. 如申請專利範圍第20項所述之半導體元件的形成方法，其中縮小所述開口的大小包括改變所述開口的底部的形狀以造成曲面側壁，所述曲面側壁於所述底部朝向所述升高的源極/汲極區的表面呈曲面。 The method of forming a semiconductor device according to claim 20, wherein reducing the size of the opening comprises changing a shape of a bottom of the opening to cause a curved sidewall, the curved sidewall being elevated toward the bottom toward the bottom The surface of the source/drain region is curved. 如申請專利範圍第21項所述之半導體元件的形成方法，其中縮小所述開口的大小包括對所述升高的源極/汲極區與所述開口的側壁進行射頻蝕刻，於所述開口的所述底部改變所述開口的形狀以造成所述曲面側壁，所述曲面側壁朝向所述升高的源極/汲極區的所述表面處呈曲面。 The method of forming a semiconductor device according to claim 21, wherein reducing the size of the opening comprises radio-etching the elevated source/drain region and a sidewall of the opening, the opening The bottom portion changes the shape of the opening to create the curved side wall, the curved side wall being curved toward the surface of the raised source/drain region. 如申請專利範圍第19項所述之半導體元件的形成方法，其中施行所述預非晶化佈植包括形成包括與所述表面遠離的預非晶化佈植的下輪廓的所述非晶化部分，所述預非晶化佈植的下輪廓具有曲面剖面。 The method of forming a semiconductor device according to claim 19, wherein the performing the pre-amorphization implant comprises forming the amorphization including a lower profile of a pre-amorphized implant away from the surface In part, the lower profile of the pre-amorphized implant has a curved profile. 如申請專利範圍第19項所述之半導體元件的形成方法，其中形成所述金屬矽化物包括形成包括與所述表面遠離的矽化物的下輪廓的所述金屬矽化物，其中所述矽化物的下輪廓具有曲面剖面。 The method of forming a semiconductor device according to claim 19, wherein the forming the metal halide includes forming the metal halide including a lower profile of a telluride away from the surface, wherein the germanide The lower profile has a curved profile. 如申請專利範圍第24項所述之半導體元件的形成方法，其中形成所述金屬矽化物包括在與閘極氧化層相同或更高的高度形成所述矽化物的下輪廓，其中所述閘極氧化層包含於直接與所述升高的源極/汲極區鄰接的閘極結構中。 The method of forming a semiconductor device according to claim 24, wherein the forming the metal halide comprises forming a lower profile of the germanide at a height equal to or higher than a gate oxide layer, wherein the gate The oxide layer is included in a gate structure that is directly adjacent to the elevated source/drain regions. 一種半導體元件，包括：基板，包括PMOS區以及NMOS區；第一接觸窗孔洞，位於絕緣層內，所述第一接觸窗孔洞露出在所述PMOS區內的第一升高的源極/汲極區；第一金屬接觸窗，位於所述第一升高的源極/汲極區上的所述第一接觸窗孔洞內；第一金屬矽化物，位於所述第一升高的源極/汲極區內並與所述第一金屬接觸窗接觸，所述第一金屬矽化物包括與所述第一升高的源極/汲極區的表面遠離的第一矽化物的下輪廓，所述第一矽化物的下輪廓具有曲面剖面，且所述第一金屬矽化物包括相對於所述第一矽化物的下輪廓的平面頂部；第二接觸窗孔洞，位於所述絕緣層內，所述第二接觸窗孔洞露出在所述NMOS區內的第二升高的源極/汲極區；第二金屬接觸窗，位於所述第二升高的源極/汲極區上的所述第二接觸窗孔洞內；以及第二金屬矽化物，位於所述第二升高的源極/汲極區內且與所述第二金屬接觸窗接觸，所述第二金屬矽化物包括與所述第二升高的源極/汲極區的表面遠離的第二矽化物的下輪廓，所述第二矽 化物的下輪廓具有曲面剖面，且所述第二金屬矽化物包括相對於所述第二矽化物的下輪廓的凸面頂部。 A semiconductor device comprising: a substrate including a PMOS region and an NMOS region; a first contact hole in the insulating layer, the first contact hole exposing a first raised source/汲 in the PMOS region a first metal contact window located in the first contact hole in the first elevated source/drain region; a first metal halide located at the first elevated source And contacting the first metal contact window in the drain region, the first metal germanide comprising a lower profile of the first germanide away from the surface of the first elevated source/drain region, The lower contour of the first telluride has a curved cross section, and the first metal halide includes a planar top portion with respect to a lower contour of the first germanide; a second contact window hole is located in the insulating layer, The second contact hole is exposed in a second elevated source/drain region in the NMOS region; a second metal contact window is located on the second elevated source/drain region a second contact window hole; and a second metal halide located at the second elevated source a pole/drain region in contact with the second metal contact window, the second metal halide comprising a lower profile of the second germanide away from a surface of the second elevated source/drain region The second 矽 The lower profile of the compound has a curved profile and the second metal halide includes a convex top with respect to a lower profile of the second vapor. 如申請專利範圍第26項所述之半導體元件，其中所述第一金屬矽化物包括具有底部與側壁的上凹部，其中所述底部接觸所述第一金屬接觸窗，且與所述第一矽化物的下輪廓的底部分開的距離比所述上凹部的側壁與所述第一矽化物的下輪廓的側壁分開的距離更大。 The semiconductor device of claim 26, wherein the first metal halide includes an upper recess having a bottom portion and a sidewall, wherein the bottom portion contacts the first metal contact window, and the first metallization The bottom of the lower contour of the object is separated by a greater distance than the side wall of the upper recess and the side wall of the lower contour of the first telluride. 如申請專利範圍第26項所述之半導體元件，其中所述第一升高的源極/汲極區包括磊晶成長的升高的源極/汲極區。 The semiconductor component of claim 26, wherein the first elevated source/drain region comprises an elevated source/drain region of epitaxial growth. 如申請專利範圍第26項所述之半導體元件，其中所述第一矽化物的下輪廓與所述第二矽化物的下輪廓高於分別與直接鄰接的閘極結構連接的通道區的高度。 The semiconductor component of claim 26, wherein the lower profile of the first germanide and the lower profile of the second germanide are higher than the height of the channel region respectively connected to the directly adjacent gate structure. 如申請專利範圍第26項所述之半導體元件，其中所述PMOS區與所述NMOS區分別包括所述半導體元件的記憶區與LSI區，所述半導體元件更包括：第三接觸窗孔洞，位於所述絕緣層內，所述第三接觸窗孔洞露出在所述基板的周圍區域內的第三升高的源極/汲極區，所述第三升高的源極/汲極區比所述第一升高的源極/汲極區更寬；第三金屬接觸窗，位於所述第三升高的源極/汲極區上的所述第三接觸窗孔洞內；第三金屬矽化物，位於所述第三升高的源極/汲極區內且與所述第三金屬接觸窗接觸，所述第三金屬矽化物包括與所述第三升 高的源極/汲極區的表面遠離的第三矽化物的下輪廓，所述第三矽化物的下輪廓具有曲面剖面，且所述第三金屬矽化物包括相對於所述第三矽化物的下輪廓的平面頂部。 The semiconductor device of claim 26, wherein the PMOS region and the NMOS region respectively comprise a memory region and an LSI region of the semiconductor component, the semiconductor component further comprising: a third contact window hole located at In the insulating layer, the third contact hole is exposed in a third elevated source/drain region in a surrounding region of the substrate, and the third elevated source/drain region is The first elevated source/drain region is wider; a third metal contact window is located in the third contact window hole on the third elevated source/drain region; the third metal is deuterated Located in the third elevated source/drain region and in contact with the third metal contact window, the third metal halide including the third liter a lower source/drain region having a surface away from a lower portion of the third germanide, a lower portion of the third germanide having a curved cross-section, and the third metal telluride comprising a third telluride The lower silhouette of the flat top.
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