TW201401052A - Method for accessing flash memory and associated memory device - Google Patents

Abstract

The present invention provides a method for accessing a flash memory, where a block of the flash memory includes pages whose quantity is (2<SP>N</SP>+M), N and M are positive integers. The method includes: writing a data stream into 1<SP>st</SP>-(2<SP>N</SP>)<SP>th</SP>pages; and backing up data of a portion of the 1<SP>st</SP>-(2<SP>N</SP>)<SP>th</SP> pages into (2<SP>N</SP>+1)<SP>th</SP>-(2<SP>N</SP>+M)<SP>th</SP>pages.

Description

Method of accessing flash memory and related memory device

The present invention relates to a method for accessing flash memory, and more particularly to a method for backing up partial data in a flash memory and related memory devices.

In some flash memory designs, especially Triple-Level Cell (TLC) flash memory, the number of data pages per block is not just a power of 2, however, Considering the design and access speed of the flash memory controller, only 2 ^N data pages are usually used to access data in one block. For example, suppose a block has 258 data pages, but only the first 256 (2 8th power) data pages are used to store data, and the last two data pages are usually unused. As a result, the space for the last two data pages is wasted.

Therefore, an object of the present invention is to provide a method for accessing a flash memory, which can utilize a material page that is not used in the prior art to back up data, so as to solve the problem of waste of data page space in the prior art. .

According to an embodiment of the invention, a method for accessing a flash memory is provided, wherein the number of data pages included in a block in the flash memory is (2 ^N +M), and N and M are both Is a positive integer, and the method includes: writing a data stream to the 1~2 ^N data pages of the block; and writing to the data pages of the 1~2 ^N data pages The data is backed up to the (2 ^N +1)~(2 ^N +M) data pages of the block.

According to another embodiment of the present invention, a memory device is provided, wherein the memory device includes a flash memory and a controller, the flash memory includes a plurality of blocks, and any of the plurality of blocks the number of pages contained in the data of (2 ^N + M), and N, M are positive integers, and the system controller is used to write a data stream through a 1 ~ 2 ^N data blocks of the In the page, and back up the data written to the partial data pages of the 1~2 ^N data pages to the (2 ^N +1)~(2 ^N +M) data pages of the block.

According to another embodiment of the present invention, a method for accessing a flash memory is provided, wherein the number of data pages included in a block in the flash memory is (2 ^N +M), the second (2 ^N +1)~(2 ^N +M) data pages are used to back up some data pages of the 1~2 ^N data pages, and N and M are positive integers, and the method includes: reading the data a data page of at least one of the data pages; and selectively reading the data page of the (2 ^N +1)~(2 ^N +M) data pages for backing up the at least one data page as the At least one data page.

According to another embodiment of the present invention, a memory device is provided, wherein the memory device includes a flash memory and a controller, the flash memory includes a plurality of blocks, and any of the plurality of blocks The number of data pages included is (2 ^N +M), and the (2 ^N +1)~(2 ^N +M) data pages are used to back up some of the data pages of the 1~2 ^N data pages. And N and M are positive integers; and the controller is configured to read data of at least one data page of the part of the data page, and selectively read the (2 ^N +1)~(2 ^N +M a material page for backing up the at least one data page as the data in the at least one data page.

100‧‧‧ memory device

110‧‧‧ memory controller

112‧‧‧Microprocessor

112C‧‧‧ Code

112M‧‧‧Reading memory

114‧‧‧Control logic

116‧‧‧Buffered memory

118‧‧‧Interface logic

120‧‧‧Flash memory

200‧‧‧ blocks

410‧‧‧Material page buffer

P0~P257‧‧‧Information Page

WL0~WL85‧‧‧ character line

300~304, 500~504‧‧‧ steps

1 is a schematic diagram of a memory device in accordance with an embodiment of the present invention.

2 is a schematic diagram of a block in a flash memory according to an embodiment of the invention.

3 is a flow chart of a method of writing data to a flash memory in accordance with an embodiment of the present invention.

Figure 4 is a schematic diagram of data backup for the block shown in Figure 2.

Figure 5 is a flow chart of a method of reading a flash memory in accordance with an embodiment of the present invention.

Please refer to FIG. 1 . FIG. 1 is a schematic diagram of a memory device 100 according to an embodiment of the present invention. The memory device 100 of the present embodiment is specifically a portable memory device (eg, conforming to SD/MMC, CF, MS, XD standard memory card). The memory device 100 includes a flash memory 120 and a controller, which can be a memory controller 110 and is used to access the flash memory 120. According to the embodiment, the memory controller 110 includes a microprocessor 112, a read only memory (ROM) 112M, a control logic 114, a buffer memory 116, and an interface logic 118. The read-only memory system is used to store a code 112C, and the microprocessor 112 is used to execute the code 112C to control access to the flash memory 120.

In a typical situation, the flash memory 120 includes a plurality of blocks, and the controller (eg, the memory controller 110 executing the code 112C through the microprocessor 112) copies the flash memory 120. Operations such as erasing and merging data are copied, erased, and combined in units of blocks. In addition, a block may record a specific number of pages, wherein the controller (eg, the memory controller 110 executing the code 112C through the microprocessor 112) writes data to the flash memory 120. The operation is written in units of data pages.

In practice, the memory controller 110 executing the program code 112C through the microprocessor 112 can perform various control operations by using its own internal components, for example, using the control logic 114 to control the access operation of the flash memory 120 ( Especially for at least one block or at least one data page The operation is performed, the buffer memory 116 is used to perform the required buffer processing, and the interface logic 118 is used to communicate with a host device.

Please refer to FIG. 2, which is a schematic diagram of a block 200 in the flash memory 120 according to an embodiment of the invention. As shown in FIG. 2, the block 200 is a three-layer storage (TLC) architecture, that is, each storage unit (ie, each transistor) in the drawing can store three bits, and the block 200 There are 86 word lines WL0~WL85, and each word line constitutes three data pages, so the block 200 contains 258 data pages P0~P257. In the following description, the content of the present invention is described by the block size shown in FIG. 2, however, this is not a limitation of the present invention. In other embodiments of the present invention, the block 200 may also be used. Have a different number of profiles.

Please refer to FIG. 1 , FIG. 3 and FIG. 4 simultaneously. FIG. 3 is a flowchart of a method for writing data to a flash memory according to an embodiment of the present invention, and FIG. 4 is a block 200. Schematic diagram of data backup. Referring to Figure 3, the flow is as follows: In step 300, the process begins. Next, in step 302, the memory controller 110 sequentially writes a data stream to the data pages P0 to P255 of the block 200, and after the data pages P0 to P255 have written the data, the flow proceeds to step 304. In step 304, the memory controller 110 backs up the data of the two data pages written to the data pages P0 to P255 to the data pages P256 and P257.

In detail, in step 304, the memory controller 110 can determine, according to a preset location information, which of the two data pages is backed up to the data pages P256 and P257, and the preset location information can be designed. The determination is based on the quality of the flash memory 120 or other tested data, that is, the preset location information can be used to indicate which of the data pages P0 to P255 has poor storage quality. In an embodiment of the invention, the block 200 is a three-layer storage. (TLC) architecture, so each word line (WL0~WL85) of block 200 includes a Most Significant Bit Page (MSB page) and a Central Significant Bit Page (Central Significant Bit Page). , CSB page) and a Least Significant Bit Page (LSB page). In addition, since the highest bit data page usually has a high error rate, the memory controller 110 can correspond to the two blocks 200. The data of the highest bit data page on the word line is backed up to the data pages P256 and P257, or the data corresponding to the middle bit data page of the two character lines in the block 200 is backed up to the data pages P256 and P257. Or, the data in the block 200 corresponding to one of the one- or two-character line and the highest-bit data page are backed up to the data pages P256 and P257.

In addition, in the process of backing up the data of the two data pages in the data pages P0~P255 to the data pages P256 and P257, refer to FIG. 4, and assume that the data of the data page P3 needs to be backed up to the data page P256, then the memory control The device 110 may copy the data of the data page P3 into the material page buffer 410 according to a copy-back command, and then copy the data in the data page buffer 410 to the data page P256; The memory controller 110 then backs up the data in another data page to the data page P257 according to the same method. In addition, in another embodiment of the present invention, the memory controller 110 can also copy the data of the data page P3 to the data page buffer 410 according to a standard read/write command. Thereafter, it is transferred to the buffer in the memory controller 110, and the data is subsequently written by the memory controller 110 to the material page P256.

In summary, since the material pages P256 and P257 in the block 200 can be used to back up data, all the storage spaces in the block 200 are compared with the case where the data pages P256 and P257 are not used in the prior art. Both can be effectively utilized.

Further, the examples given in the above FIGS. 2 to 4 are merely illustrative and not limiting as to the present invention. In other embodiments of the present invention, as long as the number of data pages included in one block is (2 ^N + M), and the memory controller 110 writes to some data pages in the 1~2 ^N data pages. The data is backed up to the (2 ^N +1)~(2 ^N +M) data pages of the block, and the process of the present invention may have other suitable changes, and these design changes are all subject to the present invention. The scope.

Next, please refer to FIG. 1 , FIG. 2 and FIG. 5 simultaneously. FIG. 5 is a flow chart of a method for reading a flash memory according to an embodiment of the invention. The following description of FIG. 5 is continued from the flow of FIG. 3, that is, the flow shown in FIG. 5 is to read the data in the block 200, and the data pages P256 and P257 in the block 200 have been backed up. The data of two data pages in the data page P0~P255. Referring to Figure 5, the flow is as follows: In step 500, the process begins. In step 502, the memory controller 110 reads the data of at least one of the data pages P0~P255 according to an instruction, wherein the data of the at least one data page is backed up in the data page P256 or P257. Next, in step 504, the memory controller 110 selectively reads the data pages P256 and P257 according to the status of reading the at least one data page as the data in the at least one data page.

In detail, in step 504, it is assumed that the material page P256 has the data of the backup material page P3. Therefore, when the memory controller 110 reads the data page P3, if the memory controller 110 determines that the data page P3 cannot be successfully read. The information (that is, the data is seriously damaged and cannot be replied with the error correction code), or because the data page P3 takes a long time to use the error correction code to reply the data, thus the reading time of the data page P3 will exceed At a predetermined time, the memory controller 110 can directly read the data of the data page P256 as the data of the data page P3. In addition, if the memory controller 110 has successfully read the data of the data page P3, it is not necessary to read the data page P256.

Briefly summarized in the present invention, in the method for accessing a flash memory of the present invention, data of a part of the data pages of the 1~2 ^N data pages in a block can be backed up to the second part of the block (2 ^N +1)~(2 ^N +M) data pages, so that each data page in the block can be effectively utilized. Further, when the data of 1 ~ 2 ^N th page in the data portion of an error data page can not be correctly read, may be by the second ^{(2 N +1) ~ (2} N + M) th profile page The backup data is restored to further improve the correctness of the data in the flash memory.

300~304‧‧‧Steps

Claims (18)

A method for accessing a flash memory, wherein the number of data pages included in a block in the flash memory is (2 ^N +M), and N and M are positive integers, and The method includes: writing a data stream to the 1~2 ^N data pages of the block; and backing up data written to the partial data pages of the 1~2 ^N data pages to the area The first (2 ^N +1)~(2 ^N +M) data pages of the block. The method of claim 1, wherein the data written to the partial data pages of the 1~2 ^N data pages is backed up to the (2 ^N +1)~(2 ^N +M) of the block. The steps in the data page include: selecting M data pages from the 1~2 ^N data pages; and sequentially transmitting the selected data page data to a data page buffer in the flash memory. And sequentially transferring the data stored in the data page buffer to the (2 ^N +1)~(2 ^N +M) data pages of the block. The method of claim 2, wherein the step of selecting the M data pages from the first to the second ^N data pages comprises: according to a preset location information from (2 ^N +1) The M data pages are selected from ~(2 ^N +M) data pages. The method of claim 1, wherein the flash memory is a Triple-Level Cell (TLC) flash memory. The method of claim 4, wherein the block of the flash memory comprises Multiple Most Significant Bit Page (MSB page), Central Significant Bit Page (CSB page), and Least Significant Bit Page (LSB page), and this part The data pages are the highest bit data pages, all of which are intermediate bit data pages, or some of the highest bit data pages. A memory device includes: a flash memory, wherein the flash memory comprises a plurality of blocks, and the number of data pages included in any of the plurality of blocks is (2) ^N + M), and N and M are positive integers; and a controller for writing a data stream to the first to second ^N data pages of the block, and writing to the first ~2 The data of some data pages in ^N data pages is backed up to the (2 ^N +1)~(2 ^N +M) data pages of the block. The memory device of claim 6, wherein the controller selects M data pages from the first to the second ^N data pages, and sequentially transmits the selected data page data to the flash memory. A data page buffer in the body, and the data stored in the data page buffer are sequentially transmitted to the (2 ^N +1)~(2 ^N +M) data pages of the block. The memory device of claim 7, wherein the controller selects the M data pages from the first to the second ^N data pages according to a preset position information. The memory device of claim 6, wherein the flash memory is a Triple-Level Cell (TLC) flash memory. The memory device of claim 9, wherein the block of the flash memory Containing a plurality of Most Significant Bit Pages (MSB pages), a Central Significant Bit Page (CSB page), and a Least Significant Bit Page (LSB page), and Some of the data pages are the highest bit data pages, all of which are intermediate bit data pages, or some of the highest bit data pages. A method for accessing a flash memory, wherein the number of data pages included in a block in the flash memory is (2 ^N +M), the second (2 ^N +1)~(2 ^N + M) data pages are used to back up some of the data pages of the 1~2 ^N data pages, and N and M are positive integers, and the method includes: reading at least one of the data pages a data page; and selectively reading a data page of the (2 ^N +1)~(2 ^N +M) data pages for backing up the at least one data page as the at least one data page data. The method of claim 11, wherein the step of selectively reading the data pages of the (2 ^N +1)~(2 ^N +M) data pages for backing up the at least one data page comprises Yes: determining whether the data of the at least one data page can be successfully read; and reading the (2 ^N +1)~(2 ^N +M) data pages when the data of the at least one data page cannot be successfully read The data page used to back up the at least one data page as the data in the at least one data page. The method of claim 11, wherein the step of selectively reading the data pages of the (2 ^N +1)~(2 ^N +M) data pages for backing up the at least one data page comprises Determining whether the time required to read the data of the at least one data page exceeds a predetermined time; and when it is judged that the time required to read the data of the at least one data page exceeds the predetermined time, the first reading is performed ( 2 ^N +1)~(2 ^N +M) data pages are used to back up the data page of the at least one data page as the data in the at least one data page. The method of claim 11, wherein the flash memory is a Triple-Level Cell (TLC) flash memory. A memory device includes: a flash memory, wherein the flash memory comprises a plurality of blocks, and the number of data pages included in any of the plurality of blocks is (2) ^N + M), the (2 ^N +1)~(2 ^N +M) data pages are used to back up the data of some data pages in the 1~2 ^N data pages, and N and M are positive integers; And a controller for reading at least one data page of the part of the data page, and selectively reading the (2 ^N +1)~(2 ^N +M) data pages for backing up the at least A data page of a data page to serve as information in the at least one data page. The memory device of claim 15, wherein the controller determines whether the data of the at least one data page can be successfully read; and when the data of the at least one data page cannot be successfully read, reading the 2 ^N +1)~(2 ^N +M) data pages are used to back up the data page of the at least one data page as the data in the at least one data page. The memory device of claim 15, wherein the controller determines whether a time required to read the data of the at least one data page exceeds a predetermined time; and when determining to read the data of the at least one data page When the required time exceeds the predetermined time, the data page of the (2 ^N +1)~(2 ^N +M) data pages for backing up the at least one data page is read as the at least one data page. Information in the middle. The memory device of claim 15, wherein the flash memory is a Triple-Level Cell (TLC) flash memory.