TW201342114A - Device for securing an electronic document - Google Patents

Device for securing an electronic document Download PDF

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Publication number
TW201342114A
TW201342114A TW101149160A TW101149160A TW201342114A TW 201342114 A TW201342114 A TW 201342114A TW 101149160 A TW101149160 A TW 101149160A TW 101149160 A TW101149160 A TW 101149160A TW 201342114 A TW201342114 A TW 201342114A
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Taiwan
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current
component
passive
passive component
voltage
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TW101149160A
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Chinese (zh)
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TWI636376B (en
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Christophe Giraud
Nicolas Morin
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Oberthur Technologies
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/86—Secure or tamper-resistant housings
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
    • G01R29/12—Measuring electrostatic fields or voltage-potential
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/77—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in smart cards
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/86—Secure or tamper-resistant housings
    • G06F21/87—Secure or tamper-resistant housings by means of encapsulation, e.g. for integrated circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/073—Special arrangements for circuits, e.g. for protecting identification code in memory
    • G06K19/07309—Means for preventing undesired reading or writing from or onto record carriers
    • G06K19/07363—Means for preventing undesired reading or writing from or onto record carriers by preventing analysis of the circuit, e.g. dynamic or static power analysis or current analysis
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/57—Protection from inspection, reverse engineering or tampering
    • H01L23/573—Protection from inspection, reverse engineering or tampering using passive means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64—Impedance arrangements
    • H01L2223/66—High-frequency adaptations
    • H01L2223/6661—High-frequency adaptations for passive devices
    • H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48237—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

This device (10) comprises: at least one passive element (40) capable of generating an electric current in the presence of an electric field or a magnetic field; and triggering means (50) of a protective measure on detection of said current when the intensity of the latter exceeds a predetermined threshold.

Description

用於保全一電子文件之裝置 Device for preserving an electronic file

本發明係關於保全電子組件之領域。 The present invention relates to the field of preserving electronic components.

故障注入之攻擊眾所周知，此等攻擊由實體上擾動組件以在執行期間修改碼或修改正處置之變量之值組成。 Attacks of fault injection are well known, and such attacks consist of physically perturbing the component to modify the code during execution or to modify the value of the variable being processed.

對應錯誤輸出允許攻擊者獲得關於儲存於組件中之秘密之資訊。 Corresponding error output allows an attacker to obtain information about the secrets stored in the component.

用於擾動一組件之一有效構件係使用一光源(舉例而言，一雷射)，該光源對該組件之撞擊之效應係在矽中產生局部光電流以產生一故障。 One of the effective components used to perturb a component is to use a light source (for example, a laser) whose effect on the impact of the component is to create a local photocurrent in the crucible to create a fault.

光擾動之攻擊係半侵入式攻擊，具體而言，其係需要曝露組件之一表面以使得光射線可撞擊該表面之攻擊。 A light-disturbing attack is a semi-invasive attack, in particular, an attack that requires exposure of one of the components to cause the light rays to strike the surface.

熟習此項技術者藉由一組件之表達「製備」知曉此操作。 Those skilled in the art will be aware of this operation by the expression "preparation" of a component.

有時必須製備一組件之事實使此等攻擊變得困難，舉例而言，此乃因其封裝之性質(一陶瓷覆蓋物難以刺穿)或經實施以防止拆封之對策。 The fact that a component must be prepared sometimes makes such an attack difficult, for example, due to the nature of its packaging (a ceramic covering is difficult to pierce) or implemented to prevent unpacking.

用於擾動一嵌入式組件之另一構件係在矽附近發射一強磁或電脈衝。磁場或電場在組件之表面處在積體電路之金屬層之層級處產生局部電流，此可產生擾動。 Another component used to perturb an embedded component emits a strong magnetic or electrical pulse near the bore. The magnetic field or electric field creates a local current at the level of the metal layer of the integrated circuit at the surface of the component, which can create a disturbance.

與光擾動之攻擊相比，稱為EMFA(電磁故障攻擊)之此等攻擊並不需要製備組件。 Such attacks, known as EMFA (Electromagnetic Fault Attack), do not require the preparation of components as compared to optically perturbed attacks.

舉例而言，在一智慧卡之情形中，注入在卡後方之電磁 擾動可容易透過卡擾動組件。 For example, in the case of a smart card, the electromagnetic injected behind the card Disturbance can easily perturb the component through the card.

電磁故障攻擊之記號「EMFA」係實際上涵蓋磁或電類型之注入之一泛用名稱。 The symbol "EMFA" of the electromagnetic fault attack actually covers a generic name for the injection of a magnetic or electrical type.

在磁擾動之情形中，擾動探針包括發送一局部強大之磁場之一小線圈。被攻擊之組件之敷金屬線接收擾動其操作之感應電流。探針利用感應耦合來注入一擾動電流。 In the case of magnetic perturbations, the perturbation probe includes a small coil that transmits one of the locally powerful magnetic fields. The metal wire of the component being attacked receives the induced current that disturbs its operation. The probe uses inductive coupling to inject a disturbing current.

在電擾動之情形中，擾動探針可係到達相對於待攻擊之組件之接地之彼電位之相當大電位之一金屬點(或一小金屬平面)。由探針施加之此電位誘發一電場，該電場之變化在敷金屬線中產生一電流。該探針使用電容性耦合來注入擾動電流。 In the case of electrical perturbations, the perturbation probe can reach a metal point (or a small metal plane) at a substantial potential relative to the potential of the ground of the component to be attacked. This potential applied by the probe induces an electric field that changes a current in the metallization line. The probe uses capacitive coupling to inject a disturbing current.

本發明提出保護一組件免受EMFA類型之攻擊之不同解決方案。 The present invention proposes a different solution to protect a component from EMFA type attacks.

更精確而言，且根據一第一態樣，本發明係關於一種裝置，該裝置包括：-至少一個被動元件，其能夠在存在一電場或一磁場之情況下產生電流；及-在偵測到該電流之後當該電流之強度超過一預定臨限值時即刻觸發模組之一保護措施之構件。 More precisely, and in accordance with a first aspect, the present invention is directed to a device comprising: - at least one passive component capable of generating an electrical current in the presence of an electric field or a magnetic field; and - detecting The component of one of the protection measures of the module is triggered as soon as the current exceeds a predetermined threshold after the current.

此裝置能夠偵測EMFA(電磁故障攻擊)擾動。 This device is capable of detecting EMFA (Electromagnetic Fault Attack) disturbances.

在一較佳實施例中，在本發明之此第一態樣中所使用之被動元件專用於電或磁擾動之偵測。此等元件並不參與對該裝置進行供應。當該裝置與另一裝置(舉例而言，一智 慧卡)交換有用資料(舉例而言，呈命令或回應之形式之訊息)時，本發明之被動元件不同於裝置之介面且並不參與此等有用資料之傳遞。換言之，在此實施例中，被動元件不同於裝置之輸入/輸出。 In a preferred embodiment, the passive components used in this first aspect of the invention are dedicated to the detection of electrical or magnetic disturbances. These components are not involved in the supply of the device. When the device is connected to another device (for example, a smart When a smart card exchanges useful information (for example, a message in the form of a command or response), the passive component of the present invention is different from the interface of the device and does not participate in the transfer of such useful material. In other words, in this embodiment, the passive component is different from the input/output of the device.

兩個主要變型係可行的。 Two major variants are feasible.

在一第一變型中，根據本發明之裝置包括一支撐件(舉例而言，一圓釘(thumbnail))及一組件，其中該被動元件或該等被動元件配置於該支撐件中。 In a first variant, the device according to the invention comprises a support member (for example, a thumb) and an assembly, wherein the passive element or the passive elements are disposed in the support member.

在本發明之一實施例中，配置於該支撐件中之該等被動元件中之至少一者係能夠在存在一磁場之情況下產生電流之一天線。 In an embodiment of the invention, at least one of the passive components disposed in the support is capable of generating one of the currents in the presence of a magnetic field.

眾所周知，此電流之強度與磁場之強度實質上成比例。 It is well known that the intensity of this current is substantially proportional to the strength of the magnetic field.

熟習此項技術者將理解，天線之設計固定可由本發明偵測到之波之頻寬之寬度。 Those skilled in the art will appreciate that the design of the antenna can be fixed by the width of the bandwidth of the wave detected by the present invention.

在本發明之一特定實施例中，天線組織於一網路中，較佳地在支撐件之整個表面上方，每一天線充當一磁感測器。 In a particular embodiment of the invention, the antennas are organized in a network, preferably over the entire surface of the support, each antenna acting as a magnetic sensor.

較佳地，該網路之天線具有達成對不同頻寬之磁場之偵測之不同特性。 Preferably, the antenna of the network has different characteristics for detecting magnetic fields of different bandwidths.

在另一實施例中，配置於該支撐件中之該等被動元件中之至少一者係能夠在存在一電場之情況下產生電流之一金屬平面。 In another embodiment, at least one of the passive components disposed in the support is capable of generating a metal plane of current in the presence of an electric field.

在此實施例中，金屬平面藉由加強與擾動源之電容耦合來擷取電場。 In this embodiment, the metal plane draws an electric field by enhancing capacitive coupling with the disturbance source.

如在天線之情形中，由金屬平面遞送之電流之強度隨著電場之強度增加。更精確而言，電流之強度等於存在於擾動探針(電場之發送者)與金屬平面之間的電位之導數乘以該探針與該平面之間的等效電容。 As in the case of an antenna, the intensity of the current delivered by the metal plane increases with the strength of the electric field. More precisely, the intensity of the current is equal to the derivative of the potential present between the perturbation probe (the sender of the electric field) and the metal plane multiplied by the equivalent capacitance between the probe and the plane.

金屬平面亦可配置於一網路中，較佳地在支撐件之整個表面上方，每一金屬平面充當一電感測器。 The metal plane can also be disposed in a network, preferably over the entire surface of the support, with each metal plane acting as an inductive detector.

該網路之金屬平面亦可經設計以偵測不同類型之電場。 The metal plane of the network can also be designed to detect different types of electric fields.

在本發明之另一變型中，根據本發明之裝置係一組件，該被動元件或該等被動元件(天線或金屬平面)配置於該組件之一敷金屬層中。 In a further variant of the invention, the device according to the invention is an assembly, the passive element or the passive elements (antenna or metal plane) being arranged in a metallized layer of the assembly.

此敷金屬層較佳地位於作用部分之一保護層下方。以一已知方式，此保護層(「保護遮蔽物」)構成在該組件經更改時防止其起作用之第一層。 The metallization layer is preferably located below one of the protective layers of the active portion. In a known manner, the protective layer ("protective shield") constitutes the first layer that prevents the component from functioning when it is modified.

有利地保護此實施例免受力圖移除包括被動元件之該層之一攻擊。 This embodiment is advantageously protected from attempts to remove one of the layers including the passive component.

根據本發明，在兩種變型中，根據本發明之裝置包括在電流之強度超過一臨限值時觸發一對策之構件。 According to the invention, in both variants, the device according to the invention comprises means for triggering a countermeasure when the intensity of the current exceeds a threshold.

可根據電磁相容性標準(CEM)定義此臨限值。 This threshold can be defined in accordance with the Electromagnetic Compatibility Standard (CEM).

在一特定實施例中，觸發一對策之此等構件包括一熔絲，該熔絲經放置與被動元件串聯且經定尺寸以在強度大於以上臨限值之一電流通過其時熔融。 In a particular embodiment, the components that trigger a countermeasure include a fuse that is placed in series with the passive component and sized to melt as the current passes through it at a strength greater than the above threshold.

在另一實施例中，觸發一對策之構件包括用於比較與由被動元件產生之電流成比例之一第一電壓與一電壓臨限值之構件。 In another embodiment, the means for triggering a countermeasure includes means for comparing a first voltage and a voltage threshold proportional to the current produced by the passive component.

在一特定實施例中，該對策由附著一介面信號與併入有該裝置之一微電路卡組成。 In a particular embodiment, the countermeasure consists of attaching an interface signal to a microcircuit card incorporating one of the devices.

特定而言，本發明在該裝置併入至一智慧卡中時應用於附著根據標準ISO7816之一介面信號，舉例而言，一時脈信號、一輸入/輸出信號或一重新初始化信號。 In particular, the present invention is applied to attach an interface signal according to standard ISO 7816, for example, a clock signal, an input/output signal or a reinitialization signal, when the device is incorporated into a smart card.

本發明亦規定包括諸如上文所提及之一裝置之一微電路卡。 The invention also provides for including a microcircuit card such as one of the devices mentioned above.

在一實施例中，該裝置係一積體電路。 In one embodiment, the device is an integrated circuit.

此積體電路可經設計以在一電話中使用。特定而言，其可係一用戶至行動電話網路之一識別電路。舉例而言，該裝置係一SIM卡。 This integrated circuit can be designed to be used in a telephone. In particular, it can be a user-to-mobile telephone network identification circuit. For example, the device is a SIM card.

作為一變體，該裝置配置於一銀行卡或一身份證件內部。 As a variant, the device is arranged inside a bank card or an identity document.

舉例而言，該裝置遵循FIPS標準或共同準則。 For example, the device follows FIPS standards or common guidelines.

根據一第二態樣，本發明係關於一種包括一支撐件及一組件之裝置，該組件之一作用部分包括電連接至該裝置之連接接針之連接接針，此裝置之特徵在於其包括擱置在該支撐件上之一金屬罩，此罩覆蓋該組件及該裝置之該等連接接針。 According to a second aspect, the invention relates to a device comprising a support member and an assembly, the active portion of the assembly comprising a connection pin electrically connected to the connection pin of the device, the device being characterized in that it comprises A metal cover resting on the support member covers the assembly and the connecting pins of the device.

本發明之此第二態樣旨在保護卡免受EMFA攻擊且並不旨在偵測此等攻擊。 This second aspect of the invention is intended to protect the card from EMFA attacks and is not intended to detect such attacks.

金屬壁保護該組件之側。 The metal wall protects the side of the assembly.

本發明之此態樣極令人感興趣之處在於：其迫使攻擊者準備(舉例而言)藉由在壁中(通常在作用部分上方)挖一洞 而使該卡遭受一EMFA攻擊。 This aspect of the invention is of great interest in that it forces the attacker to prepare, for example, a hole in the wall (usually above the active part) The card is subjected to an EMFA attack.

在一特定實施例中，此金屬罩包括包封組件及該裝置之連接接針之至少一個側壁、擱置在該支撐件上的此側壁之一邊緣、及形成該等側壁之一覆蓋物之一壁。 In a particular embodiment, the metal cover includes at least one side wall of the encapsulation assembly and the connecting pin of the device, an edge of the side wall resting on the support member, and one of the coverings forming the side wall wall.

在一特定實施例中，該組件固定至該支撐件，該裝置之連接接針直接配置於該支撐件上。 In a particular embodiment, the assembly is secured to the support member and the attachment pins of the device are disposed directly on the support member.

在另一特定實施例中，該金屬罩構成一封閉外殼，該封閉外殼之一個外部壁固定至該支撐件，該組件及模組之連接接針固定至該外殼之內部。該外殼包括用於使連接導線通過之儘可能小之孔。 In another particular embodiment, the metal cover forms a closed outer casing, an outer wall of the closed outer casing is fixed to the support member, and the connecting pin of the assembly and the module is fixed to the inner portion of the outer casing. The housing includes as small a hole as possible for the connecting wires to pass.

此實施例保護自身免受成功移除該支撐件之一攻擊者攻擊該組件。 This embodiment protects itself from attackers who successfully remove one of the supports from attacking the component.

在一特定實施例中，意欲連接至接地之作用部分之一連接接針連接至該罩，該罩自身連接至該裝置之一接地接針。 In a particular embodiment, one of the active portions intended to be connected to ground is connected to the cover, which is itself connected to one of the ground pins of the device.

此實施例增強本發明之此第二態樣之安全性。 This embodiment enhances the security of this second aspect of the invention.

本發明亦規定一種包括根據本發明之第二態樣之免受一攻擊之保護構件及根據本發明之第一態樣之用於偵測及反擊之構件之裝置。 The invention also provides a device comprising a protective member according to a second aspect of the invention protected from an attack and a member for detecting and counterattacking according to the first aspect of the invention.

本發明之其他模式及優點將自沒有任何限制特性的本發明之特定實施例之說明顯現。 Other modes and advantages of the invention will appear from the description of the specific embodiments of the invention without any limitation.

圖1圖解說明根據本發明之第一態樣之一裝置10。 Figure 1 illustrates one apparatus 10 in accordance with a first aspect of the present invention.

此裝置10包括一支撐件12及一組件14，被動元件40配置 於支撐件12中能夠在存在一磁場或一電場之情況下產生電流。 The device 10 includes a support member 12 and an assembly 14, and the passive component 40 is configured In the support member 12, a current can be generated in the presence of a magnetic field or an electric field.

此等被動元件40可包括能夠在存在一磁場之情況下產生電流之天線或能夠在存在一電場之情況下產生電流之金屬平面。 These passive components 40 may include an antenna capable of generating a current in the presence of a magnetic field or a metal plane capable of generating a current in the presence of an electric field.

在此處所闡述之實施例中，該支撐件包括天線及金屬平面兩者以使得其可同時偵測一磁場及一電場。 In the embodiments set forth herein, the support includes both the antenna and the metal plane such that it can simultaneously detect a magnetic field and an electric field.

圖2圖解說明根據本發明之第一態樣之另一裝置10。 Figure 2 illustrates another apparatus 10 in accordance with a first aspect of the present invention.

在此實施例中，裝置10係一組件，被動元件40配置於該組件之一敷金屬層15b中。舉例而言，該組件係一積體電路且層15b係在製造期間藉由一個或若干個光微影步驟獲得之積體電路之一層。 In this embodiment, device 10 is an assembly and passive component 40 is disposed in one of metallization layers 15b of the component. For example, the component is an integrated circuit and layer 15b is a layer of integrated circuitry obtained by one or several photolithography steps during fabrication.

在圖中，明顯地，包括被動元件之層15b放置於一保護層15a下方。 In the figure, it is apparent that the layer 15b including the passive element is placed under a protective layer 15a.

僅以實例之方式，此圖圖解說明構成一個(或多個)功能性敷金屬層之一層15c及一矽層18(半導體元件(電晶體、二極體...)位於其上在表面處)。 By way of example only, this figure illustrates a layer 15c and a layer 18 (semiconductor elements (transistors, diodes...) constituting one (or more) functional metallization layers on the surface ).

根據本發明之此第一態樣，裝置10包括在由被動元件產生之電流超過一預定臨限值時觸發一保護措施之構件。 In accordance with this first aspect of the invention, apparatus 10 includes means for triggering a protective measure when the current generated by the passive component exceeds a predetermined threshold.

圖3圖解說明其中一天線40連接至一熔絲55之一第一配置，熔絲55經放置與該天線串聯以使得由該天線發送之電流直接傳遞至熔絲中。 Figure 3 illustrates a first configuration in which one of the antennas 40 is coupled to a fuse 55 that is placed in series with the antenna such that current delivered by the antenna is passed directly into the fuse.

此熔絲經定尺寸以便在天線擷取源自組件自身之電磁放射或源自外部之電磁擾動時不熔融。 The fuse is sized to not melt when the antenna draws electromagnetic radiation from the component itself or electromagnetic interference from the outside.

在該兩種情況下熔絲皆不必須熔融，此乃因由一磁場感應之電流具有小於CEM標準之振幅。 In either case, the fuse does not have to be melted because the current induced by a magnetic field has an amplitude that is less than the CEM standard.

相反，熔絲55必須經定尺寸以在天線感測較強擾動(與一MFA攻擊同義)時熔融。針對該裝置設定之臨限值與熔絲之特性有關。 Instead, the fuse 55 must be sized to melt when the antenna senses a strong disturbance (synonymous with an MFA attack). The threshold set for the device is related to the characteristics of the fuse.

在圖3之實施例中，在正常模式中，亦即，當熔絲55未熔融時，天線40使電阻R2短路且僅源自該天線之電流之變化形式到達電阻R2。源自外部磁場或源自組件之電磁波之此等變化形式在電阻R2之端子處感應電壓，該等電壓弱得不足以超過電晶體M之臨限電壓以使得電阻R2之端子保持阻擋且不擾動在偵測到故障之情形中待附著之一SIG信號。 In the embodiment of FIG. 3, in the normal mode, that is, when the fuse 55 is not melted, the antenna 40 shorts the resistor R2 and only the variation of the current from the antenna reaches the resistor R2. Such variations from external magnetic fields or electromagnetic waves originating from the component induce voltages at the terminals of the resistor R2 that are weak enough to exceed the threshold voltage of the transistor M such that the terminals of the resistor R2 remain blocked and undisturbed One of the SIG signals to be attached in the event that a fault is detected.

若由天線40發射大於該臨限值之電流，則考量到外場超過CEM特性及此係一MFA攻擊：正確地定尺寸之熔絲55熔融。 If the current is greater than the threshold current from the antenna 40, then the external field is considered to exceed the CEM characteristics and the system is an MFA attack: the properly sized fuse 55 is melted.

此起始非正常模式。電阻R1及R2形成一分壓器橋且發送至電晶體M之電壓等於VCC×R2/(R1+R2)。 This starts in an abnormal mode. Resistors R1 and R2 form a voltage divider bridge and the voltage sent to transistor M is equal to VCC x R2 / (R1 + R2).

R1必須經定尺寸以使得此分壓器橋輸出電壓大於電晶體M之臨限電壓。 R1 must be sized such that the voltage divider bridge output voltage is greater than the threshold voltage of transistor M.

由於電晶體M接通，因此其形成一閉合斷續器且SIG信號藉助於電晶體M附著至接地。 Since the transistor M is turned on, it forms a closed interrupter and the SIG signal is attached to the ground by means of the transistor M.

圖4闡述其中被動元件40係一金屬平面之一實施例。 Figure 4 illustrates an embodiment in which the passive component 40 is a metal plane.

在此實施例中，在正常模式中，亦即，當熔絲55未熔融時，平面40-熔絲55總成藉由對電晶體M之控制電壓施加零 U電壓而使電晶體NMOS M之柵極與源極短路。電晶體M保持阻擋且不作用於待附著之SiG信號。 In this embodiment, in the normal mode, that is, when the fuse 55 is not melted, the plane 40-fuse 55 assembly is applied with zero by the control voltage to the transistor M. The U voltage causes the gate of the transistor NMOS M to be short-circuited with the source. The transistor M remains blocked and does not act on the SiG signal to be attached.

若一電場施加至平面，則電容性耦合產生借用最小電阻路徑行進至接地且經由熔絲傳遞之一電場。若對應於一EFA攻擊之偵測之此電流過強，則熔絲55熔融。電壓U經由電阻R1拉至VCC電位。電晶體M接通且將信號SiG附著於0 V處。 If an electric field is applied to the plane, the capacitive coupling creates an electric field that passes through the minimum resistive path to ground and through the fuse. If the current corresponding to the detection of an EFA attack is too strong, the fuse 55 melts. The voltage U is pulled to the VCC potential via the resistor R1. The transistor M is turned on and the signal SiG is attached to 0 V.

圖5闡述可在積體電路中實施之另一保護性系統。 Figure 5 illustrates another protective system that can be implemented in an integrated circuit.

在此實施例中，反應系統並非基於一熔絲之大小而是基於一電壓位準。 In this embodiment, the reaction system is not based on the size of a fuse but based on a voltage level.

此第二實施例較易於執行。 This second embodiment is easier to implement.

感測器40對應於一天線。其將其電流直接釋放至電阻R，電阻R根據歐姆定律將電流轉換成與由被動元件產生之電流成比例之U電壓。 The sensor 40 corresponds to an antenna. It discharges its current directly to the resistor R, which converts the current into a U voltage proportional to the current produced by the passive component according to Ohm's law.

電壓U施加至一電壓差動比較器60之正端子。 Voltage U is applied to the positive terminal of a voltage differential comparator 60.

舉例而言，由一分壓器橋產生之臨限電壓TS施加至此比較器之負端子。 For example, a threshold voltage TS generated by a voltage divider bridge is applied to the negative terminal of the comparator.

若電壓U不超過此臨限值，則比較器60之輸出保持等於「0」。比較器60之輸出直接連接至一非同步RS正反器之SET輸入且DET偵測停留於「0」處。 If the voltage U does not exceed this threshold, the output of the comparator 60 remains equal to "0". The output of comparator 60 is directly connected to the SET input of a non-synchronous RS flip-flop and the DET detection stays at "0".

若電壓U超過該臨限值，則比較器60之輸出在整個過衝期間達到「1」。此足以將一「1」隱形邏輯放置於RS正反器之SET輸入上且因此將DET輸出阻擋於1狀態中；RS正反器非同步操作。 If the voltage U exceeds the threshold, the output of the comparator 60 reaches "1" throughout the overshoot period. This is sufficient to place a "1" invisible logic on the SET input of the RS flip-flop and thus block the DET output in a 1 state; the RS flip-flop operates asynchronously.

放置於「1」處之此位元可然後用於參與對組件之安全動作。 This bit placed at "1" can then be used to participate in the secure action of the component.

為確保在組件啟動時DET信號在0處且為避免無法預料之安全動作，每次重新初始化組件介面ISO7816(連接至RS正反器之RESET輸入)之RESET信號之添加迫使DET信號為0。 To ensure that the DET signal is at 0 when the component is started and to avoid unpredictable safety actions, the addition of the RESET signal each time the component interface ISO7816 (connected to the RESET input of the RS flip-flop) is reinitialized forces the DET signal to be zero.

在圖6之實施例中，被動元件40係一金屬平面。如在圖5之情形中，退出金屬平面40之電流傳遞至電阻R且在比較器60之前強加U電壓。在一積體電路中實施此偵測方法係簡單的；藉助一分壓器橋調節偵測臨限值，執行此係尤其簡單的。 In the embodiment of Figure 6, the passive component 40 is a metal plane. As in the case of FIG. 5, the current exiting the metal plane 40 is transferred to the resistor R and the U voltage is imposed before the comparator 60. It is simple to implement this detection method in an integrated circuit; it is particularly simple to perform the detection threshold by means of a voltage divider bridge.

圖7A至圖7C圖解說明旨在保護組件10免受MFA攻擊的本發明之一第二態樣。 7A-7C illustrate a second aspect of the present invention that is intended to protect component 10 from MFA attacks.

在此實施例中，裝置10包括一支撐件12及一組件14，組件14之一作用部分15包括電連接至裝置10之連接接針17之連接接針16。 In this embodiment, the device 10 includes a support member 12 and an assembly 14, and an active portion 15 of the assembly 14 includes a connector pin 16 that is electrically coupled to the connector pin 17 of the device 10.

此裝置10之出眾之處在於：其包括擱置在支撐件12上且覆蓋組件14及連接接針17之一金屬罩30。 The device 10 is distinguished by the fact that it includes a metal cover 30 resting on the support member 12 and covering the assembly 14 and the connecting pin 17.

在圖7A之模式中，金屬罩30包括封裝組件及模組之連接接針之四個側壁31、擱置在支撐件12上的此側壁之一邊緣及其形成一覆蓋物之一壁32。 In the mode of FIG. 7A, the metal cover 30 includes four side walls 31 of the connector and the connector pins of the module, one edge of the side wall resting on the support member 12, and a wall 32 forming a cover.

當然，舉例而言，具有係為圓形剖面之一單個側壁31之實施例係可行的。 Of course, for example, an embodiment having a single side wall 31 that is one of a circular cross section is possible.

在圖7B之實施例中，且高度有利地，應連接至接地之一 連接接針16a直接連接至罩30，該罩自身連接至裝置之一接地接針17a。 In the embodiment of Figure 7B, and highly advantageous, one should be connected to ground The connecting pin 16a is directly connected to the cover 30, which is itself connected to one of the grounding pins 17a of the device.

在圖7C之實施例中，罩30係一封閉外殼。此外殼之一壁33固定至支撐件，組件14及模組之連接接針固定於外殼內部。 In the embodiment of Figure 7C, the cover 30 is a closed outer casing. A wall 33 of the outer casing is fixed to the support member, and the connecting pin of the assembly 14 and the module is fixed inside the outer casing.

本發明亦規定組合其中一裝置能夠偵測攻擊且抵抗其的本發明之第一態樣與第二態樣之一實施例(如參考圖1至圖6所闡述)亦受諸如圖7A至圖7C中所展示之一外殼保護。 The present invention also provides that an embodiment of the first aspect and the second aspect of the present invention (as explained with reference to Figures 1 to 6) in combination with one of the devices capable of detecting an attack and resisting it is also subject to such as Figure 7A One of the enclosures shown in 7C is protected.

10‧‧‧裝置/組件 10‧‧‧Devices/components

12‧‧‧支撐件 12‧‧‧Support

14‧‧‧組件 14‧‧‧ components

15‧‧‧作用部分 15‧‧‧Action section

15a‧‧‧保護層 15a‧‧‧Protective layer

15b‧‧‧敷金屬層/層 15b‧‧‧metal layer/layer

15c‧‧‧層 15c‧‧ layer

16‧‧‧連接接針 16‧‧‧Connecting pin

16a‧‧‧連接接針 16a‧‧‧Connecting pin

17‧‧‧連接接針 17‧‧‧Connecting pin

17a‧‧‧接地接針 17a‧‧‧ Grounding pin

18‧‧‧矽層 18‧‧‧矽

30‧‧‧金屬罩/罩 30‧‧‧Metal cover/cover

31‧‧‧側壁 31‧‧‧ side wall

32‧‧‧壁 32‧‧‧ wall

33‧‧‧壁 33‧‧‧ wall

40‧‧‧被動元件/天線/平面/感測器/金屬平面 40‧‧‧Passive Components/Antenna/Plane/Sensor/Metal Plane

50‧‧‧觸發構件 50‧‧‧ Trigger components

55‧‧‧熔絲 55‧‧‧Fuse

60‧‧‧電壓差動比較器/比較器 60‧‧‧Voltage differential comparator/comparator

DET‧‧‧偵測/輸出/信號 DET‧‧‧Detection/Output/Signal

M‧‧‧電晶體 M‧‧‧O crystal

R‧‧‧電阻 R‧‧‧resistance

R1‧‧‧電阻 R1‧‧‧ resistance

R2‧‧‧電阻 R2‧‧‧ resistance

SiG‧‧‧信號/重要信號 SiG‧‧‧Signal/Important Signal

TS‧‧‧臨限電壓 TS‧‧‧ threshold voltage

圖1及圖2圖解說明根據本發明之第一態樣之兩個裝置；圖3至圖6圖解說明用於觸發圖1及圖2之裝置之一保護措施之構件；及圖7A至圖7C圖解說明根據本發明之第二態樣之裝置。 1 and 2 illustrate two devices in accordance with a first aspect of the present invention; FIGS. 3 through 6 illustrate components for triggering a protective measure of the device of FIGS. 1 and 2; and FIGS. 7A-7C A device according to a second aspect of the invention is illustrated.

10‧‧‧裝置/組件 10‧‧‧Devices/components

12‧‧‧支撐件 12‧‧‧Support

14‧‧‧組件 14‧‧‧ components

40‧‧‧被動元件/天線/平面/感測器/金屬平面 40‧‧‧Passive Components/Antenna/Plane/Sensor/Metal Plane

Claims (12)

一種裝置(10)，其包括：至少一個被動元件(40)，其能夠在存在一電場或一磁場之情況下產生一電流；及觸發構件(50)，其係為偵測到該電流之後在該電流之強度超過一預定臨限值時之一保護措施。 A device (10) comprising: at least one passive component (40) capable of generating a current in the presence of an electric field or a magnetic field; and a triggering member (50) for detecting the current after One of the protective measures when the intensity of the current exceeds a predetermined threshold. 如請求項1之裝置(10)，其中其包括該等被動元件之一網路。 The device (10) of claim 1, wherein the network of one of the passive components is included. 如請求項2之裝置(10)，其中該網路之該等被動元件以不同方式校準以偵測不同類型之電場或磁場。 The device (10) of claim 2, wherein the passive components of the network are calibrated differently to detect different types of electric or magnetic fields. 如請求項1至3中任一項之裝置(10)，其包括一支撐件(12)及一組件(14)，其中該至少一個被動元件(40)配置於該支撐件(12)中。 A device (10) according to any one of claims 1 to 3, comprising a support member (12) and a component (14), wherein the at least one passive component (40) is disposed in the support member (12). 如請求項1至3中任一項之裝置(10)，其由一組件(14)構成，其中該至少一個被動元件(40)配置於該組件之一作用部分之一層(15b)中。 A device (10) according to any one of claims 1 to 3, which is constituted by a component (14), wherein the at least one passive component (40) is disposed in a layer (15b) of one of the active portions of the component. 如請求項5之裝置(10)，其中該被動元件放置於位於該作用部分之一保護層(15a)下方之一層(15b)中。 The device (10) of claim 5, wherein the passive component is placed in a layer (15b) below the protective layer (15a) of the active portion. 如請求項1至6中任一項之裝置(10)，其中該被動元件(40)係能夠在存在一磁場之情況下產生該電流之一天線。 The device (10) of any one of claims 1 to 6, wherein the passive component (40) is capable of generating one of the currents in the presence of a magnetic field. 如請求項1至7中任一項之裝置(10)，其中該被動元件(40)係能夠在存在一電場之情況下產生該電流之一金屬平面。 The device (10) of any one of claims 1 to 7, wherein the passive component (40) is capable of generating a metal plane of the current in the presence of an electric field. 如請求項1至8中任一項之裝置(10)，其中一對策之該觸發構件(50)包括一熔絲(55)，該熔絲經放置與該被動元件(40)串聯且經定尺寸以在強度大於該臨限值之一電流通過其時熔融。 The device (10) of any one of claims 1 to 8, wherein the trigger member (50) of a countermeasure comprises a fuse (55) placed in series with the passive component (40) and determined The dimension is melted as the current passes through it at a strength greater than the threshold. 如請求項1至8中任一項之裝置(10)，其中一對策之該觸發構件(50)包括用於比較與該電流成比例之一第一電壓與一電壓臨限值之構件(60)。 The device (10) of any one of claims 1 to 8, wherein the triggering member (50) of a countermeasure comprises means for comparing a first voltage and a voltage threshold proportional to the current (60) ). 如請求項1至10中任一項之裝置(10)，其中該措施由附著該裝置之一介面之一重要信號(SIG)組成。 The device (10) of any one of claims 1 to 10, wherein the measure consists of one of the important signals (SIG) attached to one of the interfaces of the device. 一種微電路卡，其包括如請求項1至13中任一項之一裝置(10)。 A microcircuit card comprising a device (10) according to any one of claims 1 to 13.
TW101149160A 2011-12-21 2012-12-21 Device for securing an electronic document TWI636376B (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107942154A (en) * 2017-10-16 2018-04-20 北京中电华大电子设计有限责任公司 A kind of protection structures and methods suitable for the protection of chip EMP attack N
CN110781059A (en) * 2018-07-31 2020-02-11 辉达公司 Protecting chips from electromagnetic pulse attacks using antennas

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3042055B1 (en) * 2015-10-06 2017-11-24 Inside Secure CONTREMESURES FOR ATTACKS BY INJECTION OF FAULTS BY OPTICAL AND ELECTROMAGNETIC PULSES
FR3053503B1 (en) * 2016-06-30 2019-03-29 Stmicroelectronics (Rousset) Sas METHOD FOR PROTECTING AN INTEGRATED CIRCUIT, AND CORRESPONDING INTEGRATED CIRCUIT
FR3084520B1 (en) 2018-07-25 2020-08-14 Stmicroelectronics Rousset PROTECTION METHOD FOR AN INTEGRATED CIRCUIT, AND CORRESPONDING DEVICE
FR3084521B1 (en) * 2018-07-25 2020-08-14 Stmicroelectronics Rousset PROTECTION PROCESS OF AN INTEGRATED CIRCUIT MODULE AND CORRESPONDING DEVICE
FR3084492A1 (en) 2018-07-30 2020-01-31 Stmicroelectronics (Rousset) Sas METHOD FOR DETECTING AN ATTACK BY A BEAM OF ELECTRICALLY CHARGED PARTICLES ON AN INTEGRATED CIRCUIT, AND CORRESPONDING INTEGRATED CIRCUIT
FR3099259B1 (en) 2019-07-24 2021-08-13 St Microelectronics Rousset Method for protecting data stored in a memory, and corresponding integrated circuit
WO2021030958A1 (en) 2019-08-16 2021-02-25 深圳市汇顶科技股份有限公司 Detection circuit for electromagnetic fault injection, security chip, and electronic device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5483596A (en) * 1994-01-24 1996-01-09 Paralon Technologies, Inc. Apparatus and method for controlling access to and interconnection of computer system resources
IL165468A0 (en) * 2002-06-04 2006-01-15 Nds Ltd Prevention of tampering in electronic devices
JP5159024B2 (en) 2004-01-30 2013-03-06 株式会社半導体エネルギー研究所 Semiconductor device
EP1941588A4 (en) * 2005-10-27 2011-03-16 Charles L Manto System and method for providing certifiable electromagnetic pulse and rfi protection through mass-produced shielded containers and rooms
KR100816750B1 (en) * 2006-08-11 2008-03-27 삼성전자주식회사 Smart card, detector and semiconductor integrated circuit having share block and unique block
US7804317B1 (en) * 2006-10-19 2010-09-28 Advanced Micro Devices, Inc. Test device for determining charge damage to a transistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107942154A (en) * 2017-10-16 2018-04-20 北京中电华大电子设计有限责任公司 A kind of protection structures and methods suitable for the protection of chip EMP attack N
CN110781059A (en) * 2018-07-31 2020-02-11 辉达公司 Protecting chips from electromagnetic pulse attacks using antennas

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