CN103296025A

CN103296025A - ESD (electro-static discharge) protection circuit for integrated circuit chips on circuit board

Info

Publication number: CN103296025A
Application number: CN2013101920711A
Authority: CN
Inventors: 黄德斌; 郭小东; 李志伟
Original assignee: Shenzhen Gongjin Electronics Co Ltd
Current assignee: Shenzhen Gongjin Electronics Co Ltd
Priority date: 2013-05-22
Filing date: 2013-05-22
Publication date: 2013-09-11

Abstract

The invention provides an ESD (electro-static discharge) protection circuit for integrated circuit chips on a circuit board. Key signals on the integrated circuit chips are protected by the ESD protection circuit. The ESD protection circuit comprises resistors and capacitors. The resistors are connected with key signal input pins of the integrated circuit chips, and the capacitors are connected among the key signal input ends and ground pins of the integrated circuit chips. The ESD protection circuit has the advantages that the resistor-capacitor circuit is added to the key signal pins of integrated circuits, coupling among the key signal pins and a local working ground can be strengthened, ESD interference signals which are superposed on the key signals are effectively attenuated, the key signals of the integrated circuits are guaranteed against crossing level thresholds, malfunction of the circuits is prevented, and the ESD protection capacity of the integrated circuits is improved.

Description

Integrated circuit (IC) chip ESD protection circuit on a kind of circuit board

Technical field

The present invention relates to the preventing electro-static discharge field, particularly a kind of circuit that on circuit board, integrated circuit (IC) chip is carried out electrostatic discharge protective.

Background technology

Along with development of electronic technology, the application of electronic equipment more and more widely, be not only high-tech sector such as space flight and aviation equipment, also be penetrated into the every aspect of people's lives, as household electric appliances, communication equipment, Medical Devices etc., ESD does not exist everywhere, the ESD problem is a serious threat to the operate as normal of equipment always, how protecting ESD, guarantee the operate as normal of equipment, is a long-term puzzlement engineer's a difficult problem.ESD:Electro-Static discharge, i.e. static discharge.One of the base components of current electronic device integrated circuit (IC) chip has corresponding ESD protection circuit in design, normally adopt clamp diode to wait signal is carried out clamper, as shown in Figure 1: only rely on the ESD safeguard procedures that IC interior is taked, can not guarantee the integrated circuit operate as normal.But these measures can only guarantee that integrated circuit is not damaged in actual design of electronic devices, to the operate as normal of support equipment often not enough, often find that ESD causes circuit function unusual, and equipment can't be tested by ESD.

Summary of the invention

The invention provides integrated circuit (IC) chip ESD protection circuit on a kind of circuit board, integrated circuit is closed key input signal such as reset signal (RESET_N), triggers enforcement ESD protection such as clock signal, edge-triggered interrupt signal, effectively remedied the deficiency of ESD protection circuit in the integrated circuit, the ESD protective capacities of raising equipment, assurance equipment is working properly.

Technical scheme of the present invention is: integrated circuit (IC) chip ESD protection circuit on a kind of circuit board, key signal on the integrated circuit (IC) chip is protected, comprise the resistance that links to each other with integrated circuit (IC) chip key signal input pin and be connected electric capacity between described integrated circuit (IC) chip key signal input and the grounding pin.

Further, on the above-mentioned circuit board in the integrated circuit (IC) chip ESD protection circuit: the value of described resistance and electric capacity is adjusted according to the requirement of the frequency height of key signal, rise time, fall time.

Further, on the above-mentioned circuit board in the integrated circuit (IC) chip ESD protection circuit: described integrated circuit (IC) chip key signal input pin is reset signal pin (RESET_N).

Further, on the above-mentioned circuit board in the integrated circuit (IC) chip ESD protection circuit: the value of described resistance and electric capacity is respectively 20～50 Ω and 0.01uF

Further, on the above-mentioned circuit board in the integrated circuit (IC) chip ESD protection circuit: described integrated circuit (IC) chip key signal input pin is for triggering clock signal pin or edge-triggered interrupt signal pin.

Further, on the above-mentioned circuit board in the integrated circuit (IC) chip ESD protection circuit: the value of described resistance and electric capacity is respectively 20～50 Ω and 0.001～0.0001uF.

The present invention increases R, C circuit at integrated circuit key signal pin place, can strengthen the coupling between key signal pin and the local place of working, effectively the ESD interference signal that is superimposed upon on the signal is decayed, the key signal that guarantees integrated circuit does not pass through level threshold, prevent the misoperation of circuit, strengthened the ESD protective capacities of integrated circuit.

Below in conjunction with specific embodiment the present invention is done comparatively detailed description.

Description of drawings

Fig. 1 is the circuit diagram of present integrated circuit (IC) chip when not having the ESD protection circuit.

Fig. 2 is the integrated circuit (IC) chip connection layout when having ESD protection circuit of the present invention.

Fig. 3 is the input signal that has static.

Fig. 4 is through the input signal behind the RC circuit of the present invention.

Fig. 5 and Fig. 6 are input to the signal of chip pin when not having the ESD protection circuit.

Embodiment

Embodiment 1, as shown in Figure 2, present embodiment is integrated circuit (IC) chip ESD protection circuit on a kind of circuit board, and the key signal in the integrated circuit is carried out the ESD protection, and key signal mainly contains reset signal (Reset_N), triggers clock signal, edge-triggered interrupt signal etc.Figure 2 shows that reset signal (Reset_N) increases the circuit diagram of ESD protection circuit, as shown in Figure 2, on the RESET_N pin of integrated circuit (IC) chip U1A and integrated circuit (IC) chip U2A, contact respectively respectively a resistance R 1 and R2, and between the RESET_N pin of integrated circuit (IC) chip U1A and integrated circuit (IC) chip U2A and GND, add a capacitor C 1 and C2 respectively.

The key signal input RESET_N of integrated circuit increases the protection circuit of being made up of R1, C1, and R1, C1 place near ic pin.Protection circuit is coupled the key signal at key signal input RESET_N pin place effectively by C1 on the one hand with the place of working, prevent because the circuit erroneous action that the current potential shake of place of working in the ESD process causes.On the other hand, obtained effective decay by other local signals that are coupled with ESD voltage that come such as POR_RESET_B after by the low pass filter of being formed by R1, C1, prevented from disturbing the circuit erroneous action that causes because ESD is grown, is subjected to signal transmission path.

Operation principle:

In the esd discharge process, because the interference that esd discharge forms is a very short due to voltage spikes of duration, as shown in Figure 3, the current potential of the different point of ground level no longer is consistent among the PCB, and the current potential shake of the holding wire in the plane partly under the integrated circuit and the integrated circuit also is inconsistent in the esd discharge process.

Under the situation that does not have the ESD protection circuit, in the esd discharge process, can pass through threshold level high threshold level or low-threshold-level or both as the key signal at pin place among Fig. 1, cause circuit erroneous action, reset, the register false triggering, interrupt false triggering etc. as mistake.The signal at ic pin A1 place can cause circuit erroneous action.As shown in Figure 5 and Figure 6.

Near ic pin, increase R1, C1, can strengthen the coupling between the place of working under key signal pin and the integrated circuit effectively, prevent effectively because the current potential shake on plane, place of working causes the misoperation of circuit.

In Fig. 2, by other local next signal reset signals that are coupled with ESD voltage on the pcb board, adding as shown in Figure 3 has the signal of ESD, by having obtained effective decay behind the low pass filter of being formed by R1, C1, prevent owing to signal transmission path length, be subjected to the circuit erroneous action that the ESD interference causes.The signal at ic pin place such as Fig. 4 can not cause circuit erroneous action.

The value of R1, C1 is adjusted according to the requirement of the frequency height of key signal, rise time, fall time, and R1 generally gets about 33 ohm, as 20～50 Ω; C1 triggers interrupt signal C1 for trigger clock, edge and gets little one, two order of magnitude for the desirable 0.01uF of reset signal.

Present embodiment provides a kind of ESD guard technology, increase R, C circuit at integrated circuit key signal pin place, can strengthen the coupling between key signal pin and the local place of working, effectively the ESD interference signal that is superimposed upon on the signal is decayed, the key signal that guarantees integrated circuit does not pass through level threshold, prevent the misoperation of circuit, strengthened the ESD protective capacities of integrated circuit.

Claims

1. integrated circuit (IC) chip ESD protection circuit on the circuit board, key signal on the integrated circuit (IC) chip is protected, it is characterized in that: comprise the resistance that links to each other with integrated circuit (IC) chip key signal input pin and be connected electric capacity between described integrated circuit (IC) chip key signal input and the grounding pin.

2. integrated circuit (IC) chip ESD protection circuit on the circuit board according to claim 1 is characterized in that: the value of described resistance and electric capacity is adjusted according to the requirement of the frequency height of key signal, rise time, fall time.

3. integrated circuit (IC) chip ESD protection circuit on the circuit board according to claim 1, it is characterized in that: described integrated circuit (IC) chip key signal input pin is the reset signal pin.

4. integrated circuit (IC) chip ESD protection circuit on the circuit board according to claim 3, it is characterized in that: the value of described resistance and electric capacity is respectively 20～50 Ω and 0.01uF.

5. integrated circuit (IC) chip ESD protection circuit on the circuit board according to claim 4, it is characterized in that: described resistance is 33 Ω.

6. integrated circuit (IC) chip ESD protection circuit on the circuit board according to claim 1 is characterized in that: described integrated circuit (IC) chip key signal input pin is for triggering clock signal pin or edge-triggered interrupt signal pin.

7. integrated circuit (IC) chip ESD protection circuit on the circuit board according to claim 6, it is characterized in that: the value of described resistance and electric capacity is respectively 20～50 Ω and 0.001uF～0.0001uF.