TW201340288A - Chip package structure - Google Patents

Chip package structure Download PDF

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Publication number
TW201340288A
TW201340288A TW101111122A TW101111122A TW201340288A TW 201340288 A TW201340288 A TW 201340288A TW 101111122 A TW101111122 A TW 101111122A TW 101111122 A TW101111122 A TW 101111122A TW 201340288 A TW201340288 A TW 201340288A
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Taiwan
Prior art keywords
circuit substrate
wafer
chip package
package structure
circuit
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TW101111122A
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Chinese (zh)
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TWI473242B (en
Inventor
Eric Lin
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Unimicron Technology Corp
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Priority to TW101111122A priority Critical patent/TWI473242B/en
Publication of TW201340288A publication Critical patent/TW201340288A/en
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Publication of TWI473242B publication Critical patent/TWI473242B/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

A chip package structure including a first wiring substrate, a second wiring substrate, a first chip and a plurality of first solder balls is provided. The first wiring substrate has a first surface. The second wiring substrate is located above the first surface, wherein the second wiring substrate has a containing cavity and a second surface corresponding to the first surface. The first chip is disposed on the first surface of the first wiring substrate and is electronically connected thereto. At least a part of the first chip is located within the containing cavity. The first solder balls are disposed between the first surface of the first wiring substrate and the second surface of the second wiring substrate and electronically connect the first and the second wiring substrate.

Description

晶片封裝結構Chip package structure

本發明是有關於一種晶片封裝結構，且特別是有關於一種堆疊式晶片封裝結構。This invention relates to a chip package structure, and more particularly to a stacked chip package structure.

隨著科技日新月異，積體電路(integrated circuits，IC)元件已廣泛地應用於我們日常生活當中。一般而言，積體電路的生產主要分為三個階段：矽晶圓的製造、積體電路的製作及積體電路的封裝。在目前的封裝結構中，堆疊式封裝(package on package，POP)為一種常見的封裝型態。As technology advances, integrated circuit (IC) components have been widely used in our daily lives. In general, the production of integrated circuits is mainly divided into three stages: the fabrication of germanium wafers, the fabrication of integrated circuits, and the packaging of integrated circuits. In the current package structure, a package on package (POP) is a common package type.

具體而言，晶片封裝體是經由多顆銲球來固定於另一晶片封裝體上，並藉由這些銲球與另一晶片封裝體電性連接。近年來，隨著線路基板上所需的輸入/輸出(I/O)端子數量越來越多，銲球的排列密度也日益增加，而致使銲球所需體積減小，而上下兩線路基板之間距亦隨之縮小。然而，由於晶片均具有一定的厚度，若兩線路基板間的間距縮小，則須採用薄化晶片而導致產品的成本以及晶片封裝的困難度增加。Specifically, the chip package is fixed to another chip package via a plurality of solder balls, and is electrically connected to the other chip package by the solder balls. In recent years, as the number of input/output (I/O) terminals required on a circuit substrate is increasing, the arrangement density of solder balls is also increasing, resulting in a reduction in the required volume of the solder balls, and the upper and lower circuit substrates. The distance between them also shrinks. However, since the wafers each have a certain thickness, if the pitch between the two circuit substrates is reduced, thinning of the wafer is required, resulting in an increase in the cost of the product and the difficulty in wafer packaging.

本發明提供一種晶片封裝結構，其可提高銲球密度及降低生產成本。The present invention provides a chip package structure which can increase solder ball density and reduce production cost.

本發明提出一種一種晶片封裝結構，包括一第一線路基板、一第二線路基板、一第一晶片及多個第一銲球。第一線路基板具有一第一表面。第二線路基板位於第一表面之上方，其中第二線路基板具有一容置槽及對應第一表面之一第二表面，容置槽位於第二表面。第一晶片設置於第一線路基板之第一表面上並與其電性連接，且第一晶片之至少一部分位於容置槽內。第一銲球設置於第一線路基板之第一表面及第二線路基板之第二表面之間，以電性連接第一線路基板及第二線路基板。The present invention provides a chip package structure including a first circuit substrate, a second circuit substrate, a first wafer, and a plurality of first solder balls. The first circuit substrate has a first surface. The second circuit substrate is located above the first surface, wherein the second circuit substrate has a receiving groove and a second surface corresponding to the first surface, and the receiving groove is located at the second surface. The first wafer is disposed on the first surface of the first circuit substrate and electrically connected thereto, and at least a portion of the first wafer is located in the receiving groove. The first solder ball is disposed between the first surface of the first circuit substrate and the second surface of the second circuit substrate to electrically connect the first circuit substrate and the second circuit substrate.

基於上述，本發明於第二線路基板對應於第一線路基板之表面上設置一容置槽，使設置於第一線路基板上之晶片的至少一部分容置於容置槽內，並以銲球連接第一及第二線路基板。如此，第一及第二線路基板間的間距即可有效縮小且可進而縮小銲球的體積，銲球的排列密度便可因此而提高。而且，省去了薄化晶片的製程，晶片封裝結構的生產成本可因此降低。Based on the above, the present invention provides a receiving groove on the surface of the second circuit substrate corresponding to the first circuit substrate, so that at least a portion of the wafer disposed on the first circuit substrate is received in the receiving groove, and the solder ball is used. Connecting the first and second circuit substrates. In this way, the spacing between the first and second circuit substrates can be effectively reduced, and the volume of the solder balls can be further reduced, and the arrangement density of the solder balls can be improved. Moreover, the process of thinning the wafer is omitted, and the production cost of the chip package structure can be reduced.

為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.

圖1是本發明一實施例之晶片封裝結構示意圖。請參考圖1，本實施例之晶片封裝結構100包括一第一線路基板110、一第二線路基板120、一第一晶片130及多個第一銲球140。第一線路基板110具有一第一表面112。第二線路基板120位於第一表面112之上方，其中，第二線路基板120具有一容置槽122及對應第一表面112之一第二表面124，容置槽122位於第二表面124。在本實施例中，第一線路基板110及第二線路基板120可分別為塑膠線路基板，而容置槽122之形成方式係利用雷射鑽孔，但本發明並不侷限線路基板110、120的種類及容置槽122之形成方式。1 is a schematic view showing a structure of a chip package according to an embodiment of the present invention. Referring to FIG. 1 , the chip package structure 100 of the present embodiment includes a first circuit substrate 110 , a second circuit substrate 120 , a first wafer 130 , and a plurality of first solder balls 140 . The first circuit substrate 110 has a first surface 112. The second circuit substrate 120 is located above the first surface 112. The second circuit substrate 120 has a receiving groove 122 and a second surface 124 corresponding to the first surface 112. The receiving groove 122 is located at the second surface 124. In this embodiment, the first circuit substrate 110 and the second circuit substrate 120 are respectively plastic circuit substrates, and the receiving grooves 122 are formed by laser drilling, but the present invention is not limited to the circuit substrates 110 and 120. The type and the formation of the accommodating groove 122.

承上述，第一晶片130設置於第一線路基板110之第一表面112上並與其電性連接，且第一晶片130之至少一部分容置於容置槽122內。第一銲球140分別設置於第一線路基板110之第一表面112及第二線路基板120之第二表面124之間，以電性連接第一線路基板110及第二線路基板120。在本實施例中，第一晶片130以覆晶接合的方式與第一線路基板110電性連接，且晶片封裝結構100更包括多個第二銲球190，第一線路基板110更具有相對第一表面112之一第三表面114，第二銲球190個別設置於第三表面114上，而第一線路基板110藉由第二銲球190與其他電子元件電性連接。The first wafer 130 is disposed on the first surface 112 of the first circuit substrate 110 and electrically connected thereto, and at least a portion of the first wafer 130 is received in the accommodating groove 122. The first solder balls 140 are respectively disposed between the first surface 112 of the first circuit substrate 110 and the second surface 124 of the second circuit substrate 120 to electrically connect the first circuit substrate 110 and the second circuit substrate 120. In this embodiment, the first wafer 130 is electrically connected to the first circuit substrate 110 in a flip-chip bonding manner, and the chip package structure 100 further includes a plurality of second solder balls 190, and the first circuit substrate 110 has a relative A third surface 114 of the surface 112, the second solder balls 190 are separately disposed on the third surface 114, and the first circuit substrate 110 is electrically connected to other electronic components by the second solder balls 190.

詳細而言，第二線路基板120包括一核心層126、一第一線路疊構128、一第二線路疊構129，核心層126位於第一線路疊構128及第二線路疊構129之間。在本實施例中，核心層126可為一介電核心層，線路疊構128、129可分別包括介電層、線路層及導電通孔。容置槽122則位於第二線路疊構129上。In detail, the second circuit substrate 120 includes a core layer 126, a first line stack 128, and a second line stack 129. The core layer 126 is located between the first line stack 128 and the second line stack 129. . In this embodiment, the core layer 126 can be a dielectric core layer, and the line stacks 128, 129 can respectively include a dielectric layer, a circuit layer, and a conductive via. The accommodating groove 122 is located on the second line stack 129.

如上述之配置，由於至少部分之第一晶片130容置於第二線路基板120之容置槽122內，即可在不薄化第一晶片130的情況下，有效縮減第一線路基板110與第二線路基板120的間距，如此，不僅縮小了晶片封裝結構100的厚度，更省去了薄化第一晶片130的生產成本。並且，由於縮減了第一線路基板110與第二線路基板120的間距，銲球140的體積也可隨之縮小，銲球140的排列密度便可因此而提高。As described above, since at least a portion of the first wafer 130 is received in the accommodating groove 122 of the second circuit substrate 120, the first circuit substrate 110 can be effectively reduced without thinning the first wafer 130. The pitch of the second circuit substrate 120, in this way, not only reduces the thickness of the wafer package structure 100, but also eliminates the production cost of thinning the first wafer 130. Moreover, since the pitch between the first circuit substrate 110 and the second circuit substrate 120 is reduced, the volume of the solder balls 140 can be reduced, and the arrangement density of the solder balls 140 can be improved.

在本實施例中，晶片封裝結構100更可包括一第二晶片150，第二晶片150設置於第二線路基板120相對於第一銲球140之表面上並與其電性連接。在本實施例中，第二晶片150是透過覆晶接合方式與第二線路基板120電性連接。具體而言，晶片封裝結構100更包括多個導電凸塊160，設置於第二線路基板120及第二晶片150之間，以連接第二線路基板120及第二晶片150。In this embodiment, the chip package structure 100 further includes a second wafer 150 disposed on and electrically connected to the surface of the second circuit substrate 120 relative to the first solder ball 140. In the embodiment, the second wafer 150 is electrically connected to the second circuit substrate 120 through a flip chip bonding method. Specifically, the chip package structure 100 further includes a plurality of conductive bumps 160 disposed between the second circuit substrate 120 and the second wafer 150 to connect the second circuit substrate 120 and the second wafer 150.

圖2是本發明另一實施例之晶片封裝結構示意圖。請參考圖2，本實施例之晶片封裝結構100a與圖1之晶片封裝結構100相似，惟二者主要差異之處在於：本實施例之第二晶片150是透過打線接合方式與第二線路基板120電性連接。具體而言，本實施例之晶片封裝結構100a更包括多個導線170及一封裝膠體180，導線170連接第二晶片150與第二線路基板120，且第二晶片150係藉由導線170電性連接第二線路基板120。封裝膠體180覆蓋第二晶片150及導線170。2 is a schematic view showing a structure of a chip package according to another embodiment of the present invention. Referring to FIG. 2, the chip package structure 100a of the present embodiment is similar to the chip package structure 100 of FIG. 1, but the main difference between the two is that the second wafer 150 of the embodiment is through the wire bonding method and the second circuit substrate. 120 electrical connection. Specifically, the chip package structure 100a of the present embodiment further includes a plurality of wires 170 and an encapsulant 180, the wires 170 are connected to the second wafer 150 and the second circuit substrate 120, and the second wafer 150 is electrically connected by the wires 170. The second circuit substrate 120 is connected. The encapsulant 180 covers the second wafer 150 and the wires 170.

綜上所述，本發明於第二線路基板對應於第一線路基板之表面上設置一容置槽，使設置於第一線路基板上之晶片的至少一部分容置於容置槽內，並以銲球連接第一及第二線路基板。如此，第一及第二線路基板間的間距即可有效縮小且可進而縮小銲球的體積，銲球的排列密度便可因此而提高。而且，省去了薄化晶片的製程，晶片封裝結構的生產成本也可因此降低。In summary, the present invention provides a receiving groove on the surface of the second circuit substrate corresponding to the first circuit substrate, so that at least a portion of the wafer disposed on the first circuit substrate is received in the receiving groove, and The solder balls connect the first and second circuit substrates. In this way, the spacing between the first and second circuit substrates can be effectively reduced, and the volume of the solder balls can be further reduced, and the arrangement density of the solder balls can be improved. Moreover, the process of thinning the wafer is omitted, and the production cost of the chip package structure can also be reduced.

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100、100a．．．晶片封裝結構100, 100a. . . Chip package structure

110．．．第一線路基板110. . . First circuit substrate

112．．．第一表面112. . . First surface

114．．．第三表面114. . . Third surface

120．．．第二線路基板120. . . Second circuit substrate

122．．．容置槽122. . . Locating slot

124．．．第二表面124. . . Second surface

126．．．核心層126. . . Core layer

128．．．第一線路疊構128. . . First line stack

129．．．第二線路疊構129. . . Second line stack

130．．．第一晶片130. . . First wafer

140．．．第一銲球140. . . First solder ball

150．．．第二晶片150. . . Second chip

160．．．導電凸塊160. . . Conductive bump

170．．．導線170. . . wire

180．．．封裝膠體180. . . Encapsulant

190．．．第二銲球190. . . Second solder ball

圖1是本發明一實施例之晶片封裝結構示意圖。1 is a schematic view showing a structure of a chip package according to an embodiment of the present invention.

圖2是本發明另一實施例之晶片封裝結構示意圖。2 is a schematic view showing a structure of a chip package according to another embodiment of the present invention.

100．．．晶片封裝結構100. . . Chip package structure

110．．．第一線路基板110. . . First circuit substrate

112．．．第一表面112. . . First surface

114．．．第三表面114. . . Third surface

120．．．第二線路基板120. . . Second circuit substrate

122．．．容置槽122. . . Locating slot

124．．．第二表面124. . . Second surface

126．．．核心層126. . . Core layer

128．．．第一線路疊構128. . . First line stack

129．．．第二線路疊構129. . . Second line stack

130．．．第一晶片130. . . First wafer

140．．．第一銲球140. . . First solder ball

150．．．第二晶片150. . . Second chip

160．．．導電凸塊160. . . Conductive bump

190．．．第二銲球190. . . Second solder ball

Claims (11)

一種晶片封裝結構，包括：一第一線路基板，具有一第一表面；一第二線路基板，位於該第一表面之上方，其中該第二線路基板具有一容置槽及對應該第一表面之一第二表面，該容置槽位於該第二表面；一第一晶片，設置於該第一線路基板之該第一表面上並與其電性連接，且該第一晶片之至少一部分位於該容置槽內；多個第一銲球，設置於該第一線路基板之該第一表面及該第二線路基板之該第二表面之間，以電性連接該第一線路基板及該第二線路基板。A chip package structure comprising: a first circuit substrate having a first surface; a second circuit substrate located above the first surface, wherein the second circuit substrate has a receiving groove and a corresponding first surface a second surface, the accommodating groove is located on the second surface; a first wafer is disposed on the first surface of the first circuit substrate and electrically connected thereto, and at least a portion of the first wafer is located at the second surface a plurality of first solder balls disposed between the first surface of the first circuit substrate and the second surface of the second circuit substrate to electrically connect the first circuit substrate and the first Two circuit boards. 如申請專利範圍第1項所述之晶片封裝結構，其中該第一晶片以覆晶接合方式與該第一線路基板電性連接。The chip package structure of claim 1, wherein the first wafer is electrically connected to the first circuit substrate in a flip chip bonding manner. 如申請專利範圍第1項所述之晶片封裝結構，其中該第二線路基板包括一核心層、一第一線路疊構、一第二線路疊構，該核心層位於該第一線路疊構及該第二線路疊構之間，且該容置槽位於該第二線路疊構上。The chip package structure of claim 1, wherein the second circuit substrate comprises a core layer, a first line stack, and a second line stack, wherein the core layer is located on the first line stack and The second circuit is stacked between the two lines, and the receiving groove is located on the second circuit stack. 如申請專利範圍第1項所述之晶片封裝結構，更包括：一第二晶片，設置於該第二線路基板相對於該第一銲球之表面上並與其電性連接。The chip package structure of claim 1, further comprising: a second wafer disposed on the surface of the second circuit substrate relative to the first solder ball and electrically connected thereto. 如申請專利範圍第4項所述之晶片封裝結構，其中該第二晶片是透過覆晶接合方式與該第二線路基板電性連接。The chip package structure of claim 4, wherein the second wafer is electrically connected to the second circuit substrate by flip chip bonding. 如申請專利範圍第5項所述之晶片封裝結構，更包括：多個導電凸塊，設置於該第二線路基板及該第二晶片之間，以連接該第二線路基板及該第二晶片。The chip package structure of claim 5, further comprising: a plurality of conductive bumps disposed between the second circuit substrate and the second wafer to connect the second circuit substrate and the second wafer . 如申請專利範圍第4項所述之晶片封裝結構，其中該第二晶片是透過打線接合方式與該第二線路基板電性連接。The chip package structure of claim 4, wherein the second wafer is electrically connected to the second circuit substrate by wire bonding. 如申請專利範圍第7項所述之晶片封裝結構，更包括：多個導線，連接該第二晶片與該第二線路基板；以及一封裝膠體，覆蓋該第二晶片及該些導線。The chip package structure of claim 7, further comprising: a plurality of wires connecting the second wafer and the second circuit substrate; and an encapsulant covering the second wafer and the wires. 如申請專利範圍第1項所述之晶片封裝結構，其中該第一線路基板包括塑膠線路基板。The chip package structure of claim 1, wherein the first circuit substrate comprises a plastic circuit substrate. 如申請專利範圍第1項所述之晶片封裝結構，其中該第二線路基板包括塑膠線路基板。The chip package structure of claim 1, wherein the second circuit substrate comprises a plastic circuit substrate. 如申請專利範圍第1項所述之晶片封裝結構，更包括：多個第二銲球，該第一線路基板具有相對該第一表面之一第三表面，且該些第二銲球個別設置於該第三表面上。The chip package structure of claim 1, further comprising: a plurality of second solder balls, the first circuit substrate having a third surface opposite to the first surface, and the second solder balls are individually disposed On the third surface.
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