TW201339599A - Triple-redundant failure auto-detector of analog output module - Google Patents

Abstract

An auto-detector for failure is provided. The detector detects failure of an analog output module. The detector is triple-redundant. The detector comprises an analog input unit, a multiplexer, a analog-digital converter, a microprocessor and a voltage input unit. The voltage input unit inputs a detecting voltage to the multiplexer and a voltage value is obtained by the analog-digital converter. The microprocessor processes input scan from the analog input unit to the multiplexer. Then, the analog-digital converter converts analog input data into digital input data and further compares signal values as auto-detection. Thus, the present invention reduces complexity of hardware, saves cost and enhances reliability.

Description

Triple fault-tolerant analog input module automatically detects faulty devices

The invention relates to a triple fault-tolerant analog input module for automatically detecting a fault device, in particular to a test voltage input unit inputting a test voltage to a multiplexer, and determining an analog value by an analog digital converter, and performing analog input by a microprocessor. The unit is scanned by the input of the multiplexer, and then converted into digital input data by the analog digital converter, and the signal value is automatically debugged, thereby reducing the hardware complexity, reducing the manufacturing cost, and enhancing the reliability. Efficacy.

According to the conventional triple fault-tolerant control device 6 (shown in FIG. 4), it comprises three analog input units 61 connected to each other, and a multiplexer 62 respectively connected to each type of input unit 61, and each of which is connected to each other. The analog converter 63 is connected to the microprocessor 64 of each type of digital converter 63, and the digital analog converter 65 of each of the multiplexer 62 and the microprocessor 64 respectively; thereby using three analog inputs. The input or output of unit 61 takes two majority decisions to formally input or output values as the basis for operational control.

However, in the case of the existing triple fault-tolerant control system device 6, the final decision value of the triple fault-tolerant analog input is the average value of the intermediate value or the two closest data, and the correct input data can be obtained by using this method. According to the fact that there is one input fault at the three input terminals, and the other two input terminals are still normal, the data of the faulty end will be far from the data of the normal end, and the data of the two normal ends will be quite close. As a result of the foregoing, the result obtained in the intermediate value mode is one of the two normal end data, and the result obtained in the manner of the average of the closest data is the average value of the two normal end data. For example, if the data of the two normal inputs is 101, 100, and the data of the faulty end is 10; the intermediate value is 100, and the average of the closest data is 100.5.

And the foregoing final value can be correctly obtained, but the fault only occurs on a single input terminal. If more than one input fault occurs, the obtained data cannot be ensured to be the correct value; for example, the correct input value is 100, wherein the normal input is read. 99.5. The remaining two faulty ends read 70 and 69 respectively; in the foregoing manner, the intermediate value is 70, and the average of the two closest data is 69.5, which are all incorrect values of 100.

Furthermore, if a common mode failure (such as input hardware power supply failure or analog digital conversion hardware open or short circuit) occurs, the read data may be consistent. For example, the power supply may be shorted. The result of zero reading or maximum converted data value, in the common mode fault, the current practice is generally confirmed by the read data range verification method; for example, after a period of reading, all three inputs are zero or maximum to confirm the common mode Fault; that is, the fault is detected by an over range or under range of reading range.

If the error caused by the non-common mode failure occurs, the triple fault-tolerant analog input currently only ensures that the three inputs have a fault and can ensure correct operation. Two or more faults cannot be ensured correctly. At present, some methods adopt a loop back input verification mode, and use a digital analog converter 65 output to send a known output test data voltage or current to the multiplexer during each operation cycle neutral or other neutral. 62, and then read whether the three input data meets the test data sent by the output end, and verify that the input end hardware works correctly every other period. The disadvantage of this method is that the software and hardware are complicated and the software operation cycle time is increased, and When the fault cannot be found immediately, it is necessary to wait for the neutral period after the completion of the operation cycle, and send the test data to find the fault.

In addition, the more advanced analog-to-digital conversion integrated circuit will also send a convert complete signal after the conversion is completed. It seems that it can also be used to verify that it is working correctly; however, the main purpose of this signal is to inform the back-end digits. The analog-to-digital conversion of the circuit has been completed, and it is possible to start capturing digital data, ensuring that the wrong data will not be retrieved after the conversion has not been completed, and is mainly used to verify that the hardware digits operate correctly.

In view of this, the inventors of this case have intensively discussed the above-mentioned problems of conventional inventions, and actively pursued solutions through years of experience in R&D and manufacturing of related industries. After long-term efforts in research and development, they finally succeeded in developing this book. Invented the "triple fault-tolerant analog input module automatic detection fault device" to improve the various problems of the application.

The main object of the present invention is that the test voltage can be input to the multiplexer by the test voltage input unit, and the voltage value can be judged by the analog digital converter, and the analog input unit can perform the input scan of the multiplexer by the microprocessor, and then The analog-to-digital converter converts into digital input data, and the ratio of signal values is used as automatic debugging, thereby achieving the effect of reducing hardware complexity, reducing manufacturing cost, and enhancing reliability.

For the purpose of the above, the present invention is a triple fault-tolerant analog input module automatic detection fault device, which comprises: an analog input unit; a multiplexer connected to the analog input unit; and an analog digital connection with the multiplexer a converter; a microprocessor coupled to the analog to digital converter; and a test voltage input unit coupled to the multiplexer and the microprocessor.

In the above embodiment of the invention, the analog input unit has a plurality of channels.

In the above embodiment of the present invention, the test voltage input unit includes an input selector, a first full-scale range generator connected to the input selector, and a second full-scale range generator connected to the input selector. And a third full-scale range generator connected to the input selector.

In the above embodiment of the present invention, the first full-scale range generator generates a 0.1-fold value loop setting test signal source.

In the above embodiment of the present invention, the second full-scale range generator generates a 0.5-fold value loop setting test signal source.

In the above embodiment of the present invention, the third full-scale range generator generates a 0.9-fold value loop setting test signal source.

Please refer to the "1, 2, and 3" diagrams, which are schematic diagrams of the basic architecture of the present invention, a schematic flowchart of the present invention, and a schematic diagram of the test signal source of the present invention. As shown in the figure: the present invention is a triple fault-tolerant analog input module automatic detection fault device, which at least includes an analog input unit 1, a multiplexer 2, an analog-to-digital converter 3, a microprocessor 4, and a test The voltage input unit 5 is constructed.

The analog input unit 1 mentioned above has a plurality of channels 11 to 11n.

The multiplexer 2 is connected to the analog input unit 1.

The analog digital converter 3 is connected to the multiplexer 2.

The microprocessor 4 is connected to an analog digital converter 3.

The test voltage input unit 5 is connected to the multiplexer 2 and the microprocessor 4. The test voltage input unit 5 includes an input selector 50, a first full-scale range generator 51 connected to the input selector 50, a second full-scale range generator 52 coupled to the input selector 50, and a third full-scale range generator 53 coupled to the input selector 50, wherein the first full-scale range generator 51 produces 0.1 times the value The test signal source is cyclically set. The second full-scale range generator 52 generates a 0.5-fold value loop setting test signal source, and the third full-scale range generator 53 generates a 0.9-fold value loop setting test signal source. If so, a new triple fault-tolerant analog input module is constructed by the above device to automatically detect the faulty device.

When used, three (or more) devices of the present invention may be used for the use, and in the multiplexer 2, the test voltage input unit 5 is matched with the selection of the input selector 50, and the first full-scale range generator 51 is utilized. The second full-scale range generator 52 and the third full-scale range generator 53 add a test voltage input, and the voltage value is used as a test signal source, and the analog-to-digital converter is sequentially used in each operation loop. 3 maximum input peak value (this maximum input peak value is analogous digital converter 3 converter input allow full scale range value, such as 10 volts, also known as the highest peak) 0.1 times, 0.5 times and 0.9 times value cycle, for example: this time The running loop is the highest peak of 0.1, the next running loop is the highest peak of 0.5, and the next running loop is the highest peak of 0.9, and then starting from the highest peak of 0.1, as the input sweeping operation is performed for each running loop. By the way, the function of the analog-to-digital converter 3 is verified in time, and then the input scan is used to complete the reading of the last channel 11n data in the analog input unit 1, and then the read test is added. An input signal source, to verify as the analog-digital converter 3 is operated correctly or not.

The description of the verification process steps of the analog input unit 1 of the present invention (please refer to FIG. 2):

S100: When starting operation, the test signal source is set by the previous cycle by 0.1 times, or 0.5 times or 0.9 times of the maximum input peak of the analog digital converter 3.

S101, s102: Compare whether the previous test signal source is 0.9 highest peak. If it is 0.9 times the peak value, set the peak value of the test signal to 0.1 times the peak value.

S103, s104, s105: If it is determined otherwise, whether the previous test signal source is 0.5 peak, if it is 0.5 times the peak value, set the peak value of the test signal to 0.9 times the peak value, otherwise the value is 0.5. Peak tip.

S106: Select the test signal and store the value for the next operation loop to determine the test signal source value.

S107, s108: Next, an input scan is performed, and the digital input data converted into each channel 11 to 11n by the analog digital converter 3 is sequentially read.

S109, s110: judging whether the data of all the channels 11 to 11n is read, if not, repeating steps s106, s107 and s108, if all the scanning of the channels 11 to 11n is completed, the data is first stored. The microprocessor 4 suspends processing, and then reads the test signal source; that is, the microprocessor 4 program stores the test signal source value according to s106, commands the input of the selector 50, and selects the value of the loop setting signal source to be 0.1. Or 0.5 or 0.9 highest peak, and then the test signal is converted into digital data by the analog digital converter 3, and compared with the test signal source value stored in the previous s106.

S111, s112, s113: determine whether the test signal source read value meets the test signal set value stored in the s106, if it means that the hardware function is normal and within the error range, the application program can be executed, otherwise the hardware is generated. Error warning signal.

When the 0.1 times, 0.5 times, and 0.9 times the peak value of the execution is generated, the test voltage input unit 5 can be connected in series by a plurality of resistors 54 to generate 0.1 times, 0.5 times, and 0.9 times the peak voltage in a divided manner ( As shown in FIG. 3, and with the subsequent input selector 50, the selection action of the input selector 50 can utilize the output of the microprocessor 4 to program its selection operation, and the present invention utilizes the operation. The cycle is completed in the neutral or other space to perform hardware verification. Since only the analog analog converter 3 is required to input the test signal once, the comparison is performed to judge the correct operation of the analog digital converter 3. Therefore, the verification test is performed. The steps are simple, the execution time is very short (uSec level), and the microprocessor 4 resources are hardly occupied. It has almost no influence on the operation cycle (mSec level) of the general monitoring program, and can be regarded as a non-inductive background operation, thereby achieving reliable And low-cost hardware design, and can be greatly improved compared to the current implementation speed and hardware and software cost reduction.

In summary, the triple fault-tolerant analog input module of the present invention can effectively improve the faults of the conventional use, and can input the test voltage to the multiplexer by the test voltage input unit, and judge the voltage value by the analog digital converter, and The processor executes the analog input unit through the input scan of the multiplexer, and then converts the digital input data into digital input data, and then the ratio of the signal values is automatically debugged, thereby reducing the hardware complexity and reducing the manufacturing cost. And the effect of enhancing the reliability; thereby making the invention more progressive, more practical, and more in line with the needs of the consumer, has indeed met the requirements of the invention patent application, and filed a patent application according to law.

However, the above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto; therefore, the simple equivalent changes and modifications made in accordance with the scope of the present invention and the contents of the invention are modified. All should remain within the scope of the invention patent.

(part of the invention)

1. . . Analog input unit

11~11n. . . aisle

2. . . Multiplexer

3. . . Analog digital converter

4. . . microprocessor

5. . . Test voltage input unit

50. . . Input selector

51. . . First full range generator

52. . . Second full range generator

53. . . Third full range generator

54. . . resistance

S100~s113. . . step

(customized part)

6. . . Triple fault-tolerant control device

61. . . Analog input unit

62. . . Multiplexer

63. . . Analog digital converter

64. . . microprocessor

65. . . Digital analog converter

Figure 1 is a schematic diagram of the basic architecture of the present invention.

Fig. 2 is a schematic flow chart of the present invention.

Figure 3 is a schematic diagram showing the generation of the test signal source of the present invention.

Figure 4 is a schematic diagram of a conventional triple fault-tolerant control device.

1. . . Analog input unit

11~11n. . . aisle

2. . . Multiplexer

3. . . Analog digital converter

4. . . microprocessor

5. . . Test voltage input unit

50. . . Input selector

51. . . First full range generator

52. . . Second full range generator

53. . . Third full range generator

Claims (6)

A triple fault-tolerant analog input module automatically detects faulty devices, including:
a type of input unit;
a multiplexer connected to the analog input unit;
An analog-to-digital converter connected to a multiplexer;
A microprocessor is coupled to the analog digital converter; and a test voltage input unit is coupled to the multiplexer and the microprocessor. The fault-tolerant analog input module is automatically detected according to the first aspect of the patent application scope, wherein the analog input unit has a plurality of channels. The fault-tolerant analog input module automatically detects the faulty device according to the first aspect of the patent application scope, wherein the test voltage input unit includes an input selector, a first full-scale range generator connected to the input selector, A second full-scale range generator coupled to the input selector and a third full-scale range generator coupled to the input selector. The fault-tolerant analog input module automatically detects the faulty device according to the third aspect of the patent application scope, wherein the first full-scale range generator generates a 0.1-fold loop setting test signal source. The fault-tolerant analog input module automatically detects the faulty device according to the third aspect of the patent application scope, wherein the second full-scale range generator generates a 0.5-fold value loop setting test signal source. The fault-tolerant analog input module automatically detects the faulty device according to the third aspect of the patent application scope, wherein the third full-scale range generator generates a 0.9-fold loop setting test signal source.