TW201336311A - Parallel pyramid entropy coding for video and image compression - Google Patents

Abstract

Methods, systems, and computer program products are provided to divide code blocks, such as blocks of quantized coefficient of image or video data, into smaller blocks and sub-blocks that can be processed in parallel using layered entropy coding and decoding scheme. This division is accomplished while still encoding the entire code block using the same layered entropy coding scheme.

Description

Picture system and method for video processing

The present disclosure relates generally to video processing and, more particularly, to video encoding techniques.

Many of the processing in video coding involves the processing of serial bit streams. In order to encode or decode a bitstream, the processing of these self-binding to serial operations requires a more powerful processor to do this efficiently.

In particular, when processing serial data, the clock speed becomes a limiting factor. If you need to process each piece of data before you can resolve (resolve) the next piece of data, you can increase the system speed by increasing the processing clock speed (usually linearly). However, high clock speeds require additional power and heat dissipation.

Therefore, it is desirable to provide a parallelizable coding technique.

The present invention provides a method comprising: dividing a code block into a pixel group; dividing the pixel group into sub-blocks; and encoding a pixel assigned to the sub-block using a layered coding scheme for the code block.

Preferably, dividing the code block into a pixel group comprises dividing the code block into four equal-sized pixel groups.

Preferably, dividing the pixel group into sub-blocks comprises: determining a set of cluster styles; and selecting a cluster style for configuring a corresponding sub-block of one of the pixel groups.

Preferably, selecting the cluster style comprises: determining the minimum and maximum for each sub-block Large code size; and the minimum size configuration that determines the sub-blocks for the corresponding pixel group.

Preferably, the method further comprises storing the code sizes for the sub-blocks and the pixel groups in the encoded stream using a hierarchical entropy coding scheme.

Preferably, the method further comprises: receiving a data flow including the code block; separating the code block into a pixel group using a code size and a layered decoding scheme; using the code size to open the pixel component into sub-blocks; and parallelizing Decode the sub-block.

The present invention also provides a computer readable storage device having instructions stored thereon, the instructions being executed by the computing device, the execution of the instructions causing the computing device to perform the following operations, including: dividing the code block into pixel groups; Divided into sub-blocks; and uses a layered coding scheme for code blocks to encode the pixels assigned to the sub-blocks.

Preferably, dividing the code block into a pixel group comprises dividing the code block into four equal-sized pixel groups.

Preferably, dividing the pixel group into sub-blocks comprises: determining a set of cluster styles; and selecting a cluster style for configuring a corresponding sub-block of one of the pixel groups.

Preferably, selecting the cluster pattern comprises determining a minimum and maximum code size for each sub-block; and determining a minimum size configuration for the sub-block of the corresponding pixel group.

Preferably, the operations further comprise storing the code sizes for the sub-blocks and the pixel groups in the encoded stream using a layered entropy coding scheme.

Preferably, the operations further comprise: receiving a data flow including the code block; separating the code block into a pixel group using a code size and a layered decoding scheme; using the code size to open the pixel component into sub-blocks; and decoding in parallel Subblock.

The present invention also provides a system comprising: an encoder stored in a memory and configured to perform the following operations, including: dividing a code block into a pixel group, dividing the pixel group into sub-blocks, and using A layered coding scheme of code blocks to encode the pixels assigned to the sub-blocks; and more than one processor configured to process the encoder.

Preferably, dividing the code block into a pixel group comprises dividing the code block into four equal-sized pixel groups.

Preferably, dividing the pixel group into sub-blocks comprises: determining a set of cluster styles; and selecting a cluster style for configuring a corresponding sub-block of one of the pixel groups.

Preferably, selecting the cluster pattern comprises determining a minimum and maximum code size for each sub-block; and determining a minimum size configuration for the sub-block of the corresponding pixel group.

Preferably, the encoder is further configured to: store the code sizes for the sub-blocks and the pixel groups in the encoded stream using a layered entropy coding scheme.

Preferably, the method further comprises: a decoder configured to: receive a data flow including the code block, separate the code block into a pixel group using a code size and a layered decoding scheme, and use the code size to The pixel components are opened as sub-blocks, and the sub-blocks are decoded in parallel.

100‧‧‧ Entropy coding standard

102‧‧‧Front code list

104a~104n‧‧‧ pixels

200, 500 ‧ ‧ processing

300‧‧‧Code processing

402‧‧‧8×8 code block

404a, 404b, 404c, 404d‧‧‧

405‧‧‧Sub-block

406‧‧‧Information

408‧‧‧Sub-block data

410‧‧‧ pixel data

600‧‧‧ computer system

602‧‧‧Display interface

604‧‧‧ processor

606‧‧‧Communication infrastructure

608‧‧‧ main memory

610‧‧‧Second memory

612‧‧‧ hard disk drive

614‧‧‧Removable storage drive

615, 622‧‧‧Removable storage unit

620‧‧‧ interface

624‧‧‧Communication interface

626‧‧‧Communication Path

630‧‧‧Display unit

202~210, 302~312, 502~510‧‧‧ steps

Figure 1 shows an exemplary entropy coding standard.

2 is a flow chart showing the process of steps of removing code block interdependencies in accordance with an embodiment of the present disclosure.

FIG. 3 is a flowchart showing an encoding process of a step of dividing a code block into a pixel group (sub-block) according to an embodiment of the present disclosure.

4 illustrates a manner of dividing a code block into blocks and sub-blocks in accordance with an embodiment of the present disclosure.

FIG. 5 is a flowchart showing a process of a decoding step according to an embodiment of the present disclosure.

FIG. 6 shows an exemplary computer system in which embodiments of the present disclosure may be implemented.

I. Introduction

The following detailed description refers to the accompanying drawings that illustrate exemplary embodiments. Other embodiments are also possible, and modifications may be made to the embodiments within the spirit and scope of the disclosure. Therefore, the detailed description is not intended to limit the invention. Rather, the scope of the invention is defined by the scope of the appended claims.

It will be apparent to those skilled in the art to which the present invention pertains that the present disclosure can be implemented in various embodiments, such as the software, hardware, firmware, and/or the entities shown in the drawings. Any actual software code having specific control over the hardware that implements the present disclosure is not limited to the present disclosure. Therefore, the operational behavior of the present disclosure will be described with the understanding that modifications and variations of the embodiments are possible, and within the spirit and scope of the present disclosure.

References to a module in the specification and claims are intended to mean any combination of hardware, firmware or soft component for performing the indicated function. Modules do not need to be strictly defined entities, which allows several modules to functionally overlap hardware and software components. For example, a software module can refer to a line of code within a program, which is itself a separate software program. Those of ordinary skill in the art to which this invention pertains will understand that the functionality of the modules can be defined in accordance with, for example, various formats or performance optimization techniques.

According to a disclosed embodiment, there is provided a method for dividing a code block into pixel groups for dividing a pixel group into sub-blocks, and using a code block. A coding scheme to method, computer readable storage, and system for pixel coding assigned to a sub-block.

The features and advantages of the present disclosure, as well as the structure and operation of the various embodiments of the present disclosure, are described in detail below with reference to the accompanying drawings. It should be noted that the present disclosure is not limited to the specific embodiments described herein. These embodiments are presented herein for illustrative purposes only. Based on the teachings contained herein, additional embodiments will be apparent to those of ordinary skill in the art to which this invention pertains.

Figure 1 shows an exemplary entropy coding standard 100 (prior art). Entropy coding, such as Huffman coding, relies on a corresponding variable length prefix-free codeword (or simple "code") to represent lossless (lossless) of each fixed length input. ) Data compression technology. For example, as shown in encoding standard 100, a set of pixels 104a, 104b, 104n (collectively referred to as pixels 104) are provided in the data flow. Each pixel can be composed of, for example, color intensity information including the pixel The 24-bit representation of the data (for example, 8-bit data for red, 8-bit data for green, and 8-bit data for blue). However, although the 24-bit of the data can represent 16.78 million different values, the pixel block (for example, the 16×16 pixel region in the picture) will only have at most one different value per pixel ( For example, 256 possible values). Moreover, especially after applying a lossy compression algorithm (eg, by reducing the number of unique values that can be resolved by pixel data), some repetitions are likely to mean that some pixels can have the same quantized coefficient value.

For example, assume that all pixels in a 16x16 pixel block have a color selected from a palette of only three possible colors. In this case, entropy coding may use only a maximum of two bits of data (e.g., '00=red', '01=blue', '1=yellow') to represent four possible values. These encodings are determined using known encoding techniques (such as Huffman encoding) during the encoding phase. It should be noted that in entropy coding, the code length is variable as would be understood by one of ordinary skill in the art to which the invention pertains. In the above example, after '1' is detected at the beginning of the code sequence, the color is determined to be yellow - the next bit of the data will be the beginning of the new code. The code '0' at the beginning of the code sequence only reduces the probability to 'red' or 'blue' depending on the next bit of the material.

For navigation simplicity, this behavior is typically included in a data structure such as a tree. For example, a code sequence such as "1001010111011" should be translated as 'yellow' (1), 'red' (00), 'yellow' (1), 'blue' (01), 'blue' (01), 'Yellow' (1), 'Yellow' (1), 'Blue' (01), 'Yellow' (1). The encoding itself (eg, a data structure such as a tree) may be set to a prefix code list 102 along with the encoded material. Each pixel 104 then only includes the number of data bits that are uniquely represented by their prefix code.

A serious drawback of this approach is that all code sequences must be decoded serially (sequentially). Since the segmentation between pixels is unknown in advance, it is impossible to decode the first X pixels, for example, with the first processing thread, and the second processing thread. Y pixel decoding. For example, jumping to the middle of the above example code sequence (e.g., '111011') and decoding it as usual will generate 'yellow' (1) as the first value. However, this first '1' is actually part of the encoding for 'blue' (01), but this is not possible without the serial processing of all sequences.

II. Parallelization technology

As mentioned above, existing decoding techniques must be handled in tandem. In order to understand the information needed for subsequent pixel decoding, the previous pixels must be decoded. Therefore, in order to achieve parallelism, a technique is needed to remove this interdependence.

2 is a flow diagram showing a process 200 of the steps of removing code block interdependencies in accordance with an embodiment of the present disclosure. Although one of ordinary skill in the art to which the invention pertains will appreciate that the techniques described herein can be applied at any level (e.g., with interdependent code blocks in separate pictures, interdependent pictures in separate streams, etc.) However, for example, but not limited to, a code block (eg, a 16×16 pixel block) in a picture or picture sequence is independent of other code blocks.

The method begins in step 202 and proceeds to step 204 of dividing a code block (e.g., a picture is divided into 16x16 code blocks) into pixel groups. For example, a complete picture can be divided into independent 16×16 code blocks, which in turn are divided into 8×8 pixel groups, and an 8×8 pixel group can be divided into four. A 4×4 pixel group. In step 206, a decision is made whether to further divide the new pixel group. If so, the method proceeds to step 204 to further partition the pixel groups (eg, each 4x4 pixel group can be further divided into four 2x2 pixel groups, four 4x1 The set of pixels, a combination of 2 × 1, a 2 × 3 and two 1 × 4 pixel groups ... etc.). It should be understood by those of ordinary skill in the art to which the invention pertains that the partitioning performed in step 204 can be handled by the same module or by several different modules as appropriate.

If no further partitioning is requested, then the method proceeds to step 208 where a local prefix code is provided at each layer. The method then ends at step 210. According to an embodiment of the invention, each division is named according to the layer number. The first level of all pictures The code block of the division includes "layer 0". The first group of pixels (for example, an 8×8 pixel group dividing a 16×16 code block) includes “layer 1” and the like. In the above example, layers 0 to 3 were employed.

III. Dividing code blocks

In accordance with an embodiment of the present disclosure, each code block includes a set of quantized coefficients for representing pixel values within the block. It will be understood by those of ordinary skill in the art that the code blocks can include additional or different materials, and the use of quantified coefficients is provided by way of example and not limitation. In particular, although the coefficients are typically quantized, they may be non-quantitative. Thus, the disclosed embodiments also contemplate working with a set of non-quantized coefficients.

According to an embodiment of the present disclosure, the code block is divided according to a "cluster pattern" such as a 4×4 pixel group as described above, which can be divided into four 2×2 pixels. Group, four 4x1 pixel groups, a combination of 2x1, one 2x3, and two 1x4 pixel groups, or other styles such as triangles, diagonals, or L-shaped patterns. Regardless of the style used, the encoder tells the decoder which style was selected by, for example, embedding the cluster style information in the prefix of the block or sub-block, otherwise the pattern should be known to the decoder in advance.

3 is a flow diagram showing an encoding process 300 of the steps of dividing a code block into pixel groups (sub-blocks) in accordance with an embodiment of the present disclosure. It should be understood by those of ordinary skill in the art that the present invention can be applied to various different levels of the various embodiments. The techniques described herein are provided by way of example and not limitation. For example, a 4x4 code block can be divided into four 2x2 code blocks - an implementation can always choose to make this particular partition, or a cluster style as described in further detail below can be used.

For the purposes of the examples outlined herein, the code block includes a block of pixels that are ultimately divided into 4x4 blocks (eg, a 16x16 code block is divided into 8x8 pixel groups, each 8x8 pixel group is Several pixel groups divided into 4 × 4 pixel groups. As described below, each 4x4 block is divided into further sub-blocks.

The method begins in step 302 and proceeds to determine a possible cluster to analyze Step 304 of the style. For example, if you choose between four 2x2 sub-blocks or four 4x1 sub-blocks, there are two cluster styles to analyze. Those of ordinary skill in the art to which this invention pertains will understand that multiple cluster styles are available, and that the styles analyzed can include any subset of these styles. In addition, specific styles can be used without any analysis.

In step 306, the minimum and maximum sizes for the sub-blocks are determined for a given cluster pattern. For example, through a cluster pattern of four 2x2 sub-blocks, the maximum code size used to encode each sub-block is determined. Then, through the set of four 2x2 sub-blocks, the minimum code size (ie, the code size for the individual sub-blocks with the smallest code size) and the maximum code size (ie, for individual sub-blocks with the largest code size) The code size) is determined together.

According to an embodiment of the present disclosure, the determination of the code size for each sub-block is accomplished by finding the complement size of each of the quantized coefficients of both, although those of ordinary skill in the art to which the invention pertains will understand The technique can be applied differently to other materials, or different techniques can be used to find the code size of all quantized coefficients. The maximum and minimum sizes of the sub-blocks may be determined based on the set of bytes required to represent the quantized coefficients by applying a particular code. According to an embodiment of the invention, the code is selected by a person skilled in the art of coding to encode independent quantized coefficients. As described above, this information is used to determine the minimum and maximum sizes of the corresponding cluster style (ie, the minimum and maximum code sizes for the set of sub-blocks).

In step 308, the dimensions of the various cluster styles are compared to other cluster styles. According to an embodiment of the present disclosure, minimizing a bit for a block (eg, a 4×4 block) by adding all code sizes for encoding all quantized coefficients and a prefix code size for encoding a cluster pattern The total to select a cluster style from a set of available cluster styles. For example, a decision can be made that using four 2x2 sub-blocks would require fewer bits to represent the entire block than using four 4x1 sub-blocks.

In step 310, the prefix code information for the selected configuration is stored as described below, and the method ends at step 312. As a non-limiting example, 1 is required Up to 4 bits to encode the difference between the maximum size of the coefficients of the upper left 4x4 block and the maximum size of the coefficients of each subblock in the 4x4 block, while 1 or 3 bits may be required to encode The above difference of the remaining 4×4 blocks. The algorithm can use 2 bits for the upper left 4x4 block to specify the maximum size used to encode the above difference (ie, the maximum size of the coefficients in the upper left 4x4 block and the pattern in the 4x4 block) The number of bits between the maximum size of the coefficients of the sub-blocks is the number of bits to be encoded, and 1 bit is used for the remaining 4×4 blocks to specify the bits used to encode the above difference The number of bits that are encoded, i.e., 1 or 3 bits that will be used to encode the above differences for the remaining 4x4 blocks.

According to an embodiment of the present disclosure, the size of a cluster (such as a 4x4 block) (the number of bits that will be used for encoding) is encoded as being in an upper layer (such as an 8x8 block containing the 4x4 block). A portion of the prefix, such that when the decoder decodes the bitstream, all of the bits used to encode the cluster can be extracted in parallel with all bits extracted for encoding other clusters. Apply the same idea to layers in the above example that are below the cluster level (eg, for a 4x4 block layer (layer 2) of 2x2 sub-blocks (layer 3)) (such as a cluster of 4x4 blocks) Among the four 2x2 sub-blocks, the number of bits used to encode each sub-block is encoded as a part of the prefix in the 4x4 block.

Turning to FIG. 4, as a non-limiting example consistent with embodiments of the present disclosure, an 8x8 code block 402 is shown divided into four 4x4 blocks. According to an embodiment of the present disclosure, each of the four blocks 404a, 404b, 404c, and 404d is further divided into sub-blocks according to a cluster or partition pattern.

In the case of block 404a, sub-block 405 is shown as a 2x2 block. According to an embodiment of the present disclosure, all sub-blocks 405 of block 404a are the same size. After determining the maximum size of the sub-block 405 as described above, it is compared to the maximum size of the other sub-blocks of the block 404a to determine the maximum (and minimum) size of the sub-block. Consistent with the above examples, the difference between the maximum size of block 404a and the maximum size of each sub-block may require 1 to 4 bits for encoding. Therefore, the 2-bit is specifically used to specify how many bits (from 1 to 4) are needed to encode the above difference.

The process of encoding the largest size to the size depicted in Figure 3 is done at the block level, where the maximum pattern size of each 4x4 block, i.e., 404a, 404b, 404c, and 404d, is also encoded.

4 shows, on the left hand side of the diagram, an algorithm in which the term parallel pyramid entropy coding ("PPEC") is used in accordance with an embodiment of the present disclosure. This name is derived from the concept that the expanded diagram appears to be pyramidal in shape, with the encoded pixel data 410 being the intermediate layer and the block data 406 being the top layer. In each layer, all blocks or sub-blocks can be encoded and decoded in parallel.

As shown in Figure 4, each sub-block includes encoded pixel data. As described above, the data included in each block has a number of bits for defining a bit (which is used to encode the difference between the maximum size of the block and the maximum size of each sub-block within the block), and the encoding sub-block. The bit of the data. The entire code block data includes the maximum size of each block, as well as the prefix code used to encode the pixel data (for example, the Huffman coding scheme). It will be understood by those of ordinary skill in the art to which the present invention pertains that although the present drawings show the various components described above, these components need not appear in the particular order shown in FIG. Moreover, as discussed earlier, additional layers may be introduced to provide a more detailed partitioning of sub-blocks and sub-sub-blocks. Further, a hybrid method in which a specific block is divided into sub-blocks, but other blocks are serially encoded without further division may be employed. It is to be understood by those of ordinary skill in the art that these changes and other modifications are within the spirit and scope of the disclosure.

V. Decoder side operation

Constructing a code block in the manner described above will greatly facilitate the size of the decoder. According to an embodiment of the present disclosure, a decoder operating on a code block constructed in a manner consistent with the above description may process the code blocks in parallel, and may even process the independent sub-blocks in parallel.

In the previous serial operation, each symbol within the code block needs to be decoded in order. However, by decomposing code blocks into layers as described herein, multiple symbols (eg, pixel groups, byte groups, or other groups of decodable material) can be decoded in parallel, which Provides an order of magnitude improvement for a serial processing solution running at comparable clock speeds. Alternatively, the same processing speed can be achieved using a lower clock speed, which results in high energy efficiency.

The decoder is constructed in order to parse the information included by the encoder as described above from the entire code block into separate blocks and sub-blocks. This means, for example, that the decoder should be able to understand how many divided layers are present in the code block, what cluster styles are used, and so on. All of this information is published somewhere in the header block or throughout the code block.

FIG. 5 is a flow diagram showing a process 500 of a decoding step in accordance with an embodiment of the present disclosure. The method begins in step 502 and proceeds to step 504 of dividing the block code material into separate block components (e.g., blocks 404a, 404b, 404c, and 404d of FIG. 4). In step 506, in accordance with an embodiment of the present disclosure, the various blocks are further divided into sub-blocks (eg, sub-block 405 of FIG. 4). It should be noted that because the above layers (e.g., layer 1 for layer 2 decoding) define the code size of the decoded layer, the processing of the individual blocks in step 506 can be performed in parallel. Furthermore, since the size of each sub-block is defined and already decoded, decoding of each sub-block is performed in parallel in step 508. The method ends at step 510.

VI. Example computer system implementation

Aspects of the present disclosure can be implemented by software, firmware, hardware, or a combination thereof. FIG. 6 shows an example of a computer system 600 in which the present disclosure or portions thereof can be implemented as computer readable code. For example, process 200 (FIG. 2), process 300 (FIG. 3), and process 500 (FIG. 5) can be implemented in system 600. Various embodiments of the present disclosure are described in terms of the exemplary computer system 600. After reading this description, it should be apparent that the use of other computer systems and/or computer architectures to implement the present disclosure will be apparent to those of ordinary skill in the art to which the invention pertains.

Computer system 600 includes more than one processor, such as processor 604. Processor 604 can be a dedicated purpose or general purpose processor. The processor 604 is coupled to a communication infrastructure 606 (e.g., a bus or network).

The computer system also includes a main memory 608, preferably a random access memory (RAM) And a second memory 610 can also be included. The second memory 610 can include, for example, a hard disk drive 612, a removable storage drive 614, and/or a storage bar. The removable storage drive 614 can include a floppy disk drive, a tape drive, a disk drive, a flash memory, and the like. The removable storage drive 614 reads and/or writes from the removable storage unit 615 to the removable storage unit 615 in a well known manner. The removable storage unit 615 can include a floppy disk, a magnetic tape, a compact disc, and the like that are read and written by the removable storage drive 614. As will be appreciated by those of ordinary skill in the art to which the invention pertains, the removable storage unit 615 includes a computer usable storage medium having stored software and/or material stored therein.

In an alternative implementation, the second memory 610 can include other similar devices for allowing computer programs or other instructions to be loaded into the computer system 600. Such devices may include, for example, a removable storage unit 622 and an interface 620. Examples of such devices may include a program cartridge and a cartridge interface (such as found in video game devices), a removable memory chip (such as an EPROM or PROM), and associated slots (sockets). And other removable storage units such as removable storage unit 622 and interfaces such as interface 620 that allow software and materials to be transferred from removable storage unit 622 to computer system 600.

Computer system 600 can also include a communication interface 624. Communication interface 624 allows software and data to be transferred between computer system 600 and external devices. The communication interface 624 can include a data machine, a network interface (such as an Ethernet card), a communication port, a PCMCIA card slot, and a card. The software and material transmitted via communication interface 624 may be in the form of an electronic, electromagnetic, optical signal or other signal that can be received by communication interface 624. These signals are provided to communication interface 624 via communication path 626. Communication path 626 carries signals and can be implemented using lines or cables, fiber optics, telephone lines, cellular telephone links, RF links, or other communication channels.

As used herein, the terms "computer program medium" and "computer readable medium" are used generally to refer to, for example, a removable storage unit 615, a removable storage unit 622, and a hard disk drive. The medium of the hard disk in the actuator 612. The signals carried on communication path 626 may also embody the logic described herein. The computer program medium and the computer usable medium may also refer to a memory such as main memory 608 and second memory 610, which may be a storage semiconductor (eg, DRAM, etc.). These computer program products are devices for providing a software system to system 600.

Computer programs (also referred to as computer control logic) are stored in main memory 608 and/or second memory 610. The computer program can also be received via the communication interface 624. When executed, the computer program enables computer system 600 to implement the present disclosure as described herein. In particular, when executing a computer program, the computer program enables processor 604 to perform the processes of the present disclosure, such as those described above in process 200 (FIG. 2), process 300 (FIG. 3), and process 500 (FIG. 5). step. Therefore, the computer program represents the controller of the computer system 600. The present disclosure is implemented using software. The removable storage drive 614, interface 620, hard drive 612, or communication interface 624 can be used to store the software in a computer program product and in the computer system 600.

The present disclosure also relates to a computer program product comprising software stored on a computer usable medium. Such software, when executed in more than one data processing device, causes the data processing device to operate as described herein. Embodiments of the present disclosure employ any computing available or readable medium known now or in the future. Examples of computer usable media include, but are not limited to, primary storage devices (eg, any type of random access memory), and second storage devices (eg, hard disk drives, floppy disks, CD-ROMs, ZIP disks, tapes, Magnetic storage devices, optical storage devices, MEMS, nanotechnology storage devices, etc.) and communication media (such as wired and wireless communication networks, regional networks, wide area networks, internal networks, etc.).

VII. Conclusion

It is to be understood that the specifics of the description, and not the The Summary of the Invention and the Abstract section may suggest more than one, but not all, of the embodiments of the present disclosure contemplated by the inventors, and thus, the invention The Abstract and the Abstract section are not intended to limit the scope of the disclosure and the appended claims.

The present disclosure has been described above with the aid of functional building blocks showing the implementation of specific functions and their relationships. For the convenience of the description, the boundaries of these functional building blocks are arbitrarily defined herein. As long as the specific functions and their relationships are properly performed, other boundaries can be defined.

The description of the foregoing detailed description is to be construed as a comprehensive description of the embodiments of the present invention, and the invention can be easily modified by using the technical knowledge in the field without undue experimentation without departing from the overall concept of the disclosure. And/or adjusted for various applications of this particular embodiment. Therefore, the adaptations and modifications are intended to be within the scope and meaning of the equivalents of the disclosed embodiments. It will be understood that the phraseology and terminology herein is for the purposes of the description

The scope and breadth of the disclosure should not be limited by any of the exemplary embodiments described above, but only by the scope of the appended claims and their equivalents.

200‧‧‧Process

202~210‧‧‧Steps

Claims (10)

A method comprising: dividing a code block into a pixel group; dividing the pixel group into sub-blocks; and using a layered coding scheme for the code block to encode a pixel assigned to the sub-block . The method of claim 1, wherein dividing the code block into a pixel group comprises dividing the code block into four equal-sized pixel groups. The method of claim 1, wherein dividing the pixel group into sub-blocks comprises: determining a set of cluster patterns; and selecting a cluster for configuring a corresponding sub-block of one of the pixel groups style. The method of claim 1, further comprising: storing a code size for the sub-block and the set of pixels in the encoded stream using a hierarchical entropy coding scheme. The method of claim 4, further comprising: receiving a data flow including the code block; separating the code block into a pixel group using the code size and a layered decoding scheme; The code size is described to open the pixel component into sub-blocks; and the sub-blocks are decoded in parallel. A system comprising: an encoder stored in a memory and configured to perform the operations of: dividing a code block into a pixel group, dividing the pixel group into sub-blocks, and using the code for the code a hierarchical coding scheme of the block to assign to the child A pixel encoding of the block; and more than one processor configured to process the encoder. The system of claim 6, wherein dividing the code block into a pixel group comprises dividing the code block into four equal-sized pixel groups. The system of claim 6, wherein dividing the pixel group into sub-blocks comprises: determining a set of cluster patterns; and selecting a cluster for configuring a corresponding sub-block of one of the pixel groups style. The system of claim 6 wherein the encoder is further configured to: include code for the sub-block and the set of pixels using a layered entropy coding scheme The size is stored in the encoded stream. The method of claim 9, further comprising: a decoder configured to: receive a data flow including the code block, using the code size and a layered decoding scheme The code blocks are separated into groups of pixels, the code size is used to open the pixel components into sub-blocks, and the sub-blocks are decoded in parallel.