TW201336074A - Semiconductor structure and method for forming the same - Google Patents

Abstract

A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, a first source/drain region, a second source/drain region, a first stack structure and a second stack structure. The first source/drain region is formed in the substrate. The second source/drain region is formed in the substrate. The first stack structure is on the substrate between the first source/drain region and the second source/drain region. The first stack structure comprises a first dielectric layer and a first conductive layer on the first dielectric layer. The second stack structure is on the first stack structure. The second stack structure comprises a second dielectric layer and a second conductive layer on the second dielectric layer.

Description

Semiconductor structure and method of forming same

The present invention relates to semiconductor structures and methods of forming the same, and more particularly to metal oxide semiconductors and methods of forming the same.

In recent decades, the semiconductor industry has continued to shrink the size of semiconductor structures while improving the unit cost of speed, performance, density, and integrated circuits.

For example, in order to increase the breakdown voltage (BVdss) of a semiconductor structure such as a lateral double-diffused metal oxide semiconductor (LDMOS) or an extended-dip metal-oxide-semiconductor (EDMOS), one method is to reduce the doping concentration of the drain region and Increase the drift length. However, this method increases the specific turn-on resistance (Ron, sp) of the semiconductor structure, so that the semiconductor structure cannot obtain good trade-offs of Ron, sp and BVdss to obtain a desired small sensitivity (fimure of merit; FOM= Ron, sp /BVdss).

The disclosure relates to semiconductor structures and methods of forming the same. The semiconductor structure operates well.

A semiconductor structure is provided. The semiconductor structure includes a substrate, a first source/drain region, a second source/drain region, a first stack structure, and a second stack structure. The first source/drain region is formed in the substrate. A second source/drain region is formed in the substrate. The first stack structure is on a substrate between the first source/drain region and the second source/drain region. The first stack structure includes a first dielectric layer and a first conductive layer. The first conductive layer is on the first dielectric layer. The second stack structure is on the first stack structure. The second stack structure includes a second dielectric layer and a second conductive layer. The second conductive layer is on the second dielectric layer.

A method of forming a semiconductor structure is provided. The method includes the following steps. A first source/drain region is formed in the substrate. A second source/drain region is formed in the substrate. Forming a first dielectric layer on the substrate between the first source/drain region and the second source/drain region, and forming a first conductive layer on the first dielectric layer to form a first stacked structure. Forming a second dielectric layer on the first conductive layer of the first stacked structure and forming a second conductive layer on the second dielectric layer to form a second stacked structure.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the preferred embodiment will be described in detail with reference to the accompanying drawings.

First embodiment

Figure 1 shows a top view of the semiconductor structure. 2 is a cross-sectional view of the semiconductor structure taken along line AB in FIG. 1. Figure 3 is a cross-sectional view of the semiconductor structure taken along line CD in Figure 1.

Referring to FIGS. 2 and 3, the semiconductor structure includes a substrate 102. For example, substrate 102 can include bulk silicon, silicon on insulator (SOI), and the like. The substrate 102 can be formed by an epitaxial process or a non-epilation process. The first doped region 104 includes a doping well 106 and a doping well 108. The doping well 106 is formed in the substrate 102 using a implantation step. The doping well 108 is formed in the doping well 106 using a implantation step. The second doped region 110 is formed in the doping well 106 of the first doped region 104 using a implantation step. The first source/drain region 112 is formed in the doping well 108 of the first doped region 104 using a implantation step. The second source/drain region 114 is formed in the second doping region 110 using a implantation step. The heavily doped region 116 is formed in the second doped region 110 using a implantation step.

Referring to FIGS. 1 and 2, a plurality of mutually separated insulating structures 118 are doped in the first doping region 104 between the first source/drain region 112 and the second source/drain region 114. Well 106 and doping well 108. The insulating structure 118 is not limited to the field oxide (FOX) formed by a local oxidation of silicon (LOCOS) process as shown in FIG. In an embodiment, the insulating structure 118 may comprise shallow trench isolation (STI), deep trench isolation (DTI), or other suitable structure.

Referring to FIGS. 2 and 3 , the first stacked structure 120 is formed in the first doping region 104 and the second doping region between the first source/drain region 112 and the second source/drain region 114 . 110 on. The first stacked structure 120 includes a first dielectric layer 122 and a first conductive layer 124. The first dielectric layer 122 is formed on the first doping region 104 and the second doping region 110 between the first source/drain region 112 and the second source/drain region 114. The first conductive layer 124 is formed on the first dielectric layer 122. In an embodiment, for example, the first stack structure 120 forms a dielectric material (not shown) on the substrate 102, and forms a conductive material (not shown) on the dielectric material, and then patterns the dielectric material and the conductive material. The material is formed. The dielectric material and the conductive material may be patterned while etching using the patterned mask layer such that the sides of the formed first dielectric layer 122 are aligned with the sides of the first conductive layer 124. The first dielectric layer 122 may include an oxide or a nitride such as hafnium oxide, tantalum nitride, or hafnium oxynitride. For example, the first dielectric layer 122 is an oxide or has an oxide-nitride-oxide (ONO) structure. The first conductive layer 124 can comprise polysilicon, metal halide, metal, or other suitable material.

Referring to FIGS. 2 and 3 , the second stack structure 126 is formed on the first stack structure 120 . The second stack structure 126 includes a second dielectric layer 128 and a second conductive layer 130 formed on the second dielectric layer 128. In an embodiment, for example, the second stack structure 126 is formed by forming a dielectric material (not shown) and forming a conductive material (not shown) on the dielectric material, and then patterning the dielectric material and the conductive material. . The dielectric material and the conductive material may be patterned simultaneously using a patterned mask layer such that the sides of the formed second dielectric layer 128 are aligned with the sides of the second conductive layer 130. The second dielectric layer 128 may include an oxide or a nitride such as hafnium oxide, tantalum nitride, or hafnium oxynitride. For example, the second dielectric layer 128 is an oxide or has an oxide-nitride-oxide (ONO) structure. The second conductive layer 130 may include polysilicon, metal halide, metal, or other suitable material.

Referring to FIGS. 1 and 2, the first stack structure 120 has a plurality of protrusions 132 that are separated from each other. The projections 132 of the first stack structure 120 extend beyond the second stack structure 126. In addition, the projections 132 extend correspondingly to the insulating structure 118.

Referring to FIG. 3, the second stack structure 126 is located on the top surface and the side surface of the first stack structure 120. Moreover, the second stack structure 126 can extend onto the doping well 106 of the first doped region 104.

Referring to FIGS. 2 and 3 , in some embodiments, the doping well 106 and the doping well 108 of the first doping region 104 , and the first source/drain region 112 and the second source/drain region The 114 series has a first conductivity type such as an N conductivity type. The substrate 102, the second doped region 110, and the heavily doped region 116 have a second conductivity type, such as a P conductivity type, relative to the first conductivity type. In other embodiments, the first conductivity type is a P conductivity type, and the second conductivity type is an N conductivity type.

In an embodiment, for example, the semiconductor structure is a metal oxide semiconductor such as a lateral double-diffused metal oxide semiconductor (LDMOS) or an extended drain MOS (EDMOS). The first source/drain region 112 is used as a drain. The second source/drain region 114 serves as a source. The first stacked structure 120 serves as the primary gate structure for controlling the channels of the semiconductor structure. In this example, the first dielectric layer 122 of the first stacked structure 120 is used as a gate dielectric layer, and the first conductive layer 124 of the first stacked structure 120 is used as a gate electrode layer. The second stacked structure 126 formed of the second dielectric layer 128 and the second conductive layer 130 plays an important role in the function of impedance high voltage and can reduce the accumulation layer resistance.

The semiconductor structure of an embodiment has a plurality of spaced apart insulating structures 118 in the drift region. Additionally, the projections 132 of the first stack structure 120 extend onto the insulating structure 118. It is thus possible to cause an electric field peak along the edge of the first conductive layer 124 of the first stack structure 120. In addition, the semiconductor structure can obtain a good trade-off between specific on-state resistance (Ron, sp) and breakdown voltage (BVdss) to obtain a desired figure of merit (FOM).

In an embodiment, the thickness of the first dielectric layer 122 of the first stacked structure 120 is less than the thickness of the second dielectric layer 128 of the second stacked structure 126, and thus the semiconductor structure can have a high drain breakdown voltage. In addition, the thickness of the second dielectric layer 128 is less than the thickness of the insulating structure 118, thereby reducing the resistance of the accumulation layer of the semiconductor structure. In more detail, the first dielectric layer 122 and the second dielectric layer 128 may each have a uniform thickness. In the example where the insulating structure 118 has a non-uniform thickness, the thickness of the second dielectric layer 128 is less than the maximum thickness of the insulating structure 118. For example, the thickness of the second dielectric layer 128 is less than the maximum thickness of the insulating structure 118 that is a field oxide.

The semiconductor structure of the embodiment can be formed by a CMOS process having a poly-insulator-poly capacitor (PIP) process, so that the process can be compatible with the process of other devices and the manufacturing cost is reduced.

Second embodiment

4 and 5 illustrate cross-sectional views of the semiconductor structure. The top view of the semiconductor structure of the second embodiment can be similar to FIG. For example, Figure 4 is drawn along line AB in Figure 1. Figure 5 is drawn along the CD line in Figure 1. The semiconductor structure shown in FIGS. 4 and 5 differs from the semiconductor structure shown in FIGS. 2 and 3 in that the semiconductor structures shown in FIGS. 4 and 5 are omitted from FIG. 2 and FIG. The doping well 108 of the first doped region 104 in the figure. In other words, the first source/drain region 212 is formed in the doping well 206 of the first doped region 204.

Third embodiment

Figure 6 shows a top view of the semiconductor structure. Figure 7 is a cross-sectional view of the semiconductor structure taken along line EF of Figure 6. The semiconductor structure of the third embodiment illustrated in FIGS. 6 and 7 is different from the semiconductor structure of the first embodiment illustrated in FIGS. 1 and 2 in that the insulating structure 318 is formed in the first doping region. The doping well 306 of 304. In one embodiment, the cross-sectional view of the semiconductor structure along line GH in FIG. 6 is similar to FIG.

Fourth embodiment

Figure 8 is a top view of the semiconductor structure. Figure 9 is a cross-sectional view of the semiconductor structure taken along line IJ of Figure 8. Figure 10 is a cross-sectional view of the semiconductor structure taken along line KL of Figure 8. The difference between the semiconductor structure shown in FIGS. 8 to 10 and the semiconductor structure shown in FIGS. 1 to 3 is that the second stacked structure 426 has a plurality of mutually separated projections 434 extending beyond the first. Stack structure 420. Referring to FIGS. 8 and 9 , the protrusion 434 of the second stacked structure 426 extends over the doping well 406 of the first doping region 404 between the insulating structure 418 and the first stacked structure 420 . In addition, the projections 434 extend correspondingly to the insulating structure 418, thereby enabling an electric field peak along the edges of the second conductive layer 424 of the second stacked structure 426. In addition, the semiconductor structure can be well balanced with Ron, sp and BVdss to achieve the desired FOM. Referring to FIG. 10, the second stack structure 426 is located on the top surface and the side surface of the first stack structure 420.

Fifth embodiment

Figure 11 is a top view of the semiconductor structure. Figure 12 is a cross-sectional view of the semiconductor structure taken along line MN of Figure 11. The semiconductor structure of the fifth embodiment shown in FIGS. 11 and 12 differs from the semiconductor structure of the fourth embodiment shown in FIGS. 8 and 9 in that a plurality of mutually separated top doped regions 536 are Correspondingly formed in the doping well 506 of the first doped region 504 below the insulating structure 518. In an embodiment, the top doped region 536 has a second conductivity type, such as a P conductivity type. The use of a top doped region 536 can reduce the specific turn-on resistance of the semiconductor structure and increase the breakdown voltage. In one embodiment, the cross-sectional view of the semiconductor structure along the OP line in FIG. 11 is similar to FIG.

According to the above embodiment, the semiconductor structure has insulating structures separated from each other, and the protrusions of the first stacked structure or the second stacked structure are correspondingly extended to the insulating structure. Therefore, the semiconductor structure can obtain a good balance of specific on-state resistance (Ron, sp) and breakdown voltage (BVdss), and obtain a desired figure of merit (FOM). The thickness of the first dielectric layer of the first stacked structure is less than the thickness of the second dielectric layer of the second stacked structure, thereby increasing the drain breakdown voltage of the semiconductor structure. In addition, the thickness of the second dielectric layer is less than the thickness of the insulating structure, which can reduce the electrical resistance of the accumulation layer of the semiconductor structure. The use of a top doped region can reduce the specific turn-on resistance of the semiconductor structure and increase the breakdown voltage. The semiconductor structure of the embodiments is compatible with the fabrication of other devices and is inexpensive to manufacture.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

102. . . Base

104, 204, 304, 404, 504. . . First doped region

106, 108, 206, 306, 406, 506. . . Doping well

110. . . Second doped region

112, 212, 512. . . First source/bungee area

114,514. . . Second source/bungee area

116. . . Heavily doped region

118, 318, 418, 518. . . Insulation structure

120, 420. . . First stack structure

122. . . First dielectric layer

124. . . First conductive layer

126, 426. . . Second stack structure

128. . . Second dielectric layer

130, 430. . . Second conductive layer

132, 434. . . Protrusion

536. . . Top doped region

1 is a top view of a semiconductor structure in accordance with an embodiment.

2 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

3 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

4 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

FIG. 5 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

Figure 6 illustrates a top view of a semiconductor structure in accordance with an embodiment.

FIG. 7 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

Figure 8 illustrates a top view of a semiconductor structure in accordance with an embodiment.

Figure 9 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

Figure 10 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

11 is a top view of a semiconductor structure in accordance with an embodiment.

Figure 12 is a cross-sectional view of a semiconductor structure in accordance with an embodiment.

102. . . Base

104. . . First doped region

106, 108. . . Doping well

110. . . Second doped region

112. . . First source/bungee area

114. . . Second source/bungee area

116. . . Heavily doped region

118. . . Insulation structure

120. . . First stack structure

122. . . First dielectric layer

124. . . First conductive layer

126. . . Second stack structure

128. . . Second dielectric layer

130. . . Second conductive layer

132. . . Protrusion

Claims (10)

A semiconductor structure comprising:
a substrate;
a first source/drain region formed in the substrate;
a second source/drain region formed in the substrate;
a first stacked structure on the substrate between the first source/drain region and the second source/drain region, wherein the first stacked structure comprises a first dielectric layer and a first conductive layer The first conductive layer is located on the first dielectric layer; and a second stacked structure is disposed on the first stacked structure, wherein the second stacked structure includes a second dielectric layer and a second conductive layer. The second conductive layer is on the second dielectric layer. The semiconductor structure of claim 1, wherein the first dielectric layer has a thickness less than a thickness of the second dielectric layer. The semiconductor structure of claim 1, further comprising a plurality of mutually separated insulating structures on the substrate between the first source/drain region and the second source/drain region. The semiconductor structure of claim 3, wherein the thickness of the second dielectric layer is less than the thickness of the insulating structure. The semiconductor structure of claim 3, wherein the first stacked structure or the second stacked structure has a plurality of mutually separated projections correspondingly extending to the insulating structures. The semiconductor structure of claim 5, wherein the protrusion of the second stacked structure extends over the substrate between the insulating structure and the first stacked structure. For example, the semiconductor structure described in claim 1 of the patent scope further includes:
a first doped region formed in the substrate and having a first conductivity type; and a second doped region formed in the first doped region and having a first conductivity type Second conductivity type,
Wherein the first source/drain region is formed in the first doped region and has the first conductivity type, and the second source/drain region is formed in the second doped region and has the first Conductive type. The semiconductor structure of claim 7, further comprising a plurality of mutually separated top doped regions, the first formed between the first source/drain region and the second source/drain region In the doped region, and having the second conductivity type. The semiconductor structure of claim 1, wherein a side of the first dielectric layer is aligned with a side of the first conductive layer, and a side of the second dielectric layer is aligned with the second conductive layer. Side of the side. A method of forming a semiconductor structure, comprising:
Forming a first source/drain region in a substrate;
Forming a second source/drain region in the substrate;
Forming a first dielectric layer on the substrate between the first source/drain region and the second source/drain region, and forming a first conductive layer on the first dielectric layer to form a first stacked structure; and forming a second dielectric layer on the first conductive layer of the first stacked structure, and forming a second conductive layer on the second dielectric layer to form a second stack structure.