TW201332065A - Interposer for hermetic sealing of sensor chips and for their integration with integrated circuit chips - Google Patents

Abstract

Integration of sensor chips with integrated circuit (IC) chips. At least a first sensor chip including a first sensor is affixed to a first side of an interposer to hermitically seal the first sensor within a first cavity. An IC chip is affixed to a second side of the interposer opposite the first sensor, the IC chip is electrically coupled to the first sensor by a through via in the interposer. In embodiments, the first sensor includes a MEMS device and the IC chip comprises a circuit to amplify a signal from the MEMS device. The interposer may be made of glass, with the first sensor chip and the IC chip flip-chip bonded to the interposer by compression or solder. Lateral interconnect traces provide I/O between the devices on the interposer and/or a PCB upon which the interpose is affixed.

Description

Hermetic seal for sensor wafers and interposer for integrated circuit chip integration

Embodiments of the present invention are generally in the field of microelectronic packaging, and more particularly, with respect to package level integration of sensors in integrated circuits (ICs).

Many techniques use IC chips (such as those used to adjust and/or process signals generated by sensors) to integrate sensors such as accelerometers, gyroscopes, and the like. While monolithic integration of sensors and ICs has been made in several applications, monolithic integration is an expensive option, and sensors are typically required to be fabricated on top of a complex IC stack. As the complexity of ICs and sensors continues to increase, the single-rock solution becomes less attractive because the cost and intimacy of the IC with the sensor will limit the flexibility/diversity of the catalog.

Board level integration is another technique in which packaged sensor wafers and packaged IC wafers are placed onto a printed circuit board (PCB). At this level of integration, there is little difference between the sensor wafer and the IC chip, so that the combined technique advantageously advances continuously; however, the main disadvantage of the board level integration is the size due to the many packaged devices. Effectively increased. Typically, the respective package contains an organic package substrate that has been established to a thickness of a millimeter, and the encapsulation material also increases the wafer size of the wafer laterally. During the PCB assembly, the alignment limit of the pick and place tool further limits the assembly density of the device.

Encapsulation level integration is the third technology, which falls somewhere between the integration technologies of the single stone and board level. Package level integration typically involves bonding multiple wafers to a single organic package substrate. 1 is a cross-sectional view of integrated package 100 including sensor wafers 108 and ICs 109 attached to an organic package substrate 120 having cores 125 with build layers 130, 131 in which interconnect traces 135 are embedded. The difference between the sensor wafer and the IC wafer becomes apparent for package level integration. For example, although IC 109 is typically flip-chip bonded to organic package substrate 120, sensor wafer 108 is typically not flip chip bonded because sensor wafer 108 has ceramic cover 110 when received from a sensor supplier. To provide protection and hermetic sealing of the sensor 105 within the cavity 207. Therefore, in order to provide an electrical connection 116 between the sensor 105 and the organic package substrate 120, a through via (TSV) 115 is formed through the germanium substrate 101. However, TSVs are not easy to form and, therefore, are expensive. Another problem faced by package level integration is that the thickness of the organic package substrate 120 is relatively large, so that the thickness T1 is about 500 micrometers (μm) or more due to the wafers 108, 109 attached to one side of the organic package substrate 120. Big. If an additional device is attached to the second side of the organic package substrate 120, the thickness is even increased more. Thus, even if the integrated package 100 is bonded to the PCB (eg, with solder bumps 140), the integrated package 100 requires a larger physical space than when integrated in a single stone. This larger physical size not only limits the formation factor of the end user device, but the performance of the sensor can be reduced due to the larger interconnect track length between the sensor 105 and the IC die 109 relative to the solitary implementation. .

Therefore, the above limitations of the prior art can be overcome to integrate the sensor And IC wafers and their techniques for generating structures are advantageous.

In the following description, numerous details are set forth; however, it will be apparent to those skilled in the <RTIgt; In order to avoid obscuring the present invention, the well-known methods and devices are shown in block diagram form and not in detail. Reference throughout the specification to the "embodiments" is intended to encompass the particular features, structures, functions, or characteristics described in connection with the embodiments. The appearances of the phrase "in the embodiment" are, Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, the first embodiment can be combined with the second embodiment, and the two embodiments are not mutually exclusive.

The terms "coupled" and "connected" with their derivatives may be used herein to describe the structural relationships between the components. It should be understood that such terms are not intended as synonyms for each other. Rather, in particular embodiments, "connected" may be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupling" may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other (with other intervening elements therebetween), and/or that the two or more elements cooperate with each other Or interaction (for example, as in the context of efficacy relationships).

As used herein, "above", "under" The terms "face", "between", and "above" refer to the relative position of a layer of material relative to other layers. Therefore, a layer disposed above or below another layer may be associated with the other layer. Direct contact, or may have one or more intervening layers. Further, a layer disposed between the two layers may be in direct contact with the two layers, or may have one or more intervening layers. In contrast, above the second layer The first layer is in direct contact with the second layer.

Embodiments of the present invention use an interposer to hermetically seal the sensor within the cavity and provide a point of physical and electrical coupling of the sensor die to the IC die. Although many of the technical advantages apparent to the skilled reader are described below, an initial significant interposer has the advantage that multiple sensor wafers can be mounted to the same interposer such that a hermetic seal is provided for all senses. Tester chips, regardless of their function or source of supply. Another significant advantage of the interposer is that the IC wafer can be mounted to the side with the sensor wafer mounted therein by electrically coupling the vias of the two wafers to the interconnect length that is closer to the interconnect length of the monolithic integration. Opposite side. Yet another advantage is the low material cost for the interposer relative to the germanium substrate and TSV, and the low cost of forming the through via. While these advantages all contribute to reducing physical size, embodiments in which the interposer is directly mounted to the PCB have a further reduction in physical size by eliminating any organic package substrate. A further significant advantage is that the lateral interconnect traces can be formed on the interposer at a low cost, providing I/O to the interposer and a wide variety of wafers between the interposer and the PCB.

2 is a diagram of integrating first and second IC chips with first, second, and third sensor wafers 208A, 208B, 208C in accordance with an embodiment of the present invention. A cross-sectional view of representative system 200 of 205A, 205B on interposer 201. Generally, the sensor and IC chip are attached to both sides of the interposer 201. In the illustrative embodiment, the first sensor wafer 208A disposed on the first substrate is attached to the first side 202 of the interposer 201, and the IC wafer 205A disposed on the second substrate is overcoated. The crystal (C4) is connected to 222A and attached to the second side 203 of the interposer 201. Therefore, the expensive TSV does not need to pass through the substrate of the IC wafer 205A or the substrate of the first sensor wafer 208A.

Although the IC chips attached to the interposer 201 can be any analogous, digital, or analogous to the control of the sensor wafers 208A, 208B, and/or 208C or the processing of their signals in the art. The signal circuit is mixed, but in the representative embodiment, the first IC wafer 205A has a functional correspondence with a sensor wafer disposed most relative to the IC wafer. For example, the first IC die 205A has a functional correspondence with the first sensor die 208A, and the second IC die 205B has a functional correspondence with the second and third sensor wafers 208B, 208C. In one of the embodiments, the first IC die 205A includes an amplifier circuit to amplify signals received from the first sensor die 208A (i.e., as produced by the sensor 105). Because the sensor 105 can provide a signal having a relatively low signal-to-noise ratio (SNR), the I/O of the first IC chip 205A is performed by the through-hole 250A for the lowest signal loss and crosstalk. , is beneficial. In the depicted embodiment, the first sensor chip 208A and 205A of the first line across the thickness of the IC chip interposer approximate alignment, and both the minimum permitted by the intermediary of its line defining the nature of the layer thickness T ₂ of the The length of the via interconnect 250A is electrically coupled. In a further embodiment, the interposer thickness T ₂ is less than the lateral spacing between the devices disposed on the same side of the intermediate layer (eg, side 202) such that the via 250A connects the amplifier circuit to the sensor 105. The interconnect track length is minimized. For example, depending on whether the material selected with the interposer 201 and the additional package substrate are to be used, the interposer thickness T ₂ may range between about 100 micrometers (μm) and about 500 micrometers, and at the same time, the sensor The wafer lateral dimension S ₁ may range from 1 millimeter (mm) to 2 millimeters, or larger, and the lateral gap G ₁ anywhere between adjacent devices is 200 micrometers to 1 millimeter. In another embodiment depicted by FIG. 2, the second IC die 205A is coupled to both the second and third sensor wafers 208B and 208C for receiving from the second and third senses. The output signal of one of the transistors 208B, 208C transmits a signal to the other of the second and third sensor wafers 208B, 208C. By routing the through holes 250B to both the second and third sensor wafers 208B, 208C, the three wafers 205B, 208B, and 208C can be closely placed and intimately combined in a level of competition with the monolithic integration. No accompanying costs, and loss of flexibility at the device level.

As further shown in FIG. 2, the first sensor wafer 208A includes the sensor wafer substrate 101A and is surrounded by the sensor 105 in the cavity 207 between the sensor wafer substrate 101A and the interposer 201. The inner hermetic seal 210A is attached to the interposer 201. Thus, in essence, the sensor wafer 208A is flip-chip bonded to the bond pads on the interposer 201, and the interposer 201 forms a hermetic cap material that covers the sensor 105. According to the lateral dimension S _{1 of the} sensor wafer and the tolerance limit of the sensor 105 for contamination, the electrical connection between the sensor and the through hole is in the airtight cavity (for example, the connection 212A and the through) Hole 250A), or an electrical connection between the sensor and the through hole, is disposed outside of the hermetic seal (eg, connection 212C and through hole 250B) to maintain cavity 207 without solder. By electrically connecting 212A on the same side of the sensor wafer 208A as the sensor 105, there is no need to form a TSV through the sensor substrate 101A, which typically has 50 to 500 microns. Thickness of 矽.

The second and third sensor wafers 208B, 208C disposed on the second and third substrates 101B, 101C are also attached to the first side 202 of the interposer 201. Although the second and third sensor wafers 208B, 208C are selectively attachable to the second side 203 of the interposer 201, as described elsewhere herein, sealing all of the sensor wafers in the interposer A plurality of sensor wafers on the same side can be relatively easy. While each of the sensor wafers 208A, 208B, 208C may be identical, in advantageous embodiments, the sensor wafers are at least different articles and, preferably, different functions. In an embodiment, at least one of the sensor wafers 208A, 208B, 208C requires a cavity 207 to function. In one of the embodiments, at least one of the sensor wafers 208A, 208B, 208C includes a microelectromechanical system (MEMS) having an unlocking structure to enable the unlocking structure to be relative to the sensor wafer 101 is anchored to the sensor wafer substrate 101 in a manner that is physically placed within the cavity 207. For example, the first sensor die 208A can include any MEMS accelerometer that is well known in the art, and since embodiments of the invention are not limited in this respect, Further explanation is provided herein. In a further embodiment, the second sensor wafer 208B is accompanied by a second MEMS device having a function other than an accelerometer. In a representative embodiment, a second sensor wafer 208B comprising any of the MEMS gyroscopes known in the art is bonded to the interposer 201 by a hermetic seal 210B, which can be sealed It is the same or different structure as the hermetic seal 210A. The third sensor die 208C can be any other MEMS-based or non-MEMS sensor known in the art. In a representative embodiment, a third sensor wafer 208C comprising any of the MEMS resonators known in the art is bonded to the interposer 201 by a hermetic seal 210C, which can be sealed It is the same or different structure as the hermetic seals 210A and 210B.

In an embodiment, the interposer 201 includes lateral electrical interconnect traces 251 electrically coupled to one or more of the first, second, and third sensor wafers 208A, 208B, 208C Together with and/or to the IC chip attached to the first interposer side 202, and/or electrically coupled to the first IC die 205A to the second IC die 205B attached to the second interposer side 203. The lateral electrical interconnect traces 251 can further electrically route the traces from all devices attached to the interposer 201 to the electrical connections 232 directly attached to the PCB 260, and in a representative embodiment, form an integrated system 200. In an alternative embodiment, the electrical connections 232 are attached to an organic package substrate (not depicted), and the organic package substrate is then attached to the PCB 260. In either embodiment, the lateral electrical interconnect traces 251 can be copper or aluminum, etc., if conventional wafer level thin film fabrication techniques are used. Or; advantageously, an anisotropic conductive adhesive (ACA) laminated or printed onto the interposer 201, if using LCD fabrication techniques. The ACA technology includes an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), and the like. The lateral electrical interconnect traces 251 can be any ACA material known in the art of liquid crystal displays (LCDs) or thin film transistors (TFTs). Lateral electrical interconnect traces 251 are formed in dielectric layers 240 and 241 deposited on interposer 201. For example, dielectric layers 240 and 241 may be cerium oxide, or preferably tantalum nitride, to form a hermetic barrier at a lower thickness than cerium oxide.

In an embodiment, the interposer 201 is 100 to 500 microns thick glass. In general, any glass known to be suitable for LCD applications can be used, and a representative interposer 201 is a borosilicate glass. The LCD glass embodiments have thermal expansion coefficients that are well matched to the thermal expansion coefficients (CTE) of the sensor wafers 208A, 208B, 208C and IC wafers 205A, 205B. LCD glass materials are also relatively inexpensive compared to many other potential interposer materials such as tantalum. As described elsewhere herein, the LCD glass is also modified for the formation of the through vias 250A, 250B, while allowing the vertical electrical interconnection to be lower than the TSV requiring erosion and/or depth 矽 plasma etch processing. The cost is formed. Moreover, the LCD glass provides a low-contaminant material that is well hermetically sealed by the sensor wafers 208A, 208B, and 208C.

The general architecture and materials used in the embodiments of the invention illustrated by the integration system 200 are utilized. 3A, 3B, 3C, and 3D are further cross-sectional views of electrical and hermetic joint structures that can be used in accordance with embodiments of the present invention. As described above, when the assembly order can be mixed and assembled, it is mixable The sensor wafer and the IC chip are on the same side of the interposer. However, in an advantageous embodiment, the sensor wafers requiring a hermetic cavity are disposed on an interposer surface (side) and the IC wafer is disposed on the opposite interposer surface (side). For example, the embodiments enable the hermetic cavity to be first joined to a very clean surface (eg, glass) in a bonding sequence, for example, in a clean situation. In the representative embodiments depicted in Figures 3A, 3B, 3C, and 3D, the hermetic seal to the interposer is less fluxed. In a further embodiment in which the sensor is highly sensitive to contaminants, the bonding material has a low vapor pressure at the junction temperature.

In the first embodiment depicted in FIG. 3A, the electrical connections are made between direct contact pads 327 and interposer pads 328 in a direct metal compression bond, each of which may be, for example, gold ( Au) or copper (Cu) to form an intrinsic, Au or Cu joint. One or more of the interposer pads 328 can be directly coupled to the through holes 250A. As further shown in Figure 3A, the hermetic seal 210A is achieved as a continuous loop of frit. The frit has the advantage of being directly bonded to the massive surface of the sensor wafer (i.e., without pads) and the interposer (having a glass or other dielectric surface). In a representative embodiment, the sensor pads 327 are disposed on the base 318 to adequately separate the sensor wafer from the hermetic seal 210A. In an alternative embodiment, a bottom pad 318 can be disposed over the interposer 201 to accommodate sensor wafers from different sources and/or different structures. More generally, any one of the hermetic seal 210A, the pads 327, 328 can be placed on the mechanical mount as needed.

In the second embodiment depicted in Figure 3B, the electrical connection and the gas Both of the tight seals are provided by metal-to-metal compression bonding. For this embodiment, the sensor metal ring pads 337 and the interposer metal ring pads 338 are joined to form, for example, essentially a joint of Au or Cu, while continuously surrounding the sensor 105 and sealing the cavity 207. As with the individual electrical connections, the sensor metal ring pads 337 are disposed on the base 319, although the interposer metal ring pads 338 may also be coupled to the base 319, or instead of the base 319, be placed in the mount on. With the Au-Au or Cu-Cu hermetic seal of compression bonding, the electrical connection including the sensor pad 337 and the interposer pad 328 is compression-bonded Au-Au or Cu-Cu, as used for The embodiment of Figure 3A is described.

In the third embodiment depicted in FIG. 3C, the electrical connection includes a solder joint 348 that couples the sensor pads 327 to the interposer pads 328, while the hermetic seal 210A is a frit. In this embodiment, the solder is preferably deposited on the interposer 201 using conventional techniques (eg, electroplating, microspheres, solder paste, reflow, etc.), and the sensor pads 327 are A metal coating finish that minimizes oxidation (making the flux avoidable) and compatible with the selected solder. In a particular embodiment, the sensor pad 327 includes at least one of Au, Pt, or Pd.

In the fourth embodiment depicted in FIG. 3D, the electrical connections and hermetic seals comprise solder joints 348, 358, respectively. These solder embodiments are advantageous for relaxing flatness or leveling the bond with respect to embodiments of compression bonding. As with the embodiment for compression bonding, the solder sealing ring includes a sensor metal ring pad 337 and an interposer metal ring pad 338. Preferably, the sensor metal ring pad 337 and the interposer metal ring pad 338 are combined. The solder joint 358 is the same solder composition as the electrical solder joint 348.

Embodiments using solder joints that couple the sensor wafer to the interposer can use different types of solder. 4A and 4B are cross-sectional views of solder joints according to two of the embodiments. In the first embodiment depicted in FIG. 4A, the solder joint 358 that bonds the sensor wafer to the interposer is a fixed solder composition having a sufficiently high melting temperature, and a solder composition having a lower melting temperature. The subsequent solder bonding (e.g., electrical connections 222A and 232) between the interposer and the IC die and/or PCB does not compromise the solder joint 358. For embodiments using a plurality of sensor wafers on a single interposer, the same solder composition can be used for all of the sensor wafers. As depicted in FIG. 4A, the sensor pads 337 and the interposer pads 338 serve as a mechanical substrate for the solder joints 358 with minimal solder-pad response, resulting in a large block composition of the solder joints 358. The composition of the metal alloy components in the as-deposited solder is substantially the same. Representative high temperature solder alloys that may be used include, but are not limited to, cadmium-silver binary alloys (eg, Cd ₉₅ Ag ₅ ), zinc-tin binary alloys (eg, Zn ₉₅ Sn ₅ ), gold-bismuth A meta-alloy (for example, Au _96.8 Si _3.2 ), a gold-niobium binary alloy (for example, Au _87.5 Ge _12.5 ), and a gold-indium binary alloy (for example, Au ₈₂ In ₁₈ ).

For such embodiments, in the integrated system 200 (Fig. 2), the hermetic seal 210A and/or the electrical connection 212A of the interposer 201 can be a first solder joint having a high melting temperature composition, and at the same time The first IC wafer 205A is comprised of a composition comprising a low melting temperature (eg, binary The second solder joint of the SnAg alloy is electrically connected to the interposer 201 by the electrical connection 222A.

In the second embodiment depicted in FIG. 4B, the solder joint 358 that bonds the sensor wafer to the interposer is reactive solder. The solder joint 358 has a composition having a low melting temperature, but reacts to form an intermetallic compound or solid melt having a sufficiently high melting temperature to allow subsequent solder bonding between the interposer and the IC wafer and/or PCB ( For example, electrical connections 222A and 232) do not damage solder joint 358. As depicted in FIG. 4B, the sensor pads 337 and the interposer pads 338 react during bonding to form a component having both solder from the pads 337, 338 and the non-deposited solder. The solder joint 358A of the composition. After a higher temperature anneal, the entire solder-pad reaction results in an intermetallic or solid melt 358B. Representative low temperature solder alloys that can be used to form such intermetallic or solid melts include, but are not limited to, indium (In) and alloys thereof. For a representative In solder and Cu pads 337, 338, a Cu _x In _1-x solid melt having a higher melting temperature than In is formed. For a representative In solder and Au pads 337, 338, an Au _x In _1-x solid melt having a higher melting temperature than In is formed.

For such embodiments, in the integrated system 200 (Fig. 2), the hermetic seal 210A and/or the electrical connection 212A of the interposer 201 may be a first solder joint having a reactive intermetallic composition, and At the same time, the first IC wafer 205A is physically attached to the interposer 201 by an electrical connection 222A comprising a second solder joint of a low melting temperature composition (eg, a binary SnAg alloy).

According to this embodiment, the IC wafer can be bonded to the interposer with or without an underfill. 5A is a cross-sectional view of the first IC wafer 205A that is flip-chip bonded to the interposer 201 without the underfill (eg, voids) between the electrical connections 222A. 5B is a cross-sectional view of the first IC wafer 205A that is flip-chip bonded to the interposer 201 with the underfill 255 between the electrical connections 222A. From the mechanical perspective view of the embodiment for the glass interposer, the underfill 255 may be dispensed with because the CTE mismatch between the interposer and the IC wafer (substantially, germanium) is small. However, in order to achieve this simplification in the architecture, the IC wafer should be soldered with a composition having a higher melting temperature than the solder composition used for the bonding of the interposer (eg, to the PCB), such that the The sexual connection 222A does not split during the subsequent solder reflow. Thus, for embodiments in which a higher temperature solder composition is used for the sensor wafer, three solder compositions having three melting temperatures will be used. For example, in the embodiment depicted in FIG. 2, the electrical connections 212A, 212B, 212C and/or the hermetic seals 210A, 210B, 210C comprise a first solder joint having a first composition having a highest melting temperature, The electrical connection 222A includes a second solder joint having a second composition having an intermediate melting temperature, and the electrical connection 232 includes a third composition having a melting temperature lower than a melting temperature of both the first and second solder joints. Third solder joint.

Figure 6 is a functional block diagram of an mobile computing platform 700 using an integrated system 200 in accordance with an embodiment of the present invention. The mobile computing platform 700 can be any portable device that is configured for electronic data display, electronic data processing, and wireless electronic data transmission. For example, mobile computing platform The 700 can be any of a tablet computer, a smart phone, a laptop personal computer, and the like, and includes a display screen 705, a board level integration device 710, and a battery 713; in a representative embodiment, the display screen 705 series touch screen (capacitive, inductive, resistive, etc.). As depicted, the greater the level of integration of the board level integration device 710, the larger the portion of the mobile computing device 700 that may be occupied by the battery 713 or a memory such as a solid state drive (not depicted) for the largest platform. Functional use. Thus, as described herein, the ability of the IC wafer to integrate the sensor wafer onto the interposer disposed directly on the PCB enables the performance and formation factors of the mobile computing platform 700 to be further enhanced.

The board level integration device 710 is further depicted in an expanded view 720. According to this embodiment, the board level integration device 710 includes one or more power management integrated circuits (PMICs) 715, an RF integrated circuit (RFIC) 725 including RF transmitters and/or receivers, a controller 711 thereof, And one or more central processing cores 730, 731 for processing the received input on a PCB 260 incorporating the integrated system 200. Functionally, the PMIC 715 performs battery power conditioning, DC to DC conversion, and the like, and thus, has an input coupled to the battery 713 and all other functional modules having integrated circuitry 710 that provides current supply to the board level, The output of, for example, the first IC 205A and/or the sensor 208A in the integrated system 200 is included. As further depicted, in this representative embodiment, RFIC 725 has an output coupled to the antenna while providing a carrier frequency of approximately 2 GHz (eg, 1.9 GHz in RFIC 725 designed for 3G or GSM mobile communications), And may further have an integration device 710 coupled to the board level Inputs for communication modules such as RF analog and digital baseband modules (not depicted).

7 and 8A through 8C are flow diagrams illustrating a method of integrating a sensor wafer and an IC chip onto an interposer in accordance with an embodiment of the present invention. The method 800 of FIG. 7 begins with operation 810 of receiving an interposer, one or more sensor wafers, and one or more IC chips. In one embodiment, the sensor wafer is received from the source as one of a number of unencapsulated sensors still in the form of a wafer, and the sensor wafer singulation will be performed as part of operation 810. At operation 820, all of the sensor wafer systems that are integrated onto the interposer are attached to one or both sides of the interposer. In a representative embodiment, all of the sensor wafers that are integrated onto the interposer are attached to bond pads on the interposer, and the bond pads are disposed on the same first side of the interposer. At operation 850, all of the IC chips to be integrated onto the interposer are bonded to the at least one bond pad electrically coupled to the through vias in the interposer, and the through vias are further coupled to the interposer The first side is coupled to at least one bond pad of the sensor wafer and is attached to the interposer, for example, to the second side of the interposer. At operation 895, the interposer is attached to the organic package substrate, for example, by solder bumps, or is directly attached to the PCB.

FIG. 8A further depicts a method 801 for forming an interposer that can be used in method 800 in accordance with an embodiment. The method 801 begins with operation of the glass interposer substrate at operation 805. At operation 806, a columnar defect is introduced into the glass at a location where the through hole will be provided. In one embodiment, the columnar defects are transmitted through a laser that is exposed to the desired energy. Formed by the time of desire. Next, the glass interposer is immersed in the wet etchant solution to selectively etch the region of the glass interposer having the columnar defects, thereby allowing the through holes to be opened in the glass interposer. Conventional plating techniques are then used to form a vertical electrical interconnect. At operation 807, the lateral interconnect traces are formed by electroplating or laminating an anisotropic conductive adhesive (ACA). For example, an anisotropic conductive paste is printed on the interposer and hardened, or an anisotropic conductive film is laminated on the glass interposer. At operation 808, the dielectric layer is built into the glass by thin film deposition techniques (eg, chemical vapor deposition) or by spin coating techniques (eg, spin coating on glass, etc.) One or both sides of the interposer. Operations 807 and 808 are repeated until a predetermined number of lateral interconnect layers are formed. Method 801 then returns to operation 810 of method 800.

FIG. 8B depicts a method 802 that further describes a particular embodiment of operations 820 and 850 in method 800. The method 802 begins with operation 811 with the receipt of a plurality of sensor wafers and, for example, an interposer of a glass interposer formed by method 801. At operation 821, a pressure system is applied to the plurality of sensor wafers against the first side of the interposer to maintain each of the sensor wafers to be integrated onto the interposer. In a representative embodiment, the applied pressure is slight, only to keep the sensor wafers in physical contact with the interposer. At operation 825, a thermal system is applied locally to each of the sensor wafers, or across the entire interposer, such that the solder bumps present between each of the sensor wafers and the interposer are bonded. In an alternative embodiment in direct pad-to-pad bonding, operations 821 and 825 lack solder and are performed at higher pressures and/or temperatures. Attached permanently After adding a plurality of sensor wafers to the interposer, the solder wafer is attached to the second side of the interposer at operation 851, for example, any of the flip chip (C4) bonding techniques known in the art. Method 802 then returns to operation 895 (Fig. 7).

FIG. 8C depicts a method 803 that further describes a particular embodiment of operations 821 and 851 in method 802. The method 803 begins at operation 822 where the bond pads of the interposer (eg, on the first side) are tied at a first soldering temperature, with the first solder tab bonded to the bond pads of each of the plurality of sensor wafers. At operation 852, the bond pads of the interposer (eg, on the second side) are bonded to the bond pads of the IC wafer with a second solder joint at a second soldering temperature that does not cause the first solder tab to reflow. In a first embodiment in which the first solder joint comprises solder that forms an intermetallic product with the bond pads, the first soldering temperature is about the same as the second soldering temperature. In a second embodiment in which the first solder joint includes solder that does not form an intermetallic product with the bond pads, the first solder temperature is higher than the second solder temperature. Then, the method 803 returns to operation 895, wherein if the IC wafer is not underfilled, the bond pads of the interposer (eg, on the second side) are at a lower than the first and second soldering operations 822 and 852. The third soldering temperature of both temperatures is bonded to the bond pads on the package substrate or PCB with a third solder joint.

It will be appreciated that the above description is illustrative and not limiting. For example, although the flowchart in the drawings shows a particular sequence of operations performed by certain embodiments of the present invention, it will be appreciated that the order may not be required (e.g., alternative embodiments may be performed in a different order. Such operations, Combine certain operations, overlap certain operations, and so on). Furthermore, many of the other embodiments will be apparent to those skilled in the art in the <RTIgt; Although the present invention has been described with reference to the specific representative embodiments, it is to be understood that the invention is not limited to the described embodiments, and may be Modifications and variations are implemented. Therefore, the scope of the invention should be determined by reference to the appended claims, and the scope of the equivalents of the scope of the claims.

100‧‧‧Integrated package

108‧‧‧Sensor wafer

109‧‧‧Integrated Circuit (IC)

120‧‧‧Organic package substrate

125‧‧‧ core

130,131‧‧‧Building layers

135‧‧‧Interconnect track

110‧‧‧Ceramic cover

105‧‧‧Sensor

107‧‧‧ Cavity

116,212A~212C‧‧‧Electrical connection

115‧‧‧矽 Through Hole (TSV)

101‧‧‧矽 substrate

T ₂ ‧‧‧interlayer thickness

140‧‧‧ solder bumps

200‧‧‧ integrated system

205A‧‧‧First IC chip

205B‧‧‧Second IC chip

208A‧‧‧First sensor chip

208B‧‧‧Second sensor chip

208C‧‧‧ third sensor chip

201‧‧‧Interposer thickness

202‧‧‧ first side

203‧‧‧ second side

222A‧‧‧Front connection

250A, 250B‧‧‧through holes

207‧‧‧ cavity

210A~210C‧‧‧Airtight seal

101A~101C‧‧‧Sensor wafer substrate

251‧‧‧ lateral electrical interconnection track

232‧‧‧Electrical connection

260‧‧‧Printed circuit board

240,241‧‧‧ dielectric layer

327‧‧‧Sensor pads

328‧‧‧Intermediary layer pads

318,319‧‧‧Base

337,338‧‧‧Metal ring mat

348,358‧‧‧ solder joints

255‧‧‧Underfill

700‧‧‧Mobile Computing Platform

710‧‧‧ board level integrated device

713‧‧‧Battery

711‧‧‧ Controller

730,731‧‧‧Central Processing Unit Core

715‧‧‧Power Management Integrated Circuit

725‧‧‧RF integrated circuit

800~803‧‧‧ method

810~895‧‧‧ operation

G ₁ ‧‧‧lateral clearance

S ₁ ‧‧‧ lateral dimension

The embodiments of the present invention are described by way of example and not limitation, and may be more fully understood by reference to the detailed description of the drawings. Cross-sectional view of the integrated sensor chip integrated with the IC chip; FIG. 2 is a cross-sectional view of the integrated microelectronic device integrated with the sensor chip and the IC chip on the interposer according to the embodiment of the present invention; 3B, 3C, and 3D are cross-sectional views of an electrical and hermetic joint structure according to an embodiment of the present invention; FIGS. 4A and 4B are cross-sectional views of a solder joint according to an embodiment of the present invention; 5B is a cross-sectional view of a flip chip bonded IC wafer with and without an underfill according to an embodiment of the present invention; and FIG. 6 is an integrated embodiment of the present invention using an integrated interposer Functional block diagram of a sensor computing chip and an IC chip mobile computing platform; and 7 and 8A to 8C are flowcharts depicting an integrated sensor chip and IC chip on an interposer in accordance with an embodiment of the present invention .

101A~101C‧‧‧Sensor wafer substrate

105‧‧‧Sensor

200‧‧‧ integrated system

201‧‧‧Interposer thickness

202‧‧‧ first side

203‧‧‧ second side

205A‧‧‧First IC chip

205B‧‧‧Second IC chip

207‧‧‧ cavity

208A‧‧‧First sensor chip

208B‧‧‧Second sensor chip

208C‧‧‧ third sensor chip

210A~210C‧‧‧Airtight seal

212A~212C‧‧‧Electrical connection

222A‧‧‧Front connection

232‧‧‧Electrical connection

240,241‧‧‧ dielectric layer

250A, 250B‧‧‧through holes

251‧‧‧ lateral electrical interconnection track

260‧‧‧Printed circuit board

G ₁ ‧‧‧lateral clearance

S ₁ ‧‧‧ lateral dimension

T ₂ ‧‧‧interlayer thickness

Claims (26)

An integrated microelectronic device comprising: a first sensor chip attached to a first side of an interposer, the first sensor chip including a first sensor, wherein the first sensor is An interposer is hermetically sealed in the first cavity; and an integrated circuit (IC) chip is attached to the second side of the interposer opposite to the first sensor, the integrated circuit chip is The through hole in the interposer is electrically coupled to the first sensor. The integrated microelectronic device of claim 1, wherein the interposer comprises 100 to 500 micrometers (μm) thick glass, and wherein each of the integrated circuit and the sensor wafer comprises 50 to 500 μm thick.矽 substrate. The integrated microelectronic device of claim 2, wherein the glass is a borosilicate glass. The integrated microelectronic device of claim 1, wherein the first sensor comprises a first microelectromechanical system (MEMS), the first microelectromechanical system comprising a mechanically displaceable structure, the mechanically The displaced structure is anchored to the first sensor wafer, and wherein the integrated circuit wafer includes an amplifier circuit that amplifies a signal received by the through hole and received from the first sensor. The integrated microelectronic device of claim 4, wherein each of the first sensor chip and the integrated circuit chip is flip-chip bonded, and each of the first sensor and the integrated circuit is The electrical coupling is electrically coupled to a bond pad disposed on the interposer. The integrated microelectronic device of claim 4, further comprising a second sensor chip attached to the first side of the interposer, the second sensor chip comprising a second sensor, the second sensor chip The second sensor is hermetically sealed in the second cavity by the interposer. The integrated microelectronic device of claim 1, wherein the interposer further comprises a lateral electrical interconnect trace electrically coupled to the integrated circuit trace to the At least one of the second integrated circuit wafer on the second interposer side or the bond pad on the second interposer side is electrically coupled to a printed circuit board (PCB). The integrated microelectronic device of claim 7, wherein the lateral electrical interconnect traces comprise an anisotropic conductive adhesive (ACA). The integrated microelectronic device of claim 1, wherein the first and second cavities are physically attached to the interposer by a continuous loop of frit, solder, Cu, or Au. The integrated microelectronic device of claim 9, wherein the integrated circuit chip is bonded to the interposer by a solder joint, and no underfill is disposed between the solder joints. The integrated microelectronic device of claim 10, wherein the first cavity is physically sealed to the interposer by a first solder joint having a first composition, and wherein the integrated circuit chip is The interposer is physically attached to the interposer by a second solder joint having a second composition having a higher melting temperature than the second composition. The integrated microelectronic device of claim 11, wherein the second cavity is formed by a second solder joint having a first composition. The body is attached to the interposer. The integrated microelectronic device of claim 11, wherein the first composition comprises at least one of Cd, Zn, and Au, and wherein the second composition comprises a Sn-Ag alloy. An integrated system comprising: a printed circuit board (PCB); and an integrated microelectronic device according to claim 1 of the patent application, directly attached to the printed circuit board, wherein the interposer further comprises a lateral electrical interconnection trace The lateral electrical interconnect traces electrically couple the solder joints to at least one of the integrated circuit wafer, the first sensor wafer, and the second sensor wafer, the solder joints Attached to the printed circuit board. The integrated system of claim 14, wherein the solder joints are further attached to the interposer, and the printed circuit board has a lower melting temperature than both the first solder joint and the second solder joint. a melting temperature composition, the first solder joint is coupled to the first cavity to the interposer, and the second solder joint is coupled to the integrated circuit wafer to the interposer. The integrated system of claim 14, wherein the solder joints are further attached to the organic package substrate, the organic package substrate being disposed between the interposer and the printed circuit board. The integrated system of claim 14, further comprising at least one of: a power management integrated circuit (PMIC) attached to the printed circuit board, The power management integrated circuit includes at least one of a switching voltage regulator or a switched mode direct current to direct current (DC-DC) converter; and a radio frequency (RF) integrated circuit (RFIC) attached to the printed circuit board, The RF integrated circuit includes a power amplifier that is operable to generate a carrier frequency. An mobile computing platform comprising: a display screen; a battery; an antenna; and an integrated system as claimed in claim 14. A method of packaging a microelectronic device, comprising: hermetically sealing a first sensor in a first cavity by attaching a first sensor wafer to a first side of the interposer; and by adding an additional product The body circuit (IC) chip is coupled to the second side of the interposer opposite to the first sensor chip, and electrically coupled to the integrated circuit chip to the first sensor, the interposer including a through hole, The through hole is electrically connected to the first and second sides of the interposer. The method of claim 19, wherein the attaching the first sensor wafer to the first side of the interposer and the attaching the second sensor wafer to the interposer further comprises: simultaneously applying pressure against the interposer Up to the first and second sensor wafers, and heating the interposer to permanently attach the first and second sensor wafers. For example, the method of applying for the scope of claim 19, wherein an additional body is added The second side of the circuit chip to the interposer further includes soldering the integrated circuit wafer after attaching the first and second sensor wafers to the interposer. The method of claim 21, wherein the attaching the first and second sensor wafers to the interposer is further included at a first soldering temperature, and the first solder joint is bonded to the bonding pad of the interposer to the first And a bonding pad of the second sensor wafer; and wherein the integrating the circuit chip to the interposer further comprises a second soldering temperature that does not cause the first solder joint to reflow, and bonding the interposer with the second solder joint Bonding pads to the bond pads of the integrated circuit die. The method of claim 22, wherein bonding the bonding pads of the interposer to the bonding pads of the first and second sensor wafers with the first solder joint further comprises forming the first solder joint with a high temperature solder composition And wherein bonding the bonding pad of the interposer to the bonding pad of the integrated circuit wafer with the second solder joint further comprises forming the second solder joint with a low temperature solder composition. The method of claim 22, wherein bonding the bonding pads of the interposer to the bonding pads of the first and second sensor wafers with the first solder joint further comprises forming the first solder joint with a low temperature solder composition And annealing the first solder joint to form an intermetallic compound having a melting temperature higher than the first soldering temperature; and wherein the bonding pad of the interposer is bonded to the integrated body with a second solder joint The bonding pad of the circuit wafer further includes forming the first portion with a low temperature solder composition Two solder joints. The method of claim 19, further comprising: forming a lateral electrical interconnect trace to electrically couple the first interposer across the at least one of the first and second sides of the interposer Pad to the second interposer bond pad, the first interposer bond pad being attached to at least one of the integrated circuit die, the first sensor die, and the second sensor die, and the second The interposer bond pads will be attached to the printed circuit board (PCB). The method of claim 25, wherein the forming the lateral electrical interconnect trace further comprises an anisotropic conductive adhesive (ACA) process, including printing or laminating the anisotropic conductive adhesive, or further comprising a semiconductor Wafer interconnect processing sequence, including dielectric film deposition, dielectric film etching, and metal trace plating.