TW201331910A - Liquid crystal display - Google Patents

Abstract

A liquid crystal display (LCD) including a LCD Panel having a plurality of pixels, a source driver outputting a plurality of pixel voltages to the LCD panel, a gate driver and a timing controller is provided. During performing a polarity inverting on a polarity signal corresponding to a first frame, the timing controller sequentially outputs a first start signal and a second start signal to the gate driver in a first frame period corresponding to the first frame. The gate driver sequentially outputs a plurality of first scan signals and a plurality of second scan signals to the LCD panel according to the first start signal and the second start signal, so that the brightness corresponding to a plurality of gray levels in the first frame are equal to the brightness corresponding to the gray levels in a plurality of previous frames and a plurality of following frames.

Description

LCD Monitor

This invention relates to a display, and more particularly to a liquid crystal display.

With the rapid advancement of optoelectronic technology and semiconductor technology, flat panel displays such as liquid crystal displays (LCDs) have flourished in recent years. Due to the high space utilization, low power consumption, no radiation and low electromagnetic interference of liquid crystal displays, liquid crystal displays have become the mainstream of the current flat panel display market. Since the liquid crystal display panel itself does not have the function of emitting light, the backlight module must be disposed behind the liquid crystal display panel to provide a surface light source required for the liquid crystal display panel. The liquid crystal display panel adjusts the light transmittance and the reflectance of the light source by controlling the rotation angle of the liquid crystal to display an image.

In general, the rotation angle of liquid crystal molecules is determined by the voltage difference across the liquid crystal layer and the direction of the electric field. In order to avoid the phenomenon of polarization of liquid crystal molecules, liquid crystal displays generally adopt a polarity inversion driving method, that is, alternately driving liquid crystal molecules with voltages of different polarities (such as positive polarity and negative polarity) at different times. In the above driving method, the polarity of the voltage applied to the liquid crystal molecules is determined by the direction of the electric field applied to the liquid crystal molecules. If the voltage of the pixel electrode is greater than the common voltage, the liquid crystal molecules are driven by a positive voltage, and conversely, the liquid crystal molecules are driven by a negative voltage.

When the liquid crystal display panel displays a dynamic picture, the grayscale value displayed by each pixel on the liquid crystal display panel may continuously change. In the case where the gray scale value is changed, the liquid crystal molecules of the liquid crystal display panel may still be polarized, that is, the liquid crystal molecules in the pixels may have a DC voltage remaining, so that the afterimage is displayed on the liquid crystal display panel.

In order to suppress the polarization of the liquid crystal molecules caused by the liquid crystal display panel displaying the dynamic picture, the polarity signal of a specific picture is reversed in polarity, so that the polarity signal corresponding to the specific picture is the same as the polarity signal of the previous picture. Therefore, when the liquid crystal display panel writes the specific picture, each pixel will be charged in the same polarity, so that the brightness corresponding to each gray level in the specific picture is higher than that in each adjacent picture. The brightness corresponding to the order, thus causing the picture to flicker.

The present invention provides a liquid crystal display that can make the brightness corresponding to a plurality of grayscale values in a picture after the polarity signal is inverted the same as the brightness corresponding to the grayscale values in other picture pictures, to avoid the phenomenon of flickering of the picture.

The invention provides a liquid crystal display comprising a liquid crystal display panel, a source driver, a gate driver and a timing controller. The liquid crystal display panel has a plurality of pixels. The source driver is coupled to the liquid crystal display panel for outputting a plurality of pixel voltages to the liquid crystal display panel. The gate driver is coupled to the liquid crystal display panel. The timing controller is coupled to the source driver and the gate driver for polarity inversion of the polarity signal output to the source driver. When the timing controller performs polarity inversion on the polarity signal corresponding to the first picture, the timing controller sequentially outputs the first start signal and the second start signal to the gate at least during the first picture period corresponding to the first picture. driver. The gate driver sequentially outputs the plurality of first scan signals and the plurality of second scan signals to the liquid crystal display panel according to the first start signal and the second start signal, so as to correspond to the plurality of gray scale values of the first screen. The brightness is the same as the brightness corresponding to the grayscale values of the plurality of previous pictures and the plurality of consecutive pictures.

In an embodiment of the present invention, the timing controller sequentially outputs the first start signal and the second start signal to the gate driver during the first picture period, so that each pixel receives the corresponding first scan signal. The polarity of the pixel voltage received by the driver is opposite to the polarity of the pixel voltage received by the driving of the corresponding second scan signal.

In an embodiment of the invention, the source driver generates the pixel voltages in a column inversion driving manner, and the first start signal and the second start signal are successive outputs or an even number of horizontal scanning periods.

In one embodiment of the invention, the source driver generates the pixel voltages in a 1+n column inversion driving manner, where n is a positive integer greater than or equal to two. And, the first start signal and the second start signal are intervals n-1+i×2n horizontal scanning periods, where i is a positive integer greater than or equal to zero.

In an embodiment of the invention, the timing controller outputs the first start signal to the gate driver during a plurality of previous pictures corresponding to the previous pictures and during a plurality of consecutive pictures corresponding to the consecutive pictures.

In an embodiment of the invention, the timing controller outputs the second start signal to the gate driver during a plurality of previous pictures corresponding to the previous pictures and during a plurality of consecutive pictures corresponding to the consecutive pictures.

In an embodiment of the present invention, the timing controller sequentially outputs the first start signal and the second start signal to a plurality of previous picture periods corresponding to the previous pictures and a plurality of consecutive picture periods corresponding to the consecutive pictures to Gate driver.

In an embodiment of the present invention, the timing controller outputs the first start signal and the first sequence during the first picture period, the plurality of previous picture periods corresponding to the previous pictures, and the plurality of consecutive picture periods corresponding to the consecutive pictures. And activating the signal to the gate driver such that the pixel voltage received by the driving of the corresponding first scanning signal is the same as the pixel voltage received by the driving of the corresponding second scanning signal. polarity.

In an embodiment of the invention, the source driver generates the pixel voltages in a column inversion driving manner, and the first start signal and the second start signal are spaced apart by an odd number of horizontal scanning periods.

In an embodiment of the invention, the source driver generates the pixel voltages in a 1+n column inversion driving manner, and the first start signal and the second start signal are at intervals of 2n-1+i×2n levels. During the scan.

In the liquid crystal display according to the embodiment of the present invention, the timing controller sequentially outputs the first start signal and the corresponding period during the picture period corresponding to the first picture or the picture period corresponding to the previous picture, the first picture, and the connection picture. The second start signal is sent to the gate driver, so that each pixel of the liquid crystal display panel has a brightness corresponding to the plurality of grayscale values in the first picture being the same as the brightness corresponding to the grayscale values in the previous picture or the subsequent picture. Thereby, the phenomenon of flickering of the screen can be avoided.

The above described features and advantages of the present invention will be more apparent from the following description.

1 is a schematic diagram of a system of a liquid crystal display according to an embodiment of the invention. Referring to FIG. 1 , in the present example, the liquid crystal display 100 includes a timing controller 110 , a gate driver 120 , a source driver 130 , and a liquid crystal display panel 140 . The timing controller 110 is coupled to the gate driver 120 and the source driver 130. The gate driver 120 and the source driver 130 are respectively coupled to the liquid crystal display panel 140. The liquid crystal display panel 140 is configured with a plurality of scanning lines 141, a plurality of data lines 143, and a plurality of pixels arranged in an array (eg, P11~P14, P21~P24, P31~P34, P41~P44), wherein each pixel ( For example, P11~P14, P21~P24, P31~P34, and P41~P44 are respectively coupled to the corresponding scan line 141 and data line 143.

The timing controller 110 sequentially receives a plurality of consecutive previous pictures PRF, a first picture F1, and a plurality of consecutive pictures CTF, and outputs a plurality of display materials DD and polarities according to the previous picture PRF, the first picture F1, and the consecutive pictures CTF. The signal POL is applied to the source driver 130 to control the source driver 130 to output a plurality of pixel voltages VP to the data line 143 of the liquid crystal display panel 140. Moreover, the timing controller 110 may output the first start signal STV1 to the gate driver 120 to control the gate driver 120 to output the plurality of first scan signals SC1 to the scan line 141 of the liquid crystal display panel 140, and the timing controller 110 may The second start signal STV2 is output to the gate driver 120 to control the gate driver 120 to output the plurality of second scan signals SC2 to the scan line 141 of the liquid crystal display panel 140. The pixels of the liquid crystal display panel 140 (such as P11~P14, P21~P24, P31~P34, P41~P44) are received by the corresponding first scan signal SC1 and/or the corresponding second scan signal SC2 to receive the pictures. The voltage VP is used to display images corresponding to the picture PRF, the first picture F1, and the connection picture CTF.

2 is a timing diagram of the polarity signal of FIG. 1 in accordance with an embodiment of the present invention. Referring to FIG. 1 and FIG. 2 , in the embodiment, the timing controller 110 can perform polarity inversion on the polarity signal POL corresponding to the first screen F1 to reduce the probability that the liquid crystal molecules of the liquid crystal display panel 140 are polarized. In general, the polarity signal POL corresponding to each picture is different from the polarity signal corresponding to the next picture, that is, the polarity signal POL corresponding to the previous picture PRF_2 is different from the polarity signal POL corresponding to the previous picture PRF_1, and the first picture F1 corresponds to The polarity signal POL is different from the polarity signal POL corresponding to the subsequent picture CTF. When the timing controller 110 performs polarity inversion on the polarity signal POL corresponding to the first picture F1, the polarity signal POL corresponding to the first picture F1 is the same as the polarity signal POL of the previous picture (ie, the previous picture PRF_1).

At this time, the timing controller 110 sequentially outputs the first start signal STV1 and the second start signal STV2 to the gate driver 130 at least during the picture period corresponding to the first picture F1 (ie, during the first picture period), and the gate The driver 130 sequentially outputs the first scan signal SC1 and the second scan signal SC2 to the scan line 141 of the liquid crystal display panel 140 according to the first start signal STV1 and the second start signal STV2, so as to be on the first screen F1. The brightness corresponding to the plurality of grayscale values is the same as the brightness corresponding to the grayscale values in the previous picture RPF and the subsequent picture CTF to avoid flickering of the picture.

3 is a timing diagram of the polarity of the start signal, the scan signal, and the pixel voltage of FIG. 1 in accordance with the first embodiment of the present invention. Referring to FIG. 1 to FIG. 3, in the present embodiment, it is assumed that the source driver 120 generates these pixel voltages VP in a column inversion driving manner. Accordingly, the polarity of the pixel voltage VP outputted to the same data line 143 by the source driver 120 during different horizontal scanning periods (corresponding to the pulse width of one scanning signal) is alternately polarity A and polarity B. Further, in accordance with the switching of the voltage level of the polarity signal POL, the polarity alternating order of the pixel voltage VP is also switched. Among them, the polarities A and the polarities B are positive polarity and negative polarity, that is, when the polarity A is positive polarity, the polarity B is negative polarity, or when the polarity B is positive polarity, the polarity A is negative polarity.

In this embodiment, during the picture period corresponding to the previous pictures PRF_2, PRF_1, the first picture F1, and the connection picture CTF (ie, during the previous picture period, the first picture period, and the subsequent picture period), the timing controller 110 outputs sequentially. The first start signal STV1 and the second start signal STV2 are connected to the gate driver 130, wherein the first start signal STV1 and the second start signal STV2 are separated by one horizontal scanning period. Therefore, the first scan signal (such as SC1_1~SC1_5) output by the gate driver 130 is separated from the corresponding second scan signal (such as SC2_1~SC2_5) by one horizontal scanning period.

As shown in FIG. 3, in the same picture, the pixels of the first column (such as P11~P14) in the liquid crystal display panel 140 are subjected to the polarity of the pixel voltage VP (such as the polarity A) driven by the first scan signal SC1_1. The polarity (eg, polarity A) of the pixel voltage VP received by the driving of the second scan signal SC2_1 is the same. In the same picture, the pixels of the second column (such as P21~P24) in the liquid crystal display panel 140 are driven by the first scan signal SC1_2, and the polarity of the pixel voltage VP (such as the polarity B) is the same as that of the second scan. The polarity of the pixel voltage VP received by the driving of the signal SC2_2 (such as the polarity B), and so on.

According to the above, each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) will be the same during the picture period corresponding to the previous pictures PRF_2, PRF_1, the first picture F1 and the connection picture CTF. Polar charging, so that the charging effect of each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) will tend to be saturated. Further, each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) is precharged by the pixel voltage VP received by the driving of the first scanning signal SC1, so that each pixel One pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) is driven by the second scanning signal SC2 to receive another pixel voltage VP corresponding to the displayed grayscale value, each drawing The voltage stored in the prime (such as P11~P14, P21~P24, P31~P34, P41~P44) will be approximately equal to the received pixel voltage VP.

Accordingly, each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) receives the same gray during the screen period corresponding to the previous pictures PRF_2, PRF_1, the first picture F1, and the connection picture CTF. When the pixel voltage of the order is VP, the brightness displayed by each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) will be the same, so the flickering of the picture can be avoided.

Further, in the above embodiment, the first start signal STV1 and the second start signal STV2 are spaced apart by one horizontal scanning period. In other embodiments, when the interval between the first start signal STV1 and the second start signal STV is an odd number (ie, 1, 3, 5, etc.) horizontal scanning periods, each pixel (eg, P11~) P14, P21~P24, P31~P34, P41~P44) are performed by the pixel voltage VP received by the driving of the first scanning signal SC1 and the pixel voltage VP received by the driving of the second scanning signal SC2. Polar charging.

4 is a timing diagram of the polarity of the start signal, scan signal, and pixel voltage of FIG. 1 in accordance with a second embodiment of the present invention. Referring to FIG. 1 to FIG. 4, in the present embodiment, it is also assumed that the source driver 120 generates these pixel voltages VP in a column inversion driving manner. In this embodiment, during the picture period corresponding to the previous pictures PRF_2, PRF_1, the first picture F1, and the connection picture CTF, the timing controller 110 sequentially outputs the first start signal STV1 and the second start signal STV2 to the gate. The pole driver 130, wherein the first start signal STV1 and the second start signal STV2 are spaced apart by two horizontal scanning periods. Therefore, the first scan signal (such as SC1_1~SC1_5) output by the gate driver 130 is spaced apart from the corresponding second scan signal (such as SC2_1~SC2_5) by two horizontal scanning periods.

As shown in FIG. 4, in the same picture, the pixels of the first column (such as P11~P14) in the liquid crystal display panel 140 are subjected to the polarity of the pixel voltage VP (such as the polarity A) driven by the first scan signal SC1_1. Conversely, the polarity (eg, polarity B) of the pixel voltage VP received by the driving of the second scan signal SC2_1. In the same picture, the pixels of the second column (such as P21~P24) in the liquid crystal display panel 140 are driven by the first scan signal SC1_2 to receive the polarity of the pixel voltage VP (such as the polarity B) opposite to the second scan. The polarity of the pixel voltage VP received by the drive of the signal SC2_2 (such as the polarity A), and so on.

According to the above, each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) will be different in the picture period corresponding to the previous pictures PRF_2, PRF_1, the first picture F1 and the connection picture CTF. Polar charging, so that each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) will have the same charging effect. Further, each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) is charged with a different polarity by the pixel voltage VP received by the driving of the first scanning signal SC1, so that Each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) is driven by the second scan signal SC2 to receive another pixel voltage VP corresponding to the displayed grayscale value. The pixels (such as P11~P14, P21~P24, P31~P34, and P41~P44) will have approximately the same voltage stored in the same grayscale value.

Accordingly, each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) receives the same gray during the screen period corresponding to the previous pictures PRF_2, PRF_1, the first picture F1, and the connection picture CTF. When the pixel voltage of the order is VP, the brightness displayed by each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) will be the same, so the flickering of the picture can be avoided.

Further, in the above embodiment, the first start signal STV1 and the second start signal STV2 are spaced apart by two horizontal scanning periods. In other embodiments, the first start signal STV1 and the second start signal STV are consecutive outputs (such as the second start signal STV2 shown by the dashed line) or the interval is even (ie, 2, 4, 6, etc.) During each horizontal scanning period, each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) uses its pixel voltage VP received by the driving of the first scanning signal SC1 and its second scanning. The pixel voltage VP received by the driving of the signal SC2 is charged in an opposite polarity. Wherein, when the first start signal STV1 and the second start signal STV are consecutive outputs, each second scan signal (refer to the second scan signal SC2_1~SC2_5 indicated by the broken line) is connected to the corresponding first scan signal (eg SC1_1~SC1_5).

Figure 5 is a timing diagram of the polarity of the start signal, scan signal and pixel voltage of Figure 1 in accordance with a third embodiment of the present invention. 6 is a timing diagram of the polarity of the start signal, the scan signal, and the pixel voltage of FIG. 1 in accordance with the fourth embodiment of the present invention. Referring to FIG. 1, FIG. 2, FIG. 5 and FIG. 6, in the present embodiment, it is also assumed that the source driver 120 generates these pixel voltages VP in a column inversion driving manner. In general, since the polarity signal POL corresponding to the first picture F1 is reversed in polarity, the polarity signal POL corresponding to the first picture F1 is the same as the polarity signal POL of the previous picture (ie, the previous picture PRF_1). Therefore, in the picture period corresponding to the first picture F1, each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) is charged in the same polarity, so that each of the first pictures F1 The brightness corresponding to the grayscale value is higher than the brightness corresponding to each grayscale value in the previous picture RPF or the subsequent picture CTF, so that the picture flickers.

According to the above, the reason for the flickering of the screen is that each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) is charged with the same polarity during the screen corresponding to the first picture F1, so each is made The pixels (such as P11~P14, P21~P24, P31~P34, P41~P44) can solve the problem by charging with different polarities during the picture period corresponding to the first picture F1. In this embodiment, during the picture period corresponding to the first picture F1, the timing controller 110 outputs the sequence to the gate driver 130, wherein the first start signal STV1 and the second start signal STV2 are separated by two levels. During the scan, each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) will be charged with different polarity.

Moreover, during the period of the screen corresponding to the previous pictures PRF_2, PRF_1 and the subsequent picture CTF, the operation of the liquid crystal display 100 can be similar to a conventional liquid crystal display. In other words, during the picture period corresponding to the previous pictures PRF_2, PRF_1 and the subsequent picture CTF, the timing controller 110 outputs the first start signal STV1 or the second start signal STV2 to the gate driver 130, and the gate driver 130 corresponds to the output. The first scan signal (such as SC1_1~SC1_5) or the second scan signal (such as SC2_1~SC2_5) may be determined according to the design of those skilled in the art.

Further, in the above embodiment, in the picture period corresponding to the first picture F1, the first start signal STV1 and the second start signal STV2 are spaced apart by two horizontal scanning periods. In other embodiments, during the picture period corresponding to the first picture F1, the first start signal STV1 and the second start signal STV are consecutive outputs or the intervals are even (ie, 2, 4, 6, etc.) During horizontal scanning, each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) uses its pixel voltage VP received by the driving of the first scanning signal SC1 and its second scanning signal. The pixel voltage VP received by the driver of SC2 is charged in an opposite polarity.

Figure 7 is a timing diagram of the polarity of the start signal, scan signal and pixel voltage of Figure 1 in accordance with a fifth embodiment of the present invention. Referring to FIG. 1 , FIG. 2 and FIG. 7 , in the present embodiment, it is assumed that the source driver 120 generates these pixel voltages VP in a 1+n column inversion driving manner, where n is a positive integer greater than or equal to 2, and This n is set to 2 for explanation. That is, in the pixel voltage VP outputted to the same data line 143 by the source driver 120, the polarities of the first, fourth, and fifth pen pixel voltages VP are one of the polarity A and the polarity B, The polarities of the two- and third-stroke pixel voltages VP are the other of the polar A and the polar B, and the rest are deduced by analogy. Further, in accordance with the switching of the voltage level of the polarity signal POL, the polarity alternating order of the pixel voltage VP is also switched. Among them, the polarities A and the polarities B are positive polarity and negative polarity, that is, when the polarity A is positive polarity, the polarity B is negative polarity, or when the polarity B is positive polarity, the polarity A is negative polarity.

In this embodiment, during the picture period corresponding to the previous pictures PRF_2, PRF_1, the first picture F1, and the connection picture CTF, the timing controller 110 sequentially outputs the first start signal STV1 and the second start signal STV2 to the gate. The pole driver 130, wherein the first start signal STV1 and the second start signal STV2 are intervals 3 (ie, 2n-1) horizontal scanning periods. Therefore, the first scan signal (such as SC1_1~SC1_5) output by the gate driver 130 is separated from the corresponding second scan signal (such as SC2_1~SC2_5) by three horizontal scanning periods.

As shown in FIG. 7, in the same picture, the pixels of the first column (such as P11~P14) in the liquid crystal display panel 140 are subjected to the polarity of the pixel voltage VP (such as the polarity A) driven by the first scan signal SC1_1. The polarity (eg, polarity A) of the pixel voltage VP received by the driving of the second scan signal SC2_1 is the same. In the same picture, the pixels of the second column (such as P21~P24) in the liquid crystal display panel 140 are driven by the first scan signal SC1_2, and the polarity of the pixel voltage VP (such as the polarity B) is the same as that of the second scan. The polarity of the pixel voltage VP received by the driving of the signal SC2_2 (such as the polarity B), and so on. Therefore, in the picture period corresponding to the previous pictures PRF_2, PRF_1, the first picture F1, and the connection picture CTF, the charging effect of each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) tends to be In saturation, that is, the voltage stored in each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) is approximately equal to the received pixel voltage VP, thereby avoiding the phenomenon of flickering of the picture. .

In the above embodiment, the first start signal STV1 and the second start signal STV2 are intervals 3 (ie, 2n-1) horizontal scanning periods. In other embodiments, when the interval between the first start signal STV1 and the second start signal STV is 2n-1+i×2n (3, 7, 11, etc. in this embodiment) horizontal scanning period Each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) is driven by the pixel voltage VP received by the driving of the first scanning signal SC1 and driven by the second scanning signal SC2 The received pixel voltage VP is charged in the same polarity, where i is a positive integer greater than or equal to zero.

Figure 8 is a timing diagram of the polarity of the start signal, scan signal and pixel voltage of Figure 1 in accordance with a sixth embodiment of the present invention. Referring to FIG. 1 , FIG. 2 , FIG. 7 and FIG. 8 , in the embodiment, it is also assumed that the source driver 120 generates the pixel voltages VP in a 1+n column inversion driving manner, and n is set to 2 for explanation. . In this embodiment, during the picture period corresponding to the previous pictures PRF_2, PRF_1, the first picture F1, and the connection picture CTF, the timing controller 110 sequentially outputs the first start signal STV1 and the second start signal STV2 to the gate. The pole driver 130, wherein the first start signal STV1 and the second start signal STV2 are interval 1 (ie, n-1) horizontal scanning periods. Therefore, the first scan signal (such as SC1_1~SC1_5) output by the gate driver 130 is separated from the corresponding second scan signal (such as SC2_1~SC2_5) by one horizontal scanning period.

As shown in FIG. 8, in the same picture, the pixels of the first column (such as P11~P14) in the liquid crystal display panel 140 are subjected to the polarity of the pixel voltage VP (such as the polarity A) driven by the first scan signal SC1_1. Conversely, the polarity (eg, polarity B) of the pixel voltage VP received by the driving of the second scan signal SC2_1. In the same picture, the pixels of the second column (such as P21~P24) in the liquid crystal display panel 140 are driven by the first scan signal SC1_2 to receive the polarity of the pixel voltage VP (such as the polarity B) opposite to the second scan. The polarity of the pixel voltage VP received by the drive of the signal SC2_2 (such as the polarity A), and so on. Therefore, in the screen period corresponding to the previous pictures PRF_2, PRF_1, the first picture F1, and the connection picture CTF, the charging effect of each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) will be the same. , that is, each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) is driven by the second scan signal SC2 and receives the pixel voltage VP corresponding to the displayed grayscale value. A pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) will display approximately the same voltage value stored in the same grayscale value, thus avoiding the phenomenon of flickering.

In the above embodiment, the first start signal STV1 and the second start signal STV2 are interval 1 (i.e., n-1) horizontal scanning periods. In other embodiments, when the first start signal STV1 and the second start signal STV are in a horizontal scanning period of interval n-1+i×2n (1, 5, 9, etc. in this embodiment) Each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) is driven by the pixel voltage VP received by the driving of the first scanning signal SC1 and driven by the second scanning signal SC2 The received pixel voltage VP is charged in an opposite polarity, where i is a positive integer greater than or equal to zero.

Figure 9 is a timing diagram of the polarity of the start signal, scan signal and pixel voltage of Figure 1 in accordance with a seventh embodiment of the present invention. Figure 10 is a timing diagram of the polarity of the start signal, scan signal and pixel voltage of Figure 1 in accordance with an eighth embodiment of the present invention. Referring to FIG. 1 , FIG. 2 , FIG. 9 and FIG. 10 , in the embodiment, it is also assumed that the source driver 120 generates the pixel voltages VP in a 1+n column inversion driving manner, and n is set to 2 for explanation. . According to the above, the reason for the flickering of the screen is that each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) is charged with the same polarity during the screen corresponding to the first picture F1, so each is made The pixels (such as P11~P14, P21~P24, P31~P34, P41~P44) can solve the problem by charging with different polarity during the screen corresponding to the first picture F1.

In this embodiment, during the picture period corresponding to the first picture F1, the timing controller 110 outputs the sequence to the gate driver 130, wherein the first start signal STV1 and the second start signal STV2 are at interval 1 (ie, N-1) During the horizontal scanning period, each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) will be charged with different polarity. Moreover, during the period of the screen corresponding to the previous pictures PRF_2, PRF_1 and the subsequent picture CTF, the operation of the liquid crystal display 100 can be similar to a conventional liquid crystal display. In other words, during the picture period corresponding to the previous pictures PRF_2, PRF_1 and the subsequent picture CTF, the timing controller 110 outputs the first start signal STV1 or the second start signal STV2 to the gate driver 130, and the gate driver 130 corresponds to the output. The first scan signal (such as SC1_1~SC1_5) or the second scan signal (such as SC2_1~SC2_5) may be determined according to the design of those skilled in the art.

Further, in the above embodiment, in the picture period corresponding to the first picture F1, the first start signal STV1 and the second start signal STV2 are interval 1 (i.e., n-1) horizontal scanning periods. In other embodiments, during the picture period corresponding to the first picture F1, when the first start signal STV1 and the second start signal STV are separated by n-1+i×2n (1, 5 in this embodiment). 9...etc.) During each horizontal scanning period, each pixel (such as P11~P14, P21~P24, P31~P34, P41~P44) uses its pixel voltage received by the driving of the first scanning signal SC1. The VP and its pixel voltage VP received by the driving of the second scan signal SC2 are hetero-polarized, where i is a positive integer greater than or equal to zero.

In summary, in the liquid crystal display of the embodiment of the present invention, the timing controller sequentially outputs the first start signal and the second start signal to the gate driver during the picture period corresponding to the previous picture, the first picture, and the connection picture. So that each pixel of the liquid crystal display panel exhibits the same polarity charging or the opposite polarity charging. Alternatively, the timing controller sequentially outputs the first start signal and the second start signal to the gate driver during the picture period corresponding to the first picture, so that each pixel of the liquid crystal display panel is rendered or asymmetrically charged. Thereby, the brightness corresponding to the plurality of grayscale values in the first picture can be the same as the brightness corresponding to the grayscale values in the previous picture or the subsequent picture, to avoid the phenomenon that the picture flickers.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

100. . . LCD Monitor

110. . . Timing controller

120. . . Gate driver

130. . . Source driver

140. . . LCD panel

141. . . Scanning line

143. . . Data line

A, B. . . polarity

CTF. . . Connection screen

DD. . . Display data

F1. . . First picture

P11~P14, P21~P24, P31~P34, P41~P44. . . Pixel

POL. . . Polarity signal

PRF, PRF_1, PRF_2. . . Previous screen

SC1, SC1_1~SC1_5. . . First scan signal

SC2, SC2_1~SC2_5. . . Second scan signal

STV1. . . First start signal

STV2. . . Second start signal

VP. . . Pixel voltage

1 is a schematic diagram of a system of a liquid crystal display according to an embodiment of the invention.

2 is a timing diagram of the polarity signal of FIG. 1 in accordance with an embodiment of the present invention.

3 is a timing diagram of the polarity of the start signal, the scan signal, and the pixel voltage of FIG. 1 in accordance with the first embodiment of the present invention.

4 is a timing diagram of the polarity of the start signal, scan signal, and pixel voltage of FIG. 1 in accordance with a second embodiment of the present invention.

Figure 5 is a timing diagram of the polarity of the start signal, scan signal and pixel voltage of Figure 1 in accordance with a third embodiment of the present invention.

6 is a timing diagram of the polarity of the start signal, the scan signal, and the pixel voltage of FIG. 1 in accordance with the fourth embodiment of the present invention.

Figure 7 is a timing diagram of the polarity of the start signal, scan signal and pixel voltage of Figure 1 in accordance with a fifth embodiment of the present invention.

Figure 8 is a timing diagram of the polarity of the start signal, scan signal and pixel voltage of Figure 1 in accordance with a sixth embodiment of the present invention.

Figure 9 is a timing diagram of the polarity of the start signal, scan signal and pixel voltage of Figure 1 in accordance with a seventh embodiment of the present invention.

Figure 10 is a timing diagram of the polarity of the start signal, scan signal and pixel voltage of Figure 1 in accordance with an eighth embodiment of the present invention.

100. . . LCD Monitor

110. . . Timing controller

120. . . Gate driver

130. . . Source driver

140. . . LCD panel

141. . . Scanning line

143. . . Data line

CTF. . . Connection screen

DD. . . Display data

F1. . . First picture

P11~P14, P21~P24, P31~P34, P41~P44. . . Pixel

POL. . . Polarity signal

PRF. . . Previous screen

SC1. . . First scan signal

SC2. . . Second scan signal

STV1. . . First start signal

STV2. . . Second start signal

VP. . . Pixel voltage

Claims (14)

A liquid crystal display comprising: a liquid crystal display panel having a plurality of pixels; a source driver coupled to the liquid crystal display panel for outputting a plurality of pixel voltages to the liquid crystal display panel; and a gate driver coupled The liquid crystal display panel; and a timing controller coupled to the source driver and the gate driver for polarity inversion of a polarity signal outputted to the source driver, when the timing controller corresponds to a When the polarity signal of a picture is reversed in polarity, the timing controller sequentially outputs a first start signal and a second start signal to the gate at least in a first picture period corresponding to the first picture. The gate driver sequentially outputs a plurality of first scan signals and a plurality of second scan signals to the liquid crystal display panel according to the first start signal and the second start signal, so that in the first screen The brightness corresponding to the plurality of grayscale values is the same as the brightness of the grayscale values in the plurality of previous pictures and the plurality of consecutive pictures. The liquid crystal display of claim 1, wherein the timing controller sequentially outputs the first start signal and the second start signal to the gate driver during the first picture period, so that each The polarity of the pixel voltage received by the driving of the corresponding first scanning signal is opposite to the polarity of the pixel voltage received by each of the pixels driven by the corresponding second scanning signal. The liquid crystal display of claim 2, wherein the source driver generates the pixel voltages in a column inversion driving manner. The liquid crystal display of claim 3, wherein the first start signal and the second start signal are successive outputs or an even number of horizontal scanning periods. The liquid crystal display of claim 2, wherein the source driver generates the pixel voltages in a 1+n column inversion driving manner, wherein n is a positive integer greater than or equal to 2. The liquid crystal display of claim 5, wherein the first start signal and the second start signal are intervals n-1+i×2n horizontal scanning periods, wherein i is a positive integer greater than or equal to zero . The liquid crystal display of claim 2, wherein the timing controller outputs the first start signal during a plurality of previous pictures corresponding to the previous pictures and during a plurality of consecutive pictures corresponding to the consecutive pictures To the gate driver. The liquid crystal display of claim 2, wherein the timing controller outputs the second start signal during a plurality of previous pictures corresponding to the previous pictures and during a plurality of consecutive pictures corresponding to the consecutive pictures To the gate driver. The liquid crystal display of claim 2, wherein the timing controller outputs the first start signal during a plurality of previous pictures corresponding to the previous pictures and during a plurality of consecutive pictures corresponding to the consecutive pictures And the second start signal to the gate driver. The liquid crystal display according to claim 1, wherein the timing controller is in the period of the first picture, during the plurality of previous pictures corresponding to the previous pictures, and during the plurality of consecutive pictures corresponding to the consecutive pictures. And sequentially outputting the first start signal and the second start signal to the gate driver, so that each of the pixels is driven by the corresponding first scan signal to receive the same polarity of the pixel voltage The pixels are polarated by the pixel voltage received by the corresponding second scan signal. The liquid crystal display of claim 10, wherein the source driver generates the pixel voltages in a column inversion driving manner. The liquid crystal display of claim 11, wherein the first start signal and the second start signal are an odd number of horizontal scanning periods. The liquid crystal display of claim 10, wherein the source driver generates the pixel voltages in a 1+n column inversion driving manner, wherein n is a positive integer greater than or equal to 2. The liquid crystal display of claim 13, wherein the first start signal and the second start signal are intervals of 2n-1+i×2n horizontal scanning periods, wherein i is a positive integer greater than or equal to zero .