TW201330275A - Thin-film transistor and manufacturing method for thin-film transistor - Google Patents

Abstract

One thin-film transistor (100) is provided with layered oxides (30), between a gate electrode (220) and a channel (40), comprising a layer (32) that is in contact with a gate electrode (20) and that comprises a first oxide (which may contain unavoidable impurities) containing bismuth (Bi) and niobium (Nb), and a layer (34) that is contact with the channel (40) and that comprises a second oxide (which may contain unavoidable impurities) which is one type selected from a group consisting of an oxide containing lanthanum (La) and tantalum (Ta), an oxide containing lanthanum (La) and zirconium (Zr), and an oxide containing strontium (Sr) and tantalum (Ta); and the channel (40) is a channel oxide (which may contain unavoidable impurities) and comprises indium (In) and zinc (Zn).

Description

Thin film transistor and method for manufacturing thin film transistor

The present invention relates to a thin film transistor and a method of manufacturing a thin film transistor.

In the past, it has been revealed that a purpose is to switch at a high speed with a low driving voltage, and to use a ferroelectric material (for example, BLT (Bi _4-X La _X Ti ₃ O ₁₂ ), PZT (Pb (Zr _X , Ti _{1- X} ) O ₃ )) is used as a thin film transistor of a gate insulating layer. On the other hand, it is also disclosed that one purpose is to increase the concentration of the carrier, and an oxide conductive material such as indium tin oxide (ITO), zinc oxide (ZnO) or LSCO (La _X Sr _1-X CuO ₄ ) is used. A thin film transistor as a channel layer (Patent Document 1).

Here, in view of the above-described method for producing a thin film transistor, first, a stacked film of Ti and Pt as gate electrodes is formed by electron beam evaporation. Further, a gate insulating layer made of the above BLT or PZT is formed on the gate electrode by a sol-gel method. Further, a channel layer made of ITO is formed on the gate insulating layer by RF sputtering. Next, Ti and Pt are formed on the channel layer by electron beam evaporation to form a source electrode and a drain electrode. Thereafter, by the RIE method and the wet etching method (mixed solution of HF and HCl), the element region is separated from the other element regions (Patent Document 1).

Prior technical literature

Patent Document 1: Japanese Laid-Open Patent Publication No. 2006-121029

However, although conventional thin film transistors have several examples in which a gate insulating layer or a via is formed by a composite oxide, it is still not preferable to realize a material having high characteristics as a thin film transistor and a suitable manufacturing method thereof. . In addition, with the high performance of the gate insulating film and/or the respective channels, it is one of the technical problems to be solved in order to achieve high performance of the thin film transistor in order to improve the overall performance of such a stack. In addition, in addition to the gate insulating layer and the channel, there are still many research and development spaces for the implementation of the thin film transistor in which the gate electrode, the source electrode, or the drain electrode are formed by oxide.

Further, in the prior art, since the procedure of a vacuum process or a procedure using the photolithography method, which requires a long time and/or an expensive apparatus, is a general adopter, the use efficiency of the raw materials and the manufacturing energy source is extremely inferior. In the case of the above-described production method, since a large amount of processing and a long period of time are required for producing a thin film transistor, it is not preferable from the viewpoint of industriality and mass productivity. Moreover, the conventional technology also has a problem that it is difficult to have a large area.

The present invention achieves high performance of a thin film transistor in which an oxide is at least suitable for a channel and a gate insulating layer by solving at least one of the above problems, or simplification and saving of a manufacturing process of the thin film transistor Energyization. As a result, the present invention contributes greatly to the provision of a thin film transistor excellent in industrial properties and mass productivity.

The inventors of the present invention have diligently studied and analyzed the selection and combination of a gate insulating film or an oxide of a channel function from among many existing oxides. It has been found to be interesting, for example, if the oxide properties of the gate insulating layer are high, if they are combined with the oxide of the channel (for example, the degree of interdiffusion of atoms at the interface between the layers and the resulting If the difference in interface defect density is poor, etc., when stacking these or the like, the performance level of the gate insulating layer may not be fully realized, or the function of the gate insulating layer or the channel may not be fully realized.

However, the inventor of the present invention succeeded in discovering a channel layer after many trial and error and detailed analysis results. If a gate insulating layer is combined with a specific oxide layer to form a special stacked structure, the gate insulating layer is formed. The performance can be properly played. As a result, a high performance thin film transistor in which the oxides are applied to the channel and the gate insulating layer can be realized. Further, the inventors of the present invention have found that the oxide can be produced by using a program which is greatly simplified or even energy-saving and which is easy to increase in size compared with the prior art. In addition, when an oxide which is applicable as a gate electrode of a thin film transistor and/or a source electrode or a drain electrode is developed, the efficiency is further improved. The present invention has been created based on the above various points of view.

A thin film transistor of the present invention is provided with a stacked oxide between a gate electrode and a channel, the stacked oxide having a layer of a first oxide (which may contain unavoidable impurities) connected to the gate The electrode is an oxide composed of bismuth (Bi) and niobium (Nb) or bismuth (Bi) and zinc. An oxide composed of (Zn) and niobium (Nb); and a layer of a second oxide (which may contain unavoidable impurities) is in contact with the channel and is selected from the group consisting of lanthanum (La) and lanthanum (Ta). One of a group consisting of an oxide composed of lanthanum (La) and zirconium (Zr), and an oxide composed of strontium (Sr) and strontium (Ta). Further, the channel of the thin film transistor is an oxide for a channel (which may contain unavoidable impurities).

In the thin film electromorph system, a stacked oxide that is connected to the first oxide of the gate electrode and the second oxide that is in contact with the channel is provided between the gate electrode and the channel. Here, although the first oxide has a relatively high dielectric constant, the value of the overflow current is large and the surface flatness is low. On the other hand, although the dielectric constant of the second oxide is relatively low, the value of the overflow current is extremely small, and the surface flatness is excellent. Further, according to the detailed analysis by the inventors of the present invention, it has been found that the stacked oxide can appropriately exhibit individual advantages by disposing the first oxide on the gate side and the second oxide on the channel side. Specifically, the high-capacitance gate insulator such as the first oxide contributes to a steep rise in the gate current with respect to the gate voltage and an increase in the on-current in the transistor characteristics. Furthermore, the presence of the second oxide contributes to low leakage current and surface smoothness, thereby reducing the off current of the drain with respect to the gate voltage and increasing the mobility of the electric field effect. Therefore, according to the thin film transistor, a high-performance thin film transistor in which the gate insulating layer and the via are formed of an oxide can be realized.

Further, as another aspect of the thin film transistor, the gate electrode is selected from the group consisting of an oxide composed of lanthanum (La) and nickel (Ni), an oxide composed of bismuth (Sb) and tin (Sn), and An oxide for a gate electrode of a group consisting of an oxide composed of indium (In) and tin (Sn) (may contain an inevitable oxide The impurity is the preferred state. Thereby, the gate electrode, the gate insulating layer, and the high-performance thin film transistor in which the channel is entirely formed of an oxide can be realized.

In another aspect of the thin film transistor, the thin film transistor further includes a source electrode and a drain electrode, and the source electrode and the gate electrode are oxides composed of indium (In) and tin (Sn) The oxide (which may contain unavoidable impurities) or an oxide composed of lanthanum (La) and nickel (Ni) (which may contain unavoidable impurities) is preferred. Thereby, a high-performance thin film transistor in which the gate electrode, the gate insulating layer, the channel, the source electrode, and the drain electrode are all formed of an oxide can be realized.

Further, a method for producing a thin film transistor of the present invention is a process for forming a gate electrode layer (hereinafter also referred to as a "gate electrode layer forming process") and forming an oxide for a channel (which may contain unavoidable impurities). The formation process of the channel (hereinafter also referred to as "channel formation process") includes the following processes (1) and (2): (1) the first oxide formation process is performed by (Bi) precursors and precursors containing niobium (Nb) are precursor solutions of solute, or precursors containing bismuth (Bi), precursors containing zinc (Zn), and before containing niobium (Nb) The first precursor solution in which the precursor is a solute precursor solution is heated in an oxygen-containing atmosphere such that the bismuth (Bi) and the bismuth (Nb) or the bismuth (Bi) and the zinc (Zn) The first oxide (which may contain unavoidable impurities) composed of the niobium (Nb) is formed to be in contact with the gate electrode layer; and (2) the second oxide formation process is selected from The precursor of the lanthanum (La) precursor and the precursor of lanthanum (Ta) are used as the precursor solution of the solute, the precursor of the lanthanum (La) precursor and the precursor containing the zirconium (Zr) are used as the precursor of the solute. a body solution, and a second precursor solution containing one of a group consisting of a strontium (Sr) precursor and a precursor containing strontium (Ta) as a solute precursor solution is heated in an oxygen-containing atmosphere. La (La) and the tantalum (Ta), the second oxide composed of the tantalum (La) and the zirconium (Zr), or the tantalum (Sr) and the tantalum (Ta) (may contain unavoidable The impurities are formed in such a manner as to be in contact with the channel.

Further, it is also possible to carry out a process such as substrate movement, inspection, and the like which are not related to the gist of the present invention.

According to the method for manufacturing the thin film transistor, the simpler processing without using the photolithography method (for example, an inkjet method, a screen printing method, a gravure/emboss printing method, or a nanoimprint method) can be used to form the first 1 oxide and second oxide. Furthermore, it is also easy to increase the area. Therefore, according to the method for producing a thin film transistor, it is possible to provide a method for producing a thin film transistor which is excellent in industrial properties and mass productivity.

Further, as another aspect of the method for manufacturing the thin film transistor, further, the gate electrode layer forming process is a precursor solution for a gate electrode (with a lanthanum (La) precursor and a nickel-containing (Ni) The precursor is a solute precursor solution, a precursor containing bismuth (Sb) and a precursor containing tin (Sn) as a solute precursor solution, or a precursor containing indium (In) and tin ( The Sn) precursor is a solute precursor solution) heated in an oxygen-containing atmosphere to form an oxide composed of the lanthanum (La) and the nickel (Ni), and the bismuth (Sb) and the tin (Sn) a preferred method of forming an oxide or an oxide composed of the indium (In) and the tin (Sn), that is, an oxide for a gate electrode (which may contain unavoidable impurities) state. Thereby, the gate electrode, the gate insulating layer, and the channel are all made of oxygen. A high performance thin film transistor formed by the compound.

Further, as another aspect of the method for producing the thin film transistor, the first oxide forming process or the second oxide forming process further includes a press molding process for forming the first oxide or the second oxide. Before using the first precursor layer, the first precursor layer using the first precursor solution or the second precursor layer using the second precursor solution as a starting material is heated in an oxygen-containing atmosphere at 80 ° C or higher and 300 ° C or lower. In a state where a stamper is applied to form a stamper structure for the first precursor layer or the second precursor layer, this is another preferred embodiment. Thereby, there is no need for a vacuum program or a procedure using photolithography, or a process such as an ultraviolet irradiation process, which requires a long time and/or expensive equipment. Further, since the first oxide and the second oxide are formed by a relatively low-temperature heat treatment without requiring the above-described respective processes, industrial properties and mass productivity are excellent.

In addition, the manufacturing method of the above-mentioned thin film transistor is the same, and the forming process of the channel further includes a molding process for using the precursor solution for the channel as a starting material before forming the oxide for the channel. The channel precursor layer is subjected to compression molding in an oxygen-containing atmosphere at a temperature of 80 ° C or more and 300 ° C or less to form a stamper structure for the channel precursor layer. This is another preferred embodiment. As a result, procedures that require relatively long periods of time and/or expensive equipment, such as vacuum procedures, procedures using photolithography, or ultraviolet irradiation procedures, become unnecessary. Further, since the oxide for the gate electrode can be formed by heat treatment at a relatively low temperature without the above-described procedure, it is excellent in industrial properties and mass productivity.

In still another aspect of the method for fabricating the thin film transistor, the gate electrode layer forming process further includes a stamping process, and the gate electrode is used before forming the oxide for the gate electrode. The precursor layer for a gate electrode using a precursor solution as a starting material is subjected to compression molding in an oxygen-containing atmosphere at a temperature of 80° C. or higher and 300° C. or lower to form a stamper structure for the precursor layer for the gate electrode. This is another preferred form. As a result, procedures that require relatively long periods of time and/or expensive equipment, such as vacuum procedures, procedures using photolithography, or ultraviolet irradiation procedures, become unnecessary. Further, since the oxide for the gate electrode can be formed by heat treatment at a relatively low temperature without the above-described procedure, it is excellent in industrial properties and mass productivity.

Furthermore, in still another aspect of the method for fabricating the thin film transistor, the process of forming the source electrode and the drain electrode further includes a stamping process for forming an oxide for the source electrode or a gate electrode. Before the oxide is used, the source/drain electrode precursor layer composed of the source/drain electrode precursor solution is subjected to compression molding in an oxygen-containing atmosphere and heated at 80° C. or higher and 300° C. or lower. It is a further preferred aspect to form a stamper structure for the source/drain electrode precursor layer. As a result, procedures that require relatively long periods of time and/or expensive equipment, such as vacuum procedures, procedures using photolithography, or ultraviolet irradiation procedures, become unnecessary. In addition, since the oxide for the source electrode and the oxide for the gate electrode can be formed by heat treatment at a relatively low temperature without the above-described procedure, it is excellent in industrial properties and mass productivity.

On the other hand, the "molding" in this case is sometimes called "nano imprinting".

According to the thin film transistor of the present invention, a high-performance thin film transistor in which the gate insulating layer and the via are formed of an oxide can be realized. Further, according to the method for producing a thin film transistor of the present invention, since the first oxide and the second oxide can be formed by a relatively simple process, a thin film transistor excellent in industrial properties and mass productivity can be provided. Manufacturing method.

Hereinafter, a thin film transistor 100 as an embodiment of the present invention and a method of manufacturing the same will be described in detail based on the accompanying drawings. In addition, in this description, unless otherwise stated, the common reference part is given to the common part. Further, in the drawings, the elements of the present embodiment are not necessarily described while maintaining the reduction ratio of each other. Furthermore, in order to facilitate the viewing of the various figures, a part of the symbols are omitted.

<First embodiment>

1A to 1M are schematic cross-sectional views showing a process of manufacturing the thin film transistor 100 of the present embodiment, respectively. Further, the degree of easy viewing of the characters is considered, and the drawing numbers after FIG. 1H are numbered as FIG. 1J. Further, although the thin film transistor of the present embodiment has a so-called bottom gate structure, the present embodiment is not limited to this structure. Therefore, those having ordinary skill in the art to which the present invention pertains should be able to apply the general technical common knowledge, and refer to the description of the embodiment, and form a top gate structure by changing the order of the processes. Furthermore, the temperature in the present application means the set temperature of the heater. by Since the drawings are simplified, the patterning of the extraction electrodes from the respective electrodes is omitted.

[Process of Thin Film Transistor 100]

(1) Formation of gate electrode

In the present embodiment, first, as shown in FIG. 1A, a precursor for a gate electrode is formed on a highly heat-resistant glass substrate (specifically, Corning (registered trademark) 1737) 10 as a substrate by a known spin coating method. The body layer 20a, wherein the precursor electrode layer 20a for the gate electrode uses a precursor containing lanthanum (La) and a precursor containing nickel (Ni) as a solute precursor solution (referred to as a precursor solution for a gate electrode). Hereinafter, the precursor solution for a gate electrode is also used as a starting material. Thereafter, as a preliminary sintering, it was heated at 250 ° C for about 5 minutes. Further, the preliminary sintering is carried out in an oxygen atmosphere or in the atmosphere (hereinafter also collectively referred to as "oxygen-containing atmosphere"). Thereafter, as the main sintering, the gate electrode precursor layer 20a is heated in an oxygen atmosphere (for example, 100% by volume, but not limited thereto. The same applies to the following "oxygen atmosphere") at 550 ° C for about 20 minutes, such as As shown in Fig. 1B, an oxide layer 20 for a gate electrode made of lanthanum (La) and nickel (Ni) is formed on the high heat resistant glass 10 (although impurities which are unavoidable may be contained, the same applies hereinafter).

Here, in the present embodiment, the high heat resistant glass is used as the base material, but the base material of the present embodiment is not limited to the high heat resistant glass. For example, an insulating substrate other than the high heat resistant glass (for example, an SiO ₂ /Si substrate, an alumina (Al ₂ O ₃ ) substrate, an STO (SrTiO) substrate), and a surface of the Si substrate via the SiO ₂ layer and the Ti layer may be used. Various substrates of a semiconductor substrate (for example, a Si substrate, a SiC substrate, a Ge substrate, or the like) formed with an STO (SrTiO) layer insulating substrate or the like.

Further, an example of the yttrium-containing (La) precursor for forming the gate electrode oxide layer 20 of the present embodiment is yttrium acetate. As another example, cerium nitrate, cerium chloride or various cerium oxides (for example, cerium isopropoxide, cerium oxide, cerium ethoxide, cerium methoxy ethoxylate) may be used. Further, an example of the nickel (Ni)-containing precursor for forming the gate electrode oxide layer 20 of the present embodiment is nickel acetate. As another example, nickel nitrate, nickel chloride or various nickel alkoxides (for example, nickel isopropoxide, nickel butoxide, nickel ethoxylate, nickel methoxyethoxylate) may be used.

Further, in the present embodiment, the gate electrode oxide layer 20 composed of lanthanum (La) and nickel (Ni) is used, but the gate electrode oxide layer 20 is not limited to this composition. For example, an oxide layer for a gate electrode made of bismuth (Sb) and tin (Sn) may be used (although impurities which are unavoidable may be contained. The same applies hereinafter). In this case, as an example of the precursor of cerium (Sb), cerium acetate, cerium nitrate, cerium chloride or various cerium oxides (for example, cerium isopropoxide, cerium oxide, cerium oxide, cerium oxide) may be used. Methoxyethoxylate). Further, as an example of the tin-containing (Sn) precursor, tin acetate, tin nitrate, tin chloride or various tin alkoxides (for example, tin isopropoxide, tin oxide, tin ethoxylate, tinplate) may be used. Oxy ethoxylate). Further, an oxide composed of indium (In) and tin (Sn) may be used (although impurities which are unavoidable may be contained. The same applies hereinafter). In this case, as an example of the indium (In)-containing precursor, indium acetate, indium nitrate, indium chloride, or various indium alkoxides (for example, indium isopropoxide, indium butoxide, or the like) may be used. Indium ethoxylate, indium methoxy ethoxylate). Further, the example of the tin-containing (Sn) precursor is the same as the above example.

(2) Formation of gate insulating layer

Next, as shown in FIG. 1C, on the gate electrode oxide layer 20, a ruthenium-containing (Bi) precursor and a ruthenium-containing (Nb) precursor are formed as a solute by a known spin coating method. The bulk solution (referred to as a first precursor solution. Hereinafter, the same as the solution of the first precursor) is the first precursor layer 32a as a starting material. Thereafter, it was heated at 250 ° C for about 5 minutes as a preliminary sintering. In the present embodiment, in order to obtain a sufficient thickness (for example, about 180 nm) of the first oxide layer 32, the first precursor layer 32a is formed by spin coating and the preliminary sintering is repeated five times. Thereafter, as the main sintering, the first precursor layer 32a is heated at 550 ° C for about 20 minutes in an oxygen atmosphere, and as shown in FIG. 1D, bismuth (Bi) is formed on the gate electrode oxide layer 20. The first oxide layer 32 composed of niobium (Nb) (which may contain unavoidable impurities. The same applies hereinafter). Further, the first oxide layer 32 composed of bismuth (Bi) and niobium (Nb) is also referred to as a BNO layer.

Here, an example of the bismuth (Bi)-containing precursor used in the first oxide layer 32 of the present embodiment is bismuth octoate. As another example, ruthenium chloride, ruthenium nitrate, or various decane oxides (for example, ruthenium isopropoxide, ruthenium oxide, ruthenium ethoxylate, ruthenium methoxy ethoxylate) may be used. Further, an example of the niobium (Nb)-containing precursor used in the first oxide layer 32 of the present embodiment is bismuth octoate. Other examples may be cerium chloride, cerium nitrate or various cerium oxides (e.g., cerium isopropoxide, cerium oxide, cerium ethoxylate, cerium methoxy ethoxylate).

Thereafter, as shown in FIG. 1E, a second precursor layer 34a is formed on the first oxide layer 32 by a known spin coating method, wherein the second precursor layer 34a is used to contain a lanthanum (La) precursor. And the precursor containing ruthenium (Ta) is a solute precursor solution (referred to as a second precursor solution. Hereinafter, the solution for the second precursor is also the same) as a starting material. Thereafter, it was heated at 250 ° C for about 5 minutes as a preliminary sintering. In the present embodiment, in order to obtain a sufficient thickness (for example, about 20 nm) of the second oxide layer 34, the second precursor layer 34a is formed by the spin coating method and the preliminary sintering is performed once. Thereafter, as a main sintering system, the second precursor layer 34a is heated at 550 ° C for about 15 minutes in an oxygen atmosphere, and as shown in FIG. 1F, lanthanum (La) and tantalum (Ta) are formed on the first oxide layer 32. The second oxide layer 34 (which may contain unavoidable impurities. The same applies hereinafter). Further, the second oxide layer 34 composed of lanthanum (La) and tantalum (Ta) is also referred to as an LTO layer.

On the other hand, in the thin film transistor 100 of the present embodiment, the stacked oxide of the first oxide layer 32 and the second oxide layer 34 is used as the gate insulating layer 30. Further, in the first oxide layer 32 of the present embodiment, the atomic composition ratio of bismuth (Bi) to niobium (Nb) is 铌 (Nb) when the bismuth (Bi) is 1. Further, in the second oxide layer 34 of the present embodiment, the atomic composition ratio of lanthanum (La) to tantalum (Ta) is 钽 (Ta) is 1.5 when lanthanum (La) is 1. Further, at this time, the thickness of the first oxide layer 32 is about 160 nm, and the thickness of the second oxide layer 34 is about 20 nm. Further, regarding the atomic composition ratio of bismuth (Bi) and bismuth (Nb) in the first oxide layer 32, when bismuth (Bi) is 1, ytterbium (Nb) is 0.33 or more and 3 or less, and the present embodiment can be used with high accuracy. At least a part of the effects of the embodiment. In addition, regarding the second oxidation The atomic composition ratio of the lanthanum (La) to the cerium (Ta) of the material layer 34 is such that when lanthanum (La) is 1, the yttrium (Ta) is 0.11 or more and 9 or less, and at least the effect of the embodiment can be exhibited with high accuracy. portion.

Here, an example of the yttrium-containing (La) precursor used in the second oxide layer 34 of the present embodiment is yttrium acetate. In other examples, cerium nitrate, cerium chloride, or various decane oxides (e.g., cerium isopropoxide, cerium oxide, cerium ethoxide, cerium methoxy ethoxylate) may be used. Further, an example of the tantalum-containing (Ta) precursor used in the second oxide layer 34 of the present embodiment is a ruthenium oxide. Other examples include cerium nitrate, cerium chloride, or various other decane oxides (e.g., cerium isopropoxide, cerium oxide, cerium ethoxide, cerium methoxy ethoxylate).

Further, in the present embodiment, the second oxide layer 34 composed of lanthanum (La) and tantalum (Ta) is used, but the second oxide layer 34 is not limited to this composition. For example, a second oxide layer composed of lanthanum (La) and zirconium (Zr) may be used (although impurities which are unavoidable may be contained. The same applies hereinafter. Also referred to as an LZO layer). In this case, an example of the precursor containing lanthanum (La) is yttrium acetate. As another example, cerium nitrate, cerium chloride or various cerium oxides (for example, cerium isopropoxide, cerium oxide, cerium ethoxide, cerium methoxy ethoxylate) may be used. Further, an example of a precursor containing zirconium (Zr) is zirconium butoxide. As another example, zirconium nitrate, zirconium chloride or various other zirconium alkoxides (e.g., zirconium isopropoxide, zirconium butoxide, zirconium ethoxide, zirconium oxymethane) may be used. Further, a second oxide layer composed of strontium (Sr) and tantalum (Ta) may be used (although impurities which are unavoidable may be contained. The same applies hereinafter. Also referred to as an STO layer). In this case, an example of the precursor containing ruthenium (Sr) is ruthenium acetate. As another example, nitrate can be used. Barium strontium, strontium chloride or various decane oxides (for example bismuth isopropoxide, bismuth oxide, cesium ethoxylate, methoxymethoxy ethoxylate). Further, the example of the precursor containing ruthenium (Ta) is the same as the above example.

(3) Formation of the channel

Thereafter, as shown in FIG. 1G, a channel precursor layer 40a is formed on the second oxide layer 34 by a known spin coating method, wherein the channel precursor layer 40a is used to include an indium (In) precursor and A precursor solution for a channel containing a zinc (Zn) precursor as a solute (hereinafter, a solution for a channel precursor is also the same) is used as a starting material. Thereafter, as a preliminary sintering system, the channel precursor layer 40a was heated at 250 ° C for about 5 minutes. Thereafter, as the main sintering, the channel precursor layer 40a is heated in an oxygen atmosphere at 350 ° C. or higher and 550 ° C or lower for about 15 minutes, and as shown in FIG. 1H, indium is formed on the second oxide layer 34. In) an oxide layer 40 for channel formed of zinc (Zn) (which may contain unavoidable impurities. The same applies hereinafter). Further, the channel oxide layer 40 composed of indium (In) and zinc (Zn) is also referred to as an IZO layer. Further, in the channel oxide layer 40 of the present embodiment, the atomic composition ratio of indium (In) to zinc (Zn) is 0.5, and when indium (In) is 1, zinc (Zn) is 0.5. Further, the thickness of the channel oxide layer 40 is about 20 nm. Further, in particular, a thin film transistor having an atomic composition ratio of zinc (Zn) of 0.25 or more and 1 or less when indium (In) is 1 in the channel oxide 40 is preferable from the viewpoint of improving electric field effect mobility. .

Here, an example of the indium (In) precursor used for the channel oxide layer 40 of the present embodiment is indium acetylacetonate. Other examples may use indium nitrate, indium chloride, or various indium alkoxides (eg, indium isopropoxy Compound, indium butoxide, indium ethoxylate, indium methoxy ethoxylate). Further, an example of the zinc-containing (Zn) precursor used in the channel oxide layer 40 of the present embodiment is zinc chloride. Other examples may be zinc nitrate, zinc acetate, or various zinc alkoxides (e.g., zinc isopropoxide, zinc butoxide, zinc ethoxylate, zinc methoxyethoxylate).

Further, in the present embodiment, the channel oxide layer 40 made of indium (In) and zinc (Zn) is used, but the channel oxide layer is not limited to this composition. For example, the channel oxide is an oxide composed of gallium (Ga) and zinc (Zn), an oxide composed of aluminum (Al) and zinc (Zn), and zinc (Zn) and tin (Sn). An oxide composed of an oxide, zinc (Zn), indium (In), and tin (Sn), an oxide composed of indium (In), gallium (Ga), and zinc (Zn), and lanthanum (La) An oxide composed of indium (In) and zinc (Zn), an oxide composed of yttrium (Hf) and indium (In) and zinc (Zn), strontium (Sc) and indium (In) and zinc (Zn) One of the constituent oxide groups can also exert at least a part of the effects of the present embodiment. In addition, examples of gallium (Ga), zinc (Zn), aluminum (Al), indium (In), or tin (Sn) precursors may be metal organic acid salts, metal inorganic acid salts, metal halides, Or a variety of metal alkoxides.

Therefore, the process for forming the channel oxide layer 40 can be carried out in such a manner that a precursor solution selected from the group consisting of a precursor containing indium (In) and a precursor containing zinc (Zn) as a solute is used, and gallium is used. (Ga) precursor and zinc-containing (Zn) precursor are solute precursor solution, aluminum-containing (Al) precursor and zinc-containing (Zn) precursor are solute precursor solution, zinc-containing (Zn) precursors and tin-containing (Sn) precursors are solute precursors The solution, the zinc-containing (Zn) precursor and the indium-containing (In) precursor and the tin-containing (Sn) precursor are the solute precursor solution, the indium-containing (In) precursor and the gallium-containing (Ga) Before the precursor and the zinc-containing (Zn) precursor are the solute precursor solution, before the lanthanum-containing (La) precursor and the indium-containing (In) precursor and the zinc-containing (Zn) precursor are used as the solute The body solution, the precursor containing yttrium (Hf) and the precursor containing indium (In) and the precursor containing zinc (Zn) are precursor solutions of solute, precursors containing strontium (Sc) and indium containing (In) before the precursor and the zinc-containing (Zn) precursor is a solute precursor solution, one of the channel precursor precursor solution is used as a starting material for the passage of the precursor layer in an oxygen-containing atmosphere, Forming an oxide composed of the indium (In) and the zinc (Zn), an oxide composed of the gallium (Ga) and the zinc (Zn), and the aluminum (Al) and the zinc (Zn) An oxide composed of the zinc (Zn) and the tin (Sn), an oxide composed of the zinc (Zn) and the indium (In) and the tin (Sn), The indium (In) and the oxide formed by the gallium (Ga) and the zinc (Zn) (La) and an oxide composed of the indium (In) and the zinc (Zn), an oxide composed of the hafnium (Hf) and the indium (In) and the zinc (Zn), and the crucible (Sc) And an oxide for a channel of the group consisting of the indium (In) and the oxide composed of the zinc (Zn). Further, it is considered that since each of the above-mentioned oxides is an amorphous oxide, a good interface state can be obtained with the second oxide which is in contact with the channel, and as a result, electrical characteristics of the transistor itself can be improved.

Further, the thin film transistor in which the thickness of the oxide for each channel is 5 nm or more and 80 nm or less is suitable from the viewpoint of obtaining high electric field effect mobility (μ _FE ). Further, the thin film transistor having a thickness of 20 nm or more and 40 nm or less is more suitable. In particular, as long as the thickness of the channel oxide layer 40 composed of indium (In) and zinc (Zn) is in the range of 20 nm or more and 80 nm or less, an electric field effect mobility of 1 (cm ² /Vs) or more can be obtained (μ _FE As long as the thickness is 20 nm or more and 40 nm or less, an electric field effect mobility (μ _FE ) of 5 (cm ² /Vs) or more can be obtained.

(4) Formation of source electrode and drain electrode

Thereafter, as shown in FIG. 1J, the patterned photoresist film 90 is formed on the channel oxide layer 40 by a known photolithography method, and is known on the channel oxide layer 40 and the photoresist film 90. A ITO (indium tin oxide) layer 50 is formed by sputtering. The target of the present embodiment is ITO containing 5 wt% of tin oxide (SnO ₂ ), which is formed at room temperature. Thereafter, when the photoresist film 90 is removed, the drain electrode 52 and the source electrode 54 of the ITO layer are formed on the channel oxide layer 40 as shown in FIG. 1K.

Thereafter, after the patterned photoresist film 90 is formed on the gate electrode 52, the source electrode 54, and the channel oxide layer 40 by a known photolithography method, the photoresist film 90 and the drain electrode 52 are used. A portion and a portion of the source electrode 54 are used as a cover, and the exposed channel oxide layer 40 is removed by dry etching of a known argon (Ar) plasma. As a result, the thin film transistor 100 is fabricated by forming the patterned channel oxide layer 40.

As described above, the thin film transistor 100 of the present embodiment is particularly worth mentioning that the gate electrode, the gate insulating layer, the channel, the source electrode, and the drain electrode are all formed of a metal oxide. Further, in the present embodiment, since the gate electrode, the gate insulating layer, and the channel are formed by heating a solution of various precursors in an oxygen-containing atmosphere, it is compared with the conventional one. The method can easily achieve a large area, and industrial and even mass production can be particularly improved.

[Characteristics of Thin Film Transistor 100]

Next, the inventors investigated various characteristics of the thin film transistor 100 manufactured by the above-described manufacturing method.

[1. Current-voltage characteristics]

2 is a Vg-Id characteristic diagram of the thin film transistor 100. Further, Table 1 shows the characteristics of the thin film transistor 100 with respect to the subcritical characteristic (SS), the electric field effect mobility ( _μFE ), and the capacitance per unit area (C _OX ) of the gate insulating layer 30 of the stacked oxide.

As shown in Fig. 2 and Table 1, the Vg-Id characteristics of the thin film transistor 100 of the first embodiment described above were obtained, and good characteristics of the crystal were obtained.

On the other hand, as described above, the thin film transistor 100 of the present embodiment is particularly worthy of mentioning that the stacked oxide formed by the first oxide layer 32 and the second oxide layer 34 is regarded as the gate insulating layer 30. Use this. After many trial and error, the inventor of the present invention found that the first oxide layer composed of bismuth (Bi) and niobium (Nb) has a very high dielectric constant (typically, ε _r is 60 or more and 250 or less). 32. However, in the present embodiment, it has been found that when a channel layer which is an amorphous oxide is disposed on the first oxide layer 32, the so-called overflow current increases (representatively, 10 at 1 MV/cm). ^-6 A/cm ² or more), the surface flatness is lowered, and the mutual diffusion of atoms with the interface of the channel material becomes very large, so that it is difficult to obtain sufficient characteristics of the crystal. After that, after further research and detailed analysis, it was found that if the leakage current as a monomer is very small (representatively, it is 10 ^-7 A/cm ² or less in 1 MV/cm), the surface is flat. The second oxide layer 34 which is excellent in properties and whose atomic interdiffusion at the interface with the channel material is suppressed is interposed between the first oxide layer 32 and the channel oxide layer 40, thereby obtaining a transistor. Fully versatile.

Further, the combined capacitance of the gate insulating layer 30 of the stacked oxide formed by the first oxide layer 32 and the second oxide layer 34 is 5 × 10 ^-8 F / cm ² or more and 1 × 10 ^-6 F / cm ^{2 is} better. In this range, in the transistor characteristics, a steep rise in the gate current with respect to the gate voltage and an increase in the on-current can be achieved, and the shutdown current of the drain with respect to the gate voltage can be reduced, and the electric field effect mobility can be reduced. Increases are also possible. From the foregoing viewpoints, a more preferable synthetic capacitance range is 1 × 10 ^-7 F / cm ² or more and 1 × 10 ^-6 F / cm ² or less. Further, the composite dielectric coefficient of the stacked oxide formed of the first oxide layer 32 and the second oxide layer 34 is preferably 60 or more and 200 or less, from the viewpoint of improving the transistor characteristics.

[2. Observation by section TEM]

Further, in various analysis processes, it was confirmed that the first oxide layer 32 contains a crystal phase and an amorphous phase. In more detail, it is understood that the first oxide layer 32 contains a crystal phase, a microcrystalline phase, and an amorphous phase. Fig. 3 is a view showing the inclusion of the first oxide 32 according to the first embodiment. A cross-sectional TEM (Transmission Electron Microscopy) photograph of a stack structure of a first oxide produced by a process having the same process. As shown in FIG. 3, it was confirmed that at least a part of the first oxide 32 has a crystal structure. In more detail, the amorphous phase, the microcrystalline phase, and the crystalline phase were confirmed in the first oxide 32. In the present application, the term "microcrystalline phase" means a crystal phase in which the crystal phase does not grow in the same manner from the upper end to the lower end in the film thickness direction of the layer when a certain layered material is formed. Further, according to the study by the inventors of the present invention, since the first oxide layer 32 contains an amorphous state of microcrystals, the first oxide layer 32 is generally provided with a high dielectric constant, but is considered to be considered to have a high dielectric constant. The value of the overflow current exceeds the applicable allowable range of the thin film transistor, and the surface flatness of the first oxide layer 32 is low.

On the other hand, the second oxide layer 34 does not have a specific crystal structure, but a substantially amorphous layer is obtained, which is an interesting taste. Fig. 4 shows an AFM (Atomic Force Microscopy) image of the surface of the second oxide produced by the same process as the manufacturing process of the second oxide 34 of the present embodiment. As shown in FIG. 4, it was confirmed that the second oxide layer 34 is amorphous unlike the first oxide layer 32 having a constant crystal structure. Therefore, it is considered that the second oxide layer 34 contributes to the formation of a good bonding interface (an interface where atoms are mutually diffused) with the channel oxide layer 40, and as a result, the overflow current can be reduced. Further, in the present embodiment, since the first oxide layer 32 and the second oxide layer 34 are formed in a state in which they are not completely crystallized, the electrical characteristics are exhibited. The edge layer 30 is formed by a relatively low temperature heat treatment, which is particularly noteworthy.

<Second embodiment>

In the present embodiment, the atomic composition ratios of lanthanum (La) and tantalum (Ta) of the base material, the gate electrode, and the second oxide layer are the same as those of the first embodiment. Therefore, the description overlapping with the first embodiment will be omitted.

Fig. 1M is a schematic cross-sectional view showing the structure of the thin film transistor 200 of the present embodiment. The gate electrode of the thin film transistor 200 of the present embodiment is formed of a platinum (Pt) layer 220. The platinum layer 220 is formed by a known sputtering method on a SiO ₂ /Si substrate (that is, a substrate on which a hafnium oxide film is formed on a tantalum substrate) 210 as a substrate. Further, in order to improve the adhesion between the platinum (Pt) layer 220 and the SiO ₂ /Si substrate as the substrate, in the present embodiment, a TiO _X film (not shown) having a thickness of about 10 nm is formed on the SiO ₂ . Further, in the second oxide layer 234 of the present embodiment, the atomic composition ratio of lanthanum (La) to tantalum (Ta) is 钽 (Ta) is 4 when 镧 (La) is 1.

<Third embodiment>

This embodiment is the same as the second embodiment except that the second oxide layer is different. Therefore, the description overlapping with the first and second embodiments will be omitted.

Fig. 1M also shows a schematic cross-sectional view of the structure of the thin film transistor 300 of the present embodiment. The second oxide layer 334 of the present embodiment is a so-called composite oxide composed of lanthanum (La) and zirconium (Zr) formed by a precursor solution, wherein the precursor solution is a lanthanum-containing (La) precursor. And the precursor containing zirconium (Zr) is a solute. Further, regarding the second oxygen of the embodiment The atomic composition ratio of lanthanum (La) to zirconium (Zr) in the layer 334 is 7. When lanthanum (La) is 3, zirconium (Zr) is 7. Further, at this time, the thickness of the first oxide layer 32 is about 160 nm, and the thickness of the second oxide layer 334 is about 20 nm.

<Fourth embodiment>

This embodiment is the same as the second embodiment except that the second oxide layer is different. Therefore, the description of the first and second embodiments will be omitted.

Fig. 1M also shows a schematic cross-sectional view of the structure of the thin film transistor 400 of the present embodiment. The second oxide layer 434 of the present embodiment is a so-called composite oxide composed of strontium (Sr) and strontium (Ta) formed of a precursor solution, wherein the precursor solution is a strontium-containing (Sr) precursor. And the solute containing the precursor of cerium (Ta). Further, in the second oxide layer 434 of the present embodiment, the atomic composition ratio of strontium (Sr) to strontium (Ta) is 钽 (Ta) is 1 when 锶(Sr) is 1. Further, the thickness of the first oxide layer 32 at this time is about 160 nm, and the thickness of the second oxide layer 434 is about 20 nm.

[Characteristics of Thin Film Transistors 200, 300, and 400 of Second to Fourth Embodiments]

As a result of examining the Vg-Id characteristics of the thin film transistors 200, 300, and 400 of the second to fourth embodiments, the results are not inferior to those of the thin film transistor 100 of the first embodiment.

Fig. 5 is a Vg-Id characteristic diagram of the thin film transistors 200, 300, and 400. In addition, Table 2 shows the capacitance per unit area of the thin film transistors 200, 300, 400 with respect to the subcritical characteristic (SS), the electric field effect mobility ( _μFE ), and the gate insulating layer 30 of the stacked oxide (C). _OX ) characteristics.

Further, even in the case of the above-described respective second oxide layers 334 and 434, the overflow current value is typically 1 MV/cm or less in the range of 10 ^-7 A/cm ² or less. In particular, the value of the overflow current of the second oxide layer 334 belonging to the LZO layer is typically 1 MV/cm or less in the order of 10 ^-8 A/cm ² .

Further, in the case where the second oxide layer 234 belonging to the LTO layer is used, the composite specific dielectric constant ε _r of the stacked oxide of the first oxide layer 32 and the second oxide layer 234 is about 123. Further, when the second oxide layer 334 belonging to the LZO layer is used, the composite specific dielectric constant ε _r of the stacked oxide of the first oxide layer 32 and the second oxide layer 334 is about 94. On the other hand, when the second oxide layer 434 belonging to the STO layer is used, the composite specific dielectric constant ε _r of the stacked oxide of the first oxide layer 32 and the second oxide layer 434 is about 134 and becomes high. The value, this point is especially worth mentioning.

On the other hand, the first oxide layer 32 in each of the above embodiments is formed by sintering a precursor solution containing a ruthenium (Bi) precursor and a ruthenium (Nb) precursor as a solute. As described above in the present application, the method of forming the precursor oxide solution as a starting material and sintering it to form the first oxide layer 32 and other oxide layers is convenient. For the sake of explanation, it is also called "solution method". The first oxide layer 32 formed by the solution method is a suitable insulating layer because of a small dielectric loss. Fig. 6 is a graph showing the tan δ value of the first oxide layer 32 formed by the solution method, which represents the ratio of dielectric loss to frequency (Hz). In addition, FIG. 6 also shows a BNO layer formed by a known sputtering method as a modification of the first oxide layer 32 of the present embodiment ("Other Embodiment 1"), and as "Other Embodiment 2" The results of the composite oxide (BZNO layer) composed of bismuth (Bi) and zinc (Zn) and niobium (Nb) formed by a solution method in the same manner as in the first embodiment. Further, as for the precursor solution of the composite oxide in the other Example 2, the bismuth (Bi)-containing precursor is ruthenium octoate. As another example, ruthenium chloride, ruthenium nitrate or various decane oxides may be used. Further, an example of the zinc-containing (Zn) precursor is zinc chloride. As another example, zinc nitrate, zinc acetate or various zinc alkoxides (for example, zinc isopropoxide, zinc butoxide, zinc ethoxylate, zinc methoxyethoxylate) may be used. Further, in the case where zinc acetate is used as the zinc-containing (Zn) precursor, in order to increase the solubility of zinc, it is preferable to add a small amount of the additive monoethanolamine to zinc acetate. As another additive, diethylamine ethanol, acetamidineacetone, or diethanolamine can also be used. Further, an example of a precursor containing cerium (Nb) is bismuth octoate. As another example, cerium chloride, cerium nitrate or various decane oxides (for example, cerium isopropoxide, cerium oxide, cerium ethoxide, cerium methoxy ethoxylate) may be used.

As shown in Fig. 6, it can be seen that the tan oxide value of the first oxide layer 32 of the present embodiment and the BNO layer (other embodiment 1) formed by the sputtering method is different from that of the other embodiment 2. Less electrical loss). Furthermore, also It is understood that even if the composition is the same, the dielectric loss of the first oxide layer 32 formed by the solution method is less than that of the BNO layer formed by the sputtering method (other embodiment 1).

As described above, the first oxide layer 32 formed by the solution method has characteristics of higher dielectric constant and less dielectric loss. Further, since it is not required to be complicated and expensive equipment such as a vacuum device, it can be formed in a short period of time, and therefore contributes greatly to the provision of a thin film transistor excellent in industriality and mass productivity. Similarly, the second oxide layers 34, 234, 334, and 434 formed by the solution method, the channel oxide 40, and the gate electrode oxides 20 and 220 are also complicated and expensive without requiring a vacuum device or the like. The equipment can be formed in a short period of time, and therefore contributes greatly to the provision of industrial and even mass-produced thin film transistors. Therefore, the thin film transistor including the first oxide layer 32 formed by the solution method can be said to have no zinc (Zn) in the first oxide layer 32 and can realize high performance of the thin film transistor. Quite excellent. Further, the BZNO film used in the above "Other Example 2" is inferior to the first oxide layer 32 (i.e., the BNO layer) from the viewpoint of dielectric loss, but is a thin film transistor using a BZNO film. The leakage current is small, so the BZNO film is also an example of a substitutable BNO layer.

<Fifth Embodiment>

In the present embodiment, the same applies to the first embodiment except that the stamper is applied during the formation of the partial layer of the first embodiment. Therefore, the description overlapping with the first embodiment will be omitted.

[Process of Thin Film Transistor 500]

7A to 7G are schematic cross-sectional views showing a process of a method of manufacturing the thin film transistor 500 of the present embodiment. In addition, in order to simplify the drawing, the description of the patterning of the electrodes drawn from the respective electrodes is omitted.

(1) Formation of gate electrode

In the present embodiment, first, a precursor electrode layer 520a for a gate electrode is formed on a SiO ₂ /Si substrate (hereinafter also simply referred to as "substrate") 210 as a substrate by a known spin coating method (which is used to contain lanthanum (La) The precursor and the precursor containing nickel (Ni) are the precursor solution of the solute as the starting material). Thereafter, as the preliminary sintering, the gate electrode precursor layer 520a was heated in the air at 150 ° C for about 5 minutes. By preparing the sintering, the solvent in the precursor electrode layer 520a for the gate electrode can be sufficiently evaporated, and a preferable gel state (which is considered to be the state of the residual organic chain before thermal decomposition) can be formed which can exhibit subsequent plastic deformation characteristics. . In order to achieve the above viewpoint with higher accuracy, the preliminary sintering temperature is preferably 80 ° C or more and 250 ° C or less. After that, in order to pattern the gate electrode, as shown in FIG. 7A, the gate electrode mold M1 was used, and the stamper was applied at a pressure of 5 MPa while being heated to 200 °C. As a result, the gate electrode precursor layer 520a having a thick layer portion having a layer thickness of about 100 nm to about 300 nm and a thin layer portion having a layer thickness of about 10 nm to about 100 nm is formed by the gate electrode mold M1 of the present embodiment. .

Further, according to the study by the inventors, plastic deformation of the gate electrode precursor layer 520a is performed by heating the gate electrode precursor layer 520a in a range of 80 ° C or more and 300 ° C or less in the above-described press molding process. The ability will become high and the main solvent can be removed sufficiently. Thus, right When the gate electrode precursor layer 520a is subjected to a press molding process, heating in a range of 80 ° C or more and 300 ° C or less is preferable. Here, when the heating temperature at the time of the press molding is less than 80 ° C, the plastic deformation ability of each precursor layer is lowered by the influence of the temperature decrease of the precursor layer of the precursor electrode layer 520a for the gate electrode, so that the molding of the stamper structure is formed. The dimensional realization of the molding, or the reliability after molding, may be deficient in stability. Further, when the heating temperature at the time of press molding exceeds 300 ° C, since the decomposition of the organic chain (oxidative thermal decomposition) which is the source of the plastic deformation ability is continuously performed, the plastic deformation ability is lowered. Further, from the above viewpoint, when the gate electrode precursor layer 520a is subjected to press molding, heating in a range of 100 ° C or more and 250 ° C or less is more preferable.

Thereafter, the gate electrode precursor layer 520a is completely etched, and as shown in FIG. 7B, the gate electrode precursor layer 520a is removed from the region other than the region corresponding to the gate electrode (for the gate electrode) The precursor layer 520a is fully etched). Further, the etching process of the present embodiment is performed by a wet etching technique which does not employ a vacuum process, but it may be etched by a so-called dry etching technique using a plasma slurry. Further, a well-known technique of performing plasma treatment under atmospheric pressure can also be employed.

Thereafter, as the main sintering, the gate electrode precursor layer 520a is heated at 580 ° C for about 15 minutes in an oxygen atmosphere, and as shown in FIG. 7C, lanthanum (La) and nickel (Ni) are formed on the substrate 210. The gate electrode oxide layer 520 is formed (although it may contain unavoidable impurities. The same applies hereinafter).

(2) Formation of gate insulating layer

Next, the first precursor layer 32a is formed on the substrate 210 and the patterned gate electrode oxide layer 520 in the same manner as in the first embodiment (before using the bismuth (Bi)-containing precursor and the ytterbium-containing (Nb) layer. The precursor is a solute precursor solution as a starting material). After the preliminary sintering was carried out in the same manner as in the first embodiment, the first precursor layer 32a was heated at 550 ° C for about 20 minutes in an oxygen atmosphere as the main sintering.

Thereafter, the second precursor layer 34a is formed on the first oxide layer 32 in the same manner as in the first embodiment (the precursor solution containing yttrium (La) precursor and yttrium (Ta) precursor is used as the solute precursor solution. Starting material). After the preliminary sintering was carried out in the same manner as in the first embodiment, the second precursor layer 34a was heated at 550 ° C for about 15 minutes in an oxygen atmosphere as the main sintering. As a result, as shown in FIG. 7D, a second oxide layer 34 made of lanthanum (La) and tantalum (Ta) is formed on the first oxide layer 32 (it is possible to contain unavoidable impurities. The same applies hereinafter. ).

On the other hand, in the thin film transistor 500 of the present embodiment, the stacked oxide of the first oxide layer 32 and the second oxide layer 34 is used as the gate insulating layer 30. Further, the thickness of the first oxide layer 32 of the present embodiment is about 180 nm, and the thickness of the second oxide layer 34 is about 20 nm.

(3) Formation of the channel

Then, on the second oxide layer 34, a channel precursor layer is formed in the same manner as in the first embodiment (a precursor for a channel containing a precursor containing indium (In) and a precursor containing zinc (Zn) as a solute is used. The solution is used as a starting material). Thereafter, preliminary sintering is performed in the same manner as in the first embodiment. Formal sintering. As a result, a channel oxide layer 40 made of indium (In) and zinc (Zn) is formed on the second oxide layer 34 (it may contain unavoidable impurities. The same applies hereinafter). Further, the thickness of the channel oxide layer 40 of the present embodiment is about 20 nm.

Further, in the present embodiment, in order to pattern the channel, after the preliminary sintering for the channel precursor layer, a channel-specific mode (not shown) may be used in the same manner as the patterning of the gate electrode. The other state of the die-casting process. In other words, before the formation of the channel oxide 40, the press molding process is performed in an oxygen-containing atmosphere in a state of heating to 80 ° C or more and 300 ° C or less to form a stamper structure for the channel precursor layer. The stamping process, which is the other state that can be used. Further, for the stamper processing for forming the channel, conditions such as a preferable heating temperature range or pressure similar to the patterning of the gate electrode can be applied.

(4) Formation of source electrode and drain electrode

In the present embodiment, then, in the case of the solution method, press molding is performed to form a source electrode and a drain electrode composed of an ITO layer. Specifically, it is as follows.

First, a source/drain electrode precursor layer 550a is formed on the channel oxide layer 40 by a known spin coating method (using an indium-containing (In) precursor and a tin-containing (Sn) precursor as a solute. The source/drain electrode precursor solution (the same applies to the source/drain electrode precursor solution) is used as the starting material).

Here, examples of the indium (In) precursor used for the source/drain electrode oxide layer 550 of the present embodiment may be indium acetate or nitric acid. Indium, indium chloride, or various indium alkoxides (eg, indium isopropoxide, indium butoxide, indium ethoxylate, indium methoxy ethoxylate). Further, examples of the tin-containing (Sn) precursor used in the source/drain electrode oxide layer 550 of the present embodiment may be tin acetate, tin nitrate, tin chloride, or various tin alkoxides (for example). For example, tin isopropoxide, tin oxide, tin ethoxylate, tin methoxy oxide).

Thereafter, as a preliminary sintering, the source/drain electrode precursor layer 550a was heated at 150 ° C in the atmosphere for about 5 minutes. Thereafter, in order to pattern the source/drain electrodes, as shown in FIG. 7E, the source/drain electrode mold M2 is used in a state of being heated to 200 ° C, and compression molding is performed under a pressure of 5 MPa. .

As a result, a source/drain electrode precursor layer 550a having a layer thickness of about 100 nm to about 300 nm is formed in a region (a) of the source electrode and the drain electrode in the future. Further, a source/drain electrode precursor layer 550a having a layer thickness of about 10 nm to about 100 nm is formed in a region (Fig. 7F (b)) in which the channel oxide layer 40 remains in the future. On the other hand, a source/drain electrode precursor layer 550a having a layer thickness of about 10 nm to about 100 nm is formed in a region where the channel oxide layer 40 is removed ((c) of FIG. 7F). Further, at least a part of the effects of the present embodiment can be obtained by using the source/drain electrode mold M2 and applying a press molding at a pressure of 1 MPa or more and 20 MPa or less.

Thereafter, as the main sintering, the source/drain electrode precursor layer 550a is heated in the atmosphere at 250 ° C. or higher and 400 ° C or lower in the atmosphere for about 5 minutes to form the source/drain electrode oxide layer 550.

Thereafter, dry etching is performed on the entire surface of the source/drain electrode oxide layer 550 by argon (Ar) plasma. As a result, the source/drain electrode oxide layer 550 in the thinnest region ((c) of FIG. 7F) is first etched, and then the exposed channel oxide layer 40 is continuously etched. Next, the oxide layer 550 for the source/drain electrode of the second thin region ((b) of FIG. 7F) is etched, and the oxide layer for the channel at the thinnest region ((c) of FIG. 7F) is etched. After 40 is etched, the plasma treatment is stopped. As described above, in the present embodiment, the thickness of each layer in the regions (b) and (c) is adjusted, and the region (c) is removed in a state in which the channel oxide layer 40 of the region (b) remains. The channel uses an oxide layer 40. As a result, as shown in FIG. 7G, the separation of the channel region itself can be achieved, and the source electrode 554 and the drain electrode 552 are completely separated by the channel region.

In the present embodiment, the film transistor 500 of the present embodiment is produced by heating at 500 ° C for about 15 minutes in a nitrogen atmosphere. Since the oxygen treatment in the ITO is caused by the heat treatment, the defect becomes a conductive oxygen-defective carrier, so that the conductivity can be improved. Fig. 8 is a plan view of an optical microscope obtained by the thin film transistor 500 manufactured in the present embodiment. As shown in Fig. 8, the separation of the channel regions of the sub-micro order (specifically, about 500 nm) can be realized by the compression molding process of the present embodiment, which is particularly worthy of explanation. Further, the source electrode 554 and the drain electrode 552 formed in the present embodiment have a resistivity of 10 ^-3 Ωcm or less.

Further, although the etching process of the present embodiment is etched by dry etching using argon (Ar) plasma, it may be carried out by a wet etching technique which does not use a vacuum program.

Further, according to the research by the inventors, when the source/drain electrode precursor layer 550a is heated in the range of 80 ° C or more and 250 ° C or less, the source/drain electrode precursor layer 550a is used in the preliminary sintering. The plastic deformation ability becomes high, and the main solvent can be sufficiently removed. Therefore, it is preferable to heat the source/drain electrode precursor layer 550a in a range of 80 ° C or more and 250 ° C or less. Further, the upper limit of the temperature range and the adjustment according to the preliminary sintering are the same as the basis for the preliminary sintering of the precursor electrode layer 520a for the gate electrode. Further, the heating temperature of the source/drain electrode precursor layer 550a is more preferably in the range of 100 ° C to 250 ° C.

As described above, in the present embodiment, a "die-casting process" in which a part of the oxide layer is subjected to press molding to form a stamper structure is employed. By using this stamping process, there is no need for a vacuum process or a procedure using photolithography, or an ultraviolet irradiation process, which requires a long time and/or expensive equipment. Further, in the present embodiment, since the source electrode and the drain electrode are also formed by a solution method, all the oxide layers constituting the gate electrode, the gate insulating film, the channel, the source electrode, and the drain electrode element are It is formed by the solution method, which deserves special explanation. Therefore, the thin film transistor 500 of the present embodiment is extremely excellent in industrial property and mass productivity.

[Characteristics of Thin Film Transistor 500 of Fifth Embodiment]

Vg- of the thin film transistor 500 of the fifth embodiment described above As a result of investigation of the Id characteristics, good characteristics of the transistor can be obtained.

Fig. 9 is a Vg-Id characteristic diagram of the thin film transistor 500. Further, Table 3 shows the characteristics of the thin film transistor 500 with respect to subcritical characteristics (SS) and electric field effect mobility (μ _FE ). Further, V _D of FIG. 9 is a voltage (V) applied between the source electrode and the drain electrode of the thin film transistor 500.

As shown in FIG. 9 and Table 3, the ON/OFF ratio of the thin film transistor 500 is about 10 ⁶ steps. As described above, each of the layers constituting the thin film transistor 500 is an oxide layer and is formed by a solution method and a press molding process, but it has been confirmed that the function of the transistor itself can be exhibited.

<Sixth embodiment>

In the present embodiment, the stamping process is mainly performed in the formation of the gate insulating layer in the fifth embodiment, and the fifth embodiment is similar to the fifth embodiment. Therefore, the description overlapping with the first or fifth embodiment will be omitted.

[Process of Thin Film Transistor 600]

10A to 10D are schematic cross-sectional views showing a process of a method of manufacturing the thin film transistor 600 of the present embodiment. Further, in order to simplify the drawing, the description of the patterning of the electrodes drawn from the respective electrodes is omitted.

(1) Formation of gate electrode

In the present embodiment, as in the fifth embodiment, the gate electrode precursor layer 520a is first formed on the SiO ₂ /Si substrate 210 as a substrate. Thereafter, as a preliminary sintering, the gate electrode precursor layer 520a is heated at 80 ° C or more and 250 ° C or less in about 5 minutes. Then, in order to pattern the gate electrode, as shown in FIG. 10A, the gate electrode mold M1 is used, and the gate electrode mold M1 is used, and the stamper is applied at a pressure of 1 MPa or more and 20 MPa or less in a state of being heated at 80 ° C or more and 300 ° C or less. . As a result, the gate electrode precursor layer 520a having a thick layer portion having a thickness of about 100 to 300 nm and a thin layer portion having a layer thickness of about 10 nm to about 100 nm is formed by the gate electrode mold M1 of the present embodiment.

Thereafter, the gate electrode precursor layer 520a is completely etched, and the gate electrode precursor layer 520a (the etching process for the gate electrode precursor layer 520a) is removed from the region other than the gate electrode region. Thereafter, main sintering is performed in the same manner as in the fifth embodiment to form an oxide layer 520 for a gate electrode made of lanthanum (La) and nickel (Ni) on the substrate 210 (although impurities which are unavoidable may be contained). The same is true below.).

(2) Formation of gate insulating layer

Next, on the substrate 210 and the patterned gate electrode oxide layer 520, the first precursor layer 632a is formed in the same manner as in the first embodiment (using a bismuth (Bi)-containing precursor and a ytterbium-containing (Nb) layer. The precursor is a solute precursor solution as a starting material). Thereafter, preliminary sintering is performed in a state of being heated to 80 ° C or more and 250 ° C or less in an oxygen-containing atmosphere.

Next, on the first precursor layer 632a, a second precursor layer 634a is formed in the same manner as in the first embodiment (a precursor solution containing a lanthanum (La) precursor and a ruthenium (Ta) precursor is used as a solute precursor solution. Starting material). Thereafter, preliminary sintering is performed in a state of being heated to 80 ° C or more and 250 ° C or less in an oxygen-containing atmosphere.

In the present embodiment, the first precursor layer 632a and the second precursor layer 634a in the stacked state in which only preliminary sintering is performed are subjected to press molding. Specifically, in order to pattern the gate insulating layer, as shown in FIG. 10B, in the state of being heated to 80 ° C or more and 300 ° C or less, the gate insulating layer mold M3 is used, and the pressure is 1 MPa or more and 20 MPa or less. Apply compression molding. As a result, the first precursor layer 632a and the second precursor layer 634a are formed by the gate insulating layer mold M3 of the present embodiment (all having a thick layer portion having a layer thickness of about 100 nm to about 300 nm and a layer thickness of about 10 nm). A precursor insulating layer 630a for a gate insulating layer of a stacked structure of about 100 nm.

Thereafter, the gate insulating layer precursor layer 630a is completely etched, and as shown in FIG. 10C, the gate insulating layer precursor layer 630a is removed from the region other than the region corresponding to the gate insulating layer 630 (for the gate) The insulating layer is etched by the precursor layer 630a. Further, although the etching process for the precursor insulating layer 630a of the gate insulating layer of the present embodiment is performed by a wet etching technique using no vacuum process, it may be etched by a so-called dry etching technique using plasma.

Thereafter, the main sintering is performed at 550 ° C for about 20 minutes to form a gate insulating layer including the stacked oxide of the first oxide layer 632 and the second oxide layer 634 on the gate electrode oxide layer 520. 630 (but can contain unavoidable impurities. The same applies below.). Further, the thickness of the first oxide layer 632 of the present embodiment is from about 50 nm to about 250 nm, and the thickness of the second oxide layer 634 is from about 5 nm to about 50 nm.

(3) Formation of channel, source electrode, and drain electrode

Thereafter, similarly to the fifth embodiment, after the channel oxide layer 40 is formed, the source electrode 554 and the drain electrode 552 are formed to be completely separated via the channel region. As a result, the thin film transistor 600 shown in Fig. 10E was produced. Therefore, as described above, since the gate electrode, the gate insulating layer, the channel, the source electrode, and the gate electrode can be easily patterned by the solution method and the press molding process, the thin film electricity of the embodiment The crystal 600 is extremely excellent in industrial properties and mass productivity.

<Seventh embodiment>

In the present embodiment, the indium oxide is mainly used for the channel material of the second embodiment, and the second embodiment is similar to the second embodiment. Therefore, the description overlapping with the first or second embodiment will be omitted.

Fig. 1M also shows a schematic cross-sectional view of the structure of the thin film transistor 700 of the present embodiment. The channel material of the thin film transistor 700 of the present embodiment is indium oxide as described above.

In the channel formation process of the present embodiment, first, a precursor layer for a channel is formed on the second oxide layer 34 by a known spin coating method (a precursor solution for a channel using a precursor containing indium (In) as a solute is used. As a starting material). Thereafter, as the preliminary sintering, the precursor layer was heated at 250 ° C for about 5 minutes. After that, as the main sintering, the precursor layer is heated in an oxygen atmosphere at 350 ° C or higher and 550 ° C or lower for about 15 minutes. A channel oxide layer 740 made of indium oxide is formed on the second oxide layer 34. Further, the thickness of the channel oxide layer 740 is about 20 nm.

Here, an example of the indium (In) precursor used for the channel oxide layer 740 of the present embodiment is indium acetylacetonate. Other examples may include indium nitrate, indium chloride, or various indium alkoxides (e.g., indium isopropoxide, indium butoxide, indium ethoxylate, indium methoxyethoxylate).

Further, the X-ray diffraction (XRD) of the indium oxide layer formed by the same process as the channel oxide layer 740 of the present embodiment was investigated, and an interesting result was obtained. Figure 11A is a graph showing the X-ray diffraction (XRD) results of an indium oxide layer formed by the same process as that of the thin film transistor 700. For comparison, Fig. 11B shows the X-ray diffraction (XRD) results of the IZO layer formed by the same process as that of the thin film transistor of the first embodiment.

In Fig. 11A, it is confirmed that the peak indicated by (a) of In ₂ O ₃ (222) and the peak indicated by (b) of In ₂ O ₃ (400) are considered to be displayed. Therefore, it is understood that the channel oxide layer 740 of the present embodiment has at least crystallinity. On the other hand, in FIG. 11B, as described above, since no peak was observed, it was confirmed that it was amorphous at least in the measurement range. Further, the peak of (c) of FIG. 11A is derived from the peak of yttrium oxide (SiO ₂ ) on the substrate on which the indium oxide layer is formed, and the peak of (d) of FIG. 11B is derived from the substrate on which the IZO layer is formed (quartz The crest.

Next, the electrical characteristics of the thin film transistor 700 of the present embodiment were investigated. Fig. 12 is a Vg-Id characteristic diagram of the thin film transistor 700 of the present embodiment. Further, Table 4 shows the characteristics of the thin film transistor 700 regarding the subcritical characteristic (SS) and the electric field effect mobility (μ _FE ).

As shown in FIG. 12 and Table 4, the ON/OFF ratio of the thin film transistor 700 is a value exceeding the order of 107. In addition, it was confirmed that this other electrical property is also a good result for the transistor.

Therefore, the thin film transistor 700 can obtain good electrical characteristics even if the channel of one of the constituent crystal layers is crystalline.

<Other Embodiments>

In order to appropriately achieve the effects of the above embodiments, the solvent of the first precursor solution is preferably selected from the group consisting of ethanol, propanol, butanol, 2-methoxyethanol, 2-ethoxyethanol, and 2-butoxyethanol. A mixture of two alcohols in a group. Further, the solvent of the second precursor solution is preferably an alcohol solvent selected from the group consisting of ethanol, propanol, butanol, 2-methoxyethanol, 2-ethoxyethanol, and 2-butoxyethanol, or A carboxylic acid solvent selected from the group consisting of acetic acid, propionic acid, and octanoic acid. Further, the solvent of the channel precursor solution is preferably an alcohol solvent selected from the group consisting of ethanol, propanol, butanol, 2-methoxyethanol, 2-ethoxyethanol, 2-butoxyethanol, or A carboxylic acid solvent selected from the group consisting of acetic acid, propionic acid, and octanoic acid.

Further, in order to appropriately achieve the effects of the above embodiments, the solvent of the precursor solution for the gate electrode layer is preferably selected from the group consisting of ethanol and propanol. An alcohol solvent of a group of butanol, 2-methoxyethanol, 2-ethoxyethanol, or 2-butoxyethanol, or a carboxylic acid solvent selected from the group consisting of acetic acid, propionic acid, and octanoic acid. Further, the solvent of the precursor solution for the source/drain electrode is an alcohol selected from the group consisting of ethanol, propanol, butanol, 2-methoxyethanol, 2-ethoxyethanol, and 2-butoxyethanol. A solvent or a carboxylic acid solvent selected from the group consisting of acetic acid, propionic acid, and octanoic acid is preferred.

Further, in the above-described respective embodiments, as the main sintering in the solution method, at least a part of the effects of the above embodiments can be obtained as long as the heating temperature for forming the first oxide is 450 ° C or more and 700 ° C or less. Further, as the main sintering in the solution method, at least a part of the effects of the above embodiments can be obtained as long as the heating temperature for forming the second oxide is 250 ° C or more and 700 ° C or less. Further, as the main sintering in the solution method, at least a part of the effects of the above embodiments can be obtained as long as the heating temperature for forming the channel oxide is from 250 ° C to 700 ° C.

Further, in the above-described respective embodiments, as the main sintering in the solution method, at least a part of the effects of the above embodiments can be obtained as long as the heating temperature for forming the oxide for the gate electrode is 500 ° C or more and 900 ° C or less. Further, as the main sintering in the solution method, at least one effect of each of the above embodiments can be obtained as long as the heating temperature for forming the source/drain electrode oxide is 450 ° C or more and 700 ° C or less.

Further, in the fifth and sixth embodiments described above, in the formation of several oxide layers, a "die-casting process" for performing press molding is performed. The pressure in this compression molding process is not limited to the representative ones. 5MPa. As described in several examples, at least a part of the effects of the above embodiments can be obtained as long as the pressure in the press molding process is in the range of 1 MPa to 20 MPa.

In the fifth and sixth embodiments described above, the precursor layers are subjected to compression molding for the high plastic deformation ability. As a result, even if the pressure applied during the press molding is a low pressure of 1 MPa or more and 20 MPa or less, each precursor layer is deformed along with the surface shape of the mold, so that the desired degree can be formed with high precision. The die structure. Further, by setting the pressure to a low pressure range of 1 MPa or more and 20 MPa or less, the mold is less likely to be damaged when the press molding is performed, and it is also advantageous in increasing the area.

Here, the reason why the pressure is in the range of "1 MPa or more and 20 MPa or less" is as follows. First, when the pressure is less than 1 MPa, there is a case where the pressure is too low and the respective precursors cannot be laminated. On the other hand, if the pressure is 20 MPa, since the precursor can be sufficiently laminated, it is not necessary to apply the above pressure. From the above viewpoints, in the press molding process of the fifth and sixth embodiments, it is preferable to apply a press molding at a pressure in a range of 2 MPa or more and 10 MPa or less.

Further, in order to form the preliminary sintering of each oxide layer in each of the above embodiments, the preliminary sintering temperature is preferably 100 ° C or more and 250 ° C or less. This is because the solvent in the various precursor layers can be evaporated with higher accuracy. Further, in particular, in the case where the press molding process is subsequently performed, the preliminary sintering can be performed in the above temperature range to form the energy. A more appropriate gel state (in a state before the thermal decomposition and an organic chain remains) in which a plastically deformable property can be obtained in the future.

Further, in the press molding process of the fifth and sixth embodiments, a mold which is previously heated to 80 ° C or more and 300 ° C or less is used (the representative is the gate electrode mold M1, the source/drain electrode mold M2). Or, the gate insulating layer is molded by the mold M3) into other preferred modes.

The reason why the preferred temperature of the mold is 80 ° C or more and 300 ° C or less is as follows. First, in the case of less than 80 ° C, the plastic deformation ability of each precursor layer is lowered due to a decrease in the temperature of each precursor layer. Further, in the case of more than 300 ° C, the curing reaction of each precursor layer is excessively performed, and the plastic deformation ability of each precursor layer is lowered. From the above point of view, in the press molding process, it is more preferable to apply a stamper by using a mold which has been heated to 100 ° C or more and 250 ° C or less.

Further, in the above-mentioned press molding process, it is preferable to apply a mold release treatment to the surface of each of the precursor layers which are contacted by the stamper surface, and/or to apply a mold release treatment to the stamper surface of the mold, and then, Compression molding is applied to each precursor layer. By applying the above treatment, since the frictional force between each of the precursor layers and the mold can be reduced, the stamping process can be performed with higher precision for each of the precursor layers. Further, the release agent used for the release treatment may, for example, be a surfactant (for example, a fluorine-based surfactant, a ruthenium-based surfactant, a nonionic surfactant, or the like), or a fluorine-containing diamond carbon.

Further, in the press molding process and the main sintering process for each of the precursor layers of the above embodiments, each precursor layer (for example, a precursor layer for a gate electrode layer) in which the precursor layer is subjected to press molding is included. The process in which the thinnest region of the middle layer is removed to completely etch the precursor layer is a better state. This is because the precursor layers can be sintered more conventionally and then etched, and it is easy to remove unnecessary regions. Therefore, in the above embodiments, the above-described more preferable state can be employed instead of the process of performing the entire surface etching after the main sintering.

As described above, the disclosure of the above embodiments is described for the purpose of describing the embodiments, and is not intended to limit the invention. Further, modifications that are within the scope of the invention, including other combinations of the embodiments, are also included in the scope of the claims.

10‧‧‧High heat resistant glass

20,520‧‧‧Oxide layer for gate electrode

20a, 520a‧‧ ‧ precursor layer for gate electrode

30,630‧‧‧ gate insulation

32,632‧‧‧1st oxide layer

32a, 632a‧‧‧1st precursor layer

34,234,334,434,634‧‧‧2nd oxide layer

34a, 634a‧‧‧2nd precursor layer

40,740‧‧‧Oxide layer for channels

40a‧‧‧Precursor layer for channels

50‧‧‧ITO layer

52,552‧‧‧汲electrode

54,554‧‧‧Source electrode

90‧‧‧Photoresist film

210‧‧‧Substrate

100,200,300,400,500,600,700‧‧‧film transistor

220‧‧ ‧ platinum layer

550‧‧‧Oxide layer for source/drain electrodes

550a‧‧‧Precursor layer for source/drain electrodes

630a‧‧‧Precursor layer for gate insulation

M1‧‧‧ gate electrode mold

M2‧‧‧ source/drain electrode

M3‧‧‧mode for gate insulation

Fig. 1A is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a first embodiment of the present invention.

Fig. 1B is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a first embodiment of the present invention.

Fig. 1C is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a first embodiment of the present invention.

Fig. 1D is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a first embodiment of the present invention.

Fig. 1E is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a first embodiment of the present invention.

Fig. 1F is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a first embodiment of the present invention.

Fig. 1G is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a first embodiment of the present invention.

Fig. 1H is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a first embodiment of the present invention.

Fig. 1J is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a first embodiment of the present invention.

Fig. 1K is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to the first embodiment of the present invention.

Fig. 1 is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a first embodiment of the present invention.

Fig. 1M is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a first embodiment of the present invention.

Fig. 2 is a graph showing the Vg-Id characteristics of the thin film transistor of the first embodiment of the present invention.

Fig. 3 is a cross-sectional TEM photograph showing a stack structure including a first oxide produced by the same process as that of the first oxide of the first embodiment of the present invention.

Fig. 4 is a view showing an AFM image of the surface of the second oxide which is produced by the same process as the second oxide of the first embodiment of the present invention.

Fig. 5 is a graph showing the Vg-Id characteristics of the thin film transistor of the second to fourth embodiments of the present invention.

Fig. 6 is a graph showing tan δ values of the first oxide layer according to the first to fourth embodiments of the present invention with respect to frequency (Hz).

Fig. 7A is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a fifth embodiment of the present invention.

Fig. 7B is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a fifth embodiment of the present invention.

Fig. 7C is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a fifth embodiment of the present invention.

Fig. 7D is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a fifth embodiment of the present invention.

Fig. 7E is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a fifth embodiment of the present invention.

Fig. 7F is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a fifth embodiment of the present invention.

Fig. 7G is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a fifth embodiment of the present invention.

Fig. 8 is a plan view showing a film obtained by an optical microscope of a thin film transistor according to a fifth embodiment of the present invention.

Fig. 9 is a graph showing the Vg-Id characteristics of the thin film transistor of the fifth embodiment of the present invention.

Fig. 10A is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a sixth embodiment of the present invention.

Fig. 10B is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a sixth embodiment of the present invention.

Fig. 10C is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a sixth embodiment of the present invention.

Fig. 10D is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a sixth embodiment of the present invention.

Fig. 10E is a schematic cross-sectional view showing a process of a method for producing a thin film transistor according to a sixth embodiment of the present invention.

Fig. 11A is a view showing the results of X-ray diffraction (XRD) of an indium oxide layer formed by the same process as that of the thin film transistor of the seventh embodiment of the present invention.

Fig. 11B is a view showing the result of X-ray diffraction (XRD) of the IZO layer formed by the same process as that of the thin film transistor of the first embodiment of the present invention.

Fig. 12 is a view showing the Vg-Id characteristic of the thin film transistor of the seventh embodiment of the present invention.

10(210)‧‧‧High heat resistant glass

20(220)‧‧‧Oxide layer for gate electrode

30‧‧‧ gate insulation

32‧‧‧1st oxide layer

34,234,334,434‧‧‧2nd oxide layer

40 (740) ‧ ‧ channel oxide layer

52‧‧‧汲electrode

54‧‧‧Source electrode

Claims (28)

A thin film transistor is provided with a stacked oxide between a gate electrode and a channel, the stacked oxide having a layer of a first oxide (which may contain unavoidable impurities) connected to the gate electrode, An oxide composed of bismuth (Bi) and niobium (Nb), or an oxide composed of bismuth (Bi) and zinc (Zn) and niobium (Nb); and, second oxide (may not contain a layer of impurities to be avoided, which is connected to the channel, is an oxide selected from lanthanum (La) and tantalum (Ta), an oxide composed of lanthanum (La) and zirconium (Zr), and One of a group of oxides composed of strontium (Sr) and strontium (Ta); this channel is an oxide for channels (which may contain unavoidable impurities). The thin film transistor of claim 1, wherein the channel oxide is amorphous. The thin film transistor of claim 1, wherein the channel is selected from the group consisting of an oxide composed of indium (In) and zinc (Zn), an oxide composed of gallium (Ga) and zinc (Zn), An oxide composed of aluminum (Al) and zinc (Zn), an oxide composed of zinc (Zn) and tin (Sn), and an oxidation of zinc (Zn) and indium (In) and tin (Sn) An oxide composed of indium (In), gallium (Ga) and zinc (Zn), an oxide composed of lanthanum (La) and indium (In) and zinc (Zn), and yttrium (Hf) An oxide composed of indium (In) and zinc (Zn), an oxide composed of strontium (Sc), indium (In) and zinc (Zn), and an oxide for channel in a group of indium oxide. The thin film transistor according to any one of claims 1 to 3, wherein the gate electrode is selected from the group consisting of oxides of lanthanum (La) and nickel (Ni), and bismuth (Sb) and tin (Sn) a gate electrode for one of the oxides and the oxides composed of indium (In) and tin (Sn) Oxide (which may contain unavoidable impurities). The thin film transistor according to any one of claims 1 to 4, further comprising a source electrode and a drain electrode; and the source electrode and the drain electrode are made of indium (In) and tin (Sn) An oxide (which may contain unavoidable impurities) or an oxide composed of lanthanum (La) and nickel (Ni) (which may contain unavoidable impurities). The thin film transistor according to any one of claims 1 to 5, wherein the second oxide is amorphous. The thin film transistor according to any one of claims 1 to 6, wherein the first oxide comprises a crystalline phase and an amorphous phase. The thin film transistor according to any one of claims 1 to 7, wherein the stacked oxide has a combined capacitance of 5 × 10 ^-8 F/cm ² or more and 1 × 10 ^-6 F/cm ² or less. The thin film transistor according to any one of claims 1 to 7, wherein the stacked oxide has a composite dielectric constant of 60 or more and 200 or less. The thin film transistor according to any one of claims 1 to 8, wherein the channel layer has a thickness of 5 nm or more and 80 nm or less. The thin film transistor according to any one of claims 1 to 8, wherein the first oxide is an oxide composed of bismuth (Bi) and niobium (Nb) (which may contain unavoidable impurities), and When the bismuth (Bi) is 1, the atomic composition ratio of the cerium (Nb) is 0.33 or more and 3 or less; and the second oxide is an oxide composed of lanthanum (La) and tantalum (Ta) (which may be inevitably contained) When the lanthanum (La) is 1, the atomic composition ratio of the lanthanum (Ta) is 0.11 or more and 9 or less. The thin film transistor according to claim 1 or 2, wherein the channel oxide is an oxide composed of indium (In) and zinc (Zn), and the indium (In) is 1 when the zinc ( The atomic composition ratio of Zn) is 0.25 or more and 1 or less. A method for manufacturing a thin film transistor includes a first oxide formation process and a second oxidation between a formation process of a gate electrode layer and a formation process of a channel for forming an oxide for a channel (which may contain unavoidable impurities) The first oxide forming process is performed by using a first precursor layer (for using a precursor containing bismuth (Bi) and a precursor containing ruthenium (Nb) as a precursor solution of solute, or The precursor containing bismuth (Bi), the precursor containing zinc (Zn), and the precursor containing ruthenium (Nb) as the precursor solution of the precursor solution of the solute as a starting material are heated in an oxygen-containing atmosphere. And the first oxide (which may contain unavoidable impurities) composed of the bismuth (Bi) and the bismuth (Nb) or the bismuth (Bi) and the zinc (Zn) and the niobium (Nb) Formed in contact with the gate electrode layer; the second oxide forming process is performed by using a second precursor layer (using a precursor selected from the group consisting of lanthanum (La) and ruthenium (Ta) The precursor is a solute precursor solution, a precursor containing lanthanum (La) and a precursor containing zirconium (Zr) as a precursor solution of solute, and a precursor containing strontium (Sr) The precursor containing ruthenium (Ta) is a second precursor solution of a group of solute precursor solutions as a starting material) heated in an oxygen-containing atmosphere so that the lanthanum (La) and the lanthanum (Ta) are heated. a second oxide composed of the lanthanum (La) and the zirconium (Zr) or the yttrium (Sr) and the lanthanum (Ta) (which may be unavoidable) The impurities are formed in such a manner as to be in contact with the channel. The method for producing a thin film transistor according to claim 13, wherein the channel oxide is amorphous. The method for manufacturing a thin film transistor according to claim 13 , wherein the formation process of the channel is to use a precursor solution selected from the group consisting of a precursor containing indium (In) and a precursor containing zinc (Zn) as a solute. a precursor solution containing a gallium (Ga) precursor and a zinc-containing (Zn) precursor as a solute precursor solution, a precursor containing an aluminum (Al) precursor, and a zinc-containing (Zn) precursor as a solute precursor solution The zinc-containing (Zn) precursor and the tin-containing (Sn) precursor are the solute precursor solution, the zinc-containing (Zn) precursor and the indium-containing (In) precursor and the tin-containing (Sn) The precursor is a solute precursor solution, a precursor containing indium (In) and a precursor containing gallium (Ga) and a precursor containing zinc (Zn) are precursor solutions of solute, containing lanthanum (La) The precursor and the indium-containing (In) precursor and the zinc-containing (Zn) precursor are the solute precursor solution, the yttrium-containing (Hf) precursor and the indium-containing (In) precursor and zinc-containing ( The precursor of Zn) is a solute precursor solution, a precursor containing cerium (Sc), a precursor containing indium (In) and a precursor containing zinc (Zn) as a precursor solution of solute, and indium ( In) precursor One channel in the group is heated with a precursor layer using a precursor solution as a starting material in an oxygen-containing atmosphere to form an oxide selected from the group consisting of the indium (In) and the zinc (Zn). An oxide composed of gallium (Ga) and the zinc (Zn), an oxide composed of the aluminum (Al) and the zinc (Zn), and the zinc (Zn) and the tin (Sn) An oxide, an oxide composed of the zinc (Zn) and the indium (In) and the tin (Sn), and an oxide composed of the indium (In) and the gallium (Ga) and the zinc (Zn) From the lanthanum (La) and the indium (In) An oxide composed of zinc (Zn), an oxide composed of the hafnium (Hf) and the indium (In) and the zinc (Zn), and the indium (Sc) and the indium (In) and the zinc ( One of the oxides composed of Zn) and one of the group consisting of indium oxide. The method for producing a thin film transistor according to any one of claims 13 to 15, wherein a heating temperature for forming the first oxide is 450 ° C or higher and 700 ° C or lower; for forming the second oxide The heating temperature is from 250 ° C to 700 ° C; the heating temperature for forming the oxide for the channel is from 250 ° C to 700 ° C. The method for manufacturing a thin film transistor according to any one of claims 13 to 16, wherein the gate electrode layer forming process is a precursor layer for an electrode layer (for use with a lanthanum (La) precursor and The precursor containing nickel (Ni) is a solute precursor solution, a precursor containing bismuth (Sb) and a precursor containing tin (Sn) as a solute precursor solution, or a precursor containing indium (In) And the precursor solution containing the tin (Sn) precursor as the precursor of the solute precursor solution is heated in an oxygen atmosphere, thereby forming the lanthanum (La) and the nickel (Ni) The oxide to be formed, the oxide composed of the antimony (Sb) and the tin (Sn), or the oxide for the gate electrode of the oxide composed of the indium (In) and the tin (Sn) Processes that can contain unavoidable impurities). The method for producing a thin film transistor according to claim 17, wherein the heating temperature for forming the oxide for the gate electrode is 500 ° C or more and 900 ° C or less. The method for manufacturing a thin film transistor according to any one of claims 13 to 18, further comprising a process of forming a source electrode and a drain electrode; the process for forming the source electrode and the drain electrode is a source Precursor layer for pole/drain electrodes (for use of precursors containing indium (In) and precursors containing tin (Sn) as precursor solution of solute or precursor of lanthanum (La) and nickel (Ni The precursor is a source of the solute precursor solution and the precursor solution for the drain electrode is used as a starting material to be heated in an oxygen-containing atmosphere, thereby forming the indium (In) and the tin (Sn). The oxide or the source/drain electrode oxide (which may contain unavoidable impurities) of the oxide composed of the lanthanum (La) and the nickel (Ni). The method for producing a thin film transistor according to claim 19, wherein the heating temperature for forming the source/drain electrode oxide is 450 ° C or more and 700 ° C or less. The method for producing a thin film transistor according to any one of claims 13 to 15, wherein the first oxide forming process or the second oxide forming process further comprises a stamping process, Before using the first oxide or the second oxide, the first precursor layer using the first precursor solution as a starting material or the second precursor layer using the second precursor solution as a starting material is included The press molding process is performed in an oxygen atmosphere at a temperature of 80 ° C or more and 300 ° C or less to form a stamper structure for the first precursor layer or the second precursor layer. The method for manufacturing a thin film transistor according to any one of claims 13 to 15, wherein the forming process of the channel further comprises a stamping process, and the pass is used before forming the oxide for the channel. The channel precursor precursor is used as a channel for the channel precursor, and the precursor layer is subjected to compression molding in an oxygen-containing atmosphere at a temperature of 80° C. or higher and 300° C. or lower to form a stamper structure for the channel precursor layer. The method for manufacturing a thin film transistor according to claim 17 or 18, wherein the gate electrode layer forming process further comprises a stamping process, and the gate is used before forming the oxide for the gate electrode. The precursor electrode layer for a gate electrode using a precursor electrode as a starting material is subjected to compression molding in an oxygen-containing atmosphere at a temperature of 80 ° C or more and 300 ° C or less to form a pressure of the precursor layer for the gate electrode. Mold construction. The method for manufacturing a thin film transistor according to claim 19 or 20, wherein the method of forming the source electrode and the drain electrode further comprises a stamping process for forming the source/drain electrode oxide Previously, the source/drain electrode precursor layer was used as a starting material for the source/drain electrode precursor layer in an oxygen-containing atmosphere and heated at 80° C. or higher and 300° C. or lower for compression molding. The stamper structure is formed on the source/drain electrode precursor layer. The method for producing a thin film transistor according to any one of claims 13 to 24, wherein the second oxide is amorphous. The method for producing a thin film transistor according to any one of claims 13 to 25, wherein the first oxide comprises a crystalline phase and an amorphous phase. The method for producing a thin film transistor according to any one of claims 13 to 24, wherein the press molding process is performed at a pressure in a range of 1 MPa or more and 20 MPa or less. The method for producing a thin film transistor according to any one of claims 13 to 24, wherein the molding process is performed by using a mold heated to a temperature in a range of 80 ° C or more and 300 ° C or less in advance. Mold processing.