JP6033594B2 - THIN FILM TRANSISTOR AND METHOD FOR PRODUCING THIN FILM TRANSISTOR - Google Patents

Description

  The present invention relates to a thin film transistor and a method for manufacturing the thin film transistor.

Conventionally, a ferroelectric material (for example, BLT (Bi _{4 -X} La _X Ti ₃ O ₁₂ ), PZT (Pb (Zr _X , Ti ₁ )) is used as a gate insulating layer for the purpose of high-speed switching with a low driving voltage. _{-X) O} 3)) adopted TFTs is disclosed. On the other hand, for the purpose of increasing the carrier concentration, an oxide conductive material (for example, indium tin oxide (ITO), zinc oxide (ZnO), or LSCO (La _X Sr _1-X CuO ₄ )) is used as a channel. An adopted thin film transistor is also disclosed (Patent Document 1).

  Here, looking at the manufacturing method of the above-described thin film transistor, first, a laminated film of Ti and Pt is formed by electron beam evaporation as a gate electrode. On the gate electrode, a gate insulating layer made of the above-described BLT or PZT is formed by a sol-gel method. Further, a channel made of ITO is formed on the gate insulating layer by RF sputtering. Subsequently, Ti and Pt are formed on the channel by an electron beam evaporation method, thereby forming a source electrode and a drain electrode. Thereafter, the element region is separated from other element regions by the RIE method and the wet etching method (mixed solution of HF and HCl) (Patent Document 1). The inventors of the present application have also studied selection and combination of oxides that appropriately exhibit the function as a thin film transistor (Patent Document 2).

JP 2006-11029 A WO2011 / 138958

  However, in the conventional thin film transistor, there are several examples in which the gate insulating layer or the channel is formed of a multi-component oxide, but selection of a material that realizes high characteristics as a thin film transistor and an appropriate manufacturing method therefor has not been made yet. It is midway. In addition to improving the performance of each of the gate insulating layer and / or the channel, improving the performance of the stacked layers as a whole is one of the technical problems to be solved for improving the performance of the thin film transistor. One.

  In addition, in the prior art, a process that requires a relatively long time and / or expensive equipment such as a vacuum process or a process using a photolithography method is generally used, so that the use efficiency of raw materials and manufacturing energy is very poor. Become. When the manufacturing method as described above is adopted, many processes and a long time are required to manufacture the thin film transistor, which is not preferable from the viewpoint of industrial property or mass productivity. In addition, there is a problem in the prior art that it is relatively difficult to increase the area.

  The present invention solves at least one of the above-described problems, thereby improving the performance of a thin film transistor in which an oxide is applied to at least a channel and a gate insulating layer, or simplification and energy saving of a manufacturing process of such a thin film transistor. Is realized. As a result, the present invention greatly contributes to the provision of a thin film transistor excellent in industrial property or mass productivity.

  The inventors of the present application have conducted intensive research and analysis on selection and combination of oxides that can appropriately function as a gate insulating layer and / or a channel, among many existing oxides. As a result, some interesting findings were obtained.

  Specifically, suppressing excessive oxygen vacancies in the channel greatly contributes to improving various characteristics of the thin film transistor. Specifically, when an oxide composed of indium (In) and zinc (Zn) is employed as the channel, it is easy to generate an oxygen deficient state, so that it is difficult to perform the channel function. It became. As a result of repeating trial and error, the present inventors have found that the introduction of a new element can contribute to the formation of an appropriate oxygen deficiency state while suppressing oxygen deficiency. By further analysis and examination, it has been found that the new element can contribute to amorphization as compared with the case where the element is not added.

  In addition to the compatibility with the above-described channel, the gate insulating layer controls the dielectric constant to realize a high-performance thin film transistor. Therefore, as a result of repeated analysis and examination on applicability of a gate insulating layer in which a plurality of layers are stacked in addition to a single gate insulating layer, the inventors have found that useful insulation suitable for the above-described channel is obtained. Succeeded in finding a layer.

  All of the above findings are the result of many trials and errors and detailed analysis by the inventors of the present invention, and a channel material that forms a good interface with a gate insulating layer of a specific single layer or stacked oxide layer. By combining them, a high-performance thin film transistor can be realized. In addition, the inventors of the present application have found that these oxides can be produced by a process that can be greatly simplified or energy-saving as compared with the prior art and can be easily increased in area. The present invention has been created based on the above viewpoints.

  One thin film transistor of the present invention includes a gate insulating layer containing silicon oxide (which may contain unavoidable impurities) between a gate electrode and a channel. In addition, in the thin film transistor, the channel includes indium (In) and zinc (Zn), and the atomic ratio of 0.046 to 0.375 when the indium (In) is 1. A channel oxide containing zirconium (Zr) (which may contain unavoidable impurities).

  According to this thin film transistor, since it is possible to suppress excessive oxygen deficiency, which is difficult to form in the case of an oxide made of indium (In) and zinc (Zn), various thin film transistors as thin film transistors Characteristics (for example, reduction of hysteresis or ON / OFF ratio) can be remarkably improved. Further, according to this thin film transistor, the amorphous phase can be formed relatively easily by containing a predetermined amount of zirconium (Zr), so that the flatness of the oxide layer can be improved. In addition, since a stable amorphous phase having a high crystallization temperature can be formed, a favorable interface with the gate insulating layer can be formed. Furthermore, since it becomes possible to form the amorphous phase relatively easily, the moldability of the oxide as a layer is improved (for example, easier stamping and / or improved accuracy after molding by stamping) ) Can be realized.

  Also, in one thin film transistor manufacturing method of the present invention, a gate insulating layer precursor layer starting from a gate insulating layer precursor solution containing polysilazane as a solute is heated in a water vapor-containing atmosphere. To form a gate insulating layer forming step for forming a gate insulating layer containing silicon oxide (which may contain inevitable impurities), a step for forming the gate electrode layer and a channel for forming a channel oxide (which may contain inevitable impurities) It is included during the formation process. In addition, in this thin film transistor manufacturing method, the above-described channel formation step is 0 when the precursor containing indium (In), the precursor containing zinc (Zn), and the indium (In) are set to 1. Heating a channel precursor layer starting from a channel precursor solution having a precursor containing zirconium (Zr) having an atomic ratio of 0.046 to 0.375 in an oxygen-containing atmosphere. Therefore, for a channel containing indium (In) and zinc (Zn) and containing zirconium (Zr) having an atomic ratio of 0.046 or more and 0.375 or less when the above-mentioned indium (In) is set to 1. This is a step of forming an oxide (which may include inevitable impurities).

  According to this thin film transistor manufacturing method, it is possible to suppress excessive oxygen vacancies that are difficult to form in the case of an oxide made of indium (In) and zinc (Zn). As described above, a thin film transistor excellent in various characteristics (for example, reduction in hysteresis or ON / OFF ratio) can be manufactured. In addition, according to the method of manufacturing the thin film transistor, the gate insulating layer and the channel are formed by a relatively simple process that does not use a photolithography method (for example, an inkjet method, a screen printing method, an intaglio / letter printing method, or a nanoimprint method). Can be formed. In addition, it is easy to increase the area. Therefore, according to the method for manufacturing a thin film transistor, a method for manufacturing a thin film transistor excellent in industrial property or mass productivity can be provided. Furthermore, according to this method of manufacturing a thin film transistor, an amorphous phase can be formed relatively easily by containing a predetermined amount of zirconium (Zr). Therefore, an oxide layer having high flatness can be formed. A thin film transistor can be manufactured. In addition, since an amorphous phase can be formed relatively easily, a good interface with the gate insulating layer can be formed. Furthermore, since it becomes possible to form the amorphous phase relatively easily, the moldability of the oxide as a layer is improved (for example, easier stamping and / or improved accuracy after molding by stamping) ) Can be realized.

  According to another thin film transistor manufacturing method of the present invention, in addition to the above thin film transistor manufacturing method, the above-mentioned gate insulating layer precursor solution is used as the first gate insulating layer precursor solution, and When the layer precursor layer is the first gate insulating layer precursor layer, the gate insulating layer forming step described above uses a precursor containing lanthanum (La) and a precursor containing zirconium (Zr) as a solute. A multi-component oxide containing lanthanum (La) zirconium (Zr) by heating a precursor layer for a second gate insulating layer starting from a precursor solution for the second gate insulating layer in an oxygen-containing atmosphere. This is a step of forming a layer (which may contain inevitable impurities) so as to have a laminated structure with the silicon oxide layer.

  According to this thin film transistor manufacturing method, since the gate insulating layer is formed by the laminated structure of the above-described multi-component oxide layer and the above-described silicon oxide layer, the above-described thin film transistor having a relatively high relative dielectric constant is provided. The multi-component oxide can have a suitable dielectric constant as a whole gate insulating layer due to the presence of a silicon oxide layer formed from polysilazane having a relatively low dielectric constant. According to the inventors' previous research and analysis, zirconium (Zr) gate insulation contained in a channel which is an oxide containing indium (In), zinc (Zn) and zirconium (Zr) described above. Since diffusion into the layer may form a so-called trap order in the gate insulating layer, it has also been found that the above multi-element oxide is preferably disposed on the side in contact with the channel.

  By the way, in the present application, “embossing” is sometimes referred to as “nanoimprint”.

  According to one thin film transistor of the present invention, a high performance thin film transistor in which a gate insulating layer and a channel are both formed of an oxide is realized. In addition, according to the method for manufacturing a thin film transistor of the present invention, an oxide is formed by a relatively simple process, so that a method for manufacturing a thin film transistor excellent in industrial property or mass productivity can be provided.

It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 1st Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 1st Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 1st Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 1st Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 1st Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 1st Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 1st Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 1st Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the whole structure of the thin-film transistor in the 1st Embodiment of this invention, and its manufacturing method. It is a graph which shows the Vg-Id characteristic of the thin-film transistor in the 1st Embodiment of this invention. It is a graph which shows the XPS (X-ray Photoelectron Spectroscopy) analysis result of the oxygen atom contained in the oxide for channels in which only thickness differs from the channel in the 1st Embodiment of this invention. It is a graph which shows the XPS (X-ray Photoelectron Spectroscopy) analysis result of the oxygen atom contained in the oxide as a measuring object for reference. It is a figure which shows the AFM image and surface roughness of the surface oxide of the oxide for channels from which only the channel and thickness differ in the 1st Embodiment of this invention, and the reference | standard measurement object. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 2nd Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 2nd Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 2nd Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 2nd Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the whole structure of the thin-film transistor in the 2nd Embodiment of this invention, and its manufacturing method. The Vg-Id characteristic of the thin-film transistor in the 2nd Embodiment of this invention is shown. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 3rd Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 3rd Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 3rd Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 3rd Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the manufacturing method of the thin-film transistor in the 3rd Embodiment of this invention. It is a cross-sectional schematic diagram which shows one process of the whole structure and the manufacturing method of the thin-film transistor in the 3rd Embodiment of this invention.

  Embodiments of the present invention will be described in detail with reference to the accompanying drawings. In this description, common parts are denoted by common reference symbols throughout the drawings unless otherwise specified. In the drawings, elements of the present embodiment are not necessarily described with each other kept to scale. Further, some symbols may be omitted to make each drawing easier to see.

<First Embodiment>
1. Overall Configuration of Thin Film Capacitor of this Embodiment FIGS. 1 to 8 are cross-sectional schematic views showing one process of a method of manufacturing a thin film transistor 100, respectively. FIG. 9 is a schematic cross-sectional view showing one process and the entire configuration of the method of manufacturing the thin film transistor 100 according to this embodiment. As shown in FIG. 9, in the thin film transistor 100 according to this embodiment, the gate electrode 20, the gate insulating layer 34, the channel 44, the source electrode 58, and the drain electrode 56 are stacked in this order on the substrate 10 from the lower layer. .

  The thin film transistor 100 employs a so-called bottom gate structure, but this embodiment is not limited to this structure. Therefore, a person skilled in the art can form a top gate structure by changing the order of the steps by referring to the description of the present embodiment with ordinary technical common sense. Moreover, the display of the temperature in this application represents the surface temperature of the heating surface of the heater which contacts a board | substrate. Further, in order to simplify the drawing, description of patterning of the extraction electrode from each electrode is omitted.

Examples of the substrate 10 include a high heat-resistant glass, a SiO ₂ / Si substrate (that is, a substrate in which a silicon oxide film is formed on a silicon substrate; hereinafter, also simply referred to as “substrate”), an alumina (Al ₂ O ₃ ) substrate, An STO (SrTiO) substrate, an insulating substrate having an STO (SrTiO) layer formed on the surface of the Si substrate via a SiO ₂ layer and a Ti layer, etc.), a semiconductor substrate (eg, Si substrate, SiC substrate, Ge substrate, etc.) Various insulating base materials can be applied.

Examples of the material of the gate electrode 20 include a metal material such as platinum, gold, silver, copper, aluminum, molybdenum, palladium, ruthenium, iridium, and tungsten, or a metal material such as an alloy thereof, and a conductive material including ruthenium oxide. Metal oxide, p ⁺ -silicon layer, or n ⁺ -silicon layer can be applied.

  In the thin film transistor 100 according to the present embodiment, the gate insulating layer 34 may include silicon oxide (provided that unavoidable impurities are included) starting from a precursor solution for a gate insulating layer containing polysilazane as a solute. The same applies to oxides of other materials as well as oxides of materials.

  The thickness of the gate insulating layer 34 of this embodiment is preferably 50 nm or more and 300 nm or less. The upper limit of the thickness of the gate insulating layer 34 is not particularly limited, but, for example, if it exceeds 300 nm, it is not preferable because it may affect channel interface characteristics. On the other hand, it is not preferable that the thickness is less than 50 nm from the viewpoints of an increase in leakage current and deterioration of the coating property of the film on the substrate. Depending on the type of device using the gate insulating layer 34 of this embodiment, even a thickness of less than 50 nm can be applied, and the lower limit value is not particularly limited.

  The relative dielectric constant of the gate insulating layer 34 is preferably 3 or more and 100 or less. When the relative dielectric constant of the gate insulating layer 34 exceeds 100, the time constant becomes large, which hinders high-speed operation of the transistor. On the other hand, when the relative dielectric constant is less than 3, the amount of charge induced by the gate insulating film increases. This is not preferable because there is a possibility that the device characteristics may deteriorate due to the reduction. From the above viewpoint, the relative dielectric constant is more preferably 3 or more and 10 or less.

  The channel 44 of this embodiment is made of a channel oxide containing indium (In), zinc (Zn), and zirconium (Zr). The channel oxide includes zirconium (Zr) having an atomic ratio of 0.046 to 0.375 when indium (In) is 1. As will be described later, a thin film transistor in which the atomic ratio of zirconium (Zr) in the channel 44 is 0.046 or more and 0.375 or less when indium (In) is 1 is indium (In). In the case of an oxide composed of zinc (Zn), excessive oxygen vacancies that are difficult to form can be suppressed. As a result, various characteristics (for example, reduction of hysteresis or ON / OFF ratio) as the thin film transistor can be remarkably improved. According to further research and analysis by the inventors of the present application, when zirconium (Zr) having an atomic ratio of 0.03 or more and 0.07 or less when indium (In) in the channel 44 is 1, is included. It has been found that hysteresis is most reduced.

  In addition, since the channel oxide of this embodiment is in an amorphous phase, it is considered that a favorable interface state with the gate insulating layer 34 in contact with the channel 44 can be obtained. As a result, a thin film transistor having good electrical characteristics can be formed. Note that the channel 44 made of a channel oxide containing indium (In), zinc (Zn), and zirconium (Zr) is also called a ZIZO layer.

  A thin film transistor in which the thickness of the channel 44 is 5 nm to 80 nm and the thickness of the channel 44 is 5 nm to 80 nm easily covers the gate insulating layer 34 and the like with high accuracy and easily modulates the conductivity of the channel. Therefore, this is a preferred embodiment.

  In addition, the source electrode 58 and the drain electrode 56 of the present embodiment are made of ITO (Indium Tin Oxide).

2. 1. Manufacturing Method of Thin Film Transistor 100 (1) Formation of Gate Electrode First, as shown in FIG. 1, the gate electrode 20 is a SiO ₂ / Si substrate (hereinafter simply referred to as “substrate”) which is a base material by a known sputtering method or CVD method. (Also referred to as 10).

(2) Formation of Gate Insulating Layer Next, as shown in FIG. 2, a gate insulating layer precursor solution containing polysilazane as a solute is formed on the gate electrode 20 by a known spin coating method as a starting material. A gate insulating layer precursor layer 32 is formed.

  More specifically, the polysilazane according to the present embodiment introduces dichlorosilane, trichlorosilane, and ammonia into a reaction solvent (for example, hydrocarbons, ethers, amides, amines, esters). Can be synthesized in the presence of a catalyst.

  Thereafter, the gate insulating layer precursor layer 32 starting from a gate insulating layer precursor solution having a concentration of 5% by weight obtained by dissolving the polysilazane of the present embodiment, which is a solute, in xylene, as described above. It is formed on the electrode 20. In order to finally obtain a sufficient thickness of the gate insulating layer 34 (for example, about 120 nm), in this embodiment, the precursor layer 32 for the gate insulating layer is formed by one spin coating method.

  Thereafter, for example, a baking process is performed in the atmosphere at a predetermined time (for example, 2 hours) for heating at 250 ° C. or higher and 450 ° C. or lower. In the present embodiment, “in the atmosphere” includes water vapor. In addition, by this baking, polysilazane can be converted into a silicon oxide film because it can undergo a hydrolysis reaction with water vapor to form part or all of the Si—N bond of polysilazane. .

  As a result, as shown in FIG. 3, a gate insulating layer 34 that is a silicon oxide layer is formed on the gate electrode 20.

  By the way, the gate insulating layer 34 in this embodiment is formed by baking the precursor solution for gate insulating layers which uses polysilazane as a solute. In the present application, as described above, the method of forming the gate insulating layer 34 and other oxide layers by firing the precursor solution as a starting material is also referred to as “solution method” for convenience.

(3) Formation of Channel As shown in FIG. 4, a channel precursor layer 42 is formed on the gate insulating layer 34 by a known spin coating method. In the present embodiment, a precursor containing indium (In), a precursor containing zinc (Zn), and zirconium having an atomic ratio of 0.046 to 0.375 when the indium (In) is 1. A channel precursor layer 42 starting from a channel precursor solution having a precursor containing (Zr) as a solute is formed.

  Thereafter, as the preliminary firing, the channel precursor layer 42 is heated in a range of 80 ° C. or higher and 250 ° C. or lower for a predetermined time. Note that the above-described pre-baking is performed in an oxygen atmosphere or in the air (hereinafter collectively referred to as “oxygen-containing atmosphere”).

  Further, after that, as the main firing, the channel precursor layer 42 is placed in an oxygen atmosphere (for example, 100% by volume, but is not limited thereto. The same applies to the following “oxygen atmosphere”) for a predetermined time of 350 ° C. or higher. By heating in a range of 550 ° C. or lower, a channel 44 that is an oxide made of indium (In), zinc (Zn), and zirconium (Zr) is formed on the gate insulating layer 34 as shown in FIG. Is done.

  Here, an example of a precursor containing indium (In) for the channel 44 in this embodiment is indium acetylacetonate. As other examples, indium acetate, indium nitrate, indium chloride, or various indium alkoxides (for example, indium isopropoxide, indium butoxide, indium ethoxide, indium methoxyethoxide) may be employed. An example of a precursor containing zinc (Zn) for the channel 44 in this embodiment is zinc chloride. As other examples, zinc nitrate, zinc acetate, or various zinc alkoxides (for example, zinc isopropoxide, zinc butoxide, zinc ethoxide, zinc methoxyethoxide) may be employed. An example of a precursor containing zirconium (Zr) for the channel 44 in this embodiment is zirconium butoxide. As other examples, zirconium nitrate, zirconium chloride, or various other zirconium alkoxides (eg, zirconium isopropoxide, zirconium butoxide, zirconium ethoxide, zirconium methoxyethoxide) may be employed.

(4) Formation of Source Electrode and Drain Electrode Further, as shown in FIG. 6, after a resist film 90 patterned by a known photolithography method is formed on the channel 44, the channel 44 and the resist film 90 are formed. Then, the ITO layer 50 is formed by a known sputtering method. The target material of the present embodiment is, for example, ITO containing 5 wt% tin oxide (SnO ₂ ), and is formed at room temperature. Thereafter, when the resist film 90 is removed, the drain electrode 56 and the source electrode 58 made of the ITO layer 50 are formed on the channel 44 as shown in FIG.

  Thereafter, a resist film 90 patterned by a known photolithography method is formed on the drain electrode 56, the source electrode 58, and the channel 44, and then the resist film 90, a part of the drain electrode 56, and the source electrode 58 are formed. Using the part as a mask, the exposed channel 44 is removed using a known dry etching method using argon (Ar) plasma. As a result, the patterned channel 44 is formed, whereby the thin film transistor 100 is manufactured.

3. Characteristics of Thin Film Transistor 100 Next, Example 1 will be described in order to describe the first embodiment in more detail, but the present embodiment is not limited to this example. For Example 1, the characteristics of the thin film transistor 100 were examined by the following method.

Example 1
In Example 1, first, a p ⁺ -silicon layer was formed on the substrate 10 as the gate electrode 20. The p ⁺ -silicon layer was formed by a known CVD method. In Example 1, a TiO _X film (not shown) having a thickness of about 10 nm is formed on SiO ₂ . If the substrate 10 is a p ⁺ -silicon substrate, the substrate 10 can serve as a gate electrode.

  Next, a gate insulating layer precursor layer 32 starting from a gate insulating layer precursor solution containing polysilazane as a solute is formed on the gate electrode 20 by a known spin coating method. Thereafter, the gate insulating layer precursor layer 32 is heated at 250 ° C. or higher and 450 ° C. or lower for 2 hours in the atmosphere, whereby the gate insulating layer 34 which is a silicon oxide layer is formed on the gate electrode 20. . The thickness of the gate insulating layer 34 was about 121 nm at 250 ° C., about 118 nm at 350 ° C., and about 115 nm at 450 ° C.

  Thereafter, on the gate insulating layer 34, by a known spin coating method, a precursor for a channel containing a precursor containing indium (In), a precursor containing zinc (Zn), and a precursor containing zirconium (Zr) as a solute. A channel precursor layer 42 starting from the body solution was formed. Indium acetylacetonate was used as a precursor containing indium (In) for the channel precursor layer 42. Further, zinc butoxide was adopted as a precursor containing zinc (Zn) for the channel precursor layer 42. Further, zirconium butoxide was adopted as a precursor containing zirconium (Zr).

  Next, as a preliminary firing, the channel precursor layer is heated to 250 ° C. for about 5 minutes. After that, as the main firing, the channel precursor layer 42 is heated in an oxygen atmosphere at 500 ° C. for about 10 minutes to thereby form a channel oxide made of indium (In), zinc (Zn), and zirconium (Zr). A layer was formed. The atomic ratio of indium (In), zinc (Zn), and zirconium (Zr) in the channel oxide layer of Example 1 is 0.5 when zinc (Zn) is 1 when indium (In) is 1. And zirconium (Zr) was 0.046. The thickness of the channel oxide layer was about 20 nm. Thereafter, as in the first embodiment, the source electrode 58 and the drain electrode 56 were formed.

(1) Current-Voltage Characteristics FIG. 10 shows, as an example, the Vg-Id characteristics of the thin film transistor 100 including the gate insulating layer 34 formed by heating the gate insulating layer precursor layer 32 at 450 ° C., and OFF It is a graph which shows an electric current. Note that V _D (1.5 V) in FIG. 10 is a voltage (V) applied between the source electrode 58 and the drain electrode 56 of the thin film transistor 100. Table 1 shows a threshold value (V _th ), a field effect mobility (μ _FE ), and an ON / OFF ratio in the thin film transistor 100.

As shown in FIG. 10 and Table 1, when the Vg-Id characteristic of the thin film transistor 100 in the first embodiment was examined, the threshold value (V _th ) was 2.6 V, and the field effect mobility (μ _FE ) was 19 0.7 cm ² / Vs. The ON / OFF ratio was 4.3 × 10 ⁷ . Therefore, the thin film transistor 100 can sufficiently exhibit the function as a transistor even though the gate insulating layer and the channel that form the thin film transistor 100 are an oxide layer and are formed by employing a solution method. Was confirmed. In this example, the main baking temperature of the channel 44 was 500 ° C., but from the results of experiments by the inventors, if the heating temperature in the main baking is 350 ° C. or more and 500 ° C. or less, the channel 44 functions as a thin film transistor. Confirmed to do. In addition, it was also confirmed that if the heating temperature in the main baking is 400 ° C. or higher and 500 ° C. or lower, the stability of each electrical characteristic of the transistor is improved.

(2) Relative permittivity In Example 1, the relative permittivity used the Toyo Technica company make and 1260-SYS type | mold broadband dielectric constant measuring system. As a result, when the relative dielectric constant of the oxide of the gate insulating layer 34 was measured, it was approximately 3 or more and 6 or less.

(3) Crystal structure analysis by XRD analysis The channel in Example 1 was analyzed by an X-ray diffraction (XRD: X-Ray Diffraction) apparatus. As a result, since no characteristic peak was observed, it was found that the channel oxide constituting the channel was an amorphous phase. In this embodiment, since the channel oxide contains zirconium (Zr), it is possible to form an amorphous phase relatively easily, so that the flatness of the oxide layer can be improved. . In addition, since an amorphous phase can be formed relatively easily, a good interface with the gate insulating layer 34 can be formed.

(4) Analysis of Oxygen Atoms in Oxide Using XPS Measuring Device About oxygen atoms contained in channel oxides that differ only in thickness from the channel in Example 1 An oxygen atom was analyzed. Specifically, this analysis object is an oxide made of indium (In), zinc (Zn), and zirconium (Zr) having a thickness of about 30 nm. Therefore, it can be said that this oxide is substantially a channel oxide.

FIG. 11 is a graph showing the results of XPS analysis of oxygen atoms contained in the oxide composed of indium (In), zinc (Zn), and zirconium (Zr). FIG. 12 is a graph showing the result of XPS analysis of oxygen atoms contained in the oxide as the reference measurement target. The reference measurement object is an oxide composed of indium (In) and zinc (Zn) (and therefore does not include zirconium (Zr)), and the first embodiment is different except for the difference in material. Formed by the same solution method. Further, (a1) in FIG. 11 and (a2) in FIG. 12 are considered to be peaks derived from metal-oxygen bonds. For example, in the case of a ZIZO layer, the peaks in (a1) in FIG. 11 and (a2) in FIG. 12 are considered to be peaks indicating the bond between O ²⁻ and Zr, In, or Zn. Further, (c1) in FIG. 11 and (c2) in FIG. 12 are considered to be peaks derived from weak oxygen bonds derived from H ₂ O, O ₂ , or CO ₂ on the surface in the above-described oxide. . 11 (b1) and FIG. 12 (b2) are peaks of 531 eV or more and 532 eV or less (also referred to as the vicinity of 531 eV), which reflect the above-described oxygen deficiency state in the oxide, or oxide It is a peak that is considered to originate from the oxygen deficiency state in the inside.

As shown in FIGS. 11 and 12, it can be seen that an oxide containing zirconium (Zr) has a smaller peak in the vicinity of 531.9 eV than an oxide not containing zirconium.
More specifically, in (b1) shown in FIG. 11, when the total number of oxygen atoms is 1, the number of oxygen atoms caused by a peak near 531.9 eV was 0.200. In (b2) shown in FIG. 12, when the total number of oxygen atoms is 1, the number of oxygen atoms caused by a peak near 531.9 eV was 0.277.

  Further analysis by the inventors later revealed that the peak in the vicinity of 531.9 eV became smaller as the content of zirconium (Zr) in the oxide was increased. Therefore, it is considered that oxygen deficiency is suppressed by forming the peak state (b1) shown in FIG. Therefore, it is considered that the peak state of (b1) shown in FIG. 11 contributes to adjustment to an appropriate carrier concentration when the transistor is operated and improvement of interface characteristics with the gate insulating film. In particular, if the number of oxygen atoms due to the peak in the range of 531 eV or more and 532 eV or less when the total number of oxygen atoms is 1 is 0.19 or more and 0.21 or less, excessive oxygen In order to suppress defects, it contributes to improvement of various characteristics (for example, reduction of hysteresis, ON / OFF ratio) as a thin film transistor.

(5) Observation of oxide surface by AFM and analysis of its surface roughness Furthermore, observation of an AFM (Atomic Force Microscopy) image of the oxide for a channel that differs only in thickness from the channel in Example 1, and analysis of its surface roughness Went. FIG. 13 is a diagram showing an AFM image and surface roughness of the channel oxide and the surface of the oxide as the reference measurement target.

  Specifically, as in the case of the XPS analysis result, an oxide (sample A in FIG. 13) of indium (In), zinc (Zn), and zirconium (Zr) having a thickness of about 30 nm is an analysis target. Therefore, it can be said that this oxide is substantially a channel oxide. Further, it is an oxide composed of indium (In) and zinc (Zn) (and thus does not contain zirconium (Zr)), and is formed by the same solution method as in the first embodiment except for the difference in material. The sample (sample B in FIG. 13) was also analyzed as a reference measurement object.

  As shown in FIG. 13, from the viewpoint of surface roughness, an oxide containing zirconium (Zr) has a smaller root mean square (RMS) value than an oxide not containing it. Was confirmed. Further analysis by the inventors later revealed that the RMS value decreases as the zirconium (Zr) content in the oxide is increased. Therefore, it became clear that the channel in Example 1 can improve flatness by containing zirconium (Zr). This high flatness can contribute to improvement in dimensional accuracy particularly when forming a thin film transistor having a stacked structure, and leads to improvement in interface characteristics between the channel and the gate insulating film.

  As described above, it has been clarified that the thin film transistor 100 of the present embodiment can achieve good electrical characteristics as a thin film transistor. In addition, according to the method of manufacturing the thin film transistor 100 of the present embodiment, the gate insulating layer and the channel are formed of an oxide and are formed using a solution method, so that the area is increased as compared with the conventional method. As a result, industriality and mass productivity are significantly improved.

<Second Embodiment>
1. Overall Configuration of Thin Film Capacitor of this Embodiment FIGS. 14 to 18 are schematic cross-sectional views showing a part of the manufacturing method of the thin film transistor 200, respectively. FIG. 18 is a schematic cross-sectional view showing a part of the process and the overall configuration of the method of manufacturing the thin film transistor 200 according to this embodiment. As shown in FIG. 18, in the thin film transistor 200 according to the present embodiment, the gate electrode 20, the first gate insulating layer 234a, the second gate insulating layer 234b (laminated gate insulating layers) are formed on the substrate 10 from the lower layer. 234), the channel 44, the source electrode 58, and the drain electrode 56 are stacked in this order.

  In this embodiment, the gate insulating layer 234 of the thin film transistor 200 includes a second gate insulating layer 234b that is a layer of a multi-component oxide (which may include inevitable impurities) made of lanthanum (La) and zirconium (Zr), The second embodiment is the same as the first embodiment except that the first gate insulating layer 234a made of the same silicon oxide as the silicon oxide employed in the first embodiment has a stacked structure. Therefore, only the configuration different from the configuration of the thin film transistor 100 of the first embodiment and the manufacturing method thereof will be described for the configuration of the thin film transistor 200.

  As shown in FIG. 14, the thin film transistor 200 in this embodiment employs a stacked structure of a second gate insulating layer 234b and a first gate insulating layer 234a as the gate insulating layer 234.

  In the method of manufacturing the thin film transistor 200 of the present embodiment, first, as shown in FIG. 14, the first gate insulating layer 234a which is the same as the silicon oxide employed in the first embodiment is formed on the gate electrode 20 on the substrate 10. Is formed.

  After that, as shown in FIG. 15, the second gate insulation having a lanthanum (La) -containing precursor and zirconium (Zr) -containing precursor as a solute on the first gate insulating layer 234a by a known spin coating method. A second gate insulating layer precursor layer 232b is formed using the layer precursor solution as a starting material.

  An example of a precursor containing lanthanum (La) for the multi-component oxide 234b for the second gate insulating layer in the present embodiment is lanthanum acetate. As other examples, lanthanum nitrate, lanthanum chloride, or various lanthanum alkoxides (for example, lanthanum isopropoxide, lanthanum butoxide, lanthanum ethoxide, lanthanum methoxyethoxide) may be employed. An example of a precursor containing zirconium (Zr) for the multi-component oxide 234b for the second gate insulating layer in the present embodiment is zirconium butoxide. As other examples, zirconium nitrate, zirconium chloride, or various other zirconium alkoxides (eg, zirconium isopropoxide, zirconium butoxide, zirconium ethoxide, zirconium methoxyethoxide) may be employed.

  Then, it heats at 80 degreeC or more and 250 degrees C or less for predetermined time as preliminary baking. By the way, this pre-baking sufficiently evaporates the solvent in the second gate insulating layer precursor layer 232b and at the same time favors a gel state (before thermal decomposition) to develop characteristics that enable plastic deformation. Thus, it can be considered that the organic chain remains). Speaking from the above viewpoint, the pre-baking temperature is preferably 80 ° C. or higher and 250 ° C. or lower. This temperature range is also a preferred temperature range for pre-baking in other materials.

  This pre-baking is performed in an oxygen-containing atmosphere. In the present embodiment, in order to finally obtain a sufficient thickness (for example, about 125 nm) of the gate insulating layer 34, a plurality of formations and preliminary firings of the second gate insulating layer precursor layer 232b by the above-described spin coating method are performed. Repeat once. After that, as the main firing, the second gate insulating layer precursor layer 232b is heated at 350 ° C. or higher and 550 ° C. or lower for a predetermined time in an oxygen atmosphere, and as shown in FIG. A second gate insulating layer 234b that is an oxide of lanthanum (La) and zirconium (Zr) is formed over the one gate insulating layer 234a. Note that a layer formed of an oxide containing lanthanum (La) and zirconium (Zr) is also referred to as an LZO layer.

  Thereafter, as in the first embodiment, a precursor containing indium (In), a precursor containing zinc (Zn), and zirconium (Zr) are formed on the second gate insulating layer 234b by a known spin coating method. A channel precursor layer 42 starting from a channel precursor solution containing the precursor contained therein as a solute was formed. Thereafter, preliminary firing and main firing similar to those of the first embodiment are performed.

  Thereafter, similarly to the first embodiment, the drain electrode 56 and the source electrode 58 made of the ITO layer 50 are formed on the channel 44, whereby the first gate insulating layer 234a and the second gate insulating layer 234b are formed. The thin film transistor 200 of this embodiment including the gate insulating layer 234 having a stacked structure is manufactured.

  In the present embodiment, the gate insulating layer 234 in which the second gate insulating layer 234b is stacked on the first gate insulating layer 234a is employed. However, the present embodiment is not limited to this structure. For example, the use of a gate insulating layer in which the first gate insulating layer 234a is stacked on the second gate insulating layer 234b is another point in that at least a part of the effect of the present embodiment is achieved. This is a preferred embodiment.

  However, the diffusion of zirconium (Zr) contained in the channel 44 into the gate insulating layer 234 is not preferable because it may form a so-called trap order in the gate insulating layer. Therefore, from the viewpoint of preventing the diffusion of zirconium (Zr) contained in the channel 44 into the gate insulating layer 234 with high accuracy, gate insulation in which the second gate insulating layer 234b is stacked on the first gate insulating layer 234a. The layer 234 is employed, and the second gate insulating layer 234b is preferably disposed so as to be in contact with the channel 44.

  In addition, when the thickness of the first gate insulating layer 234a which is a silicon oxide layer is 1, the thickness of the second gate insulating layer 234b which is a multi-component oxide layer is 0.1 or more and 2 or less. It is a preferable aspect from the viewpoint of achieving the above-described effect with higher accuracy.

3. Characteristics of Thin Film Transistor 200 Next, Example 2 will be described in order to describe the second embodiment in more detail, but the present embodiment is not limited to this example. For Example 2, the characteristics of the thin film transistor 200 were examined by the following method.

(Example 2)
In Example 2, the precursor containing lanthanum (La) for the multi-component oxide 234b for the second gate insulating layer was lanthanum acetylacetonate. A precursor containing zirconium (Zr) for the multi-component oxide 234b for the second gate insulating layer was zirconium butoxide. A thin film transistor 200 was fabricated under the same conditions as in Example 1 except for these. The thickness for the second gate insulating layer was about 120 nm.

(1) Current-Voltage Characteristics FIG. 19 is a graph showing the Vg-Id characteristics of the thin film transistor 200. V _D in FIG. 19 is a voltage (V) applied between the source electrode 58 and the drain electrode 56 of the thin film transistor 200. Table 1 shows a threshold value (V _th ), a field effect mobility (μ _FE ), and an ON / OFF ratio in the thin film transistor 200.

As shown in FIG. 19 and Table 2, when the Vg-Id characteristic of the thin film transistor 200 in the second embodiment was examined, the threshold value (V _th ) was 0 V, and the field effect mobility (μ _FE ) was 3.17 cm. ² / Vs. The ON / OFF ratio was a very high value of the order of 10 ⁸ or more. Therefore, the thin film transistor 200 can sufficiently exhibit the function as a transistor even though the gate insulating layer and the channel that form the thin film transistor 200 are an oxide layer and are formed by employing a solution method. Was confirmed. In this example as well, the main baking temperature of the channel 44 was 500 ° C., but from the experimental results of the inventors, if the heating temperature in the main baking is 350 ° C. or higher and 500 ° C. or lower, the channel 44 functions as a thin film transistor. Confirmed to do. In addition, it was also confirmed that if the heating temperature in the main baking is 400 ° C. or higher and 500 ° C. or lower, the stability of each electrical characteristic of the transistor is improved.

(2) Relative permittivity As a result of measuring the relative permittivity in Example 2, the relative permittivity as a whole of the gate insulating layer 234 having a laminated structure was approximately 4.2 or more and 8.4 or less. .

(3) Crystal structure analysis by XRD analysis As a result of the analysis by the X-ray diffractometer of the channel in Example 2, no characteristic peak was observed, so that the channel oxide constituting the channel was an amorphous phase. I found out. Therefore, also in this embodiment, since the channel oxide contains zirconium (Zr), it becomes possible to form an amorphous phase relatively easily, so that the flatness of the oxide layer is improved. be able to. In addition, since an amorphous phase can be formed relatively easily, a good interface with the gate insulating layer 234 can be formed.

  As described above, it has become clear that the thin film transistor 200 of the present embodiment can achieve good electrical characteristics as a thin film transistor. In addition, according to the method of manufacturing the thin film transistor 200 of the present embodiment, the gate insulating layer and the channel are made of an oxide and are formed using a solution method, so that the area is increased as compared with the conventional method. As a result, industriality and mass productivity are significantly improved.

<Third Embodiment>
The present embodiment is the same as the second embodiment except that the embossing process is performed in the formation process of a part of the layers in the second embodiment. Therefore, the description overlapping with the first and second embodiments can be omitted. In the description of the present embodiment, those skilled in the art can fully understand the manner in which the embossing process is performed in the formation process of a part of the layers in the first embodiment. Omitted.

1. Manufacturing Method of Thin Film Transistor 300 FIGS. 20 to 25 are schematic cross-sectional views illustrating one process of the manufacturing method of the thin film transistor 300. FIG. FIG. 25 is a schematic cross-sectional view showing one process and the entire configuration of the method of manufacturing the thin film transistor 300 in the present embodiment. In order to simplify the drawing, the description of the patterning of the extraction electrode from each electrode is omitted.

(1) Formation of Gate Electrode First, as shown in FIG. 20, the gate electrode 20 is formed on the substrate 10 by a known sputtering method, photolithography method, and etching method. Note that the material of the gate electrode 20 of the present embodiment is platinum (Pt).

(2) Formation of Gate Insulating Layer Next, a precursor for a gate insulating layer having polysilazane as a solute on the substrate 10 and the gate electrode 20 by a known spin coating method, as in the first embodiment. A gate insulating layer precursor layer 332a is formed using the solution as a starting material.

  Thereafter, in the present embodiment, the first gate insulating layer precursor layer 332a is pre-fired. Specifically, the first gate insulating layer precursor layer 332a is heated to 80 to 250 ° C. in the atmosphere (including water vapor). By the way, this baking step evaporates the solvent in the gate insulating layer precursor layer 32 moderately or sufficiently, and at the same time favors the gel state (before thermal decomposition) to develop characteristics that enable plastic deformation. It is considered that the organic chain remains). Speaking from the above viewpoint, the firing temperature is preferably 80 ° C. or higher and 200 ° C. or lower.

  Next, a precursor solution containing a precursor containing lanthanum (La) and a precursor containing zirconium (Zr) as a solute on the first gate insulating layer precursor layer 332a by a known spin coating method is used as a starting material. The second gate insulating layer precursor layer 334b is formed. Thereafter, preliminary firing is performed in an oxygen-containing atmosphere in a state of being heated to 80 to less than 250 ° C. In the present embodiment, since a stacked structure including the first gate insulating layer precursor layer 332a is adopted, from the viewpoint of increasing the accuracy of the stamping process of the first gate insulating layer precursor layer 332a described later. In other words, the (preliminary) firing temperature for the second gate insulating layer precursor layer 334b is more preferably 80 ° C. or higher and 200 ° C. or lower.

  After the gate insulating layer precursor layer 332 having a stacked structure of the first gate insulating layer precursor layer 332a and the second gate insulating layer precursor layer 334b is formed, an embossing process is performed on the stacked structure. Is called.

  Specifically, in order to perform patterning of the gate insulating layer precursor layer 332 having a laminated structure in which only pre-baking is performed, as shown in FIG. 20, in an oxygen-containing atmosphere containing water vapor, the temperature is 100 to 250 ° C. In the heated state, the gate insulating layer mold M1 is used to perform a stamping process at a pressure of 1 MPa to 20 MPa. As a result, according to the gate insulating layer mold M1 of the present embodiment, the first gate insulating layer precursor layer 332a having a layer thickness of about 100 nm to about 150 nm and the second gate insulating layer having a layer thickness of about 50 nm to about 150 nm. A gate insulating layer precursor layer 332 is formed by laminating the precursor layer 332b for use.

  Thereafter, the gate insulating layer precursor layer 332 is removed by etching the entire surface of the gate insulating layer precursor layer 332 as shown in FIG. 21 from the region other than the region corresponding to the gate insulating layer (gate insulating layer). Etching step for the entire surface of the precursor layer 332 for use). In addition, although the etching process of the precursor layer 332 for gate insulating layers of this embodiment was performed using the wet etching technique which does not use a vacuum process, it is etched by what is called dry etching technique using plasma. Not disturb.

  Thereafter, by heating at 450 ° C. or more and 500 ° C. or less as main firing for a predetermined time, a gate insulating layer 334 is formed on the substrate 10 and the gate electrode 20 as shown in FIG.

(3) Formation of channel A die pressing process is performed on the channel precursor layer 42 that has been pre-fired only. First, on the gate insulating layer 334 and the substrate 10, as in the first embodiment, a precursor containing indium (In), a precursor containing zinc (Zn), and a precursor containing zirconium (Zr) are soluted. A channel precursor layer 42 starting from the channel precursor solution is formed. Thereafter, the channel precursor layer 42 is heated in a range of 350 ° C. or more and 550 ° C. or less for a predetermined time as preliminary firing as in the first embodiment.

  Next, as shown in FIG. 23, with the channel mold M2 being heated to 80 ° C. or higher and 300 ° C. or lower, the channel precursor layer 42 is embossed with a pressure of 1 MPa or higher and 20 MPa or lower. Apply. As a result, a channel precursor layer 42 having a layer thickness of about 50 nm or more and about 300 nm or less is formed. After that, by baking for a predetermined time in the range of 350 ° C. or more and 550 ° C. or less, as shown in FIG. 24, on the gate insulating layer 334, from indium (In), zinc (Zn), and zirconium (Zr). A channel 44 is formed.

(4) Formation of Source Electrode and Drain Electrode Next, as in the first embodiment, after a resist film patterned by a known photolithography method is formed on the channel 44, the channel 44 and the resist film are formed. Then, an ITO layer is formed by a known sputtering method. Thereafter, when the resist film is removed, a drain electrode 56 and a source electrode 58 made of an ITO layer are formed on the channel 44 as shown in FIG.

  In this embodiment, embossing is performed on the precursor layer that has obtained high plastic deformation ability. As a result, even when the pressure applied when embossing is a low pressure of 1 MPa or more and 20 MPa or less, each precursor layer comes to deform following the surface shape of the mold, and the desired embossing structure Can be formed with high accuracy. In addition, by setting the pressure in a low pressure range of 1 MPa or more and 20 MPa or less, the mold becomes difficult to be damaged when performing the stamping process, and it is advantageous for increasing the area.

  Here, the reason why the pressure is within the range of “1 MPa or more and 20 MPa or less” is as follows. First, if the pressure is less than 1 MPa, the pressure may be too low to emboss each precursor layer. On the other hand, if the pressure is 20 MPa, the precursor layer can be sufficiently embossed, so that it is not necessary to apply more pressure. From the viewpoint described above, it is more preferable to perform the embossing process at a pressure in the range of 2 MPa to 10 MPa in the embossing process in the third embodiment.

  In the third embodiment, the embossing process is performed on the gate insulating layer 334 and the channel 44 having the stacked structure of the second embodiment, but the object of the embossing process is not limited thereto. For example, it is possible to form a stamping structure on the single-layer gate insulating layer 34 according to the first embodiment by performing a stamping process under the above-described conditions.

  As described above, in the present embodiment, the “embossing process” is employed in which the embossing structure is formed by embossing the gate insulating layer 334 and the channel 44. By adopting this embossing process, a process that requires a relatively long time and / or expensive equipment such as a vacuum process, a process using a photolithography method, or an ultraviolet irradiation process becomes unnecessary. Therefore, the thin film transistor 300 and the manufacturing method thereof are extremely excellent in industrial property or mass productivity.

<Other embodiments>
In order to appropriately exhibit the effects in the above-described embodiments, the solvent of the channel precursor solution is selected from the group of ethanol, propanol, butanol, 2-methoxyethanol, 2-ethoxyethanol, and 2-butoxyethanol. A solvent that is one alcohol solvent or one carboxylic acid selected from the group of acetic acid, propionic acid, and octylic acid is preferable.

  In addition, in order to appropriately achieve the effects in the above-described embodiments, the solvent of the precursor solution for the gate insulating layer is ethanol, propanol, butanol, 2-methoxyethanol, 2-ethoxyethanol, or 2-butoxyethanol. One alcohol solvent selected from the group, or one carboxylic acid selected from the group of acetic acid, propionic acid, and octylic acid, xylene, or dibutyl ether is preferable.

  In Example 1 described above, the ratio of the number of atoms of indium (In) and zinc (Zn) in the channel oxide layer made of indium (In), zinc (Zn), and zirconium (Zr) is When indium (In) is 1, zinc (Zn) is not limited to 0.5. For example, if at least indium (In) is 1 and zinc (Zn) is in the range of 0.4 to 0.6, at least a part of the effect of Example 1 can be achieved.

  In the preliminary firing for forming each oxide layer in the third embodiment described above, the preliminary firing temperature is most preferably 80 ° C. or higher and 200 ° C. or lower. This is because the solvent in the various precursor layers can be evaporated more appropriately or sufficiently. In particular, when the embossing process is performed after that, pre-baking in the above-mentioned temperature range is preferable to develop a property that enables future plastic deformation (before the pyrolysis). It can be considered that the organic chain remains in this state.

  Moreover, in the above-mentioned 3rd Embodiment, it is supposed that a stamping process is performed with respect to the precursor layer which acquired the high plastic deformation capability. As a result, even when the pressure applied when embossing is as low as 1 MPa or more and 20 MPa or less, each precursor layer is deformed following the surface shape of the mold, and a desired embossing structure is obtained. Can be formed with high accuracy. In addition, by setting the pressure in a low pressure range of 1 MPa or more and 20 MPa or less, the mold becomes difficult to be damaged when performing the stamping process, and it is advantageous for increasing the area.

  Here, the reason why the pressure is within the range of “1 MPa or more and 20 MPa or less” is as follows. First, if the pressure is less than 1 MPa, the pressure may be too low to emboss each precursor layer. On the other hand, if the pressure is 20 MPa, the precursor layer can be sufficiently embossed, so that it is not necessary to apply more pressure. From the viewpoint described above, it is more preferable to perform the embossing process at a pressure in the range of 2 MPa to 10 MPa in the embossing process in the third embodiment described above.

  Further, in each of the above-described embossing steps, in advance, a mold release treatment for the surface of each precursor layer and / or a mold release surface for the mold pressing surface, which the mold pressing surface comes into contact with, is performed. Thereafter, it is preferable to perform a stamping process on each precursor layer. By performing such treatment, it is possible to reduce the frictional force between each precursor layer and the mold, and therefore it is possible to perform the stamping process with higher accuracy on each precursor layer. . Examples of the release agent that can be used for the release treatment include surfactants (for example, fluorine surfactants, silicon surfactants, nonionic surfactants, etc.), fluorine-containing diamond-like carbon, and the like. can do.

  In addition, each precursor layer (for example, a channel precursor layer or a gate insulating layer) that has been subjected to a stamping process between the stamping step and the main firing step for each precursor layer in each of the above-described embodiments. It is a more preferable aspect that the step of etching the precursor layer as a whole is included on the condition that the precursor layer is removed in the thinnest region of the precursor layer). This is because unnecessary regions can be removed more easily than etching after each precursor layer is finally fired. Therefore, in each of the above-described embodiments, a more preferable aspect described above can be adopted instead of the step of performing the entire etching after the main baking.

  In each of the above-described embodiments, a thin film transistor having a so-called inverted staggered structure is described. However, each of the above-described embodiments is not limited to the structure. For example, not only a thin film transistor having a staggered structure but also a thin film transistor having a so-called planar structure in which a source electrode, a drain electrode, and a channel are arranged on the same plane can achieve the effects of the above-described embodiments. The same effect can be achieved.

  As described above, the disclosure of each of the embodiments described above is described for explaining the embodiments, and is not described for limiting the present invention. In addition, modifications within the scope of the present invention including other combinations of the embodiments are also included in the claims.

DESCRIPTION OF SYMBOLS 10 Substrate 20 Gate electrode 32 Gate insulating layer precursor layer 232a, 332a First gate insulating layer precursor layer 232b, 332b Second gate insulating layer precursor layer 34, 234, 334 Gate insulating layer 234a, 334a First Gate insulating layer 234b, 334b Second gate insulating layer 42 Channel precursor layer 44 Channel 50 ITO layer 56 Drain electrode 58 Source electrode 100, 200, 300 Thin film transistor 90 Resist film M1 Gate insulating layer type M2 Channel type

Claims (10)

Lamination of a layer of a multi-component oxide (which may include unavoidable impurities) and a layer of silicon oxide ( which may include unavoidable impurities) made of lanthanum (La) and zirconium (Zr) between the gate electrode and the channel A gate insulating layer comprising a structure ;
The channel contains indium (In) and zinc (Zn), and a channel containing zirconium (Zr) having an atomic ratio of 0.046 to 0.375 when the indium (In) is 1. Oxide (which may contain inevitable impurities),
Thin film transistor. The channel oxide is in an amorphous phase;
The thin film transistor according to claim 1 . When the thickness of the silicon oxide layer is 1, the thickness of the multi-component oxide layer is 0.1 or more and 2 or less.
The thin film transistor according to claim 1 or 2 . The gate dielectric layer having the laminated structure has a relative dielectric constant of 4.2 or more and 8.4 or less.
The thin film transistor according to claim 1 . The channel is the multi-component oxide, and
In the X-ray photoelectron spectroscopy analysis, the number of oxygen atoms caused by a peak in the range of 531 eV or more and 532 eV or less when the total number of oxygen atoms contained in the channel is 1 is 0. .19 or more and 0.21 or less,
The thin film transistor according to any one of claims 1 to 4 . Silicon oxide (unavoidable) formed by heating a precursor layer for a first gate insulating layer starting from a precursor solution for a first gate insulating layer containing polysilazane as a solute in a steam-containing atmosphere For a second gate insulating layer starting from a precursor solution for a second gate insulating layer containing a precursor containing lanthanum (La) and a precursor containing zirconium (Zr) as a solute. By heating the precursor layer in an oxygen-containing atmosphere, a multi-component oxide layer (which may contain unavoidable impurities) containing lanthanum (La) zirconium (Zr) is formed to have a stacked structure. A gate insulating layer forming step for forming an insulating layer;
Gate electrode layer forming step and the channel for oxide comprises between steps of forming the channel for forming a (which may include inevitable impurities),
The channel formation step includes a precursor containing indium (In), a precursor containing zinc (Zn), and an atomic ratio of 0.046 to 0.375 when the indium (In) is 1. By heating a channel precursor layer starting from a channel precursor solution having a precursor containing zirconium (Zr) as a solute in an oxygen-containing atmosphere, indium (In) and zinc (Zn) And forming a channel oxide (which may contain inevitable impurities) containing zirconium (Zr) having an atomic ratio of 0.046 to 0.375 when the indium (In) is 1 Is,
A method for manufacturing a thin film transistor. The channel oxide is in an amorphous phase;
The manufacturing method of the thin-film transistor of Claim 6 . When the thickness of the silicon oxide layer is 1, the thickness of the multi-component oxide layer is 0.1 or more and 2 or less.
The manufacturing method of the thin-film transistor of Claim 6 or Claim 7 . In the gate insulating layer forming step,
Before forming the gate insulating layer, the first gate insulating layer precursor layer and the first gate insulating layer are subjected to embossing in an oxygen-containing atmosphere containing water vapor and heated at 100 to less than 250 ° C. Further including a stamping step of forming a stamping structure on the two-gate insulating layer precursor layer ,
The manufacturing method of the thin-film transistor of Claim 6 . In the channel forming step,
Before forming the channel, the channel precursor layer is subjected to an embossing process in a state where the channel precursor layer is heated at 80 ° C. or more and 300 ° C. or less in an oxygen-containing atmosphere. Further comprising a stamping step for forming a stamping structure,
A method for manufacturing a thin film transistor according to any one of claims 6 to 9 .