TW201330178A - Method for manufacturing semiconductor device - Google Patents

Abstract

A method for manufacturing a semiconductor device includes providing a substrate having a first gate structure and a second gate structure formed thereon; blanketly forming a seal layer covering the first gate structure and the second gate structure on the substrate; performing a first ion implantation to form first light-doped drains (LDDs) in the substrate respectively at two sides of the first gate structure; and performing a second ion implantation to form second LDDs in the substrate respectively at two sides of the second gate structure; wherein at least one of the first ion implantation and the second ion implantation is performed to penetrate through the seal layer.

Description

Semiconductor component manufacturing method

The invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a semiconductor device capable of improving an ultra shallow junction (USJ).

In order to improve the operational efficiency of a metal-oxide-semiconductor field effect transistor (MOSFET), the conventional method is to reduce the size of the MOSFET, so that in addition to improving the operational performance of the device, the component can be simultaneously improved. Density and reduced manufacturing costs. Due to the reduction of the gate length of the conventional MOSFET, the source and the drain are easily interacted with each other, which affects the gate's ability to control the on/off state of the channel, further causing short channels. Short channel effects (SCE). In order to solve the aforementioned short channel effect problem, the prior art proposes methods of increasing the doping concentration of the host, reducing the thickness of the gate oxide layer, and shallow junction or even ultra shallow junction.

In general, the fabrication of the drain/source extension regions with ultra-shallow junctions is implanted into the shallow surface of the germanium substrate with low energy ions. However, while reducing the size of the components, the concentration of dopant atoms in the source, drain and channel must be increased, the junction depth is reduced, and the shape of the dopant concentration distribution is significantly changed. Therefore, the behavior of doping element diffusion is mastered. It is very important. In other words, as the size of the MOS transistor continues to shrink, the fabrication of the ultra-shallow joint is more difficult. Therefore, there is still a need for a method of fabricating a semiconductor component that can improve ultra-shallow bonding surfaces and provide high performance components.

Accordingly, it is an object of the present invention to provide a method of fabricating a semiconductor device that improves the ultra-shallow junction.

According to the patent application scope of the present invention, there is provided a method of fabricating a semiconductor device, which first provides a substrate having a first gate structure and a second gate structure formed thereon. The manufacturing method further includes integrally forming a seal layer on the substrate, and the cover layer covers the first gate structure and the second gate structure. In addition, the manufacturing method provided by the present invention further includes performing a first ion implantation process to form a first lightly doped drain (hereinafter referred to as a lightly-doped drain) in the substrate on both sides of the first gate structure. And performing a second ion implantation process to form a second LDD in the substrate on both sides of the second gate structure. It is noted that at least one of the first lightly doped drain process and the second lightly doped drain process penetrates the cover layer.

The method for fabricating a semiconductor device according to the present invention is to form the mask layer on the substrate comprehensively before performing the first ion implantation process or/and the second ion implantation process, and thus the first ion implantation process At least one of the second ion implantation process penetrates the mask layer to form the first LDD or/and the second LDD. Due to the arrangement of the cover layer, the first LDD or/and the second LDD can be made to obtain the desired ultra-shallow junction profile. Therefore, the method for fabricating the semiconductor device provided by the present invention can improve the ultra-shallow junction of the LDD under the tendency of the semiconductor device to continuously shrink, so that the short channel effect can be effectively suppressed and the performance of the semiconductor device can be improved.

Please refer to FIG. 1 to FIG. 3 . FIG. 1 to FIG. 3 are schematic diagrams showing a first preferred embodiment of a method for fabricating a semiconductor device according to the present invention. As shown in FIG. 1 , the preferred embodiment first provides a substrate 100 having a first region 102 and a second region 104 defined therein, and a first region 102 and a second region 104 are respectively formed with a first region. A gate structure 110 and a second gate structure 112 are formed, and a plurality of shallow trench isolation (STI) 106 are formed in the substrate 100 for providing electrical isolation. In the preferred embodiment, the first gate structure 110 is a gate structure of a p-type MOS (p-MOS) device; and the second gate structure 112 is an n-type MOS (n-MOS) device. The gate structure. As shown in FIG. 1, the first gate structure 110 and the second gate structure 112 sequentially include a gate dielectric layer 110a and 112a, a gate conductive layer 110b and 112b, respectively, from bottom to top, and Patterned hard masks 110c and 112c defining gate structures 110/112.

Please continue to see Figure 1. Next, a cover layer 120 is formed on the substrate 100 in a blanket. As shown in FIG. 1, the cover layer 120 covers the first gate structure 110 and the second gate structure 112. In the preferred embodiment, the mask layer 120 may include tantalum oxide, tantalum nitride, a composite film layer containing tantalum oxide and tantalum nitride, a carbon-containing tantalum nitride layer, and silicon carbon nitride (SiCN). , hexachlorodisilane (HCD), or carbon doped hexachlorodisilane (CHCD), but is not limited thereto. The cover layer 120 has a thickness ranging from 25 angstroms to 50 angstroms. After the mask layer 120 is formed, an insulating layer (not shown) having an etching rate different from that of the mask layer 120 is formed on the substrate 100, and a portion of the insulating layer is removed by an etch back method, and the first gate is removed. A sidewall of the structure 110 and a sidewall of the second gate structure 112 respectively form a first sidewall 122. As shown in FIG. 1, a portion of the cover layer 120 covered by the insulating layer may also serve as a portion of the first side wall member 122.

Please refer to Figure 2. After forming the first sidewall sub-122, a patterned mask 130, such as a patterned photoresist, is formed on the substrate 100, and the patterned mask 130 covers the second region 104 to expose the first region 102. Subsequently, as shown in Fig. 2, a first ion implantation process 132 is performed, such as a tilted ion implantation process. The first ion implantation process 132 is configured to implant a p-type dopant, such as boron (boron, B) or boron difluoride (BF ₂ ), into the first gate. A substrate 100 is formed on both sides of the structure 110, and a first LDD 110d is formed in the substrate 100 on both sides of the first gate structure 110. In addition, the first ion implantation process 132 can further form other doped regions by using the patterned mask 130 to match the doping, energy, and doping angles of different conductivity types, for example, phosphorus (P) or arsenic can be utilized. Arsenic, Ar) and other n-type dopants form a pocket-type pocket region (not shown), or use germanium (Ge), fluorine (Fluorine, F) or carbon (carbon, C), etc. The dopant is co-implanted.

Please refer to Figure 3. After the first LDD 110d is formed, the patterned mask 130 is removed and another patterned mask 140 is formed on the substrate 100. The patterned mask 140 covers the first region 102 and exposes the second region 104. Then, as shown in FIG. 3, a second ion implantation process 142, such as an oblique ion implantation process, is performed to pass the n-type dopant, such as P or Ar, into the cover layer 120. The substrate 100 is implanted in the substrate 100 on both sides of the second gate structure 112 to form a second LDD 112d. The second ion implantation process 142 can also form other doped regions by using the patterned mask 140 to match the doping, energy, and doping angles of different conductivity types, for example, p-type dopants such as B or BF ₂ can be used. A pocket-type doped region (not shown) is formed, or co-doped with a dopant such as Ge, F or C. Thereafter, the patterned mask 140 is removed to expose the mask layer 120 and subsequent processes such as source/drain electrodes (shown in Figures 9 through 12). It should be noted that in the preferred embodiment, the n-type LDD is formed after the p-type LDD is formed first. However, in a variation of the preferred embodiment, the n-type LDD may be formed first to form a p-type. LDD.

The method for fabricating the semiconductor device according to the first preferred embodiment is to form the mask layer 120 on the substrate 100 before forming the p-type LDD and the n-type LDD. Therefore, the first ion implantation process 132 and the first The two-ion implantation process 142 must penetrate the cover layer 120, that is, the n-type and p-type dopants must penetrate the cover layer 120 to enter the substrate 100, and the first LDD 110d and the second LDD 112d are available. A profile with an ultra-shallow junction.

Please refer to FIG. 4 to FIG. 6 . FIG. 4 to FIG. 6 are schematic diagrams showing a second preferred embodiment of a method for fabricating a semiconductor device according to the present invention. It is to be noted that in the second preferred embodiment, the same components as those of the first preferred embodiment have the same reference numerals. The preferred embodiment differs from the first preferred embodiment in that the preferred embodiment is provided after the substrate 100 having the first gate structure 110 and the second gate structure 112 is provided, that is, at the first gate. A sidewall of the structure 110 and a sidewall of the second gate structure 112 respectively form a first sidewall 122. The width of the first side wall 122 is not more than 65 angstroms, but is not limited thereto. After the first sidewalls 122 are formed, a mask layer 120 is formed on the substrate 100 in a comprehensive manner. The thickness of the mask layer 120 and the material selection thereof are the same as those of the first preferred embodiment, and thus will not be described herein.

Please refer to Figure 5. After the mask layer 120 is formed, a patterned mask 130, such as a patterned photoresist, is formed on the substrate 100, and the patterned mask 130 covers the second region 104 to expose the first region 102. A first ion doping process 132 is then performed as shown in FIG. The first ion implantation process 132 is formed by implanting the dopant penetrating cover layer 120 into the substrate 100 on both sides of the first gate structure 110, and forming respectively in the substrate 100 on both sides of the first gate structure 110. A first LDD 110d.

After forming the first LDD 110d, the patterned mask 130 is removed, and another patterned mask 140 is formed on the substrate 100, and the patterned mask 140 covers the first region 102 to expose the second region. 104. Then, as shown in FIG. 6, a second ion doping process 142 is performed to implant the dopant penetrating capping layer 120 into the substrate 100 on both sides of the second gate structure 112 to form a The second LDD 112d. Thereafter, the patterned mask 140 is removed to expose the mask layer 120 and subsequent processes such as source/drain electrodes (shown in Figures 9 through 12). It should be noted that in the preferred embodiment, the n-type LDD is formed after the p-type LDD is formed first. However, in a variation of the preferred embodiment, the n-type LDD may be formed first to form a p-type. LDD.

According to the manufacturing method of the semiconductor device provided in the second preferred embodiment, the mask layer 120 is formed after the first sidewall spacer 122 is formed, so that the width of the first sidewall spacer 122 can be more accurately controlled, and the mask layer can be avoided. 120 is damaged during the etching process. More importantly, the preferred embodiment forms the mask layer 120 on the substrate 100 before forming the p-type LDD and the n-type LDD. Therefore, the first ion implantation process 132 and the second ion implantation process 142 are both It is necessary to penetrate the mask layer 120, that is, the n-type and p-type dopants must penetrate the mask layer 120 to enter the substrate 100, so that the first LDD 110d and the second LDD 112d can obtain an ultra-shallow junction. profile.

Referring to FIG. 7 to FIG. 12, FIG. 7 to FIG. 12 are schematic diagrams showing a third preferred embodiment of a method for fabricating a semiconductor device according to the present invention. It is to be noted that in the third preferred embodiment, the same components as those of the first preferred embodiment have the same reference numerals. The preferred embodiment differs from the foregoing first and second preferred embodiments in that the preferred embodiment is provided after the substrate 100 having the first gate structure 110 and the second gate structure 112 is provided. The sidewalls of the first gate structure 110 and the sidewalls of the second gate structure 112 respectively form a first sidewall spacer 122. As described above, the width of the first side wall sub-122 is not more than 65 angstroms, but is not limited thereto. After the first sidewalls 122 are formed, a patterned mask 130 is formed on the substrate 100, such as a patterned photoresist, and the patterned mask 130 covers the second region 104 to expose the first region 102. . Subsequently, as shown in FIG. 7, a first ion doping process 132 is performed, such as an oblique ion implantation process. The first ion implantation process 132 is a p-type dopant. In the preferred embodiment, a dopant such as a boron hydride cluster is preferably implanted on both sides of the first gate structure 110. A first LDD 110d is formed in the substrate 100 on both sides of the first gate structure 110.

Please refer to Figure 8. After the first ion implantation process 132 is performed to form the first LDD 110d, a cover layer 120 is formed on the substrate 100 in a comprehensive manner. The thickness of the cover layer 120 and the material selection thereof are the same as those of the first preferred embodiment. Therefore, this is not repeated here. After the mask layer 120 is formed, another patterned mask 140 is formed on the substrate 100, and the patterned mask 140 covers the first region 102 to expose the second region 104. Then, as shown in FIG. 8, a second ion doping process 142, such as an oblique ion implantation process, is performed to implant the n-type doping through-mask 120 into the second gate structure 112. Inside the substrate 100, a second LDD 112d is formed.

According to the method of fabricating the semiconductor device provided by the third preferred embodiment, when the p-type dopant contains a large hydrogen fluoride cluster, the ultra-shallow junction of the p-type LDD is automatically improved, and thus the mask layer 120 is improved. The system can be formed after the first ion implantation process 132. Since the second ion implantation process 142 is performed after the mask layer 120 is formed, the second ion implantation process must penetrate the mask layer 120, that is, the n-type dopant must penetrate the mask layer 120 to enter the substrate 100. The profile of the ultra-shallow junction can be obtained by both the first LDD 110d and the second LDD 112d.

Next, please refer to Figure 9 to Figure 13. It should be noted that the steps disclosed in FIG. 9 to FIG. 13 may be implemented after forming the first LDD 110d and the second LDD 112d in the first preferred embodiment to the third preferred embodiment. As shown in the first preferred embodiment to the third preferred embodiment, after forming the first LDD 110d and the second LDD 112d, and after removing the patterned mask 140, the sidewalls of the first gate structure 110 are attached. A sacrificial spacer 124 is sequentially formed on the sidewall of the second gate structure 112. Or as shown in FIG. 11, the sacrificial sidewalls 124 are formed only on the sidewalls 110 of the first gate structure.

Please refer to Figure 10 and Figure 11. After the sacrificial sidewalls 124 are formed, a recess (not shown) is etched into the substrate 100 on both sides of the sacrificial sidewalls 124 of the first gate structure 110. Subsequently, a selective epitaxial growth (SEG) process is performed to form an epitaxial layer 126, such as a silicon-germanium (SiGe) layer, along the substrate in the bottom and sides of the groove. 100 surface formation. In other words, the preferred embodiment can be integrated with strained silicon technology, using the lattice constant of germanium to be larger than this, forming the epitaxial layer 126 to drive the portion of the channel region. The lattice and the band structure of the wafer are changed to improve the operation speed of the p-type MOS device.

Please still refer to Figure 10 and Figure 11. After the fabrication of the epitaxial layer 126 is completed, the sacrificial sidewalls 124 and the exposed capping layer 120 are simultaneously removed, and as shown in FIG. 12, the first sidewalls 122 are exposed. After the mask layer 120 and the sacrificial sidewalls 124 are removed, a second sidewall is formed on the first sidewalls 122 of the first gate structure 110 and the second gate structure 112, as shown in FIG. Sub-128; subsequently forming a p-type doped first source/drain 110s and including n-type doping in the substrate 100 on both sides of the second sidewall 128 in the first region 102 and the second region 104, respectively. Second source/drain 112s of impurities. Since the steps of fabricating the second sidewalls 128 and the first source/drain 110s and the second source/drain 112s are known to those skilled in the art, they are not described herein. It should be noted that the first source/drain 110s are formed within the epitaxial layer 126 as shown in FIG. So far, a first MOS transistor element 150 having a p-type conductivity type and a second MOS transistor element 152 having an n-type conductivity type are completed.

According to the method for fabricating the semiconductor device provided in the first to third preferred embodiments, the mask layer 120 may be formed after the first sidewall spacer 122 is formed or after the mask layer 120 is formed on the first sidewall. After 122, the ion implantation process for forming the p-type LDD may also be performed before or after the formation of the mask layer 120 according to the selected dopant. In addition, since the mask layer 120 can be removed simultaneously with the sacrificial sidewalls 124, the fabrication methods of the semiconductor components provided by the first to third preferred embodiments do not affect subsequent components such as the first source/drain 110s and the Production of two source/bungee 112s. In other words, the fabrication method of the semiconductor device provided by the first to third preferred embodiments can effectively improve the ultra-shallow bonding of the first LDD 110d and the second LDD 112d without excessively increasing the process complexity. The first MOS transistor element 150 and the second MOS transistor element 152 are affected by the short channel effect.

Referring to FIGS. 14 to 18, FIGS. 14 to 18 are schematic views showing a fourth preferred embodiment of a method for fabricating a semiconductor device according to the present invention. As shown in FIG. 14, the preferred embodiment first provides a substrate 200 having a first region 202 and a second region 204 defined therein, and a first region 202 and a second region 204 are respectively formed with a first region. A gate structure 210 and a second gate structure 212 are formed in the substrate 200 with a plurality of STIs 206 for providing electrical isolation. In the preferred embodiment, the first gate structure 210 is a gate structure of a p-MOS device; and the second gate structure 212 is a gate structure of an n-MOS device. As shown in FIG. 14, the first gate structure 210 and the second gate structure 212 sequentially include a gate dielectric layer 210a and 212a, a gate conductive layer 210b and 212b, respectively, from bottom to top, and Patterned hard masks 210c and 212c defining gate structures 210b/212b.

Please continue to see Figure 14. Subsequently, a first sidewall 222 is formed on the sidewall of the first gate structure 210 and the sidewall of the second gate structure 212, respectively. And after the first sidewall 222 is formed, a patterned mask 230, such as a patterned photoresist, is formed on the substrate 200, and the patterned mask 230 covers the second region 204 to expose the first region 202. Subsequently, as shown in Fig. 14, a first ion doping process 232 is performed, such as an oblique ion implantation process. The first ion implantation process 232 is a p-type doping material. In the preferred embodiment, a dopant such as a boron-hydrogen ion cluster is preferably implanted into the substrate 200 on both sides of the first gate structure 210. A first LDD 210d is formed in the substrate 200 on both sides of the first gate structure 210.

Please refer to Figure 15 and Figure 16. After the first ion implantation process 320 is performed and the first LDD 210d is formed, the patterned mask 230 is removed, and then the sidewalls of the first gate structure 210 and the sidewalls of the second gate structure 212 are sequentially formed. Sacrificial sidewall 224; or as shown in FIG. 16, a sacrificial sidewall 224 is formed only on the sidewall of the first gate structure 210. After the sacrificial sidewalls 224 are formed, a recess (not shown) is etched into the substrate 200 on both sides of the sacrificial sidewalls 224 of the first gate structure 210. A SEG process is then performed to form an epitaxial layer 226, such as an epitaxial layer, along the surface of the substrate 200 in the bottom and sides of the recess.

Please refer to Figure 17. Next, the sacrificial sidewall 224 is removed, and then a masking layer 220 is formed over the substrate 200 in its entirety. And after the mask layer 220 is formed, another patterned mask 240 is formed on the substrate 200, and the patterned mask 240 covers the first region 202 to expose the second region 204. Then, as shown in FIG. 17, a second ion doping process 242, such as an oblique ion implantation process, is performed to implant the n-type doping through-mask 220 into both sides of the second gate structure 212. Within the substrate 200, a second LDD 212d is formed, respectively.

Please refer to Figure 18. After the second ion implantation process 242 is performed to form the second LDD 212d, the patterned mask 240 and the mask layer 220 are removed. Then, as shown in FIG. 18, a second sidewall 228 is formed on the sidewall of the first gate structure 210 and the sidewall of the second gate structure 212, respectively; and then further in the first region 202 and the second region 204. A first source/drain 210s including a p-type dopant and a second source/drain 212s including an n-type dopant are respectively formed in the substrate 200 on both sides of the second sidewall 228. Since the steps of fabricating the second sidewall 228 and the first source/drain 210s and the second source/drain 212s are known to those skilled in the art, no further details are provided herein. It should be noted that the first source/drain 210s are formed within the epitaxial layer 226 as shown in FIG. So far, a first MOS transistor element 250 having a p-type conductivity type and a second MOS transistor element 252 having an n-type conductivity type are completed.

The method for fabricating the semiconductor device according to the fourth preferred embodiment is to form the mask layer 220 after the SEG process is performed to form the epitaxial layer 226 and the sacrificial sidewall spacer 224 is removed, and after the mask layer 220 is formed. The second ion implantation process 242. Therefore, the second ion implantation process 242 must penetrate the cover layer 220, that is, the n-type dopant must penetrate the cover layer 220 to enter the substrate 200, and the second LDD 212d can obtain a profile having an ultra-shallow junction. In addition, since the mask layer 220 is formed after the SEG related process (such as removing the sacrificial sidewall spacers 224) in the preferred embodiment, the formation of the mask layer 220 does not affect the processes. In addition, the preferred embodiment further selects a larger hydrogenated fluoride ion cluster as the p-type dopant, so that the ultra-shallow junction of the p-type LDD is automatically improved. In other words, the manufacturing method of the semiconductor device provided by the preferred embodiment can effectively improve the ultra-shallow joint surface of the first LDD 210d and the second LDD 212d without excessively increasing the process complexity. The short channel effect is prevented from affecting the first MOS transistor element 250 and the second MOS transistor element 252.

According to the method for fabricating a semiconductor device provided by the present invention, the mask layer is formed on the substrate in a comprehensive manner before the first ion implantation process or/and the second ion implantation process, and thus the first lightly doped germanium At least one of the pole process and the second lightly doped drain process penetrates the mask layer to form the first LDD or/and the second LDD. Due to the arrangement of the cover layer, the first LDD or/and the second LDD can be made to obtain the desired ultra-shallow junction profile. Therefore, the method for fabricating the semiconductor device provided by the present invention can improve the ultra-shallow junction of the LDD under the tendency of the semiconductor device to continuously shrink, so that the short channel effect can be effectively suppressed and the performance of the semiconductor device can be improved.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100, 200. . . Base

102, 202. . . First area

104, 204. . . Second area

106, 206. . . Shallow trench isolation

110, 210. . . First gate structure

112, 212. . . Second gate structure

110a, 112a, 210a, 212a. . . Gate dielectric layer

110b, 112b, 210b, 212b. . . Gate conductive layer

110c, 112c, 210c, 212c. . . Patterned hard mask

110d, 210d. . . First lightly doped bungee

110s, 210s. . . First source/dip

112d, 212d. . . Second lightly doped bungee

112s, 212s. . . Second source/dip

120, 220. . . Cover layer

122, 222. . . First side wall

124, 224. . . Sacrifice the side wall

126, 226. . . Epitaxial layer

128, 228. . . Second side wall

130, 140, 230, 240. . . Patterned mask

132, 232. . . First ion implantation process

142, 242. . . Second ion implantation process

150, 250. . . First MOS semiconductor component

152, 252. . . Second MOS semiconductor component

1 to 3 and 9 to 13 are schematic views showing a first preferred embodiment of a method of fabricating a semiconductor device according to the present invention.

4 to 6 and 9 to 13 are schematic views showing a second preferred embodiment of a method of fabricating a semiconductor device according to the present invention.

7 to 13 are schematic views showing a third preferred embodiment of a method of fabricating a semiconductor device provided by the present invention.

14 to 18 are schematic views showing a fourth preferred embodiment of a method of fabricating a semiconductor device according to the present invention.

100. . . Base

102. . . First area

104. . . Second area

106. . . Shallow trench isolation

110. . . First gate structure

112. . . Second gate structure

110a, 112s. . . Gate dielectric layer

110b, 112b. . . Gate conductive layer

110c, 112c. . . Patterned hard mask

110d. . . First lightly doped bungee

120. . . Cover layer

122. . . First side wall

140. . . Patterned mask

142. . . Second ion implantation process

Claims (20)

A semiconductor device manufacturing method includes: providing a substrate on which a first gate structure and a second gate structure are formed; a cover layer is formed on the substrate in a comprehensive manner, and the cover is covered a layer covering the first gate structure and the second gate structure; performing a first ion implantation process to form a first lightly doped drain in the substrate on both sides of the first gate structure Lightly-doped drain (LDD); and performing a second ion implantation process to form a second lightly doped drain in the substrate on both sides of the second gate structure; wherein the first ion implantation process At least one of the second ion implantation processes penetrates the cover layer. The manufacturing method of claim 1, wherein the covering layer has a thickness and the thickness is between 25 angstroms and 50 angstroms. The manufacturing method of claim 1, wherein the covering layer comprises cerium oxide or cerium nitride. The manufacturing method of claim 1, further comprising the step of forming a first sidewall on the sidewall of the first gate structure and the sidewall of the second gate structure. The manufacturing method of claim 4, wherein the covering layer is formed after the first side wall is formed. The manufacturing method of claim 5, wherein the first ion implantation process and the second ion implantation process are performed after forming the cover layer. The manufacturing method of claim 6, wherein the first ion implantation process and the second ion implantation process penetrate the cover layer. The manufacturing method of claim 5, wherein the covering layer is formed after the performing the first ion implantation process and before performing the second ion implantation process. The manufacturing method of claim 4, wherein the covering layer is formed before the first side wall is formed, and a part of the covering layer is a part of the first side wall. The manufacturing method of claim 9, wherein the first ion implantation process and the second ion implantation process are performed after forming the first sidewall. The manufacturing method of claim 10, wherein the first ion implantation process and the second ion implantation process penetrate the cover layer. The manufacturing method of claim 1, further comprising: forming a first sacrificial spacer on a sidewall of the first gate structure; respectively, in a substrate on both sides of the first gate structure Forming an epitaxial layer; and removing the first sacrificial sidewall. The manufacturing method of claim 12, further comprising the step of forming a second sacrificial sidewall on the sidewall of the second gate structure, and the second sacrificial sidewall is before the first sacrificial sidewall is formed or Formed afterwards. The manufacturing method of claim 13, wherein the covering layer, the first sacrificial sidewall, and the second sacrificial sidewall are simultaneously removed. The manufacturing method of claim 12, wherein the covering layer is removed simultaneously with the first sacrificial sidewall. The manufacturing method of claim 15, further comprising the step of removing the cover layer and the first sacrificial sidewall: a sidewall of the first gate structure and the second gate structure Forming a second sidewall in each of the sidewalls; and forming a first source/drain and a second source/drain in the substrate on both sides of the first gate structure and the second gate structure. The manufacturing method of claim 12, wherein the covering layer is formed after removing the first sacrificial sidewall. The manufacturing method of claim 17, wherein the first ion implantation process is performed before forming the first sacrificial sidewall, and the second ion implantation process is performed after forming the mask layer. The manufacturing method of claim 18, further comprising removing the covering layer after performing the second ion implantation process. The manufacturing method of claim 19, further comprising the following steps, after removing the covering layer and the first sacrificial sidewall: the sidewall of the first gate structure and the second gate structure Forming a second sidewall in each of the sidewalls; and forming a first source/drain and a second source/drain in the substrate on both sides of the first gate structure and the second gate structure.