TW201330106A - Semiconductor process - Google Patents

Abstract

A semiconductor process includes the following steps. A substrate having a recess is provided. A decoupled plasma nitridation process is performed to nitride the surface of the recess for forming a nitrogen containing liner on the surface of the recess. A nitrogen containing annealing process is performed on the nitrogen containing liner.

Description

Semiconductor process

The present invention relates to a semiconductor process, and more particularly to a semiconductor process for forming a nitrogen-containing liner layer by a decoupled plasma nitridation process and a nitrogen-containing annealing process.

In the semiconductor manufacturing process, in order to have good isolation between the electronic components on the wafer to avoid short-circuit phenomenon caused by mutual interference of components, generally, localized oxidation isolation (LOCOS) or shallow trench isolation method is used. Isolation and protection. However, since the area of the wafer occupied by the field oxide generated in the LOCOS process is too large, and the generation process is accompanied by the bird's beak phenomenon, the current semiconductor having a line width of less than 0.25 micrometers (μm) is present. The process is almost always shallow trench isolation.

The shallow trench isolation method is to make a shallow trench between the components on the surface of the wafer and fill the insulating material to produce electrical isolation. Today's shallow trench isolation process, prior to filling the insulating material in the shallow trench, first forms an oxide on the sidewall of the shallow trench to further isolate the insulating material from the surface of the recess. However, as the size shrinks, the inverse narrow width effect (INWE) is more pronounced and the performance of the semiconductor device is seriously degraded. The inverse narrow width effect (INWE) is When the channel width is shortened, the threshold voltage of the transistor will decrease.

Therefore, the industry urgently needs a method to improve the above-mentioned negative effects to solve the bottleneck encountered in the shrinking size.

The present invention provides a semiconductor process that forms a nitrogen-containing liner layer by a decoupled plasma nitridation process and a nitrogen-containing annealing process to solve the above problems.

The present invention provides a semiconductor process comprising the steps described below. First, a substrate having a recess is provided. Next, a decoupled plasma nitridation process is performed to nitridize the surface of the recess to form a nitrogen-containing liner layer on the surface of the recess. Thereafter, a nitrogen-containing annealing process is performed on the nitrogen-containing liner layer.

Based on the above, the present invention provides a semiconductor process in which a decoupled plasma nitridation process is first performed to form a nitrogen-containing liner layer, and a nitrogen-containing annealing process is performed on the nitrogen-containing liner layer. In this way, the nitrogen-containing liner layer can effectively reduce the inverse narrow width effect (INWE) and improve the device performance. Furthermore, after performing the decoupling plasma nitridation process, a nitrogen-containing annealing process is performed on the nitrogen-containing liner layer, which can effectively increase the nitrogen concentration in the nitrogen-containing liner layer and simultaneously reduce the nitrogen concentration. The rate of decay of time.

1-7 are schematic cross-sectional views showing a semiconductor process according to a first embodiment of the present invention. As shown in Figures 1-2, a substrate 110 having a recess R is provided. In detail, as shown in FIG. 1, a substrate 110 is provided, wherein the substrate 110 is, for example, a germanium substrate, a germanium-containing substrate, a tri-five-layer germanium substrate (eg, GaN-on-silicon), and a graphene coating. A semiconductor substrate such as a graphene-on-silicon or a silicon-on-insulator (SOI) substrate. Next, a hard mask layer (not shown) is formed on the substrate 110 and patterned to form a patterned hard mask layer 120, wherein the method of forming the patterned hard mask layer 120 can be, for example, A method of etching lithography is used to form a patterned photoresist (not shown) on a hard mask layer (not shown), and the pattern of the photoresist (not shown) defines a recess corresponding to the underside thereof. The position of the slot R. Then, a hard mask layer (not shown) is patterned in a pattern of photoresist (not shown). In the present embodiment, the patterned hard mask layer 120 may include a pad oxide layer 122 on the substrate 110 and a pad nitride layer 124 on the pad oxide layer 122. Next, as shown in FIG. 2, the pattern of the hard mask layer 120 is transferred to the substrate 110 by etching or the like to form the recess R in the substrate 110.

As shown in FIG. 3, after the recess R is formed, the pad nitride layer 124 is etched back. In the present embodiment, the method of etching back the pad nitride layer 124 is, for example, a pull back process for exposing the apex angle of the groove R for subsequent nitriding to ensure the integrity of the apex angle, and The openings defined by the patterned hard mask layer 120 are enlarged to facilitate subsequent trenching processes. Since the apex angle of the filler filled in, for example, the shallow trench insulating structure is concentrated due to local stress, the apex angle is more likely to be lost in the subsequent etching or cleaning step, and a so-called top recess structure is formed. In the small line width process, the parasitic capacitance formed at the top recessed structure can significantly affect the element properties, and the retraction etching can avoid this phenomenon.

As shown in Fig. 4, a decoupling plasma nitridation process P1 is performed to nitride the surface S1 of the recess R to form a nitrogen-containing spacer layer 130 on the surface S1 of the recess R. Compared with the conventional, the nitrogen-containing liner layer 130 can effectively reduce the inverse narrow width effect (INWE) and improve the performance of components and devices such as MOS formed later. The decoupling plasma nitridation process P1 of the present embodiment is preferably performed at room temperature, but the invention is not limited thereto. In a preferred embodiment, the process time of the decoupled plasma nitridation process is 1 second to 10 minutes, the process temperature is 20 ° C to 600 ° C, and the plasma power is 1000 to 2000 watts. (Watt), and the pressure is 5~200 mTorr. In one embodiment, when the substrate 110 comprises a germanium substrate, the surface S1 of the germanium substrate is nitrided by the decoupling plasma nitridation process P1, so that the formed nitrogen-containing liner layer 130 comprises a nitride.矽 layer. In addition, before performing the decoupling plasma nitridation process P1, a pre-cleaning process (not shown) may be selectively performed to remove the etching residue, the native oxide layer or impurities, etc. of the surface S1 of the groove R. As such, the formed nitrogen-containing liner layer 130 can be made flatter and more uniform in structure. In an embodiment, the pre-cleaning process (not shown) may include a pre-cleaning process comprising dilute hydrofluoric acid and a standard cleaning solution (SC1), which is effective for cleaning impurities such as a native oxide layer.

As shown in FIG. 5, a nitrogen-containing annealing process P2 is subsequently performed on the nitrogen-containing liner layer 130. Since only the nitrogen-containing liner layer 130 formed by the decoupling plasma nitridation process P1 is performed, its nitrogen concentration rapidly decays with time. The uncertainty in this process may increase the process variables of the subsequent semiconductor process, and it is more difficult to control the quality of the formed semiconductor device. Moreover, when the nitrogen concentration is rapidly attenuated with time, the nitrogen-containing liner layer 130 formed by the present invention can effectively reduce the function of the inverse narrow width effect (INWE). Therefore, after the decoupling plasma nitridation process P1 is performed to form the nitrogen-containing liner layer 130, the nitrogen-containing annealing process P2 is further performed. Thus, on the one hand, the nitrogen concentration in the nitrogen-containing liner layer 130 can be slowed down rapidly, and on the other hand, the nitrogen concentration of the nitrogen-containing liner layer 130 can be increased, thereby increasing the nitrogen-containing liner layer 130. efficacy.

Figure 10 is a graph showing the relationship between the nitrogen concentration in the liner layer of the first embodiment of the present invention and the liner layer not subjected to the nitrogen-containing annealing process as a function of time, wherein the upper graph is for decoupling the plasma nitridation process P1 to form nitrogen. After the liner layer, the nitrogen concentration in the liner layer of the nitrogen-containing annealing process P2 is not changed with time; the following figure is to form the nitrogen-containing liner layer 130 by performing the decoupling plasma nitridation process P1. Thereafter, a graph of the relationship of the nitrogen concentration in the liner layer of the nitrogen-containing annealing process with time is performed. It can be seen from the above figure that only the nitrogen-containing liner layer formed by the decoupling plasma nitridation process P1 is attenuated by 0.61% after the first hour; however, as shown in the following figure, combined decoupling plasma nitridation The nitrogen-containing liner layer 130 formed by the process P1 and the nitrogen-containing annealing process P2 was only attenuated by 0,3% after the first hour. Next, as can be seen from the above figure, the nitrogen concentration is attenuated by 3.51% in the tenth hour after the formation of the nitrogen-containing underlayer; however, as shown in the following figure, the nitrogen concentration is only tenth after the formation of the nitrogen-containing liner layer 130. Attenuated by 2.51%. Furthermore, the relationship between the nitrogen concentration and the time curve of the graph below is shifted upward with respect to the nitrogen concentration of the above graph, so that the nitrogen concentration of the liner layer 130 of the nitrogen-containing annealing process P2 at each time is known. Both are higher than the liner layer of the nitrogen-free annealing process P2. In summary, in the present embodiment, after the formation of the nitrogen-containing liner layer 130, the nitrogen-containing annealing process P2 is performed, which can effectively increase the nitrogen concentration of the nitrogen-containing liner layer 130 and reduce the decay rate of the nitrogen concentration with time. .

In one embodiment, the nitrogen-containing annealing process P2 can be, for example, an annealing process for introducing nitrogen or an annealing process for introducing ammonia gas, but the invention is not limited thereto, and depends on actual needs and process environment. Furthermore, the annealing temperature of the nitrogen-containing annealing process P2 is preferably greater than 800 ° C, and the processing time of the nitrogen-containing annealing process P2 is preferably 10 to 60 seconds, with a sufficiently high temperature and a sufficiently long process time. , fully achieve the above process objectives. In the present invention, the nitrogen-containing annealing process P2 includes a rapid thermal processing process, but the invention is not limited thereto.

As shown in FIG. 6, after the nitrogen-containing annealing process P2 is performed on the nitrogen-containing liner layer 130, a dielectric material 140 is filled in the recess R. The material of the dielectric material 140 is, for example, an oxide, but the invention is not limited thereto. Next, a high temperature process P3 is performed to densify the dielectric material 140. Generally, the process temperature of the high-temperature process P3 is higher than 1000 ° C. In the embodiment, the process temperature of the high-temperature process P3 is 1050 ° C, so that the structure of the dielectric material 140 can be effectively made dense to achieve insulation. Etc., in turn, increases the electrical quality of the formed semiconductor structure.

As shown in FIG. 7, a polishing process P4 is performed to planarize the dielectric material 140 such that the top surface S2 is flush with the top surface S3 of the pad nitride layer 124, wherein the polishing process P4 is, for example, a chemical mechanical polishing (Chemical) Mechanical Polishing, CMP) process, but the invention is not limited thereto, and can be combined with other flattening processes. Then, the pad nitride layer 124 and the pad oxide layer 122 are sequentially removed.

The first embodiment of the present invention forms only a layer of nitrogen-containing liner layer 130. Here, a second embodiment is further provided which, after forming the nitrogen-containing liner layer 130, additionally forms a single or multi-layer liner. Floor.

8-9 are schematic cross-sectional views showing a semiconductor process of a second embodiment of the present invention. First, the previous stage process of the second embodiment of the present invention is the same as the first embodiment of the present invention. As shown in FIGS. 1-5, the steps include: providing a substrate 110; forming a patterned hard mask layer 120 on the substrate 110. The hard mask layer 120 may include a pad oxide layer 122 on the substrate 110 and the pad nitride layer 124 on the pad oxide layer 122; forming a recess R in the substrate 110; performing a decoupling plasma nitridation process P1, The surface S1 of the nitridation groove R forms a nitrogen-containing liner layer 130 on the surface S1 of the groove R; and a nitrogen-containing annealing process P3 is performed on the nitrogen-containing liner layer 130.

Similarly, the nitrogen-containing liner layer 130 of the present embodiment can effectively reduce the inverse narrow width effect (INWE) and improve device performance. The decoupled plasma nitridation process P1 is preferably carried out at room temperature, but the invention is not limited thereto. In a preferred embodiment, the process time of the decoupled plasma nitridation process P1 is 1 second to 10 minutes, the process temperature is 20 ° C to 600 ° C, and the plasma power is 1000 to 2000. Watt, and the pressure is 5~200 mTorr. However, since only the nitrogen-containing liner layer 130 formed by the decoupling plasma nitridation process P1 is performed, its nitrogen concentration rapidly decays with time. The uncertainty in this process increases the process variations of subsequent semiconductor processes and makes it difficult to control the quality of the formed semiconductor device. Moreover, when the nitrogen concentration is rapidly attenuated with time, the nitrogen-containing liner layer 130 formed by the present invention can effectively reduce the function of the inverse narrow width effect (INWE). Therefore, after the decoupling plasma nitridation process P1 is performed to form the nitrogen-containing liner layer 130, the nitrogen-containing liner layer 130 is further subjected to a nitrogen-containing annealing process P2. Thus, on the one hand, the nitrogen concentration in the nitrogen-containing liner layer 130 can be slowed down rapidly, and on the other hand, the nitrogen concentration of the nitrogen-containing liner layer 130 can be increased, thereby increasing the nitrogen-containing liner layer 130. efficacy.

Next, as shown in FIG. 8, after the nitrogen-containing annealing process P3 is performed on the nitrogen-containing liner layer 130, a second liner layer 150 is formed on the nitrogen-containing liner layer 130. The second liner layer 150 may include an oxide layer, an oxynitride layer, or even a combination of the two, etc., but the invention is not limited thereto. In this embodiment, a single layer or a plurality of second liner layers 150 are further formed than the first embodiment, which can effectively insulate the subsequently filled dielectric material 140 from the substrate 110 and achieve the purpose of insulation.

As shown in FIG. 9, the dielectric material 140 is filled and ground in the recess R such that the top surface S2 is flush with the top surface S3 of the pad nitride layer 124. In detail, a dielectric layer (not shown) may be first filled in the recess R. The material of the dielectric material is, for example, an oxide, but the invention is not limited thereto. Next, a high temperature process is performed to densify the dielectric material (not shown). Generally, the process temperature of the high temperature process is higher than 1000 ° C. In the present embodiment, the process temperature of the high temperature process is 1050 ° C, so that the structure of the dielectric material (not shown) is more effective and dense. Then, a polishing process is performed to form a planarized dielectric material 140, wherein the top surface S2 of the dielectric material 140 is flush with the top surface S3 of the pad nitride layer 124. The polishing process P4 is, for example, a chemical mechanical polishing (CMP) process, but the invention is not limited thereto. Finally, the pad nitride layer 124 and the pad oxide layer 122 are sequentially removed.

In summary, the present invention provides a semiconductor process in which a decoupled plasma nitridation process is performed to form a nitrogen-containing liner layer, and a nitrogen-containing annealing process is performed on the nitrogen-containing liner layer. In this way, the nitrogen-containing liner layer can effectively reduce the inverse narrow width effect (INWE) and improve the device performance. Furthermore, after performing the decoupling plasma nitridation process, a nitrogen-containing annealing process is performed on the nitrogen-containing liner layer, which can effectively increase the nitrogen concentration in the nitrogen-containing liner layer and simultaneously reduce the nitrogen concentration. The rate of decay of time. In a preferred embodiment, the decoupled plasma nitridation process is performed at room temperature. The nitrogen-containing annealing process may include an annealing process with a nitrogen gas or an annealing process with an ammonia gas. The annealing temperature of the nitrogen-containing annealing process is greater than 800 °C. In this way, the process efficiency of the present invention can be fully achieved by applying an appropriate temperature.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

110. . . Base

120. . . Hard mask layer

122. . . Pad oxide

124. . . Pad nitride layer

130. . . Nitrogen-containing liner

140. . . Dielectric material

150. . . Second liner layer

R. . . Groove

P1. . . Decoupling plasma nitridation process

P2. . . Nitrogen-containing annealing process

P3. . . High temperature process

P4. . . Grinding process

S1. . . surface

S2, S3. . . Top surface

1-7 are schematic cross-sectional views showing a semiconductor process according to a first embodiment of the present invention.

8-9 are schematic cross-sectional views showing a semiconductor process of a second embodiment of the present invention.

Fig. 10 is a graph showing the relationship between the nitrogen concentration in the liner layer of the first embodiment of the present invention and the liner layer not subjected to the nitrogen-containing annealing process with time.

110. . . Base

120. . . Hard mask layer

122. . . Pad oxide

124. . . Pad nitride layer

130. . . Nitrogen-containing liner

140. . . Dielectric material

R. . . Groove

P4. . . Grinding process

S1. . . surface

S2, S3. . . Top surface

Claims (18)

A semiconductor process comprising: providing a substrate having a recess; performing a decoupling plasma nitridation process, nitriding a surface of the recess to form a nitrogen-containing liner layer on a surface of the recess; And performing a nitrogen-containing annealing process on the nitrogen-containing liner layer. The semiconductor process of claim 1, wherein the decoupled plasma nitridation process is performed at room temperature. The semiconductor process of claim 1, wherein the process time of the decoupled plasma nitridation process is from 1 second to 10 minutes. The semiconductor process of claim 1, wherein the nitrogen-containing annealing process comprises an annealing process with a nitrogen gas. The semiconductor process of claim 1, wherein the nitrogen-containing annealing process comprises an annealing process for introducing ammonia gas. The semiconductor process of claim 1, wherein the nitrogen-containing annealing process has an annealing temperature greater than 800 °C. The semiconductor process of claim 1, wherein the nitrogen-containing annealing process has a process time of 10 to 60 seconds. The semiconductor process of claim 1, wherein the nitrogen-containing annealing process comprises a Rapid Thermal Processing process. The semiconductor process of claim 1, wherein after performing the nitrogen-containing annealing process on the nitrogen-containing liner layer, further comprising: forming an oxide layer on the nitrogen-containing liner layer. The semiconductor process of claim 1, after performing the nitrogen-containing annealing process on the nitrogen-containing liner layer, further comprising: forming an oxynitride layer on the nitrogen-containing liner layer. The semiconductor process of claim 1, wherein the step of providing the substrate having the recess comprises: providing the substrate; and forming the recess in the substrate. The semiconductor process of claim 11, wherein the step of forming the recess in the substrate comprises: forming a hard mask layer on the substrate; patterning the hard mask layer; and hardening the hard mask layer; A pattern of the mask layer is transferred to the substrate to form the recess in the substrate. The semiconductor process of claim 12, wherein the hard mask layer comprises a pad oxide layer on the substrate, and a pad nitride layer on the pad oxide layer. The semiconductor process of claim 13, wherein after forming the recess, the method further comprises: etching back the pad nitride layer. The semiconductor process of claim 1, wherein after the nitrogen-containing annealing process is performed on the nitrogen-containing liner layer, the method further comprises: filling a dielectric material in the recess; performing a high temperature process Densifying the dielectric material; and performing a polishing process to planarize the dielectric material. The semiconductor process of claim 1, wherein the substrate comprises a germanium substrate and the nitrogen-containing liner layer comprises a tantalum nitride layer. The semiconductor process of claim 1, wherein before performing the decoupling plasma nitridation process, the method further comprises: performing a pre-cleaning process to remove the native oxide layer and impurities on the surface of the recess. The semiconductor process of claim 17, wherein the pre-cleaning process comprises a pre-cleaning process comprising dilute hydrofluoric acid.