TW201322428A - Memory device and method of fabricating the same - Google Patents

Memory device and method of fabricating the same Download PDF

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TW201322428A
TW201322428A TW100143164A TW100143164A TW201322428A TW 201322428 A TW201322428 A TW 201322428A TW 100143164 A TW100143164 A TW 100143164A TW 100143164 A TW100143164 A TW 100143164A TW 201322428 A TW201322428 A TW 201322428A
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gate
extension
charge storage
layer
substrate
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TW100143164A
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TWI487094B (en
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Shih-Guei Yan
Wen-Jer Tsai
Chih-Chieh Cheng
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Macronix Int Co Ltd
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Abstract

A memory device including a gate, a gate dielectric and two charge storage layers is described. The gate is disposed on a substrate. The gate dielectric is disposed between the gate and the substrate. The width of the gate is greater than that of the gate dielectric, so that two gaps are present at both sides of the gate dielectric and between the gate and the substrate. Each charge storage layer includes a body portion in one of the gaps, a first extension portion connected with the body portion and protruding out of the corresponding sidewall of the gate, and a second extension portion connected to the first extension portion and extending along the sidewall of the gate, wherein an edge of the first extension portion protrudes from the sidewall of the second extension portion.

Description

記憶元件及其製造方法Memory element and method of manufacturing same

  本發明是有關於一種積體電路及其製造方法,且特別是有關於一種記憶元件及其製造方法。The present invention relates to an integrated circuit and a method of fabricating the same, and more particularly to a memory element and a method of fabricating the same.

  記憶體是用來儲存資訊或資料的半導體元件。隨著電腦微處理器的功能愈來愈強,藉軟體執行的程式與操作也隨之增加。因此,對於高容量記憶體的需求也逐漸增加。A memory is a semiconductor component used to store information or data. As computer microprocessors become more powerful, the programs and operations that are performed by software increase. Therefore, the demand for high-capacity memory is gradually increasing.

  在各種記憶體產品中,非揮發性記憶體允許多次的資料程式化、讀取及抹除操作,甚至在記憶體的電源中斷後還能保存儲存於其中的資料。由於這些優點,非揮發性記憶體已成為個人電腦與電子設備中廣泛使用的記憶體。Among various memory products, non-volatile memory allows multiple data stylization, reading and erasing operations, and even saves the data stored in the memory after the power is interrupted. Because of these advantages, non-volatile memory has become a widely used memory in personal computers and electronic devices.

  熟知的應用電荷儲存結構(charge storage structure)的可電程式化及抹除(electrically programmable and erasable)非揮發性記憶體技術,如電子可抹除可程式化唯讀記憶體(EEPROM)及快閃記憶體(flash 記憶體),已使用於各種現代化應用。快閃記憶體設計成具有記憶胞陣列,其可以獨立地程式化與讀取。一般的快閃記憶體記憶胞將電荷儲存於浮置閘。另一種快閃記憶體使用非導體材料所組成的電荷捕捉結構(charge -trapping structure),例如氮化矽,以取代浮置閘的導體材料。當電荷捕捉記憶胞被程式化時,電荷被捕捉且不會移動穿過非導體的電荷捕捉結構。在不持續供應電源時,電荷會一直保持在電荷捕捉層中,維持其資料狀態,直到記憶胞被抹除。電荷捕捉記憶胞可以被操做成為二端記憶胞(two-sided cell)。也就是說,由於電荷不會移動穿過非導體電荷捕捉層,因此電荷可位於不同的電荷捕捉處。換言之,電荷捕捉結構型的快閃記憶體元件中,在每一個記憶胞中可以儲存一個位元以上的資訊。Well-known electrically programmable and erasable non-volatile memory technologies such as electronic erasable programmable read-only memory (EEPROM) and flash memory using charge storage structures Memory (flash memory) has been used in a variety of modern applications. The flash memory is designed to have an array of memory cells that can be programmed and read independently. A typical flash memory cell stores charge in a floating gate. Another type of flash memory uses a charge-trapping structure of a non-conducting material, such as tantalum nitride, to replace the conductive material of the floating gate. When the charge trapping memory cell is programmed, the charge is captured and does not move through the non-conductor charge trapping structure. When the power supply is not continuously supplied, the charge remains in the charge trapping layer, maintaining its data state until the memory cells are erased. The charge trapping memory cell can be manipulated as a two-sided cell. That is, since the charge does not move through the non-conductor charge trapping layer, the charge can be located at a different charge trap. In other words, in the flash memory structure of the charge trapping structure type, information of more than one bit can be stored in each memory cell.

  任一記憶胞可被程式化,而在電荷捕捉結構中儲存二個完全分離的位元(以電荷分別集中靠近源極區與汲極區的方式)。記憶胞的程式化可利用通道熱電子注入,其在通道區產生熱電子。熱電子獲得能量而被捕捉在電荷捕捉結構中。將源極端與汲極端施加的偏壓互換,可將電荷捕捉至電荷捕捉結構的任一部分(近源極區、近汲極區或二者)。Any memory cell can be programmed, and two completely separate bits are stored in the charge trapping structure (in a manner where the charges are concentrated close to the source and drain regions, respectively). Stylization of memory cells can utilize channel hot electron injection, which produces hot electrons in the channel region. The hot electrons acquire energy and are captured in the charge trapping structure. Interchanging the source terminal with the bias applied by the 汲 extreme can capture charge to any portion of the charge trapping structure (near source region, near drain region, or both).

  通常,具電荷捕捉結構的記憶胞可儲存四種不同的位元組合(00、01、10與11),每一種有對應的啟始電壓。在讀取操作期間,流過記憶胞的電流因記憶胞的啟始電壓而不同。通常,此電流可具有四個不同的值,其中每一者對應於不同的啟始電壓。因此,藉由檢測此電流,可以判定儲存於記憶胞中的位元組合。Typically, a memory cell with a charge trapping structure can store four different combinations of bits (00, 01, 10, and 11), each having a corresponding starting voltage. During the read operation, the current flowing through the memory cells differs due to the starting voltage of the memory cells. Typically, this current can have four different values, each of which corresponds to a different starting voltage. Therefore, by detecting this current, the combination of bits stored in the memory cell can be determined.

  全部有效的電荷範圍或啟始電壓範圍可以歸類為記憶體操作裕度(memory operation window)。換言之,記憶體操作裕度藉由程式化位準(level)與抹除位準之間的差異來定義。由於記憶胞操作需要各種狀態之間的良好位準分離,因此需要大的記憶體操作裕度。然而,二位元記憶胞的效能通常隨著所謂「第二位元效應」而降低。在第二位元效應下,在電荷捕捉結構中定域化的電荷彼此互相影響。例如,在反向讀取期間,施加讀取偏壓至汲極端且檢測到儲存在靠近源極區的電荷(即第一位元)。然而,之後靠近汲極區的位元(即第二位元)產生讀取靠近源極區的第一位元的電位障。此能障可藉由施加適當的偏壓來克服,使用汲極感應能障降低(DIBL)效應來抑制靠近汲極區的第二位元的效應,且允許檢測第一位元的儲存狀態。然而,當靠近汲極區的第二位元被程式化至高啟始電壓狀態且靠近源極區的第一位元在未程式化狀態時,第二位元實質上提高了能障。因此,隨著關於第二位元的啟始電壓增加,第一位元的讀取偏壓已不足夠克服第二位元產生的電位障。因此,由於第二位元的啟始電壓增加,第一位元的啟始電壓提高,因而降低了記憶體操作裕度。第二位元效應減少了2位元記憶體的操作裕度。因此,亟需一種可以抑制記憶體元件中的第二位元效應的方法與元件。All valid charge ranges or starting voltage ranges can be classified as memory operating windows. In other words, the memory operation margin is defined by the difference between the programmed level and the erase level. Since memory cell operation requires good level separation between various states, a large memory operation margin is required. However, the performance of a two-dimensional memory cell generally decreases with the so-called "second bit effect." Under the second bit effect, the charges localized in the charge trapping structure interact with each other. For example, during a reverse read, a read bias is applied to the drain terminal and a charge stored near the source region (ie, the first bit) is detected. However, the bit (i.e., the second bit) that is then near the drain region produces a potential barrier that reads the first bit near the source region. This energy barrier can be overcome by applying an appropriate bias voltage, using the drain-induced energy barrier reduction (DIBL) effect to suppress the effect of the second bit near the drain region, and allowing the storage state of the first bit to be detected. However, when the second bit near the drain region is programmed to a high start voltage state and the first bit near the source region is in an unprogrammed state, the second bit substantially increases the energy barrier. Therefore, as the starting voltage with respect to the second bit increases, the read bias of the first bit is not sufficient to overcome the potential barrier generated by the second bit. Therefore, since the starting voltage of the second bit increases, the starting voltage of the first bit increases, thereby reducing the memory operating margin. The second bit effect reduces the operating margin of the 2-bit memory. Therefore, there is a need for a method and component that can suppress the second bit effect in a memory component.

本發明提供一種記憶元件,其可以提供定位的電荷儲存區域,以使電荷可以完全定位化儲存,減少第二位元效應,減少程式化干擾的行為,並且可以減少短通道效應。The present invention provides a memory element that can provide a positioned charge storage region such that charge can be fully localized, reduced second bit effect, reduced stylized interference behavior, and reduced short channel effects.

本發明提供一種記憶元件的製造方法,其可以透過簡單的製程使得所製造的記憶元件可以提供定位的電荷儲存區域,以使電荷可以完全定位化儲存,得到較佳的第二位元,減少程式化干擾的行為,並且可以減少短通道效應。The invention provides a method for manufacturing a memory element, which can make a memory storage component can provide a positioned charge storage area through a simple process, so that the charge can be completely positioned and stored, thereby obtaining a better second bit and reducing the program. Interacting behavior and reducing short-channel effects.

本發明提出一種記憶元件,包括閘極、閘介電層以及二電荷儲存層。閘極位於基底上。閘介電層位於上述閘極與基底之間。在上述閘介電層兩側、閘極下方及基底上方具有一空隙。上述各電荷儲存層包括主體部、第一延伸部與一第二延伸部。各主體部位於上述各空隙中。各第一延伸部與上述主體部連接並且突出於上述閘極之側壁。各第二延伸部與所對應的該第一延伸部的連接,且向上延伸至該閘極側壁,其中該第一延伸部的邊緣區域突出於所對應的各該第二延伸部之側壁。The invention provides a memory element comprising a gate, a gate dielectric layer and a two charge storage layer. The gate is located on the substrate. A gate dielectric layer is between the gate and the substrate. There is a gap on both sides of the gate dielectric layer, below the gate and above the substrate. Each of the charge storage layers includes a body portion, a first extension portion and a second extension portion. Each body portion is located in each of the above spaces. Each of the first extensions is coupled to the body portion and protrudes from a sidewall of the gate. The second extension portion is connected to the corresponding first extension portion and extends upward to the gate sidewall, wherein an edge region of the first extension portion protrudes from a sidewall of each of the corresponding second extension portions.

依照本發明一實施例所述,上述主體部、上述第一延伸部以及上述第二延伸部之材質相同。According to an embodiment of the invention, the main body portion, the first extending portion, and the second extending portion are made of the same material.

依照本發明一實施例所述,上述記憶元件更包括二摻雜區,位於閘極兩側的上述基底中,其中上述各電荷儲存層的第一延伸部與第二延伸部位於所對應的摻雜區上方。According to an embodiment of the invention, the memory device further includes two doped regions, the substrate on both sides of the gate, wherein the first extension and the second extension of each of the charge storage layers are located in the corresponding doping Above the miscellaneous area.

依照本發明一實施例所述,上述記憶元件更包括二襯層與二間隙壁。上述二襯層分別位於閘極與各電荷儲存層的第二延伸部之間。上述二間隙壁位於上述第一延伸部上方,分別使上述第二延伸部夾於對應的襯層與間隙壁之間。According to an embodiment of the invention, the memory element further includes a second liner and two spacers. The two liner layers are respectively located between the gate and the second extension of each of the charge storage layers. The two gap walls are located above the first extension portion, and the second extension portion is sandwiched between the corresponding liner layer and the gap wall.

依照本發明一實施例所述,上述主體部的長度與上述第一延伸部的長度比值為2:1至5:1。According to an embodiment of the invention, the ratio of the length of the main body portion to the length of the first extension portion is 2:1 to 5:1.

本發明提出一種記憶元件,包括閘極、閘介電層、二電荷儲存層及二襯層。閘極位於基底上。閘介電層位於閘極與基底之間。在上述閘介電層兩側、閘極下方及基底上方具有一空隙。上述各電荷儲存層包括主體部與延伸部。各主體部位於上述空隙中。各延伸部與上述主體部連接並且突出於閘極之側壁。各襯層位於閘極的側壁,且各電荷儲存層的延伸部的邊緣區域突出於襯層的側壁。The invention provides a memory element comprising a gate, a gate dielectric layer, a two-charge storage layer and a second liner. The gate is located on the substrate. The gate dielectric layer is between the gate and the substrate. There is a gap on both sides of the gate dielectric layer, below the gate and above the substrate. Each of the above charge storage layers includes a body portion and an extension portion. Each body portion is located in the above gap. Each of the extensions is coupled to the body portion and protrudes from a sidewall of the gate. Each of the lining layers is located on a sidewall of the gate, and an edge region of the extension of each of the charge storage layers protrudes from a sidewall of the lining.

依照本發明一實施例所述,上述主體部及上述延伸部之材質相同。According to an embodiment of the invention, the body portion and the extension portion are made of the same material.

依照本發明一實施例所述,上述記憶元件更包括二摻雜區,位於閘極兩側的上述基底中,其中上述各電荷儲存層的上述延伸部延伸至所對應的上述摻雜區上方。According to an embodiment of the invention, the memory device further includes a doped region in the substrate on both sides of the gate, wherein the extension of each of the charge storage layers extends above the corresponding doped region.

依照本發明一實施例所述,上述主體部的長度與上述延伸部的長度比值為2:1至5:1。According to an embodiment of the invention, the ratio of the length of the main body portion to the length of the extension portion is 2:1 to 5:1.

本發明還提出一種記憶元件,包括閘極、閘介電層、二電荷儲存層及二摻雜區。閘極位於基底上。閘介電層位於閘極與基底之間。在上述閘介電層兩側、閘極下方及基底上方具有一空隙。上述各電荷儲存層包括主體部與延伸部。各主體部位於上述空隙中。各延伸部與上述主體部連接並且突出於上述閘極之側壁。各摻雜區位於閘極兩側的基底中,各電荷儲存層的延伸部延伸到對應的摻雜區上方。The invention also provides a memory element comprising a gate, a gate dielectric layer, a two charge storage layer and a second doped region. The gate is located on the substrate. The gate dielectric layer is between the gate and the substrate. There is a gap on both sides of the gate dielectric layer, below the gate and above the substrate. Each of the above charge storage layers includes a body portion and an extension portion. Each body portion is located in the above gap. Each of the extensions is coupled to the body portion and protrudes from a sidewall of the gate. Each of the doped regions is located in a substrate on both sides of the gate, and an extension of each of the charge storage layers extends above the corresponding doped region.

依照本發明一實施例所述,上述主體部及延伸部之材質相同。According to an embodiment of the invention, the body portion and the extension portion are made of the same material.

依照本發明一實施例所述,上述主體部的長度與上述延伸部的長度比值為2:1至5:1。According to an embodiment of the invention, the ratio of the length of the main body portion to the length of the extension portion is 2:1 to 5:1.

本發明提出一種記憶元件的製造方法,包括:於基底上形成閘介電層以及閘介電層上的閘極,其中在閘介電層兩側、閘極下方及基底上方形成一空隙。之後形成二電荷儲存層,各電荷儲存層包括主體部與第一延伸部,其中各主體部位於上述空隙中,各第一延伸部與各主體部連接並且突出於閘極之側壁。於閘極兩側的基底中形成二摻雜區,各電荷儲存層的第一延伸部延伸到對應的摻雜區上方。The invention provides a method for fabricating a memory device, comprising: forming a gate dielectric layer on a substrate and a gate on the gate dielectric layer, wherein a gap is formed on both sides of the gate dielectric layer, below the gate and above the substrate. A second charge storage layer is then formed, each charge storage layer comprising a body portion and a first extension, wherein each body portion is located in the gap, each first extension being connected to each body portion and protruding from a sidewall of the gate. Two doped regions are formed in the substrate on both sides of the gate, and the first extension of each charge storage layer extends above the corresponding doped region.

依照本發明一實施例所述,上述記憶元件製造方法中各電荷儲存層更包括第二延伸部,各第二延伸部與上述第一延伸部連接,且向上延伸至閘極側壁,其中第一延伸部的邊緣區域突出於對應的第二延伸部之側壁。According to an embodiment of the present invention, each of the charge storage layers further includes a second extension portion, each of the second extension portions is coupled to the first extension portion and extends upward to the gate sidewall, wherein the first An edge region of the extension protrudes from a sidewall of the corresponding second extension.

依照本發明一實施例所述,上述記憶元件的製造方法中,上述各電荷儲存層的上述第一延伸部與上述第二延伸部位於所對應的上述摻雜區上方。According to an embodiment of the invention, in the method of manufacturing the memory device, the first extension portion and the second extension portion of each of the charge storage layers are located above the corresponding doped region.

依照本發明一實施例所述,上述記憶元件的製造方法,在形成上述電荷儲存層之前,更包括形成一襯材料層,覆蓋上述基底的表面、閘介電層之側壁、閘極之底部、側壁及上表面,上述各電荷儲存層的第一延伸部的邊緣區域突出於閘極側壁的襯材料層。According to an embodiment of the present invention, the method for fabricating the memory device further includes forming a liner material layer covering the surface of the substrate, the sidewall of the gate dielectric layer, and the bottom of the gate before forming the charge storage layer. The side wall and the upper surface, the edge region of the first extension portion of each of the charge storage layers protrudes from the lining material layer of the gate sidewall.

依照本發明一實施例所述,上述記憶元件的製造方法,包括形成電荷儲存材料層覆蓋上述襯材料層且填滿上述空隙,接著形成間隙壁材料層覆蓋上述電荷儲存材料層。之後,非等向蝕刻移除上述襯材料層、電荷儲存材料層及間隙壁材料層,以裸露出上述閘極以及基底之表面,留下上述襯層、電荷儲存層及二間隙壁。According to an embodiment of the present invention, a method of fabricating the memory device includes forming a layer of a charge storage material covering the liner material layer and filling the voids, and then forming a spacer material layer covering the charge storage material layer. Thereafter, the lining material layer, the charge storage material layer and the spacer material layer are removed by the non-isotropic etching to expose the gate and the surface of the substrate, leaving the lining layer, the charge storage layer and the second spacer.

依照本發明一實施例所述,上述記憶元件的製造方法,更包括於上述閘極的側壁形成一襯層,其中上述各電荷儲存層的上述第一延伸部突出於上述襯層的側壁。According to an embodiment of the present invention, the method of manufacturing the memory device further includes forming a liner on a sidewall of the gate, wherein the first extension of each of the charge storage layers protrudes from a sidewall of the liner.

本發明之記憶元件,其可以提供定位的電荷儲存區域,以使電荷可以完全定位化儲存,減少第二位元效應,減少程式化干擾的行為,並且可以減少短通道效應。The memory element of the present invention can provide a positioned charge storage area to allow charge to be fully localized, reduce second bit effect, reduce stylized interference behavior, and reduce short channel effects.

本發明之記憶元件的製造方法,其可以透過簡單的製程使得所製造的記憶元件可以提供定位的電荷儲存區域,以使電荷可以完全定位化儲存,得到較佳的第二位元,減少程式化干擾的行為,並且可以減少短通道效應。The manufacturing method of the memory element of the invention can make the fabricated memory element provide a positioned charge storage area through a simple process, so that the charge can be completely positioned and stored, thereby obtaining a better second bit and reducing stylization. Interfering behavior and can reduce short-channel effects.

為讓本發明之上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.

圖1至圖7是依照本發明實施例所繪示的一種記憶元件的製造方法的剖面示意圖。1 to 7 are schematic cross-sectional views showing a method of fabricating a memory device according to an embodiment of the invention.

請參照圖1,本發明之記憶元件的製造方法,係於基底10上形成閘介電層12,接著,於閘介電層12上形成閘極導體層14。基底10之材質例如是半導體,例如是矽,或者絕緣層上有矽(SOI)。基底10的材料也可以是其他的化合物半導體。閘介電層12之材質例如是氧化矽,或其他適合用來製作閘介電層的材料。閘介電層12的形成方法例如是熱氧化法,或是化學氣相沉積法,或其他合適的方法。閘極導體層14的材質例如是摻雜多晶矽。閘極導體層14之形成方法例如是利用化學氣相沈積法形成未摻雜多晶矽層後,進行離子植入步驟以形成之。閘極導體層14之形成方法也可以是利用化學氣相沈積法形成多晶矽層並在臨場進行摻雜。之後,在閘極導體層14上形成圖案化的硬罩幕層16以及圖案化的罩幕層18。圖案化的硬罩幕層16之材質例如是APF,形成的方法例如是化學氣相沉積法。圖案化的罩幕層18之材質例如是光阻。罩幕層18的圖案可以經由曝光與顯影的方式形成。硬罩幕層16的圖案則可以透過蝕刻製程將罩幕層18的圖案向下轉移而成。Referring to FIG. 1, a method of fabricating a memory device of the present invention is to form a gate dielectric layer 12 on a substrate 10, and then a gate conductor layer 14 is formed on the gate dielectric layer 12. The material of the substrate 10 is, for example, a semiconductor such as germanium or a germanium (SOI) on the insulating layer. The material of the substrate 10 may also be other compound semiconductors. The material of the gate dielectric layer 12 is, for example, tantalum oxide or other material suitable for use in fabricating the gate dielectric layer. The method of forming the gate dielectric layer 12 is, for example, a thermal oxidation method, or a chemical vapor deposition method, or other suitable method. The material of the gate conductor layer 14 is, for example, doped polysilicon. The method of forming the gate conductor layer 14 is, for example, forming an undoped polysilicon layer by chemical vapor deposition, and then performing an ion implantation step to form it. The gate conductor layer 14 may be formed by a chemical vapor deposition method to form a polysilicon layer and doping in the field. Thereafter, a patterned hard mask layer 16 and a patterned mask layer 18 are formed on the gate conductor layer 14. The material of the patterned hard mask layer 16 is, for example, APF, and the method of formation is, for example, chemical vapor deposition. The material of the patterned mask layer 18 is, for example, a photoresist. The pattern of the mask layer 18 can be formed by exposure and development. The pattern of the hard mask layer 16 can be formed by transferring the pattern of the mask layer 18 downward through an etching process.

之後,請參照圖2,以罩幕層18與硬罩幕層16為罩幕,基底10為蝕刻終止層,進行蝕刻製程,以將閘極導體層14圖案化為閘極14a,並繼續圖案化閘介電層12。所採用的蝕刻製程例如是非等向性蝕刻製程。非等向性蝕刻製程例如是電漿蝕刻製程。之後,將圖案化的罩幕層18以及硬罩幕層16移除。Thereafter, referring to FIG. 2, the mask layer 18 and the hard mask layer 16 are used as a mask, and the substrate 10 is an etch stop layer, and an etching process is performed to pattern the gate conductor layer 14 into the gate 14a, and continue the pattern. The dielectric layer 12 is turned on. The etching process employed is, for example, an anisotropic etching process. The anisotropic etching process is, for example, a plasma etching process. Thereafter, the patterned mask layer 18 and the hard mask layer 16 are removed.

其後,請參照圖3,對閘介電層12進行等向性蝕刻製程,以移除部分的閘介電層12,即於閘極14a下方產生底切,而形成凹槽20,此凹槽20係做為定位儲存空間(local storage space)。Thereafter, referring to FIG. 3, the gate dielectric layer 12 is subjected to an isotropic etching process to remove a portion of the gate dielectric layer 12, that is, an undercut is formed under the gate 14a to form a recess 20, which is recessed. The slot 20 is used as a local storage space.

繼之,請參照圖4,形成襯材料層22,覆蓋閘極14a的上表面、側壁與底部、閘介電層12的側壁以及基底10的表面。在一實施例中,襯材料層22共形覆蓋閘極14a的上表面、側壁與底部、閘介電層12的側壁以及基底10的表面。襯材料層22填入於圖3所示的凹槽20之中,但未填滿凹槽20,而留有空隙20a(圖4)。襯材料層22之材質例如是氧化矽,形成的方法例如是熱氧化法、臨場蒸氣產生(ISSG)氧化法、化學氣相沉積法(CVD)、原子層沉積法或爐管氧化法。Next, referring to FIG. 4, a liner material layer 22 is formed covering the upper surface of the gate 14a, the sidewalls and the bottom, the sidewalls of the gate dielectric layer 12, and the surface of the substrate 10. In one embodiment, the liner layer 22 conformally covers the upper surface of the gate 14a, the sidewalls and the bottom, the sidewalls of the gate dielectric layer 12, and the surface of the substrate 10. The lining material layer 22 is filled in the groove 20 shown in Fig. 3, but does not fill the groove 20, leaving a void 20a (Fig. 4). The material of the lining material layer 22 is, for example, ruthenium oxide, and is formed by, for example, thermal oxidation, on-site vapor generation (ISSG) oxidation, chemical vapor deposition (CVD), atomic layer deposition, or furnace tube oxidation.

之後,請參照圖5,形成電荷儲存材料層24’,覆蓋閘極14a上表面、側壁以及基底10上方的襯材料層22之表面並且填入於空隙20a之中。電荷儲存材料層24’之材質例如是氮化矽或是摻雜多晶矽。氮化矽的形成方法例如是爐管沉積法、化學氣相沉積法或原子層沉積法。摻雜多晶矽之形成方法例如是利用化學氣相沈積法形成多晶矽層並在臨場進行摻雜。Thereafter, referring to Fig. 5, a charge storage material layer 24' is formed covering the upper surface of the gate 14a, the side walls, and the surface of the liner material layer 22 above the substrate 10 and filled in the voids 20a. The material of the charge storage material layer 24' is, for example, tantalum nitride or doped polysilicon. The method of forming tantalum nitride is, for example, a furnace tube deposition method, a chemical vapor deposition method, or an atomic layer deposition method. The method of forming the doped polysilicon is, for example, forming a polycrystalline germanium layer by chemical vapor deposition and doping in the presence.

之後,在電荷儲存材料層24’上形成間隙壁材料層26,覆蓋閘極14a上表面、側壁以及基底10上方的電荷儲存材料層24’。在一實施例中,間隙壁材料層26共形閘極14a上表面、側壁以及基底10上方的電荷儲存材料層24’。間隙壁材料層26之材質例如是氧化矽,形成的方法例如是爐管氧化法、化學氣相沉積法或高溫熱氧化法(HTO)。Thereafter, a spacer material layer 26 is formed over the charge storage material layer 24', covering the upper surface of the gate 14a, the sidewalls, and the charge storage material layer 24' above the substrate 10. In one embodiment, the spacer material layer 26 conforms to the upper surface of the gate 14a, the sidewalls, and the charge storage material layer 24' above the substrate 10. The material of the spacer material layer 26 is, for example, ruthenium oxide, and the formation method is, for example, a furnace tube oxidation method, a chemical vapor deposition method, or a high temperature thermal oxidation method (HTO).

其後,請參照圖6,非等向性蝕刻間隙壁材料層26、電荷儲存材料層24’及襯材料層22,裸露出閘極14a及基底10的表面。留下的電荷儲存材料層24’作為電荷儲存層24,其包括主體部24a、第一延伸部24b及第二延伸部24c。各主體部24a位於空隙20a之中。第一延伸部24b與主體部24a連接並且突出於閘極14a側壁。第二延伸部24c位於閘極14a的側壁,且向下延伸至與第一延伸部24b連接,使得第一延伸部24b的邊緣區域突出於所對應的第二延伸部24c之側壁。Thereafter, referring to Fig. 6, the spacer material layer 26, the charge storage material layer 24', and the liner layer 22 are anisotropically etched to expose the surfaces of the gate 14a and the substrate 10. The remaining charge storage material layer 24' serves as a charge storage layer 24 including a body portion 24a, a first extension portion 24b, and a second extension portion 24c. Each body portion 24a is located in the gap 20a. The first extension portion 24b is connected to the main body portion 24a and protrudes from the side wall of the gate electrode 14a. The second extension portion 24c is located at a side wall of the gate electrode 14a and extends downward to be connected to the first extension portion 24b such that an edge region of the first extension portion 24b protrudes from a sidewall of the corresponding second extension portion 24c.

留下的襯材料層22包括三部分22a、22b、22c。襯材料層22的第一部分22a位於電荷儲存層24與基底10之間,作為穿隧介電層22a。襯材料層22的第二部分22b位於閘極14a下方,夾於閘極14a與電荷儲存層24的主體部24a之間,作為頂介電層22b。襯材料層22的第三部分22c位於閘極14a的側壁,夾於閘極14a與電荷儲存層24的第二延伸部24c之間,作為襯層22c。留下的間隙壁材料層作為間隙壁26a,位於電荷儲存層24的第一延伸部24b上方以及第二延伸部24c的側壁。The remaining lining material layer 22 includes three portions 22a, 22b, 22c. A first portion 22a of the liner layer 22 is positioned between the charge storage layer 24 and the substrate 10 as a tunneling dielectric layer 22a. The second portion 22b of the lining material layer 22 is located below the gate 14a and sandwiched between the gate 14a and the body portion 24a of the charge storage layer 24 as the top dielectric layer 22b. The third portion 22c of the lining material layer 22 is located on the sidewall of the gate 14a and sandwiched between the gate 14a and the second extension 24c of the charge storage layer 24 as a liner 22c. The remaining spacer material layer acts as a spacer 26a above the first extension 24b of the charge storage layer 24 and the sidewall of the second extension 24c.

之後進行離子植入,在基底10中形成摻雜區28、30。摻雜區28、30中植入的摻雜的導電型相同,且與基底10的導電型不同。在一實施例中,基底10有P型摻雜;摻雜區28、30有N型摻雜。另一實施例中,基底10有N型摻雜;摻雜區28、30有P型摻雜。N型摻雜例如是磷或砷;P型摻雜例如是硼或二氟化硼。摻雜區28、30可作為記憶體的源極區或汲極區。摻雜區28、30位於閘極14a兩側的基底10中,其中各電荷儲存層24的第一延伸部24b與第二延伸部24c位於所對應的摻雜區28、30上方。Ion implantation is then performed to form doped regions 28, 30 in substrate 10. The doped conductivity types implanted in the doped regions 28, 30 are the same and are different from the conductivity type of the substrate 10. In one embodiment, substrate 10 is P-doped; doped regions 28, 30 are N-doped. In another embodiment, substrate 10 is N-doped; doped regions 28, 30 are P-doped. The N-type doping is, for example, phosphorus or arsenic; the P-type doping is, for example, boron or boron difluoride. The doped regions 28, 30 can serve as the source or drain regions of the memory. The doped regions 28, 30 are located in the substrate 10 on both sides of the gate 14a, wherein the first extension 24b and the second extension 24c of each charge storage layer 24 are located above the corresponding doped regions 28, 30.

然後,請參照圖7,在基底10上形成介電層32。介電層32填入相鄰兩個閘極14a之間的空隙且具有平坦的表面,裸露出閘極14a之表面。介電層32的材質例如是氧化矽,形成的方法例如是利用化學氣相沉積法形成介電材料層,之後,再進行平坦化製程。平坦化製程例如是回蝕刻製程或是化學機械研磨製程(CMP)。Then, referring to FIG. 7, a dielectric layer 32 is formed on the substrate 10. Dielectric layer 32 fills the gap between adjacent two gates 14a and has a flat surface that exposes the surface of gate 14a. The material of the dielectric layer 32 is, for example, ruthenium oxide. The method of forming is, for example, forming a dielectric material layer by chemical vapor deposition, and then performing a planarization process. The planarization process is, for example, an etch back process or a chemical mechanical polishing process (CMP).

其後,在介電層32上方形成字元線34。字元線34的材質為導體材料,其與閘極14a電性連接。在一實施例中,字元線34延伸的方向與摻雜區28、30延伸的方向不同,例如是兩者大致呈垂直。字元線34的形成的方法例如是形成導體材料層之後,進行微影與蝕刻製程。導體材料例如是摻雜多晶矽、金屬、金屬合金或是其組合。摻雜多晶矽之形成方法例如是利用化學氣相沈積法形成未摻雜多晶矽層後,進行離子植入步驟以形成之。摻雜多晶矽之形成方法也可以是利用化學氣相沈積法形成多晶矽層並在臨場進行摻雜。金屬或金屬合金的形成方法例如是濺鍍法或是化學氣相沉積法,或其他合適的方法。Thereafter, a word line 34 is formed over the dielectric layer 32. The material of the word line 34 is a conductor material that is electrically connected to the gate 14a. In one embodiment, the direction in which word lines 34 extend is different from the direction in which doped regions 28, 30 extend, such as being substantially vertical. The method of forming the word line 34 is, for example, a lithography and etching process after forming a layer of a conductor material. The conductor material is, for example, doped polysilicon, metal, metal alloy or a combination thereof. The method of forming the doped polysilicon is, for example, forming an undoped polysilicon layer by chemical vapor deposition, and then performing an ion implantation step to form it. The method of forming the doped polysilicon may also be to form a polysilicon layer by chemical vapor deposition and dope in the field. The metal or metal alloy is formed by, for example, sputtering or chemical vapor deposition, or other suitable methods.

請參照圖7,本發明實施例之記憶元件包括閘極14a、閘介電層12、兩個電荷儲存層24、摻雜區28、30以及字元線34。Referring to FIG. 7, the memory device of the embodiment of the present invention includes a gate 14a, a gate dielectric layer 12, two charge storage layers 24, doped regions 28, 30, and word lines 34.

閘極14a位於基底10上。閘介電層12位於閘極14a與基底10之間。閘介電層12的寬度小於閘極14a,而在在閘介電層12兩側,閘極14a下方以及基底10上方各具有空隙20a。The gate 14a is located on the substrate 10. The gate dielectric layer 12 is between the gate 14a and the substrate 10. The gate dielectric layer 12 has a width smaller than the gate 14a, and has a gap 20a on both sides of the gate dielectric layer 12, below the gate 14a, and above the substrate 10.

電荷儲存層24與閘介電層12之材質不相同。各電荷儲存層24包括主體部24a、第一延伸部24b與第二延伸部24c。各主體部24a位於空隙20a中。各第一延伸部24b與各主體部24a連接並且突出於閘極14a之側壁。第二延伸部24c與所對應的第一延伸部24b連接,且向上延伸至閘極14a的側壁。換言之,第一延伸部24b的邊緣區域突出於所對應的第二延伸部24c之側壁,其剖面成反T型。主體部24a的長度L1太短將造成程式化效率的限制。主體部24a的長度L1愈長,其程式化的速度愈快,但第二位元效應影響較大。第一延伸部24b的長度愈長,愈不受閘極的控制,因此,第二位元效應的影響較小,但是,仍可以改善程式化的速度。主體部24a的長度L1例如是50埃至150埃;第一延伸部24b的長度L2例如是10埃至75埃。在一實施例中,主體部24a的長度L1與第一延伸部24b的長度L2的比值約為2:1至5:1。主體部24a、第一延伸部24b以及第二延伸部24c之材質相同。The material of the charge storage layer 24 and the gate dielectric layer 12 are different. Each of the charge storage layers 24 includes a body portion 24a, a first extension portion 24b, and a second extension portion 24c. Each body portion 24a is located in the gap 20a. Each of the first extending portions 24b is connected to each of the main body portions 24a and protrudes from the side wall of the gate electrode 14a. The second extension 24c is coupled to the corresponding first extension 24b and extends up to the sidewall of the gate 14a. In other words, the edge region of the first extension portion 24b protrudes from the side wall of the corresponding second extension portion 24c, and its cross section is inverted T-shaped. The length L1 of the main body portion 24a is too short to cause a limitation in stylized efficiency. The longer the length L1 of the main body portion 24a, the faster the stylization speed is, but the second bit effect is greatly affected. The longer the length of the first extension 24b is, the more it is not controlled by the gate, so the influence of the second bit effect is small, but the speed of stylization can still be improved. The length L1 of the main body portion 24a is, for example, 50 angstroms to 150 angstroms; and the length L2 of the first extending portion 24b is, for example, 10 angstroms to 75 angstroms. In one embodiment, the ratio of the length L1 of the body portion 24a to the length L2 of the first extension portion 24b is about 2:1 to 5:1. The main body portion 24a, the first extending portion 24b, and the second extending portion 24c are made of the same material.

穿隧介電層22a位於電荷儲存層24與基底10之間。頂介電層22b位於閘極14a下方,夾於閘極14a與電荷儲存層24的主體部24a之間。襯層22c位於閘極14a的側壁,夾於閘極14a與電荷儲存層24的第二延伸部24c之間。間隙壁26a位於電荷儲存層24的第一延伸部24b上方以及第二延伸部24c的側壁。在一實施例中,穿隧介電層22a、頂介電層22b、襯層22c以及間隙壁26a之材質與電荷儲存層24之材質不同。The tunneling dielectric layer 22a is located between the charge storage layer 24 and the substrate 10. The top dielectric layer 22b is located under the gate 14a and is sandwiched between the gate 14a and the body portion 24a of the charge storage layer 24. The lining layer 22c is located on the sidewall of the gate 14a and is sandwiched between the gate 14a and the second extension 24c of the charge storage layer 24. The spacer 26a is located above the first extension 24b of the charge storage layer 24 and the sidewall of the second extension 24c. In one embodiment, the material of the tunnel dielectric layer 22a, the top dielectric layer 22b, the liner layer 22c, and the spacers 26a is different from the material of the charge storage layer 24.

摻雜區28、30中的摻雜的導電型與基底10的導電型不同。摻雜區28、30位於閘極14a兩側的基底10中,且各電荷儲存層24的第一延伸部24b與第二延伸部24c位於所對應的摻雜區28、30上方。摻雜區28、30中所植入的摻雜的導電型相同,且與基底10的導電型不同。The doped conductivity type in the doped regions 28, 30 is different from the conductivity type of the substrate 10. The doped regions 28, 30 are located in the substrate 10 on both sides of the gate 14a, and the first extensions 24b and the second extensions 24c of the respective charge storage layers 24 are located above the corresponding doped regions 28, 30. The doped conductivity types implanted in the doped regions 28, 30 are the same and are different from the conductivity type of the substrate 10.

圖8繪示三種不同的記憶元件進行程式化時的程式化速度與汲極偏壓的關係圖。Figure 8 is a graph showing the relationship between the stylized speed and the gate bias voltage when three different memory elements are programmed.

請參照圖8,曲線100為依照本發明上述圖7實施例之電荷儲存層24(包括主體部24a、第一延伸部24b與第二延伸部24c,反T型)之記憶元件進行程式化的結果。曲線200為圖9之習知一種電荷儲存層24僅包括主體部24a之記憶元件進行程式化的結果。曲線300為圖10之習知一種電荷儲存層24僅包括第一延伸部24b與第二延伸部24c,之 L型記憶元件進行程式化的結果。由圖8的結果顯示,曲線100,在施加相同的汲極電壓進行程式化時,電荷儲存層呈反T型之記憶元件,具有較高的程式化位元啟始電壓變化率(dVt),即程式化的速度較快。 綜上所述,本發明之記憶元件,其可以提供定位的電荷儲存區域,以使電荷可以完全定位化儲存,減少第二位元效應,減少程式化干擾的行為,並且可以減少短通道效應。此外,本發明之記憶元件的製造方法,其製程簡單。Referring to FIG. 8, a curve 100 is a memory element of the memory storage layer 24 (including the main body portion 24a, the first extension portion 24b and the second extension portion 24c, the inverse T-type) of the embodiment of FIG. 7 according to the present invention. result. Curve 200 is the result of a conventional memory storage layer 24 of FIG. 9 that includes only the memory elements of body portion 24a. The curve 300 is the result of the conventional charge storage layer 24 of FIG. 10 including only the first extension 24b and the second extension 24c, and the L-shaped memory element is programmed. From the results of FIG. 8, it is shown that the curve 100, when the same gate voltage is applied for programming, the charge storage layer is an inverse T-type memory element having a high programmed bit start voltage change rate (dVt). That is, the stylization speed is faster. In summary, the memory element of the present invention can provide a positioned charge storage area to allow charge to be fully localized, reduce second bit effect, reduce stylized interference behavior, and reduce short channel effects. Further, the method of manufacturing the memory element of the present invention has a simple process.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10...基底10. . . Base

12...閘介電層12. . . Gate dielectric layer

14...閘極導體層14. . . Gate conductor layer

14a...閘極14a. . . Gate

16...圖案化的硬罩幕層16. . . Patterned hard mask layer

18...圖案化的罩幕層18. . . Patterned mask layer

20...凹槽20. . . Groove

20a...空隙20a. . . Void

22...襯材料層twenty two. . . Lining material layer

22a...第一部分/穿隧介電層22a. . . First part / tunneling dielectric layer

22b...第二部分/頂介電層22b. . . Second part / top dielectric layer

22c...第三部分/襯層22c. . . Part III / Liner

24’...電荷儲存材料層twenty four'. . . Charge storage material layer

24...電荷儲存層twenty four. . . Charge storage layer

24a...主體部24a. . . Main body

24b...第一延伸部24b. . . First extension

24c...第二延伸部24c. . . Second extension

26...間隙壁材料層26. . . Gap material layer

26a...間隙壁26a. . . Clearance wall

28、30...摻雜區28, 30. . . Doped region

32...介電層32. . . Dielectric layer

34...字元線34. . . Word line

L1、L2...長度L1, L2. . . length

100、200、300...曲線100, 200, 300. . . curve

圖1至圖7是依照本發明實施例所繪示的一種記憶元件的製造方法的剖面示意圖。1 to 7 are schematic cross-sectional views showing a method of fabricating a memory device according to an embodiment of the invention.

圖8繪示三種不同的記憶元件進行程式化時的程式化速度與汲極偏壓的關係圖。Figure 8 is a graph showing the relationship between the stylized speed and the gate bias voltage when three different memory elements are programmed.

圖9是繪示習知一種記憶元件的剖面示意圖。9 is a cross-sectional view showing a conventional memory element.

圖10是繪示習知又一種記憶元件的剖面示意圖。FIG. 10 is a cross-sectional view showing another conventional memory element.

10...基底10. . . Base

12...閘介電層12. . . Gate dielectric layer

14a...閘極14a. . . Gate

20a...空隙20a. . . Void

22...襯材料層twenty two. . . Lining material layer

22a...第一部分/穿隧介電層22a. . . First part / tunneling dielectric layer

22b...第二部分/頂介電層22b. . . Second part / top dielectric layer

22c...第三部分/襯層22c. . . Part III / Liner

24...電荷儲存層twenty four. . . Charge storage layer

24a...主體部24a. . . Main body

24b...第一延伸部24b. . . First extension

24c...第二延伸部24c. . . Second extension

26a...間隙壁26a. . . Clearance wall

28、30...摻雜區28, 30. . . Doped region

32...介電層32. . . Dielectric layer

34...字元線34. . . Word line

L1、L2...長度L1, L2. . . length

Claims (19)

一種記憶元件,包括:
一閘極,位於一基底上;
一閘介電層,位於該閘極與該基底之間,其中在該閘介電層兩側、該閘極下方及該基底上方具有一空隙;以及 二電荷儲存層,各該電荷儲存層包括一主體部、一第一延伸部與一第二延伸部,各該主體部位於各該空隙中,各該第一延伸部與各該主體部連接並且突出於該閘極之側壁,各第二延伸部與所對應的該第一延伸部連接,且向上延伸至該閘極的側壁,其中該第一延伸部的邊緣區域突出於所對應的各該第二延伸部之側壁。
A memory element comprising:
a gate located on a substrate;
a gate dielectric layer between the gate and the substrate, wherein a gap is formed on both sides of the gate dielectric layer, under the gate and over the substrate; and a charge storage layer, each of the charge storage layers a main body portion, a first extending portion and a second extending portion, each of the main body portions being located in each of the gaps, each of the first extending portions being connected to each of the main body portions and protruding from a side wall of the gate, each second The extension portion is connected to the corresponding first extension portion and extends upward to the sidewall of the gate electrode, wherein an edge region of the first extension portion protrudes from a sidewall of each of the corresponding second extension portions.
如申請專利範圍第1項所述之記憶元件,其中該些主體部、該些第一延伸部以及該些第二延伸部之材質相同。The memory device of claim 1, wherein the body portions, the first extension portions, and the second extension portions are made of the same material. 如申請專利範圍第1項所述之記憶元件,更包括二摻雜區,位於該閘極兩側的該基底中,其中各該電荷儲存層的該第一延伸部與該第二延伸部位於所對應的該摻雜區上方。The memory device of claim 1, further comprising a doped region in the substrate on both sides of the gate, wherein the first extension of each of the charge storage layers is located at the second extension Corresponding to the above doped region. 如申請專利範圍第1項所述之記憶元件,更包括:二襯層,分別位於該閘極與各該電荷儲存層的該第二延伸部之間;以及二間隙壁,位於該第一延伸部上方,分別使該第二延伸部夾於所對應的該襯層與該間隙壁之間。The memory device of claim 1, further comprising: a second liner between the gate and the second extension of each of the charge storage layers; and a second spacer located at the first extension Above the portion, the second extension portion is respectively sandwiched between the corresponding lining layer and the spacer. 如申請專利範圍第1項所述之記憶元件,其中該主體部的長度與該第一延伸部的長度比值為2:1至5:1。The memory element of claim 1, wherein a ratio of a length of the main body portion to a length of the first extension portion is 2:1 to 5:1. 一種記憶元件,包括:
一閘極,位於一基底上;
一閘介電層,位於該閘極與該基底之間,其中在該閘介電層兩側、該閘極下方以及該基底上方形成一空隙;
二電荷儲存層,各該電荷儲存層包括一主體部與一延伸部,各該主體部位於各該空隙中,各該延伸部與各該主體部連接並且突出於該閘極之側壁;以及
二襯層,位於該閘極的側壁,且各該電荷儲存層的該延伸部的邊緣區域突出於該襯層的側壁。
A memory element comprising:
a gate located on a substrate;
a gate dielectric layer is disposed between the gate and the substrate, wherein a gap is formed on both sides of the gate dielectric layer, under the gate, and over the substrate;
a second charge storage layer, each of the charge storage layers includes a body portion and an extension portion, each of the body portions being located in each of the gaps, each of the extension portions being connected to each of the body portions and protruding from a sidewall of the gate electrode; a lining layer is located on a sidewall of the gate, and an edge region of the extension portion of each of the charge storage layers protrudes from a sidewall of the lining.
如申請專利範圍第6項所述之記憶元件,其中該些主體部與該些延伸部之材質相同。The memory device of claim 6, wherein the body portions are the same material as the extension portions. 如申請專利範圍第6項所述之記憶元件,更包括二摻雜區,位於閘極兩側的該基底中,其中各該電荷儲存層的該延伸部延伸至所對應的該摻雜區上方。The memory device of claim 6, further comprising a doped region in the substrate on both sides of the gate, wherein the extension of each of the charge storage layers extends above the corresponding doped region . 如申請專利範圍第6項所述之記憶元件,其中該主體部的長度與該延伸部的長度比值為2:1至5:1。The memory element of claim 6, wherein the length of the body portion and the length of the extension are from 2:1 to 5:1. 一種記憶元件,包括:
一閘極,位於一基底上;
一閘介電層,位於該閘極與該基底之間,其中在該閘介電層兩側、該閘極下方以及該基底上方形成一空隙;
二電荷儲存層,各該電荷儲存層包括一主體部與一延伸部,各該主體部位於各該空隙中,各該延伸部與各該主體部連接並且突出於該閘極之側壁;以及
二摻雜區,位於該閘極兩側的該基底中,其中各該電荷儲存層的該延伸部延伸到對應的該摻雜區上方。
A memory element comprising:
a gate located on a substrate;
a gate dielectric layer is disposed between the gate and the substrate, wherein a gap is formed on both sides of the gate dielectric layer, under the gate, and over the substrate;
a second charge storage layer, each of the charge storage layers includes a body portion and an extension portion, each of the body portions being located in each of the gaps, each of the extension portions being connected to each of the body portions and protruding from a sidewall of the gate electrode; A doped region is located in the substrate on both sides of the gate, wherein the extension of each of the charge storage layers extends above the corresponding doped region.
如申請專利範圍第10項所述之記憶元件,其中該些主體部與該些延伸部之材質相同。The memory device of claim 10, wherein the body portions are the same material as the extension portions. 如申請專利範圍第10項所述之記憶元件,其中該些電荷儲存層之材質包括氮化矽或摻雜多晶矽。The memory device of claim 10, wherein the material of the charge storage layer comprises tantalum nitride or doped polysilicon. 如申請專利範圍第10項所述之記憶元件,其中該主體部的長度與該延伸部的長度比值為2:1至5:1。The memory element of claim 10, wherein a ratio of a length of the body portion to a length of the extension is 2:1 to 5:1. 一種記憶元件的製造方法,包括:
於一基底上形成一閘介電層以及該閘介電層上的一閘極,其中在該閘介電層兩側、該閘極下方以及該基底上方形成一空隙;
形成二電荷儲存層,各該電荷儲存層包括一主體部與一第一延伸部,各該主體部位於各該空隙中,各該第一延伸部與各該主體部連接並且突出於該閘極之側 壁;以及
於該閘極兩側的該基底中形成二摻雜區,各該電荷儲存層的該第一延伸部延伸到所對應的該摻雜區上方。
A method of manufacturing a memory element, comprising:
Forming a gate dielectric layer and a gate on the gate dielectric layer on a substrate, wherein a gap is formed on both sides of the gate dielectric layer, under the gate, and over the substrate;
Forming a two-charge storage layer, each of the charge storage layers including a body portion and a first extension portion, each of the body portions being located in each of the gaps, each of the first extension portions being connected to each of the body portions and protruding from the gate a sidewall formed on the substrate on both sides of the gate; and the first extension of each of the charge storage layers extends over the corresponding doped region.
如申請專利範圍第14項所述之記憶元件的製造方法,其中各該電荷儲存層更包括一第二延伸部,各第二延伸部與該第一延伸部連接,且向上延伸至該閘極側壁,其中該第一延伸部的邊緣區域突出於所對應的各該第二延伸部之側壁。The method of manufacturing the memory device of claim 14, wherein each of the charge storage layers further comprises a second extension, each of the second extensions being connected to the first extension and extending upward to the gate a sidewall, wherein an edge region of the first extension protrudes from a sidewall of each of the corresponding second extensions. 如申請專利範圍第15項所述之記憶元件的製造方法,其中各該電荷儲存層的該第一延伸部與該第二延伸部位於所對應的該摻雜區上方。The method of manufacturing the memory device of claim 15, wherein the first extension portion and the second extension portion of each of the charge storage layers are located above the corresponding doped region. 如申請專利範圍第14項所述之記憶元件的製造方法,在形成該些電荷儲存層之前,更包括形成一襯材料層,覆蓋該基底的表面、該閘介電層之側壁、該閘極之底部、側壁以及上表面,各該電荷儲存層的該第一延伸部的邊緣區域突出於該閘極側壁的該襯材料層。The method for manufacturing a memory device according to claim 14, further comprising forming a lining material layer covering the surface of the substrate, the sidewall of the thyristor layer, and the gate before forming the charge storage layer. The bottom portion, the side wall and the upper surface, the edge region of the first extension portion of each of the charge storage layers protrudes from the lining material layer of the gate sidewall. 如申請專利範圍第17項所述之記憶元件的製造方法,其中形成該些電荷儲存層的步驟包括:
形成一電荷儲存材料層,覆蓋於該襯材料層上且填滿該空隙;
形成一間隙壁材料層,覆蓋於該電荷儲存材料層上;以及
非等向蝕刻移除該間隙壁材料層、該電荷儲存材料層以及該襯材料層,以裸露出該閘極以及該基底之表面,留下二間隙壁、該些電荷儲存層及二襯層。
The method of manufacturing the memory device of claim 17, wherein the forming the charge storage layer comprises:
Forming a layer of charge storage material covering the liner material layer and filling the void;
Forming a spacer material layer overlying the charge storage material layer; and removing the spacer material layer, the charge storage material layer, and the liner material layer by non-isotropic etching to expose the gate and the substrate The surface leaves two spacers, the charge storage layer and the second liner.
如申請專利範圍第14項所述之記憶元件的製造方法,更包括於該閘極的側壁形成二襯層,其中各該電荷儲存層的該第一延伸部突出於對應的該襯層的側壁。The method of manufacturing the memory device of claim 14, further comprising forming a second liner on the sidewall of the gate, wherein the first extension of each of the charge storage layers protrudes from a corresponding sidewall of the liner .
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