TW201322428A - Memory device and method of fabricating the same - Google Patents

Abstract

A memory device including a gate, a gate dielectric and two charge storage layers is described. The gate is disposed on a substrate. The gate dielectric is disposed between the gate and the substrate. The width of the gate is greater than that of the gate dielectric, so that two gaps are present at both sides of the gate dielectric and between the gate and the substrate. Each charge storage layer includes a body portion in one of the gaps, a first extension portion connected with the body portion and protruding out of the corresponding sidewall of the gate, and a second extension portion connected to the first extension portion and extending along the sidewall of the gate, wherein an edge of the first extension portion protrudes from the sidewall of the second extension portion.

Description

Memory element and method of manufacturing same

The present invention relates to an integrated circuit and a method of fabricating the same, and more particularly to a memory element and a method of fabricating the same.

A memory is a semiconductor component used to store information or data. As computer microprocessors become more powerful, the programs and operations that are performed by software increase. Therefore, the demand for high-capacity memory is gradually increasing.

Among various memory products, non-volatile memory allows multiple data stylization, reading and erasing operations, and even saves the data stored in the memory after the power is interrupted. Because of these advantages, non-volatile memory has become a widely used memory in personal computers and electronic devices.

Well-known electrically programmable and erasable non-volatile memory technologies such as electronic erasable programmable read-only memory (EEPROM) and flash memory using charge storage structures Memory (flash memory) has been used in a variety of modern applications. The flash memory is designed to have an array of memory cells that can be programmed and read independently. A typical flash memory cell stores charge in a floating gate. Another type of flash memory uses a charge-trapping structure of a non-conducting material, such as tantalum nitride, to replace the conductive material of the floating gate. When the charge trapping memory cell is programmed, the charge is captured and does not move through the non-conductor charge trapping structure. When the power supply is not continuously supplied, the charge remains in the charge trapping layer, maintaining its data state until the memory cells are erased. The charge trapping memory cell can be manipulated as a two-sided cell. That is, since the charge does not move through the non-conductor charge trapping layer, the charge can be located at a different charge trap. In other words, in the flash memory structure of the charge trapping structure type, information of more than one bit can be stored in each memory cell.

Any memory cell can be programmed, and two completely separate bits are stored in the charge trapping structure (in a manner where the charges are concentrated close to the source and drain regions, respectively). Stylization of memory cells can utilize channel hot electron injection, which produces hot electrons in the channel region. The hot electrons acquire energy and are captured in the charge trapping structure. Interchanging the source terminal with the bias applied by the 汲 extreme can capture charge to any portion of the charge trapping structure (near source region, near drain region, or both).

Typically, a memory cell with a charge trapping structure can store four different combinations of bits (00, 01, 10, and 11), each having a corresponding starting voltage. During the read operation, the current flowing through the memory cells differs due to the starting voltage of the memory cells. Typically, this current can have four different values, each of which corresponds to a different starting voltage. Therefore, by detecting this current, the combination of bits stored in the memory cell can be determined.

All valid charge ranges or starting voltage ranges can be classified as memory operating windows. In other words, the memory operation margin is defined by the difference between the programmed level and the erase level. Since memory cell operation requires good level separation between various states, a large memory operation margin is required. However, the performance of a two-dimensional memory cell generally decreases with the so-called "second bit effect." Under the second bit effect, the charges localized in the charge trapping structure interact with each other. For example, during a reverse read, a read bias is applied to the drain terminal and a charge stored near the source region (ie, the first bit) is detected. However, the bit (i.e., the second bit) that is then near the drain region produces a potential barrier that reads the first bit near the source region. This energy barrier can be overcome by applying an appropriate bias voltage, using the drain-induced energy barrier reduction (DIBL) effect to suppress the effect of the second bit near the drain region, and allowing the storage state of the first bit to be detected. However, when the second bit near the drain region is programmed to a high start voltage state and the first bit near the source region is in an unprogrammed state, the second bit substantially increases the energy barrier. Therefore, as the starting voltage with respect to the second bit increases, the read bias of the first bit is not sufficient to overcome the potential barrier generated by the second bit. Therefore, since the starting voltage of the second bit increases, the starting voltage of the first bit increases, thereby reducing the memory operating margin. The second bit effect reduces the operating margin of the 2-bit memory. Therefore, there is a need for a method and component that can suppress the second bit effect in a memory component.

The present invention provides a memory element that can provide a positioned charge storage region such that charge can be fully localized, reduced second bit effect, reduced stylized interference behavior, and reduced short channel effects.

The invention provides a method for manufacturing a memory element, which can make a memory storage component can provide a positioned charge storage area through a simple process, so that the charge can be completely positioned and stored, thereby obtaining a better second bit and reducing the program. Interacting behavior and reducing short-channel effects.

The invention provides a memory element comprising a gate, a gate dielectric layer and a two charge storage layer. The gate is located on the substrate. A gate dielectric layer is between the gate and the substrate. There is a gap on both sides of the gate dielectric layer, below the gate and above the substrate. Each of the charge storage layers includes a body portion, a first extension portion and a second extension portion. Each body portion is located in each of the above spaces. Each of the first extensions is coupled to the body portion and protrudes from a sidewall of the gate. The second extension portion is connected to the corresponding first extension portion and extends upward to the gate sidewall, wherein an edge region of the first extension portion protrudes from a sidewall of each of the corresponding second extension portions.

According to an embodiment of the invention, the main body portion, the first extending portion, and the second extending portion are made of the same material.

According to an embodiment of the invention, the memory device further includes two doped regions, the substrate on both sides of the gate, wherein the first extension and the second extension of each of the charge storage layers are located in the corresponding doping Above the miscellaneous area.

According to an embodiment of the invention, the memory element further includes a second liner and two spacers. The two liner layers are respectively located between the gate and the second extension of each of the charge storage layers. The two gap walls are located above the first extension portion, and the second extension portion is sandwiched between the corresponding liner layer and the gap wall.

According to an embodiment of the invention, the ratio of the length of the main body portion to the length of the first extension portion is 2:1 to 5:1.

The invention provides a memory element comprising a gate, a gate dielectric layer, a two-charge storage layer and a second liner. The gate is located on the substrate. The gate dielectric layer is between the gate and the substrate. There is a gap on both sides of the gate dielectric layer, below the gate and above the substrate. Each of the above charge storage layers includes a body portion and an extension portion. Each body portion is located in the above gap. Each of the extensions is coupled to the body portion and protrudes from a sidewall of the gate. Each of the lining layers is located on a sidewall of the gate, and an edge region of the extension of each of the charge storage layers protrudes from a sidewall of the lining.

According to an embodiment of the invention, the body portion and the extension portion are made of the same material.

According to an embodiment of the invention, the memory device further includes a doped region in the substrate on both sides of the gate, wherein the extension of each of the charge storage layers extends above the corresponding doped region.

According to an embodiment of the invention, the ratio of the length of the main body portion to the length of the extension portion is 2:1 to 5:1.

The invention also provides a memory element comprising a gate, a gate dielectric layer, a two charge storage layer and a second doped region. The gate is located on the substrate. The gate dielectric layer is between the gate and the substrate. There is a gap on both sides of the gate dielectric layer, below the gate and above the substrate. Each of the above charge storage layers includes a body portion and an extension portion. Each body portion is located in the above gap. Each of the extensions is coupled to the body portion and protrudes from a sidewall of the gate. Each of the doped regions is located in a substrate on both sides of the gate, and an extension of each of the charge storage layers extends above the corresponding doped region.

According to an embodiment of the invention, the body portion and the extension portion are made of the same material.

According to an embodiment of the invention, the ratio of the length of the main body portion to the length of the extension portion is 2:1 to 5:1.

The invention provides a method for fabricating a memory device, comprising: forming a gate dielectric layer on a substrate and a gate on the gate dielectric layer, wherein a gap is formed on both sides of the gate dielectric layer, below the gate and above the substrate. A second charge storage layer is then formed, each charge storage layer comprising a body portion and a first extension, wherein each body portion is located in the gap, each first extension being connected to each body portion and protruding from a sidewall of the gate. Two doped regions are formed in the substrate on both sides of the gate, and the first extension of each charge storage layer extends above the corresponding doped region.

According to an embodiment of the present invention, each of the charge storage layers further includes a second extension portion, each of the second extension portions is coupled to the first extension portion and extends upward to the gate sidewall, wherein the first An edge region of the extension protrudes from a sidewall of the corresponding second extension.

According to an embodiment of the invention, in the method of manufacturing the memory device, the first extension portion and the second extension portion of each of the charge storage layers are located above the corresponding doped region.

According to an embodiment of the present invention, the method for fabricating the memory device further includes forming a liner material layer covering the surface of the substrate, the sidewall of the gate dielectric layer, and the bottom of the gate before forming the charge storage layer. The side wall and the upper surface, the edge region of the first extension portion of each of the charge storage layers protrudes from the lining material layer of the gate sidewall.

According to an embodiment of the present invention, a method of fabricating the memory device includes forming a layer of a charge storage material covering the liner material layer and filling the voids, and then forming a spacer material layer covering the charge storage material layer. Thereafter, the lining material layer, the charge storage material layer and the spacer material layer are removed by the non-isotropic etching to expose the gate and the surface of the substrate, leaving the lining layer, the charge storage layer and the second spacer.

According to an embodiment of the present invention, the method of manufacturing the memory device further includes forming a liner on a sidewall of the gate, wherein the first extension of each of the charge storage layers protrudes from a sidewall of the liner.

The memory element of the present invention can provide a positioned charge storage area to allow charge to be fully localized, reduce second bit effect, reduce stylized interference behavior, and reduce short channel effects.

The manufacturing method of the memory element of the invention can make the fabricated memory element provide a positioned charge storage area through a simple process, so that the charge can be completely positioned and stored, thereby obtaining a better second bit and reducing stylization. Interfering behavior and can reduce short-channel effects.

The above described features and advantages of the present invention will be more apparent from the following description.

1 to 7 are schematic cross-sectional views showing a method of fabricating a memory device according to an embodiment of the invention.

Referring to FIG. 1, a method of fabricating a memory device of the present invention is to form a gate dielectric layer 12 on a substrate 10, and then a gate conductor layer 14 is formed on the gate dielectric layer 12. The material of the substrate 10 is, for example, a semiconductor such as germanium or a germanium (SOI) on the insulating layer. The material of the substrate 10 may also be other compound semiconductors. The material of the gate dielectric layer 12 is, for example, tantalum oxide or other material suitable for use in fabricating the gate dielectric layer. The method of forming the gate dielectric layer 12 is, for example, a thermal oxidation method, or a chemical vapor deposition method, or other suitable method. The material of the gate conductor layer 14 is, for example, doped polysilicon. The method of forming the gate conductor layer 14 is, for example, forming an undoped polysilicon layer by chemical vapor deposition, and then performing an ion implantation step to form it. The gate conductor layer 14 may be formed by a chemical vapor deposition method to form a polysilicon layer and doping in the field. Thereafter, a patterned hard mask layer 16 and a patterned mask layer 18 are formed on the gate conductor layer 14. The material of the patterned hard mask layer 16 is, for example, APF, and the method of formation is, for example, chemical vapor deposition. The material of the patterned mask layer 18 is, for example, a photoresist. The pattern of the mask layer 18 can be formed by exposure and development. The pattern of the hard mask layer 16 can be formed by transferring the pattern of the mask layer 18 downward through an etching process.

Thereafter, referring to FIG. 2, the mask layer 18 and the hard mask layer 16 are used as a mask, and the substrate 10 is an etch stop layer, and an etching process is performed to pattern the gate conductor layer 14 into the gate 14a, and continue the pattern. The dielectric layer 12 is turned on. The etching process employed is, for example, an anisotropic etching process. The anisotropic etching process is, for example, a plasma etching process. Thereafter, the patterned mask layer 18 and the hard mask layer 16 are removed.

Thereafter, referring to FIG. 3, the gate dielectric layer 12 is subjected to an isotropic etching process to remove a portion of the gate dielectric layer 12, that is, an undercut is formed under the gate 14a to form a recess 20, which is recessed. The slot 20 is used as a local storage space.

Next, referring to FIG. 4, a liner material layer 22 is formed covering the upper surface of the gate 14a, the sidewalls and the bottom, the sidewalls of the gate dielectric layer 12, and the surface of the substrate 10. In one embodiment, the liner layer 22 conformally covers the upper surface of the gate 14a, the sidewalls and the bottom, the sidewalls of the gate dielectric layer 12, and the surface of the substrate 10. The lining material layer 22 is filled in the groove 20 shown in Fig. 3, but does not fill the groove 20, leaving a void 20a (Fig. 4). The material of the lining material layer 22 is, for example, ruthenium oxide, and is formed by, for example, thermal oxidation, on-site vapor generation (ISSG) oxidation, chemical vapor deposition (CVD), atomic layer deposition, or furnace tube oxidation.

Thereafter, referring to Fig. 5, a charge storage material layer 24' is formed covering the upper surface of the gate 14a, the side walls, and the surface of the liner material layer 22 above the substrate 10 and filled in the voids 20a. The material of the charge storage material layer 24' is, for example, tantalum nitride or doped polysilicon. The method of forming tantalum nitride is, for example, a furnace tube deposition method, a chemical vapor deposition method, or an atomic layer deposition method. The method of forming the doped polysilicon is, for example, forming a polycrystalline germanium layer by chemical vapor deposition and doping in the presence.

Thereafter, a spacer material layer 26 is formed over the charge storage material layer 24', covering the upper surface of the gate 14a, the sidewalls, and the charge storage material layer 24' above the substrate 10. In one embodiment, the spacer material layer 26 conforms to the upper surface of the gate 14a, the sidewalls, and the charge storage material layer 24' above the substrate 10. The material of the spacer material layer 26 is, for example, ruthenium oxide, and the formation method is, for example, a furnace tube oxidation method, a chemical vapor deposition method, or a high temperature thermal oxidation method (HTO).

Thereafter, referring to Fig. 6, the spacer material layer 26, the charge storage material layer 24', and the liner layer 22 are anisotropically etched to expose the surfaces of the gate 14a and the substrate 10. The remaining charge storage material layer 24' serves as a charge storage layer 24 including a body portion 24a, a first extension portion 24b, and a second extension portion 24c. Each body portion 24a is located in the gap 20a. The first extension portion 24b is connected to the main body portion 24a and protrudes from the side wall of the gate electrode 14a. The second extension portion 24c is located at a side wall of the gate electrode 14a and extends downward to be connected to the first extension portion 24b such that an edge region of the first extension portion 24b protrudes from a sidewall of the corresponding second extension portion 24c.

The remaining lining material layer 22 includes three portions 22a, 22b, 22c. A first portion 22a of the liner layer 22 is positioned between the charge storage layer 24 and the substrate 10 as a tunneling dielectric layer 22a. The second portion 22b of the lining material layer 22 is located below the gate 14a and sandwiched between the gate 14a and the body portion 24a of the charge storage layer 24 as the top dielectric layer 22b. The third portion 22c of the lining material layer 22 is located on the sidewall of the gate 14a and sandwiched between the gate 14a and the second extension 24c of the charge storage layer 24 as a liner 22c. The remaining spacer material layer acts as a spacer 26a above the first extension 24b of the charge storage layer 24 and the sidewall of the second extension 24c.

Ion implantation is then performed to form doped regions 28, 30 in substrate 10. The doped conductivity types implanted in the doped regions 28, 30 are the same and are different from the conductivity type of the substrate 10. In one embodiment, substrate 10 is P-doped; doped regions 28, 30 are N-doped. In another embodiment, substrate 10 is N-doped; doped regions 28, 30 are P-doped. The N-type doping is, for example, phosphorus or arsenic; the P-type doping is, for example, boron or boron difluoride. The doped regions 28, 30 can serve as the source or drain regions of the memory. The doped regions 28, 30 are located in the substrate 10 on both sides of the gate 14a, wherein the first extension 24b and the second extension 24c of each charge storage layer 24 are located above the corresponding doped regions 28, 30.

Then, referring to FIG. 7, a dielectric layer 32 is formed on the substrate 10. Dielectric layer 32 fills the gap between adjacent two gates 14a and has a flat surface that exposes the surface of gate 14a. The material of the dielectric layer 32 is, for example, ruthenium oxide. The method of forming is, for example, forming a dielectric material layer by chemical vapor deposition, and then performing a planarization process. The planarization process is, for example, an etch back process or a chemical mechanical polishing process (CMP).

Thereafter, a word line 34 is formed over the dielectric layer 32. The material of the word line 34 is a conductor material that is electrically connected to the gate 14a. In one embodiment, the direction in which word lines 34 extend is different from the direction in which doped regions 28, 30 extend, such as being substantially vertical. The method of forming the word line 34 is, for example, a lithography and etching process after forming a layer of a conductor material. The conductor material is, for example, doped polysilicon, metal, metal alloy or a combination thereof. The method of forming the doped polysilicon is, for example, forming an undoped polysilicon layer by chemical vapor deposition, and then performing an ion implantation step to form it. The method of forming the doped polysilicon may also be to form a polysilicon layer by chemical vapor deposition and dope in the field. The metal or metal alloy is formed by, for example, sputtering or chemical vapor deposition, or other suitable methods.

Referring to FIG. 7, the memory device of the embodiment of the present invention includes a gate 14a, a gate dielectric layer 12, two charge storage layers 24, doped regions 28, 30, and word lines 34.

The gate 14a is located on the substrate 10. The gate dielectric layer 12 is between the gate 14a and the substrate 10. The gate dielectric layer 12 has a width smaller than the gate 14a, and has a gap 20a on both sides of the gate dielectric layer 12, below the gate 14a, and above the substrate 10.

The material of the charge storage layer 24 and the gate dielectric layer 12 are different. Each of the charge storage layers 24 includes a body portion 24a, a first extension portion 24b, and a second extension portion 24c. Each body portion 24a is located in the gap 20a. Each of the first extending portions 24b is connected to each of the main body portions 24a and protrudes from the side wall of the gate electrode 14a. The second extension 24c is coupled to the corresponding first extension 24b and extends up to the sidewall of the gate 14a. In other words, the edge region of the first extension portion 24b protrudes from the side wall of the corresponding second extension portion 24c, and its cross section is inverted T-shaped. The length L1 of the main body portion 24a is too short to cause a limitation in stylized efficiency. The longer the length L1 of the main body portion 24a, the faster the stylization speed is, but the second bit effect is greatly affected. The longer the length of the first extension 24b is, the more it is not controlled by the gate, so the influence of the second bit effect is small, but the speed of stylization can still be improved. The length L1 of the main body portion 24a is, for example, 50 angstroms to 150 angstroms; and the length L2 of the first extending portion 24b is, for example, 10 angstroms to 75 angstroms. In one embodiment, the ratio of the length L1 of the body portion 24a to the length L2 of the first extension portion 24b is about 2:1 to 5:1. The main body portion 24a, the first extending portion 24b, and the second extending portion 24c are made of the same material.

The tunneling dielectric layer 22a is located between the charge storage layer 24 and the substrate 10. The top dielectric layer 22b is located under the gate 14a and is sandwiched between the gate 14a and the body portion 24a of the charge storage layer 24. The lining layer 22c is located on the sidewall of the gate 14a and is sandwiched between the gate 14a and the second extension 24c of the charge storage layer 24. The spacer 26a is located above the first extension 24b of the charge storage layer 24 and the sidewall of the second extension 24c. In one embodiment, the material of the tunnel dielectric layer 22a, the top dielectric layer 22b, the liner layer 22c, and the spacers 26a is different from the material of the charge storage layer 24.

The doped conductivity type in the doped regions 28, 30 is different from the conductivity type of the substrate 10. The doped regions 28, 30 are located in the substrate 10 on both sides of the gate 14a, and the first extensions 24b and the second extensions 24c of the respective charge storage layers 24 are located above the corresponding doped regions 28, 30. The doped conductivity types implanted in the doped regions 28, 30 are the same and are different from the conductivity type of the substrate 10.

Figure 8 is a graph showing the relationship between the stylized speed and the gate bias voltage when three different memory elements are programmed.

Referring to FIG. 8, a curve 100 is a memory element of the memory storage layer 24 (including the main body portion 24a, the first extension portion 24b and the second extension portion 24c, the inverse T-type) of the embodiment of FIG. 7 according to the present invention. result. Curve 200 is the result of a conventional memory storage layer 24 of FIG. 9 that includes only the memory elements of body portion 24a. The curve 300 is the result of the conventional charge storage layer 24 of FIG. 10 including only the first extension 24b and the second extension 24c, and the L-shaped memory element is programmed. From the results of FIG. 8, it is shown that the curve 100, when the same gate voltage is applied for programming, the charge storage layer is an inverse T-type memory element having a high programmed bit start voltage change rate (dVt). That is, the stylization speed is faster. In summary, the memory element of the present invention can provide a positioned charge storage area to allow charge to be fully localized, reduce second bit effect, reduce stylized interference behavior, and reduce short channel effects. Further, the method of manufacturing the memory element of the present invention has a simple process.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

10. . . Base

12. . . Gate dielectric layer

14. . . Gate conductor layer

14a. . . Gate

16. . . Patterned hard mask layer

18. . . Patterned mask layer

20. . . Groove

20a. . . Void

twenty two. . . Lining material layer

22a. . . First part / tunneling dielectric layer

22b. . . Second part / top dielectric layer

22c. . . Part III / Liner

twenty four'. . . Charge storage material layer

twenty four. . . Charge storage layer

24a. . . Main body

24b. . . First extension

24c. . . Second extension

26. . . Gap material layer

26a. . . Clearance wall

28, 30. . . Doped region

32. . . Dielectric layer

34. . . Word line

L1, L2. . . length

100, 200, 300. . . curve

1 to 7 are schematic cross-sectional views showing a method of fabricating a memory device according to an embodiment of the invention.

Figure 8 is a graph showing the relationship between the stylized speed and the gate bias voltage when three different memory elements are programmed.

9 is a cross-sectional view showing a conventional memory element.

FIG. 10 is a cross-sectional view showing another conventional memory element.

10. . . Base

12. . . Gate dielectric layer

14a. . . Gate

20a. . . Void

twenty two. . . Lining material layer

22a. . . First part / tunneling dielectric layer

22b. . . Second part / top dielectric layer

22c. . . Part III / Liner

twenty four. . . Charge storage layer

24a. . . Main body

24b. . . First extension

24c. . . Second extension

26a. . . Clearance wall

28, 30. . . Doped region

32. . . Dielectric layer

34. . . Word line

L1, L2. . . length

Claims (19)

A memory element comprising:
a gate located on a substrate;
a gate dielectric layer between the gate and the substrate, wherein a gap is formed on both sides of the gate dielectric layer, under the gate and over the substrate; and a charge storage layer, each of the charge storage layers a main body portion, a first extending portion and a second extending portion, each of the main body portions being located in each of the gaps, each of the first extending portions being connected to each of the main body portions and protruding from a side wall of the gate, each second The extension portion is connected to the corresponding first extension portion and extends upward to the sidewall of the gate electrode, wherein an edge region of the first extension portion protrudes from a sidewall of each of the corresponding second extension portions. The memory device of claim 1, wherein the body portions, the first extension portions, and the second extension portions are made of the same material. The memory device of claim 1, further comprising a doped region in the substrate on both sides of the gate, wherein the first extension of each of the charge storage layers is located at the second extension Corresponding to the above doped region. The memory device of claim 1, further comprising: a second liner between the gate and the second extension of each of the charge storage layers; and a second spacer located at the first extension Above the portion, the second extension portion is respectively sandwiched between the corresponding lining layer and the spacer. The memory element of claim 1, wherein a ratio of a length of the main body portion to a length of the first extension portion is 2:1 to 5:1. A memory element comprising:
a gate located on a substrate;
a gate dielectric layer is disposed between the gate and the substrate, wherein a gap is formed on both sides of the gate dielectric layer, under the gate, and over the substrate;
a second charge storage layer, each of the charge storage layers includes a body portion and an extension portion, each of the body portions being located in each of the gaps, each of the extension portions being connected to each of the body portions and protruding from a sidewall of the gate electrode; a lining layer is located on a sidewall of the gate, and an edge region of the extension portion of each of the charge storage layers protrudes from a sidewall of the lining. The memory device of claim 6, wherein the body portions are the same material as the extension portions. The memory device of claim 6, further comprising a doped region in the substrate on both sides of the gate, wherein the extension of each of the charge storage layers extends above the corresponding doped region . The memory element of claim 6, wherein the length of the body portion and the length of the extension are from 2:1 to 5:1. A memory element comprising:
a gate located on a substrate;
a gate dielectric layer is disposed between the gate and the substrate, wherein a gap is formed on both sides of the gate dielectric layer, under the gate, and over the substrate;
a second charge storage layer, each of the charge storage layers includes a body portion and an extension portion, each of the body portions being located in each of the gaps, each of the extension portions being connected to each of the body portions and protruding from a sidewall of the gate electrode; A doped region is located in the substrate on both sides of the gate, wherein the extension of each of the charge storage layers extends above the corresponding doped region. The memory device of claim 10, wherein the body portions are the same material as the extension portions. The memory device of claim 10, wherein the material of the charge storage layer comprises tantalum nitride or doped polysilicon. The memory element of claim 10, wherein a ratio of a length of the body portion to a length of the extension is 2:1 to 5:1. A method of manufacturing a memory element, comprising:
Forming a gate dielectric layer and a gate on the gate dielectric layer on a substrate, wherein a gap is formed on both sides of the gate dielectric layer, under the gate, and over the substrate;
Forming a two-charge storage layer, each of the charge storage layers including a body portion and a first extension portion, each of the body portions being located in each of the gaps, each of the first extension portions being connected to each of the body portions and protruding from the gate a sidewall formed on the substrate on both sides of the gate; and the first extension of each of the charge storage layers extends over the corresponding doped region. The method of manufacturing the memory device of claim 14, wherein each of the charge storage layers further comprises a second extension, each of the second extensions being connected to the first extension and extending upward to the gate a sidewall, wherein an edge region of the first extension protrudes from a sidewall of each of the corresponding second extensions. The method of manufacturing the memory device of claim 15, wherein the first extension portion and the second extension portion of each of the charge storage layers are located above the corresponding doped region. The method for manufacturing a memory device according to claim 14, further comprising forming a lining material layer covering the surface of the substrate, the sidewall of the thyristor layer, and the gate before forming the charge storage layer. The bottom portion, the side wall and the upper surface, the edge region of the first extension portion of each of the charge storage layers protrudes from the lining material layer of the gate sidewall. The method of manufacturing the memory device of claim 17, wherein the forming the charge storage layer comprises:
Forming a layer of charge storage material covering the liner material layer and filling the void;
Forming a spacer material layer overlying the charge storage material layer; and removing the spacer material layer, the charge storage material layer, and the liner material layer by non-isotropic etching to expose the gate and the substrate The surface leaves two spacers, the charge storage layer and the second liner. The method of manufacturing the memory device of claim 14, further comprising forming a second liner on the sidewall of the gate, wherein the first extension of each of the charge storage layers protrudes from a corresponding sidewall of the liner .