TW201320392A - Nitride semiconductor light emitting element, and method for manufacturing nitride semiconductor light emitting element - Google Patents

Abstract

Provided are: a nitride semiconductor light emitting element, which is provided on a semipolar surface, and has an increase of a bias voltage required for light emission suppressed; and a method for manufacturing the nitride semiconductor light emitting element. A multiquantum well structure of a light emitting layer (17) that is provided on a supporting base body, which has a semipolar main surface (13a), and is composed of a hexagonal nitride semiconductor, is composed of a well layer (17a), a well layer (17c), and a barrier layer (17b). The barrier layer (17b) is provided between the well layer (17a) and the well layer (17c), the well layer (17a) and the well layer (17c) are composed of InGaN, and the well layer (17a) and the well layer (17c) have an indium composition within the range of 0.15-0.50. A tilt angle (alpha) of the main surface (13a) of the hexagonal nitride semiconductor with respect to the c plane is within the range of 50-80 degrees or within the range of 130-170 degrees, and a value (L) of the film thickness of the barrier layer (17b) is within the range of 1.0-4.5 nm.

Description

Nitride semiconductor light-emitting device and method of manufacturing nitride semiconductor light-emitting device

The present invention relates to a nitride semiconductor light-emitting element.

Patent Document 1 discloses an injection of a hole in a quantum well structure (MQW (Multiple Quantum Well) structure, SQW (Single Quantum Well) structure) for improving a light-emitting element. A technique for diffusing states to improve luminous efficiency.

Patent Document 2 discloses a method of manufacturing a semiconductor light-emitting device in which a direction of piezoelectric polarization in an active layer can be selected in an appropriate direction.

Patent Document 3 discloses a nitride-based semiconductor light-emitting device in which the implantation efficiency of a carrier of a well layer is improved.

Non-Patent Document 1 discloses an LED (Light-Emitting Diode) having a multiple quantum well structure that emits a blue-green laser. Non-Patent Document 2 discloses an LD (Laser Diode) having a multiple quantum well structure that emits a green laser.

Prior technical literature Patent literature

Patent Document 1: Japanese Patent Laid-Open Publication No. 2002-270894

Patent Document 2: Japanese Patent Laid-Open Publication No. 2011-77395

Patent Document 3: Japanese Patent Laid-Open No. 2011-40709

Non-patent literature

Non-Patent Document 1: "Characterization of blue-green m-plane InGaN light emitting diodes", You-Da Lin, Arpan Chakraborty, Stuart Brinkley, Hsun Chih Kuo, Thiago Melo, Kenji Fujito, James S. Speck, Steven P. DenBaars, and Shuji Nakamura, Applied Physics Letters 94, 261108 (2009).

Non-Patent Document 2: "High Quality InGaN/AlGaN Multiple Quantum Wells for Semipolar InGaN Green Laser Diodes", You-Da Lin, Shuichiro Yamamoto, Chia-Yen Huang, Chia-Lin Hsiung, Feng Wu, Kenji Fujito, Hiroaki Ohta, James S. Speck, Steven P. DenBaars, and Shuji Nakamura, Applied Physics Express 3, (2010) 082001.

In the case where the light-emitting layer of Patent Document 1 is of the MQW structure, in order to make the hole easier to move further from the side of the p-type semiconductor layer toward the side of the n-type semiconductor layer in the MQW structure, the complex number in the MQW structure is used. In a manner that at least two of the barrier layers have different band gaps, it is preferable to form the MQW structure in such a manner that the plurality of layers gradually change from the p-type side toward the n-type side. In the case where the light-emitting layer is in the SQW structure, the barrier layer composition on the p-type side is inclined, and the band gap is formed from the p-type side toward the n-type side.

In Patent Document 2, the photoluminescence of the substrate product is measured while applying a bias voltage to the substrate product, and the bias dependence of the photoluminescence of the substrate product is obtained, and the substrate production is selected. One or a plurality of tilt angles are grown for the quantum well structure of the light-emitting layer and the p-type and n-type gallium nitride-based semiconductor layers. Then, according to the bias dependency, for the substrate Each of the selected tilt angles of the major faces estimates the direction of the piezoelectric polarization in the luminescent layer. Then, the surface orientation of the grown substrate for the manufacture of the semiconductor light-emitting device is selected by using any one of the tilt angle corresponding to the main surface of the substrate and the tilt angle corresponding to the back surface of the main surface of the substrate. A semiconductor laminate for a semiconductor light emitting element is formed on the main surface of the growth substrate.

The nitride semiconductor light-emitting device of Patent Document 3 includes a substrate including a hexagonal gallium nitride-based semiconductor, an n-type gallium nitride-based semiconductor region provided on a main surface of the substrate, and a light-emitting layer of a single quantum well structure. It is provided on the n-type gallium nitride-based semiconductor region; and a p-type gallium nitride-based semiconductor region is provided on the light-emitting layer. The light-emitting layer is provided between the n-type gallium nitride-based semiconductor region and the p-type gallium nitride-based semiconductor region, and includes a well layer, a barrier layer, and a barrier layer. The well layer is InGaN. The principal surface of the substrate extends along a reference plane which is inclined at an inclination angle of a range of 63 degrees or more and 80 degrees or less or 100 degrees or more and 117 degrees or less from a plane orthogonal to the c-axis direction of the hexagonal gallium nitride-based semiconductor. .

The LED of Non-Patent Document 1 is formed on the m-plane. The LD of Non-Patent Document 2 is formed on the (20-21) plane.

A plurality of plural quantum well structures are disclosed in Patent Documents 1 to 3 and Non-Patent Documents 1, 2 and the like. However, the quantum well configuration disposed on the semi-polar surface has a different strain or polarity than the quantum well configuration disposed on the c-plane. The difference in the nature of such a quantum well structure is that the energy band structure of the quantum well structure disposed on the semi-polar surface is given a different strain from the c-plane, so that the injection efficiency of electrons in the quantum well structure is lowered. . The decrease in the injection efficiency of electrons causes the bias voltage required for light emission to rise. Therefore, the present invention It is an object of the present invention to provide a nitride semiconductor light-emitting device and a method of manufacturing the nitride semiconductor light-emitting device which are provided on a semi-polar surface and which suppresses an increase in a bias voltage required for light emission. .

For the quantum well structure of the prior InGaN provided on the c-plane of the hexagonal nitride semiconductor, for example, a barrier layer having a film thickness of 5 nm or more and 20 nm or less is used. In particular, in the case of a light-emitting element that emits light of a relatively long wavelength, the indium composition of the well layer is relatively high, and therefore the film thickness of the barrier layer is preferably relatively thick. The crystal quality of the well layer is lowered when the indium composition is relatively high, because the properties of the crystal surface are adjusted as the barrier layer grows, and the crystal quality is restored. In the case where the light-emitting element having the quantum well structure on the semipolar surface is manufactured as described above, the inventors originally formed a light-emitting element having a quantum well structure on the c-plane, and formed about 15 nm. The luminescent layer of the multiple quantum well structure of the barrier layer of thickness. However, it is well known that in the case of a light-emitting element having a quantum well structure on a semi-polar surface, a relatively high bias voltage is required for light emission.

Therefore, in order to understand the reason why the relatively high bias voltage is required for light emission as described above, the inventors investigated the quantum of InGaN by measuring a photoluminescence (PL: Photo Luminescence) in a state where a bias voltage is applied. The optical properties of the crystal face of the well structure. As a result, the inventors found that the direction of the piezoelectric polarization of the well layer of the quantum well structure of InGaN disposed on the semipolar plane and the piezoelectric layer of the well layer of the quantum well structure of InGaN disposed on the c-plane The direction of polarization is opposite. Moreover, the inventors have found that the direction of the piezoelectric polarization of the well layer of InGaN disposed on the semipolar plane is opposite to the direction of the piezoelectric polarization of the well layer of InGaN disposed on the c-plane, which makes the quantum well structure of InGaN The injection efficiency of electrons is lowered, whereby the bias voltage required for light emission rises. Further, the problem of the electron injection efficiency in the quantum well structure of InGaN as described above is generally not recognized for the following reasons: in the quantum well structure of InGaN previously provided on the c-plane, it is provided in The direction of piezoelectric polarization of the InGaN well layer on the c-plane is not the direction in which the electron injection in the quantum well structure of InGaN is reduced; and the hole system has a small offset, so the piezoelectric polarization as described above The associated impact on injection efficiency is relatively small.

On the other hand, the inventors have found that the incorporation of indium or the growth mode of InGaN in a multi-quantum well structure of InGaN provided on a semipolar plane of a certain tilt angle contributes favorably to high quality, and is relatively high in growth. In the case of a well layer composed of indium, it is possible to grow the structure without greatly degrading the crystal quality and to realize the characteristics of the InGaN crystal in the above case. The inventors have found that by using the properties of the InGaN crystal and the semipolar surface, it is possible to use a barrier layer having a thin film thickness such as a decrease in crystallinity due to insufficient recovery of crystallinity when growing on the c-plane, and not A quantum well structure having a relatively high crystal quality which is degraded in luminous efficiency is grown. The inventors studied the relationship between the film thickness of the barrier layer of the multiple quantum well structure of InGaN disposed on a semipolar plane and the crystal quality of the quantum well structure. As a result of the research, the inventors found that a barrier layer having a relatively thin film thickness of the same level as that of the well layer is disposed on the semipolar surface, and the PL light reflecting the crystallinity is not allowed. A structure in which the strength is lowered to maintain a good crystal quality. Further, the inventors have made a light-emitting element of a quantum well structure of InGaN which is provided on a semipolar surface by actually manufacturing a barrier layer having a relatively thin film thickness of the same level as that of the well layer. In the middle, it was found that the bias voltage required for light emission is lowered, the half-width and width of the light-emitting wavelength are lowered, and the luminous efficiency is improved, and the carrier injection efficiency is improved.

Several aspects of the present invention have been accomplished based on the above knowledge gained by the inventors regarding the multiple quantum well configuration of InGaN disposed on a semi-polar surface. The isomorphs are shown below.

A first aspect of the invention relates to a nitride semiconductor light-emitting device. The nitride semiconductor light-emitting device includes: (a) a support substrate including a hexagonal nitride semiconductor having a main surface inclined from a c-plane of the hexagonal nitride semiconductor in a predetermined direction; (b) n-type nitridation; a gallium-based semiconductor layer provided on the main surface of the support substrate; (c) a light-emitting layer provided on the n-type gallium nitride-based semiconductor layer and including a gallium nitride-based semiconductor; and p-type nitride A gallium-based semiconductor layer is provided on the light-emitting layer. The light emitting layer has a multiple quantum well structure, the multiple quantum well structure comprises at least two well layers and at least one barrier layer, the barrier layer is disposed between the two well layers, and the two well layers comprise InGaN, the two The well layer has a first indium composition in a range of 0.15 or more and 0.50 or less, and the inclination angle of the main surface with respect to the c-plane is in a range of 50 degrees or more and 80 degrees or less and a range of 130 degrees or more and 170 degrees or less. The film thickness of the barrier layer is in the range of 1.0 nm or more and 4.5 nm or less.

Supporting substrate of nitride semiconductor light-emitting device according to the first aspect of the present invention The principal surface is a semipolar surface in a range of 50 degrees or more and 80 degrees or less and a range of 130 degrees or more and 170 degrees or less. The nitride semiconductor light-emitting device includes a plurality of quantum well structures disposed on the main surface. Light-emitting layer. The direction of the piezoelectric polarization generated in the well layer of the multiple quantum well structure disposed on the semipolar surface as described above is opposite to the direction of the piezoelectric polarization generated in the well layer disposed on the c-plane. Thereby, the energy band structure of the multiple quantum well structure provided on the semipolar surface produces a strain different from the c surface. The injection efficiency of electrons in the light-emitting layer is lowered due to the strain of the energy band structure. However, since the barrier layer of the nitride semiconductor light-emitting device has a relatively thin film thickness and is in the range of 1.0 nm or more and 4.5 nm or less, electrons easily move over the energy barrier of the barrier layer to the adjacent well layer, thereby even The energy band structure produces strain, and the electron injection efficiency in the light-emitting layer can also be improved.

Further, in the nitride semiconductor light-emitting device according to the first aspect of the present invention, the two well layers have a relatively high first indium composition in a range of 0.15 or more and 0.50 or less. Thus, with respect to the well layer having a higher indium composition, it is considered that in order to prevent the crystallinity of the barrier layer from being lowered, a barrier layer having a relatively thick film thickness is desirable, but the nitride of the first aspect of the present invention The light-emitting layer (multiple quantum well structure) of the semiconductor light-emitting device is disposed on a semipolar surface in which the indium is doped or grown in a range of angles in which the growth of InGaN is improved, so that it is relatively constant as in the range of 1.0 nm or more and 4.5 nm or less. The barrier layer of a thin film thickness can also adjust the crystallinity while maintaining the crystal quality of the luminescent layer. In addition, when the film thickness of the barrier layer is less than 1.0 nm, the recovery of crystallinity is insufficient, and the crystallinity of the light-emitting layer is lowered.

In the first aspect of the invention, it is preferable that the film thickness of the barrier layer is The film thickness of the well layer is less than or equal to the value obtained by 0.50 nm and is greater than or equal to the value obtained by subtracting 0.50 nm from the film thickness of the well layer. The film thickness of the barrier layer has a thickness equivalent to that of the well layer. Therefore, even if the energy band structure of the light-emitting layer generates a strain due to the piezoelectric polarization opposite to the c-plane direction, since the electron easily moves over the energy barrier of the barrier layer to the adjacent well layer, the light-emitting layer The reduction in the efficiency of electron injection is also suppressed.

In the first aspect of the invention, it is preferable that the barrier layer contains InGaN, and the barrier layer has a second indium composition in a range of 0.01 or more and 0.10 or less. Since the second indium composition of the barrier layer is in the range of 0.01 or more and 0.10 or less, the energy band gap of the fault wall layer is lowered. Therefore, even if the energy band structure of the light-emitting layer generates strain due to piezoelectric polarization opposite to the c-plane direction, since electrons easily pass over the energy barrier of the barrier layer, the electron injection efficiency in the light-emitting layer is lowered. inhibition. When the second indium composition of the barrier layer exceeds 0.10, the crystallinity of the barrier layer and the light-emitting layer may be lowered.

In the first aspect of the invention, it is preferable that the n-type gallium nitride-based semiconductor layer includes an InGaN layer, and the light-emitting layer is provided on the InGaN layer, and is inside the n-type gallium nitride-based semiconductor layer. The surface of the InGaN layer on the support substrate side has misfit dislocations along the c-axis orthogonal to the surface of the InGaN layer and including the hexagonal nitride semiconductor The reference plane extends in a direction orthogonal to the reference axis and the c-axis shared by the surface of the InGaN layer, and the density of the misfit dislocations is in a range of 5 × 10 ³ cm ^-1 or more and 1 × 10 ⁵ cm ^-1 or less. . An InGaN layer is disposed between the support substrate and the light-emitting layer, and a relatively high density of misfit dislocations is generated on the surface of the support substrate side of the InGaN layer. Therefore, with the InGaN layer, the strain on the supporting substrate is alleviated, so the strain contained in the well layer is also lowered. Thereby, even if the energy band structure of the light-emitting layer generates strain due to piezoelectric polarization opposite to the c-plane direction, since the piezoelectric polarization is lowered, the decrease in electron injection efficiency in the light-emitting layer is suppressed. When the density of the misfit dislocation exceeds 1 × 10 ⁵ cm ^-1 , the adverse effect of the defect also affects the luminescent layer, resulting in a decrease in luminous efficiency.

In the first aspect of the invention, it is preferable that the InGaN layer has a third indium composition in a range of 0.03 or more and 0.05 or less. Since the indium composition of the InGaN layer which is provided between the support substrate and the light-emitting layer to relax the strain on the support substrate is in the range of 0.03 or more and 0.05 or less, the strain on the support substrate is sufficiently alleviated. Thereby, even if the energy band structure of the light-emitting layer generates strain due to piezoelectric polarization opposite to the c-plane direction, the electron injection efficiency in the light-emitting layer is effectively suppressed from being lowered. When the third indium composition of the InGaN layer exceeds 0.05, the density of misfit dislocations becomes excessively high, resulting in a decrease in luminous efficiency.

In the first aspect of the invention, it is preferable that the second indium composition increases from a side of the p-type gallium nitride based semiconductor layer toward a side of the n-type gallium nitride based semiconductor layer. Since the indium composition of the barrier layer increases from the side of the p-type gallium nitride based semiconductor layer toward the side of the n-type gallium nitride based semiconductor layer, the indium composition and p-type nitridation on the side of the n-type gallium nitride based semiconductor layer The band gap of the barrier layer is lower in the side of the n-type gallium nitride based semiconductor layer than when the indium composition on the side of the gallium-based semiconductor layer is the same. Thereby, even if the energy band structure of the light-emitting layer generates strain due to piezoelectric polarization opposite to the c-plane direction, since the energy band gap of the barrier layer is changed by relaxing the strain, the electrons are more likely to be The energy barrier of the barrier layer is passed, so that the reduction of the electron injection efficiency in the light-emitting layer is also suppressed.

In the first aspect of the invention, it is preferable that the inclination angle of the main surface with respect to the c-plane is in a range of 63 degrees or more and 80 degrees or less. When the inclination angle of the principal surface is in the range of 63 degrees or more and 80 degrees or less, in particular, the incorporation or growth mode of indium becomes good for the growth of InGaN, so that even a barrier layer having a thin film thickness can be crystallized. Sexual recovery, thereby suppressing a decrease in luminous efficiency. As a result, the luminous efficiency is not lowered, and excellent electron injection efficiency can be provided.

In the first aspect of the invention, it is preferable that the first indium composition is in a range of 0.24 or more and 0.40 or less. Since the indium composition of the well layer is in the range of 0.24 or more and 0.40 or less, the light-emitting layer emits light having an emission wavelength of 500 nm or more and 570 nm or less. In this way, when the indium composition of the well layer is relatively large, the energy band deviation between the well layer and the barrier layer is relatively large, so the influence of the strain of the energy band structure due to piezoelectric polarization becomes significant, but even In the case of the above, it is also possible to sufficiently suppress the decrease in the injection efficiency of electrons in the light-emitting layer.

In the first aspect of the invention, it is preferable that the second indium composition is in a range of 0.01 or more and 0.06 or less. Since the indium composition of the barrier layer is in the range of 0.01 or more and 0.06 or less, the decrease in crystallinity is sufficiently suppressed.

In the first aspect of the invention, it is preferable that a thickness of the barrier layer is in a range of 1.0 nm or more and 3.5 nm or less. Since the film thickness of the barrier layer is in the range of 1.0 nm or more and 3.5 nm or less, it is relatively thin. Thereby, even if the strain is generated in the energy band structure, electrons easily pass over the energy barrier of the barrier layer. By moving to the adjacent well layer, it is also possible to sufficiently suppress the decrease in the injection efficiency of electrons in the light-emitting layer.

A second aspect of the invention relates to a method of producing a nitride semiconductor light-emitting device. The manufacturing method includes the steps of: (a) preparing a substrate including a hexagonal nitride semiconductor and having a principal surface inclined from a c-plane of the hexagonal nitride semiconductor in a predetermined direction; (b) being on the substrate (n) growing a light-emitting layer containing a gallium nitride-based semiconductor on the n-type gallium nitride-based semiconductor layer; and (d) growing the light-emitting layer on the light-emitting layer; A gallium nitride based semiconductor layer. In the manufacturing method, the light-emitting layer includes at least a first well layer, a second well layer, and at least one barrier layer, and sequentially grows on the n-type gallium nitride-based semiconductor layer in the step of growing the light-emitting layer In the first well layer, the barrier layer, and the second well layer, the first well layer and the second well layer include InGaN, and the first well layer and the second well layer have a range of 0.15 or more and 0.50 or less. In the first indium composition, the inclination angle of the main surface with respect to the c-plane is in a range of 50 degrees or more and 80 degrees or less, and a range of 130 degrees or more and 170 degrees or less, and the film thickness of the barrier layer is 1.0 nm or more. Range below 4.5 nm.

In the nitride semiconductor light-emitting device according to the second aspect of the present invention, the main surface of the support substrate is in a range of 50 degrees or more and 80 degrees or less, and a semipolar surface in a range of 130 degrees or more and 170 degrees or less. A nitride semiconductor light-emitting device according to a second aspect of the invention includes a light-emitting layer of a multiple quantum well structure provided on the main surface. The direction of piezoelectric polarization generated in a well layer of a multiple quantum well structure disposed on a semipolar surface as described above The direction of the piezoelectric polarization of the well layer disposed on the c-plane is opposite, whereby the energy band structure of the multiple quantum well structure disposed on the semi-polar surface produces a strain different from that of the c-plane. The injection efficiency of electrons in the light-emitting layer is lowered due to the strain of the energy band structure. However, since the barrier layer of the nitride semiconductor light-emitting device according to the second aspect of the present invention has a relatively thin film thickness and is in the range of 1.0 nm or more and 4.5 nm or less, electrons easily move over the energy barrier of the barrier layer to move adjacent to each other. The well layer can improve the injection efficiency of electrons in the light-emitting layer even if strain is generated in the energy band structure.

Further, in the nitride semiconductor light-emitting device of the second aspect of the invention, the two well layers have a relatively high first indium composition in a range of 0.15 or more and 0.50 or less. Thus, with respect to the well layer having a higher indium composition, it is considered that the crystallinity of the barrier layer is not lowered, and it is desirable that the barrier layer having a relatively thick film thickness is nitrided by the nitride semiconductor according to the second aspect of the present invention. The light-emitting layer (multiple quantum well structure) of the element is provided on the semipolar surface in which the indium is doped or grown in a range in which the growth of InGaN is good, so that it is relatively constant as in the range of 1.0 nm or more and 4.5 nm or less. The barrier layer of a thin film thickness can also adjust the crystallinity to maintain the crystal quality of the light-emitting layer. In addition, when the film thickness of the barrier layer is less than 1.0 nm, the recovery of crystallinity is insufficient, and the crystallinity of the light-emitting layer is lowered.

In a second aspect of the present invention, preferably, the film thickness of the barrier layer is a value obtained by adding a film thickness of the well layer to a value of 0.50 nm or less and subtracting 0.50 nm from a film thickness of the well layer. the above. The film thickness of the barrier layer has a thickness equivalent to that of the well layer. Thus, even in the band of the luminescent layer The structure produces a strain due to piezoelectric polarization opposite to the c-plane direction, and since electrons easily move over the energy barrier of the barrier layer to the adjacent well layer, the decrease in electron injection efficiency in the light-emitting layer is also suppressed.

In the second aspect of the invention, it is preferable that the barrier layer contains InGaN, and the barrier layer has a second indium composition in a range of 0.01 or more and 0.10 or less. Since the second indium composition of the barrier layer is in the range of 0.01 or more and 0.10 or less, the energy band gap of the fault wall layer is lowered. Therefore, even if the energy band structure of the light-emitting layer generates strain due to piezoelectric polarization opposite to the c-plane direction, since electrons easily pass over the energy barrier of the barrier layer, the electron injection efficiency in the light-emitting layer is lowered. inhibition. When the second indium composition of the barrier layer exceeds 0.10, the crystallinity of the barrier layer and the light-emitting layer may be lowered.

In a second aspect of the present invention, preferably, the n-type gallium nitride based semiconductor layer includes an InGaN layer, and the light emitting layer is provided on the InGaN layer, and is inside the n-type gallium nitride based semiconductor layer. The surface of the InGaN layer on the substrate side has misfit dislocations along a reference plane orthogonal to the surface of the InGaN layer and including the c-axis of the hexagonal nitride semiconductor. The reference axis shared by the surface of the InGaN layer and the direction orthogonal to the c-axis extend, and the density of the misfit dislocations is in the range of 5 × 10 ³ cm ^-1 or more and 1 × 10 ⁵ cm ^-1 or less. An InGaN layer is provided between the substrate and the light-emitting layer, and a misalignment dislocation having a relatively high density is generated on the surface of the substrate side of the InGaN layer. Therefore, the strain on the substrate is alleviated by the InGaN layer, so the strain contained in the well layer is also lowered. Thereby, even if the energy band structure of the light-emitting layer generates strain due to piezoelectric polarization opposite to the c-plane direction, since the piezoelectric polarization is lowered, the decrease in electron injection efficiency in the light-emitting layer is suppressed. When the density of the misfit dislocation exceeds 1 × 10 ⁵ cm ^-1 , the adverse effect of the defect also affects the luminescent layer, resulting in a decrease in luminous efficiency.

In the second aspect of the invention, it is preferable that the InGaN layer has a third indium composition in a range of 0.03 or more and 0.05 or less. Since the indium composition of the InGaN layer which is provided between the substrate and the light-emitting layer to moderate the strain on the substrate is in the range of 0.03 or more and 0.05 or less, the strain on the substrate is sufficiently alleviated. Thereby, even if the energy band structure of the light-emitting layer generates strain due to piezoelectric polarization opposite to the c-plane direction, the electron injection efficiency in the light-emitting layer is effectively suppressed from being lowered. When the third indium composition of the InGaN layer exceeds 0.05, the density of misfit dislocations becomes excessively high, resulting in a decrease in luminous efficiency.

In the second aspect of the invention, it is preferable that the second indium composition increases from a side of the p-type gallium nitride based semiconductor layer toward a side of the n-type gallium nitride based semiconductor layer. Since the indium composition of the barrier layer increases from the side of the p-type gallium nitride based semiconductor layer toward the side of the n-type gallium nitride based semiconductor layer, the indium composition and p-type nitridation on the side of the n-type gallium nitride based semiconductor layer The band gap of the barrier layer is lower in the side of the n-type gallium nitride based semiconductor layer than when the indium composition on the side of the gallium-based semiconductor layer is the same. Thereby, even if the energy band structure of the light-emitting layer generates a strain due to the piezoelectric polarization opposite to the c-plane direction, since the energy band gap of the barrier layer is changed by relaxing the strain, the electron easily passes over the barrier layer. The energy barrier is such that the reduction in the injection efficiency of electrons in the light-emitting layer is also suppressed.

In the second aspect of the invention, it is preferable that the inclination angle of the main surface with respect to the c-plane is in a range of 63 degrees or more and 80 degrees or less. When the main face is tilted When the angle is in the range of 63 degrees or more and 80 degrees or less, in particular, the incorporation or growth mode of indium is good for the growth of InGaN. Therefore, even if the barrier layer is thin, the crystallinity can be restored. It can suppress the decrease in luminous efficiency. As a result, the luminous efficiency is not lowered, and excellent electron injection efficiency can be provided.

In the second aspect of the invention, it is preferable that the first indium composition is in a range of 0.24 or more and 0.40 or less. Since the indium composition of the well layer is in the range of 0.24 or more and 0.40 or less, the light-emitting layer emits light having an emission wavelength of 500 nm or more and 570 nm or less. In this way, when the indium composition of the well layer is relatively large, the energy band deviation between the well layer and the barrier layer is relatively large, so the influence of the strain of the energy band structure due to piezoelectric polarization becomes significant, but even In the case as described above, it is also possible to sufficiently suppress the decrease in the injection efficiency of electrons in the light-emitting layer.

In the second aspect of the invention, it is preferable that the second indium composition is in a range of 0.01 or more and 0.06 or less. Since the indium composition of the barrier layer is in the range of 0.01 or more and 0.06 or less, the decrease in crystallinity is sufficiently suppressed.

In the second aspect of the invention, it is preferable that the barrier layer has a film thickness of 1.0 nm or more and 3.5 nm or less. Since the film thickness of the barrier layer is in the range of 1.0 nm or more and 3.5 nm or less, it is relatively thin. Thereby, even if strain is generated in the energy band structure, electrons easily move to the adjacent well layer beyond the energy barrier of the barrier layer, so that the electron injection efficiency in the light-emitting layer can be sufficiently suppressed from being lowered.

According to the present invention, it is possible to provide a light-emitting surface which is disposed on a semi-polar surface A nitride semiconductor light-emitting device in which the rise in the bias voltage is suppressed and a method of manufacturing the nitride semiconductor light-emitting device.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and the repeated description is omitted. FIG. 1 is a view schematically showing a structure of a light-emitting element 11 which is a nitride semiconductor light-emitting device of the embodiment and a structure of an epitaxial substrate for the light-emitting element 11. The light-emitting element 11 shown in FIG. 1 is exemplified as a light-emitting diode (LED) for evaluating the spontaneous emission light of an epitaxial structure (applied to an epitaxial structure of an LD) facing a laser diode (LD). It can also be LD.

The light-emitting element 11 is shown in part (a) of Fig. 1, and the epitaxial substrate EP1 for the light-emitting element 11 is shown in part (b) of Fig. 1 . The epitaxial substrate EP1 has the same epitaxial layer structure as the epitaxial layer structure (the support base 13, the n-type gallium nitride semiconductor layer 15, the light-emitting layer 17, and the p-type gallium nitride semiconductor layer 19) of the light-emitting element 11 . In the following description, the semiconductor layer constituting the light-emitting element 11 will be described. The epitaxial substrate EP1 includes semiconductor layers (semiconductor films) corresponding to the semiconductor layers constituting the light-emitting elements 11, and the description for the light-emitting elements 11 is applied to the corresponding semiconductor layers.

The orthogonal coordinate system S and the crystal coordinate system CR are shown in FIG. The crystal coordinate system CR is a coordinate system for indicating the crystal axes (c-axis, a-axis, and m-axis) of the hexagonal nitride semiconductor supporting the substrate 13. The x-axis and the a-axis of the hexagonal nitride semiconductor supporting the substrate 13 are in the same direction, and the YZ plane is the m-axis and the supporting substrate of the hexagonal nitride semiconductor supported by the substrate 13. The c-axis of the hexagonal nitride semiconductor of 13 is parallel to the plane defined.

As shown in part (a) of Fig. 1, the light-emitting element 11 includes a support substrate 13, an n-type gallium nitride-based semiconductor layer 15, a light-emitting layer 17, a p-type gallium nitride-based semiconductor layer 19, a p-side electrode 21, and an insulating film. 23 and n side electrode 25. The n-type gallium nitride based semiconductor layer 15 includes an n-type GaN layer 15a, an n-type cladding layer 15b, and an n-type guiding layer 15c. The light-emitting layer 17 has a multiple quantum well structure composed of a well layer 17a, a barrier layer 17b, and a well layer 17c. Furthermore, the luminescent layer 17 can also have a multiple quantum well structure comprising more than three well layers. The p-type gallium nitride based semiconductor layer 19 includes a p-type guiding layer 19a, a p-type cladding layer 19b, and a p-type contact layer 19c. The n-type gallium nitride based semiconductor layer 15, the light-emitting layer 17, and the p-type gallium nitride based semiconductor layer 19 are formed on the support substrate 13 by epitaxial growth. On the main surface 13a of the support substrate 13, an n-type GaN layer 15a, an n-type cladding layer 15b, an n-type guiding layer 15c, a well layer 17a, a barrier layer 17b, a well layer 17c, and a p-type guiding layer are sequentially disposed. 19a, p-type cladding layer 19b, p-type contact layer 19c.

The c-plane of the support base 13 extends along the surface SC. The main surface 13a of the support base 13 is oriented in the direction of the Z-axis and extends in the direction in which the XY plane extends. The main surface 13a is inclined from the c-plane in a predetermined direction. The inclination angle α of the principal surface 13a is defined based on the c-plane (the (0001) plane, the plane SC shown in FIG. 1) of the hexagonal nitride semiconductor supporting the substrate 13. For example, the main surface 13a may be inclined at an inclination angle α toward the m-axis of the support base 13 with respect to the surface SC corresponding to the c-plane. The inclination angle α is defined by the angle formed by the normal vector VN of the principal surface 13a of the support base 13 and the c-axis vector VC representing the c-axis. The inclination angle α is in a range of 50 degrees or more and 80 degrees or less and a range of 130 degrees or more and 170 degrees or less. In particular, the tilt angle α can also be between 63 degrees and 80 degrees. The scope. The main surface 13a may be, for example, inclined from the c-plane toward the m-axis, and in particular, when the inclination angle α from the c-plane toward the m-axis is 75 degrees, the main surface 13a may be combined with the hexagonal nitrogen of the support substrate 13. The (20-21) faces of the semiconductors correspond. The c-axis vector VC corresponds to the normal vector of the (0001) plane.

On the main surface 13a, the light-emitting layer 17 is provided between the n-type gallium nitride-based semiconductor layer 15 and the p-type gallium nitride-based semiconductor layer 19. On the principal surface 13a, the n-type gallium nitride based semiconductor layer 15, the light-emitting layer 17, and the p-type gallium nitride based semiconductor layer 19 are sequentially arranged in the direction (Z-axis direction) of the normal vector VN. On the principal surface 13a, the n-type GaN layer 15a, the n-type cladding layer 15b, and the n-type guiding layer 15c included in the n-type gallium nitride based semiconductor layer 15 are along the direction of the normal vector VN (Z-axis direction) ) Arranged in order. On the principal surface 13a, the well layer 17a, the barrier layer 17b, and the well layer 17c included in the light-emitting layer 17 are sequentially arranged in the direction (Z-axis direction) of the normal vector VN. On the principal surface 13a, the p-type guiding layer 19a, the p-type cladding layer 19b, and the p-type contact layer 19c included in the p-type gallium nitride based semiconductor layer 19 are along the direction of the normal vector VN (Z-axis direction) ) Arranged in order.

The support substrate 13 may comprise, for example, GaN. Since GaN is a gallium nitride-based semiconductor of a binary compound, it can provide a good crystal quality and a stable main surface of the substrate. The support base 13 may contain, in addition to GaN, a hexagonal nitride semiconductor such as GaN, InGaN, or AlGaN.

The n-type gallium nitride based semiconductor layer 15 includes an n-type gallium nitride based semiconductor. The n-type dopant of the n-type gallium nitride based semiconductor layer 15 is, for example, germanium (Si). The n-type gallium nitride based semiconductor layer 15 is provided on the support substrate 13. The n-type GaN layer 15a of the n-type gallium nitride based semiconductor layer 15 is connected to the support base 13 via the main surface 13a. The n-type GaN layer 15a includes n-type GaN. N-type cladding layer 15b and n-type The GaN layer 15a is connected. The n-type cladding layer 15b includes an n-type nitride-based semiconductor such as an n-type InAlGaN. The n-type guiding layer 15c is connected to the n-type cladding layer 15b. The n-type guiding layer 15c may include an n-type gallium nitride-based semiconductor such as n-type GaN or n-type InGaN.

The n-type guiding layer 15c may include two layers. Of the two layers, the first layer includes an n-type GaN guiding layer 15d of n-type, and the second layer includes an n-type InGaN guiding layer 15e of an n-type InGaN, an n-type GaN guiding layer 15d is connected to the n-type cladding layer 15b, the n-type InGaN guiding layer 15e is disposed on the n-type GaN guiding layer 15d, and the n-type InGaN guiding layer 15e is connected to the n-type GaN guiding layer 15d. The surface 15f of the support base 13 side of the n-type InGaN guiding layer 15e inside the n-type guiding layer 15c (the interface between the n-type GaN guiding layer 15d and the n-type InGaN guiding layer 15e) contains misfit dislocations. The misfit dislocation is along a reference axis and a c-axis which are orthogonal to the surface 15f of the n-type InGaN guiding layer 15e and include a c-axis reference plane (a surface extending along the a-plane) and the surface 15f. The direction of intersection (along the a-axis) extends. The density of the misfit dislocations is in the range of 5 × 10 ³ cm ^-1 or more and 1 × 10 ⁵ cm ^-1 or less. The indium composition (third indium composition) of the n-type InGaN guiding layer 15e is in the range of 0.03 or more and 0.05 or less.

The luminescent layer 17 has a multiple quantum well configuration. The light-emitting layer 17 contains indium and may include a gallium nitride-based semiconductor such as InGaN. The well layer 17a is connected to the n-type InGaN guiding layer 15e of the n-type guiding layer 15c. The well layer 17a contains indium and may include a gallium nitride-based semiconductor such as InGaN. The barrier layer 17b is connected to the well layer 17a. The barrier layer 17b is disposed between the well layer 17a and the well layer 17c. The barrier layer 17b contains indium and may include a gallium nitride-based semiconductor such as InGaN. The well layer 17c is connected to the barrier layer 17b. The well layer 17c contains indium and may include a gallium nitride based semiconductor such as InGaN. well Any of the band gap of the layer 17a and the band gap of the well layer 17c is smaller than the band gap of the barrier layer 17b. Furthermore, the luminescent layer 17 may comprise more than three well layers and more than two barrier layers.

The indium composition (first indium composition) of the well layer 17a is in the range of 0.15 or more and 0.50 or less. The indium composition of the well layer 17a is, for example, about 0.30, but may be about 0.25 or about 0.35. The film thickness of the well layer 17a is, for example, about 2.5 nm.

The indium composition (second indium composition) of the barrier layer 17b is in the range of 0.01 or more and 0.10 or less, but may be in the range of 0.01 or more and 0.06 or less. The film thickness of the barrier layer 17b may be equal to or less than the value obtained by adding the film thickness of the well layer 17a or the well layer 17c to 0.5 nm and subtracting 0.5 nm from the film thickness of the well layer 17a or the well layer 17c. Specifically, the film thickness of the barrier layer 17b is in the range of 4.5 nm or less, but the upper limit of the film thickness of the barrier layer 17b may be set to any of 4.0 nm, 3.5 nm, and 3.0 nm. For example, the film thickness of the barrier layer 17b may be in the range of 1.0 nm or more and 3.5 nm or less. Further, the film thickness of the barrier layer 17b may be 1.0 nm or more. The barrier layer 17b may have an indium composition that increases in the direction from the p-type gallium nitride based semiconductor layer 19 toward the n-type gallium nitride based semiconductor layer 15.

The indium composition (first indium composition) of the well layer 17c is in the range of 0.15 or more and 0.50 or less. The indium composition of the well layer 17c is, for example, about 0.30, but may be about 0.25 or about 0.35. The film thickness of the well layer 17c is, for example, about 2.5 nm. The film thickness of the well layer 17c may be, for example, 1 nm to 5 nm.

The light-emitting wavelength of the light-emitting layer 17 is such that the indium composition of the well layer (well layer 17a, well layer 17c) of the light-emitting layer 17 is in the range of 0.15 or more and 0.50 or less, so it is 480. Above nm above 600 nm. Further, the light emission wavelength of the light-emitting layer 17 may be set to be 500 nm or more and 570 nm or less. In the case of an emission wavelength of 500 nm or more and 570 nm or less, the indium composition of the well layer (well layer 17a, well layer 17c) of the light-emitting layer 17 is in the range of 0.24 or more and 0.40 or less.

The p-type gallium nitride based semiconductor layer 19 includes a p-type gallium nitride based semiconductor. The p-type dopant of the p-type gallium nitride based semiconductor layer 19 is, for example, magnesium (Mg). The p-type gallium nitride based semiconductor layer 19 is connected to the well layer 17c of the light-emitting layer 17. The p-type guiding layer 19a is disposed on the light-emitting layer 17 and is connected to the light-emitting layer 17. The p-type guiding layer 19a includes one or a plurality of p-type gallium nitride-based semiconductor layers. The p-type guiding layer 19a includes an undoped (ud, undope) InGaN layer. The undoped InGaN layer is connected to the well layer 17c. The p-type guiding layer 19a includes a p-type InGaN layer disposed on the undoped InGaN layer. The p-type InGaN layer is connected to the undoped InGaN layer. The p-type guiding layer 19a includes a p-type GaN layer provided on the p-type InGaN layer. The p-type GaN layer is connected to the p-type InGaN layer.

The p-type cladding layer 19b may include, for example, p-type InAlGaN. The p-type cladding layer 19b is provided on the p-type GaN layer included in the p-type guiding layer 19a, and is connected to the p-type GaN layer.

The p-type contact layer 19c is provided on the p-type cladding layer 19b and is connected to the p-type cladding layer 19b. The p-type contact layer 19c may include, for example, p-type GaN.

In the case where the light-emitting element 11 is an LED, as shown in FIG. 1, the p-side electrode 21 is provided on the p-type contact layer 19c. The p-side electrode 21 may contain, for example, Pd. The n-side electrode 25 is provided on the back surface 13b of the support base 13. The n-side electrode 25 covers the back surface 13b. The n-side electrode 25 is connected to the support base 13 via the back surface 13b.

Further, when the light-emitting element 11 is an LD, the p-type gallium nitride-based semiconductor layer 19 includes a ridge-shaped portion, and the p-side electrode 21 may include, for example, an electrode containing Ni/Au and a pad electrode containing Ti/Au. The n-side electrode 25 may include, for example, an electrode containing Ti/Al and a pad electrode containing Ti/Au. Further, a dielectric multilayer film is provided on the end face of the resonator. The dielectric multilayer film may comprise, for example, SiO ₂ /TiO ₂ .

In the light-emitting element 11 having the above-described configuration, the main surface 13a of the support base 13 is a semipolar surface having a range of 50 degrees or more and 80 degrees or less and a range of 130 degrees or more and 170 degrees or less, and the light-emitting element 11 is provided. A light-emitting layer 17 comprising a plurality of quantum well structures disposed on the major surface 13a. The direction of piezoelectric polarization of the light-emitting layer 17 generated in the multiple quantum well structure provided on the semipolar surface as described above becomes the direction of piezoelectric polarization generated from the well layer 17a and the well layer 17c provided on the c-plane In the opposite direction, the energy band structure of the multiple quantum well structure disposed on the semi-polar surface produces a strain different from that on the c-plane. The injection efficiency of electrons in the light-emitting layer 17 is lowered due to the strain of the energy band structure. The direction of piezoelectric polarization generated in the light-emitting layer 17 is the same direction as the direction of the p-region of the self-luminous element 11 toward the n-region. It can be understood from the energy band diagram shown in FIG. 2 that the electron E in the well layer 17a is opposite to the direction of the p-type gallium nitride based semiconductor layer (p side) 19 and the barrier V2 (based on the quantum energy level Q1). The value) is opposed to the barrier V1 (the value based on the quantum energy level Q1) with respect to the direction of the n-type gallium nitride based semiconductor layer 15 (n side), and the strain due to the energy band structure related to the piezoelectric polarization The barrier V2 of the well layer 17a is higher than the barrier V1 of the well layer 17a. The barrier V2 that is higher than the barrier rib V1 prevents the electrons E from the n-type gallium nitride based semiconductor layer 15 from moving over the well layer 17a to the well layer 17c beyond the energy barrier of the barrier layer 17b. As a result, the higher barrier of the thicker barrier layer The wall V2 has a possibility of lowering the injection efficiency in the light-emitting layer 17. However, since the film thickness of the barrier layer 17b of the light-emitting element 11 is relatively thin and is in the range of 4.5 nm or less, the electron injection efficiency and the thick barrier in the light-emitting layer 17 having the strain as described above can be constructed in the energy band. Compared to the luminescent layer of the quantum well structure of the layer, it can be improved. Referring to the energy band diagram shown in FIG. 2, the film thickness L of the barrier layer 17b is relatively thin in the range of 1.0 nm or more and 4.5 nm or less, so that the electron E from the n-type gallium nitride based semiconductor layer 15 is easy. Since the well layer 17a moves over the energy barrier of the barrier layer 17b to the well layer 17c, the injection efficiency in the light-emitting layer 17 can be suppressed from being lowered. Here, the thickness of the well layer 17a to the well layer 17c may range from 1 nm to 5 nm.

Further, the two well layers (well layer 17a and well layer 17c) of the light-emitting element 11 have a relatively high indium composition in the range of 0.15 or more and 0.50 or less. Thus, with respect to the well layer 17a and the well layer 17c having a higher indium composition, it is considered that the crystallinity of the growth of the barrier layer 17b is not completely deteriorated in the growth of the well layer, and it is desirable that the film thickness is relatively relatively high. Thick barrier layer 17b. However, since the light-emitting layer 17 of the light-emitting element 11 is disposed on the semi-polar surface of the angle range in which the indium of the grown growth of InGaN is good or the growth mode is good, the barrier layer 17b of the film thickness in the range of 4.5 nm or less can be adjusted. Crystallinity. In this manner, the crystal quality of the light-emitting layer 17 including the relatively thin barrier layer can be maintained.

In the case where the film thickness of the barrier layer 17b is less than 1.0 nm, there is a case where sufficient crystallinity is not recovered in the barrier layer 17b when the crystal grows, and the crystallinity of the light-emitting layer 17 is lowered. Moreover, referring to FIG. 2, in the energy band structure in which strain is generated by piezoelectric polarization, the energy band of the hole H is biased. The shift is relatively small, so that the energy band structure containing strain hardly affects the injection efficiency.

Moreover, the value L of the film thickness of the barrier layer 17b may be obtained by adding the film thickness of the well layer 17a or the well layer 17c to the value obtained by adding 0.50 nm and subtracting 0.50 nm from the film thickness of the well layer 17a or the well layer 17c. Above the value. In this case, the film thickness of the barrier layer 17b has a thickness equivalent to that of the well layer 17a or the well layer 17c. Thereby, even if the energy band structure of the light-emitting layer 17 contains the strain due to the piezoelectric polarization opposite to the c-plane direction, the electrons easily move from the well layer 17a beyond the energy barrier of the barrier layer 17b having the same thickness as the well layer. Since the adjacent well layer 17b is formed, the decrease in the injection efficiency of electrons in the light-emitting layer 17 is also suppressed. Here, the thickness of the well layer 17a to the well layer 17c may range from 1 nm to 5 nm.

Further, when the barrier layer 17b contains InGaN, the barrier layer 17b may have an indium composition in a range of 0.01 or more and 0.1 or less. The barrier layer 17b having an indium composition in the range of 0.01 or more and 0.10 or less, because of the reduced barrier layer 17b, is caused by the piezoelectric polarization in the opposite direction to the c-plane due to the energy band structure of the light-emitting layer 17. The orientation of the strain surface changes the energy band gap of the barrier layer 17b in such a manner as to relax the strain, and electrons easily pass over the energy barrier of the barrier layer 17b, so that the decrease in the injection efficiency of electrons in the light-emitting layer 17 is suppressed. When the indium composition of the barrier layer 17b exceeds 0.10, the crystallinity of the barrier layer 17b and the light-emitting layer 17 is lowered.

Further, the n-type InGaN guiding layer 15e may have an indium composition in a range of 0.03 or more and 0.05 or less. The n-type InGaN guiding layer 15e provided between the supporting substrate 13 and the light-emitting layer 17 has a relaxation strain of 0.03 or more and 0.05 or less. When the composition of indium is in the range, the strain contained in the light-emitting layer 17 is sufficiently alleviated. Thereby, in the energy band structure of the light-emitting layer 17 including the strain due to the piezoelectric polarization opposite to the c-plane direction, the decrease in the electron injection efficiency in the light-emitting layer 17 is effectively suppressed. Further, when the indium composition of the n-type InGaN guiding layer 15e exceeds 0.05, there is a possibility that the luminous efficiency is lowered.

Further, the n-type guiding layer 15c of the n-type gallium nitride based semiconductor layer 15 includes an n-type GaN guiding layer 15d, an n-type InGaN guiding layer 15e, and a surface (interface) 15f, and the n-type GaN guiding layer 15d is The n-type GaN guiding layer 15d and the n-type InGaN guiding layer 15e form a surface (interface) 15f between the supporting substrate 13 and the n-type InGaN guiding layer 15e, and can be formed on the n-type InGaN guiding layer 15e. A light emitting layer 17 is provided. There is a misfit dislocation on the surface 15f of the n-type InGaN guiding layer 15e away from the light-emitting layer 17 inside the n-type gallium nitride-based semiconductor layer 15. The misfit dislocation is along a reference axis and c shared by the reference plane of the c-axis of the hexagonal nitride semiconductor supporting the base 13 and the surface 15f orthogonal to the surface 15f of the n-type InGaN guiding layer 15e. The axis extends in a direction orthogonal to the axis, and the density of the misfit dislocations may be in the range of 5 × 10 ³ cm ^-1 or more and 1 × 10 ⁵ cm ^-1 or less. In this embodiment, an n-type InGaN guiding layer 15e is provided between the supporting substrate 13 and the light-emitting layer 17, and the n-type InGaN guiding layer 15e has an interface 15f close to the supporting substrate 13 and another surface close to the light-emitting layer 17. (Interface), a mismatch dislocation having a relatively high density is generated on the surface 15f. Therefore, the n-type InGaN guiding layer 15e and the misfit dislocations are moderated in the semiconductor layer strained by the n-type InGaN guiding layer 15e due to the support of the lattice constant of the substrate 13, so that the light-emitting layer 17 is The strain contained is also reduced. Thereby, the piezoelectric polarization is lowered in the light-emitting layer 17 which generates the strain due to the piezoelectric polarization opposite to the c-plane, and the decrease in the injection efficiency of electrons in the energy band structure of the light-emitting layer 17 is suppressed. When the density of misfit dislocations exceeds 1 × 10 ⁵ cm ^-1 , there is a possibility that the influence of the defects due to the dislocations affects the light-emitting layer 17 and the luminous efficiency is lowered. Further, when the indium composition of the n-type InGaN guiding layer 15e exceeds 0.05, the density of misfit dislocations becomes excessively high, resulting in a decrease in luminous efficiency.

Further, the indium composition of the barrier layer 17b can be increased from the p-type gallium nitride based semiconductor layer 19 toward the n-type gallium nitride based semiconductor layer 15.

The indium composition of the barrier layer is included from the p-type gallium nitride based semiconductor layer 19 toward the n-type nitridation since the n-type gallium nitride based semiconductor layer has a single indium composition over the p-type gallium nitride based semiconductor layer. The light-emitting layer 17 of the portion in which the gallium-based semiconductor layer 15 is increased in indium composition is a barrier of the band gap of the barrier layer 17b (the barrier in the interface near the n-type gallium nitride-based semiconductor layer 15) is moved relative to the self-well layer 17a to The electrons of the well layer 17b are lowered. Thus, with respect to the energy band structure of the light-emitting layer 17 which is strained by the piezoelectric polarization opposite to the c-plane direction, when the energy band gap of the barrier layer 17 is changed by the composition tilt, the electrons easily pass over the energy of the barrier layer 17b. The barrier is formed, so that the decrease in the injection efficiency of electrons in the light-emitting layer 17 is suppressed.

Further, the inclination angle α of the main surface 13a with respect to the c-plane may be in the range of 63 degrees or more and 80 degrees or less. When the inclination angle α of the principal surface 13a is in the range of 63 degrees or more and 80 degrees or less, in particular, the incorporation or growth mode of indium becomes good for the growth of InGaN, and thus crystallizes in the growth of the barrier layer having a thin film thickness. The recovery of sex is made possible, thereby suppressing the decrease in luminous efficiency. As a result, the luminous efficiency is not lowered, and excellent electron injection efficiency can be provided.

Further, the indium composition of the well layer 17a and the well layer 17c may be in the range of 0.24 or more and 0.40 or less. Since the indium composition of the well layer 17a and the well layer 17c is in the range of 0.24 or more and 0.40 or less, the light-emitting layer 17 emits light having an emission wavelength of 500 nm or more and 570 nm or less. Thus, in the light-emitting layer 17 having a relatively large indium composition, the energy band offset of the well layer 17a and the well layer 17c and the barrier layer 17b is relatively large, and thus the influence of the piezoelectric polarization on the energy band structure is caused. Become remarkable. However, even in the case as described above, the decrease in the injection efficiency of electrons in the light-emitting layer 17 can be sufficiently suppressed.

Further, the indium composition of the barrier layer 17b may be in the range of 0.01 or more and 0.06 or less. Since the indium composition of the barrier layer 17b is in the range of 0.01 or more and 0.06 or less, the above-described decrease in crystallinity is sufficiently suppressed.

Further, the film thickness of the barrier layer 17b may be in the range of 1.0 nm or more and 3.5 nm or less. Since the film thickness of the barrier layer 17b is in the range of 1.0 nm or more and 3.5 nm or less, it is relatively thin. Thereby, even if strain is generated in the energy band structure, electrons easily move from the well layer 17a to the adjacent well layer 17b beyond the energy barrier of the barrier layer 17b, so that the electron injection efficiency in the light-emitting layer 17 can be sufficiently suppressed from being lowered. .

As shown in part (b) of FIG. 1, the epitaxial substrate EP1 of the light-emitting element 11 includes a semiconductor layer (semiconductor film) corresponding to each of the above-described semiconductor layers of the light-emitting element 11, and the description for the above-described light-emitting element 11 is suitable for the corresponding one. The semiconductor layer. For example, the surface roughness of the epitaxial substrate EP1 has an arithmetic mean roughness of 1 nm or less in the range of 10 μm square.

Next, a method of manufacturing the light-emitting element 11 of the embodiment will be described with reference to FIGS. 3 and 4. Figure 3 is a view showing the manufacture of the light-emitting element 11 of the embodiment. A diagram of the main steps of the method. Fig. 4 is a view schematically showing a product in a main step of a method of manufacturing the light-emitting element 11 of the embodiment. In the epitaxial substrate EP shown in FIG. 4, a substrate product such as a p-side electrode and an n-side electrode is formed on the epitaxial substrate EP1 shown in part (b) of FIG. The epitaxial substrate EP is further produced by using the epitaxial substrate EP1, and the light-emitting element 11 is separated from the epitaxial substrate EP.

The epitaxial substrate EP and the light-emitting element 11 having the structure of the light-emitting element 11 were produced by the organometallic vapor phase growth method in accordance with the procedure shown in FIG. As a raw material for epitaxial growth, trimethylgallium, trimethylindium, trimethylaluminium, trimethylaluminium, ammonia (NH ₃ ), and decane (SiH _{4 ) are used.} And biscyclopentadienyl magnesium (Cp ₂ Mg).

In step S1, a substrate 13_1 (corresponding to the support substrate 13) having a main surface 13a_1 (corresponding to the main surface 13a) including a gallium nitride-based semiconductor is prepared. The substrate 13_1 is shown in part (a) of Fig. 4 and the like. The substrate 13_1 has a back surface 13b_1 (corresponding to the back surface 13b). The back surface 13b_1 is located on the opposite side of the main surface 13a_1. The main surface 13a_1 is mirror-polished (above, step S1).

Then, epitaxial growth was performed on the substrate 13_1 under the following conditions. First, in step S3, the substrate 13_1 is placed in the reaction furnace 10. A fixture made of quartz such as a quartz flow passage is disposed in the reaction furnace 10. When necessary, the heat treatment gas containing NH ₃ and H ₂ is supplied to the reaction furnace 10 at a temperature of about 1050 ° C and a furnace pressure of about 27 kPa, and heat treatment is performed for about 10 minutes. By this heat treatment, surface modification occurs on the main surface 13a_1 or the like (above, step S3).

After the heat treatment, in step S5, a gallium nitride semiconductor layer is grown on the substrate 13_1 to form an epitaxial substrate EP and an epitaxial substrate EP1. The ambient gas contains a carrier gas and a subflow gas. The ambient gas may comprise, for example, at least one of N ₂ and H ₂ . Step S5 includes the following steps S51, S52, and S53.

In step S51, the source gas and the ambient gas are supplied to the reaction furnace 10, and epitaxial growth is performed to form an n-type gallium nitride-based semiconductor layer 15_1 (corresponding to the n-type gallium nitride-based semiconductor layer 15). The n-type gallium nitride based semiconductor layer 15_1 is shown in part (a) of Fig. 4 and the like. The material gas used in the step S51 contains a raw material for the group III constituent element and the group V constituent element and an n-type dopant. First, the n-type GaN layer 15a_1 is grown on the main surface 13a_1 (corresponding to the n-type GaN layer 15a), and then the n-type GaN-based semiconductor layer 15b_1 is grown on the n-type GaN layer 15a_1 (with the n-type cladding layer 15b) Correspondingly, the n-type GaN-based semiconductor layer 15c_1 (corresponding to the n-type guiding layer 15c) is grown on the n-type GaN-based semiconductor layer 15b_1. The inclination angle of the surface 15_1a (the surface of the n-type GaN-based semiconductor layer 15c_1) of the n-type gallium nitride-based semiconductor layer 15_1 corresponds to the inclination angle of the principal surface 13a_1 (corresponding to the inclination angle α) (above, step S51). Further, the n-type GaN-based semiconductor layer 15c_1 may include two layers (corresponding to the n-type GaN guiding layer 15d and the n-type InGaN guiding layer 15e, respectively). Among the two layers constituting the n-type GaN-based semiconductor layer 15c_1, the surface on the substrate 13_1 side of the layer corresponding to the n-type InGaN guiding layer 15e (the interface constituting the two layers of the n-type GaN-based semiconductor layer 15c_1) contains a mismatch. Dislocation. The misfit dislocation is formed along the reference plane (the surface extending along the a-plane) orthogonal to the interface between the two layers constituting the n-type GaN-based semiconductor layer 15c_1 and including the c-axis and the n-type GaN-based semiconductor layer. The reference axis shared by the interface of the two layers of 15c_1 and the direction orthogonal to the c-axis (a-axis direction) extend. The density of the misfit dislocations is in the range of 5 × 10 ³ cm ^-1 or more and 1 × 10 ⁵ cm ^-1 or less. Among the two layers constituting the n-type GaN-based semiconductor layer 15c_1, the indium composition of the layer corresponding to the n-type InGaN guiding layer 15e is in the range of 0.03 or more and 0.05 or less.

In step S52, the source gas and the ambient gas are supplied to the reaction furnace 10, and epitaxial growth is performed to form a GaN-based quantum well layer 17_1 (corresponding to the light-emitting layer 17). The GaN-based quantum well layer 17_1 is shown in part (b) of Fig. 4 and the like. The material gas used in the step S52 contains a raw material for the group III constituent element and the group V constituent element. Step S52 includes the following steps S52a, S52b, and S52c. In the step S52a, the n-type GaN-based semiconductor layer 15c_1 is grown to form the GaN-based well layer 17a_1 (corresponding to the well layer 17a). In step S52b, the GaN-based well layer 17a_1 is grown to form a GaN-based barrier layer 17b_1 (corresponding to the barrier layer 17b). In the step S52c, the GaN-based barrier layer 17b_1 is grown to form the GaN-based well layer 17c_1 (corresponding to the well layer 17c) (above, step S52).

Then, in step S53, the source gas and the ambient gas are supplied to the reaction furnace 10, and epitaxial growth is performed to form a p-type gallium nitride based semiconductor layer 19_1 (corresponding to the p-type gallium nitride based semiconductor layer 19). The p-type gallium nitride based semiconductor layer 19_1 is shown in part (c) of Fig. 4 and the like. The material gas used in the step S53 contains a raw material for the group III constituent element and the group V constituent element and a p-type dopant. First, the p-type GaN-based semiconductor layer 19a_1 is grown on the GaN-based well layer 17c_1 (corresponding to the p-type guiding layer 19a), and then the p-type GaN-based semiconductor layer 19b_1 is grown on the p-type GaN-based semiconductor layer 19a_1 (and P-type coating In the case of the p-type GaN-based semiconductor layer 19b_1, the p-type GaN-based semiconductor layer 19c_1 is grown (corresponding to the p-type contact layer 19c) (above, step S53). The above steps S51, S52, and S53 are all performed to form the epitaxial substrate EP1, and the step S5 is ended.

Then, in steps S7 and S9, an n-side electrode and a p-side electrode are formed. First, step S7 and step S8 in the case of manufacturing the light-emitting element 11 of the LED will be described. In step S7, an n-side electrode and a p-side electrode are formed on the epitaxial substrate EP1 to form an epitaxial substrate EP. First, an insulating film (corresponding to the insulating film 23) is formed on the surface 19_1a of the p-type gallium nitride based semiconductor layer 19_1. Then, an opening (corresponding to the opening 23a) is provided in the insulating film by photolithography and dry etching, and the surface 19_1a of the p-type GaN-based semiconductor layer 19c_1 is exposed. Then, a p-side electrode (corresponding to the p-side electrode 21) is formed on the insulating film by vacuum evaporation. Then, after the back surface 13b_1 of the substrate 13_1 is polished, an n-side electrode (corresponding to the n-side electrode 25) is formed on the back surface 13b_1 by vacuum evaporation. The n-side electrode covers the polished back surface 13b_1. The substrate product is formed by the above process (above, step S7). Then, in step S9, the substrate product is separated to form the light-emitting element 11 (step S9).

Next, steps S7 and S9 in the case of manufacturing the light-emitting element 11 of the LD will be described. In step S7, first, a ridge-shaped portion is formed in the p-type gallium nitride based semiconductor layer 19_1 by dry etching. Here, the ridge-shaped portion extends in a direction in which the c-axis is projected on the main surface of the substrate. Then, an insulating film of SiO ₂ (corresponding to the insulating film 23) is formed on the side surface of the ridge-shaped portion, and the upper surface of the ridge-shaped portion is exposed to the opening of the insulating film. Here, the opening extends in a direction in which the c-axis is projected on the main surface of the substrate. Then, an electrode of Ni/Au is formed on the upper surface of the exposed ridge-shaped portion by vacuum deposition. Here, the electrode extends in a direction in which the c-axis is projected on the main surface of the substrate. Further, a pad electrode of Ti/Au was formed on the insulating film and the Ni/Au electrode by vacuum evaporation. The pad electrode of Ti/Au covers the insulating film and the Ni/Au electrode. The electrode of Ni/Au and the pad electrode of Ti/Au constitute a p-side electrode (corresponding to the p-side electrode 21). Then, the back surface 13b_1 of the substrate 13_1 is polished until, for example, the thickness of the epitaxial substrate EP1 is about 80 μm, and then an electrode of Ti/Al is formed on the back surface 13b_1 by vacuum deposition on the electrode of the Ti/Al. A pad electrode of Ti/Au was formed by vacuum evaporation. The electrode of Ti/Al and the pad electrode of Ti/Au constitute an n-side electrode (corresponding to the n-side electrode 25). The n-side electrode covers the back surface 13b_1 after polishing (above, step S7 in the case of LD). Then, in step S9, a laser bar is formed from the substrate product. A reflective film comprising a dielectric multilayer film (for example, SiO ₂ /TiO ₂ ) is formed on the end face of the resonator of the laser bar, and then separated into a light-emitting element 11 (step S9 in the case of LD above).

(Example)

Next, an experimental example of the light-emitting element 11 of the embodiment will be described. Fig. 5 is a view showing the configuration of an embodiment of the light-emitting element 11. The configuration shown in FIG. 5 corresponds to the configuration of the epitaxial substrate EP1. First, a GaN substrate (corresponding to the substrate 13_1 and the support substrate 13) having a semipolar main surface (corresponding to the main surface 13a_1 and the main surface 13a) is prepared. The main surface of the GaN substrate extends along a (20-21) plane inclined at 75 degrees from the c-plane toward the m-axis of the GaN substrate. Then, in the environment of NH ₃ and H ₂ , the GaN substrate was held at a temperature of about 1050 ° C for about 10 minutes, and pretreatment (thermal cleaning) was performed.

Then, after the thermal cleaning, the n-GaN layer is epitaxially grown at a temperature of about 1050 degrees Celsius (corresponding to the n-type GaN layer 15a_1 and the n-type GaN layer 15a). Then, the n-In _0.03 Al _0.14 Ga _0.83 N layer (corresponding to the n-type GaN-based semiconductor layer 15b_1 and the n-type cladding layer 15b) having a film thickness of about 2 μm is epitaxially grown to a temperature of about 840 degrees Celsius. . Then, at a temperature of about 840 ° C, an n-GaN layer having a thickness of about 200 nm is epitaxially grown (corresponding to the n-type GaN guiding layer 15d). Then, at a temperature of about 840 ° C, an n-In _J Ga _1-J N layer (corresponding to the n-type InGaN guiding layer 15e) having a thickness of about 150 nm is epitaxially grown.

Then, the temperature was lowered to about 790 degrees Celsius, and the In _0.30 Ga _0.70 N layer having a thickness of about 2.5 nm was epitaxially grown (corresponding to the GaN-based well layer 17a_1 and the well layer 17a). Then, the temperature is raised to about 840 degrees Celsius, and an In _K Ga _1-K N layer (corresponding to the GaN-based barrier layer 17b_1 and the barrier layer 17b) having an epitaxial growth film thickness L (nm) is formed. Then, the temperature is lowered to about 790 degrees Celsius, and the In _0.30 Ga _0.70 N layer (corresponding to the GaN-based well layer 17c_1 and the well layer 17c) having a thickness of about 2.5 nm is epitaxially grown.

Then, the temperature is raised to about 840 degrees Celsius, and the undoped In _0.02 Ga _0.98 N layer with a film thickness of about 50 nm is epitaxially grown, and then the epitaxial growth of p-In _0.02 Ga is about 100 nm. _0.98 N layer, then epitaxially growing a film thickness p-GaN layer of about 200 nm. An area of the p-In _0.02 Ga _0.98 N layer containing an undoped In _0.02 Ga _0.98 N layer having a film thickness of about 50 nm, a film thickness of about 100 nm, and a p-GaN layer having a film thickness of about 200 nm The p-type GaN-based semiconductor layer 19a_1 and the p-type guiding layer 19a correspond to each other. Then, at a temperature of about 840 ° C, a p-In _0.02 Al _0.07 Ga _0.91 N layer having a thickness of about 400 nm is epitaxially grown (corresponding to the p-type GaN-based semiconductor layer 19b_1 and the p-type cladding layer 19b) . Then, the temperature is raised to about 1000 degrees Celsius, and a p-GaN layer having a thickness of about 50 nm is epitaxially grown (corresponding to the p-type GaN-based semiconductor layer 19c_1 and the p-type contact layer 19c).

Hereinafter, the light-emitting element 11 (11_1) referred to as Experimental Example 1 will be described. In the light-emitting element 11_1, the indium composition J of the n-In _J Ga _1-J N layer corresponding to the n-type InGaN guiding layer 15e is 0.02, and In _K Ga corresponding to the GaN-based barrier layer 17b_1 and the barrier layer 17b The indium composition K of the _1-K N layer is 0.02, and the film thickness L of the In _K Ga _1-K N layer corresponding to the GaN-based barrier layer 17b_1 and the barrier layer 17b is 2.5 nm. The light-emitting element 11_1 manufactured in the case as described above was referred to as Experimental Example 1.

The light-emitting element 11 (11_2) referred to as Experimental Example 2 will be described. In the light-emitting element 11_2, the indium composition J of the n-In _J Ga _1-J N layer corresponding to the n-type InGaN guiding layer 15e is 0.02, and In _K Ga corresponding to the GaN-based barrier layer 17b_1 and the barrier layer 17b The indium composition K of the _1-K N layer was 0.04, and the film thickness L of the In _K Ga _1-K N layer corresponding to the GaN-based barrier layer 17b_1 and the barrier layer 17b was 2.5 nm. The light-emitting element 11_2 thus manufactured was used as Experimental Example 2. The difference between Experimental Example 2 and Experimental Example 1 is only the value of the indium composition K of the In _K Ga _1-K N layer corresponding to the GaN-based barrier layer 17b_1 and the barrier layer 17b.

The light-emitting element 11 (11_3) referred to as Experimental Example 3 will be described. In the light-emitting element 11_3, the indium composition J of the n-In _J Ga _1-J N layer corresponding to the n-type InGaN guiding layer 15e is 0.02, and In _K Ga corresponding to the GaN-based barrier layer 17b_1 and the barrier layer 17b The indium composition K of the _1-K N layer is continuously changed (increased) from 0.02 toward the n side from the p side to the value of 0.04, and In _K Ga _1-K N corresponding to the GaN barrier layer 17b_1 and the barrier layer 17b. The film thickness of the layer has a value L of 2.5 nm. The light-emitting element 11_3 manufactured in this manner was referred to as Experimental Example 3. The difference between Experimental Example 3 and Experimental Example 1 is only the value of the indium composition K of the In _K Ga _1-K N layer corresponding to the GaN-based barrier layer 17b_1 and the barrier layer 17b.

The light-emitting element 11 (11_4) referred to as Experimental Example 4 will be described. In the light-emitting element 11_4, the indium composition J of the n-In _J Ga _1-J N layer corresponding to the n-type InGaN guiding layer 15e is 0.04, and In _K Ga corresponding to the GaN-based barrier layer 17b_1 and the barrier layer 17b The indium composition K of the _1-K N layer is 0.02, and the film thickness L of the In _K Ga _1-K N layer corresponding to the GaN-based barrier layer 17b_1 and the barrier layer 17b is 2.5 nm. The light-emitting element 11_4 thus manufactured was referred to as Experimental Example 4. The difference between Experimental Example 4 and Experimental Example 1 is only the value of the indium composition J of the n-In _J Ga _1-J N layer corresponding to the n-type InGaN guiding layer 15e.

Experimental Examples 5 to 7 will be described. Further, with respect to Experimental Example 1, the film thickness L of the In _K Ga _1-K N layer corresponding to the GaN-based barrier layer 17b_1 and the barrier layer 17b was 0.5 nm. The light-emitting element 11_5 thus manufactured was referred to as Experimental Example 5. With respect to Experimental Example 1, the film thickness L of the In _K Ga _1-K N layer corresponding to the GaN-based barrier layer 17b_1 and the barrier layer 17b was 5 nm. The light-emitting element 11_6 manufactured in this manner was referred to as Experimental Example 6. With respect to Experimental Example 1, the film thickness L of the In _K Ga _1-K N layer corresponding to the GaN-based barrier layer 17b_1 and the barrier layer 17b was 10 nm. The light-emitting element 11_7 thus manufactured was referred to in Experimental Example 7.

Experimental Example 1 was examined with reference to Fig. 6 . Fig. 6 is a graph showing the results of measurement of PL emission wavelengths in the experimental examples. The symbol G1a in the figure is for As a result of Experimental Example 1, the symbol G1b in the figure is the result of Experimental Example 5, in which the symbol G1c is the result of Experimental Example 6, and the symbol G1d in the figure is the result of Experimental Example 7. Referring to Fig. 6, the indium compositions of the well layers of Experimental Example 1 and Experimental Example 5 to Experimental Example 7 were all the same, but the PL emission wavelength of Experimental Example 1 was significantly shorter than Experimental Examples 5 to 7. For this reason, the following can be considered. When the main surface of the supporting substrate corresponds to a semipolar surface such as a (20-21) plane, the piezoelectric polarization of the well layer is negative, and therefore, as shown in FIG. 2, strain is generated in the energy band structure of the light emitting layer. The wave function of the electron E is biased toward the n side of the well layer, and the wave function of the hole is biased toward the p side of the well layer. However, it is considered that, as in the case of Experimental Example 1, if the film thickness of the barrier layer disposed between the adjacent two well layers is relatively thin, the adjacent two sides on both sides of the barrier layer There is an overlap in the wave function between the well layers, not only in the same well layer, but also in the combination of electrons and holes to generate luminescence, and also through the barrier layer and the electrons of the well layer on one side of the barrier layer and the well layer on the other side. Since the holes are combined to cause luminescence, a PL illuminating wavelength which is greatly shortened is detected. On the other hand, as shown by the symbol G1b in the figure, when the film thickness of the barrier layer is thinner than 2.5 nm as in Experimental Example 1 and 0.5 nm as in Experimental Example 5, it becomes a film thickness with the well layer. The thicker single quantum well structures are approximately equal, so the PL emission wavelength becomes relatively longer. Further, the PL luminescence intensity was also measured for the experimental examples. Regarding the measurement results of the PL luminescence intensity, in the case of Experimental Example 1, Experimental Example 6, and Experimental Example 7, in the range where the film thickness of the barrier layer was 2.5 nm or more and 10 nm or less, no PL luminescence intensity was observed. The difference is the case, but in the case of Experimental Example 5, the PL light intensity when the film thickness of the barrier layer is 0.5 nm is Experimental Example 1. Experiment In the case of Example 6 and Experimental Example 7, the PL luminescence intensity was as low as about 60%. The measurement results for the PL luminescence intensity in Experimental Example 5 as described above are as follows. The reason is considered to be that the film thickness of the barrier layer on the well layer having a high In composition is relatively thin, so that the recovery of crystallinity is insufficient, and a new well layer is grown on the barrier layer in the above state, so that the entire light-emitting layer The crystal quality is lowered.

Next, Experimental Example 1 was examined with reference to Figs. 7 to 11 . 7 is a graph showing measurement results of current density dependence of the emission wavelengths of Experimental Example 1 and Experimental Example 6, and FIG. 8 is a graph showing measurement results of current density dependence of the light-emitting outputs of Experimental Example 1 and Experimental Example 6. 9 and FIG. 9 are graphs showing the measurement results of the current density dependence of the half-height width of the emission wavelengths of Experimental Example 1 and Experimental Example 6, and FIGS. 10 and 11 show the IV characteristics for Experimental Example 1 and Experimental Example 6. A graph of the measurement results. Fig. 12 is a graph showing the measurement results of the IV characteristics of Experimental Example 2, Experimental Example 3, and Experimental Example 8 below. Fig. 11 is a graph showing the vertical axis (current density) of Fig. 10 by logarithm, and Fig. 13 is a graph showing the vertical axis (current density) of Fig. 12 by logarithm. The measurement results shown in FIGS. 7 to 13 are used for the p-side electrode by a Pd electrode having a size of 100 μm × 100 μm, and the Ti/Al/Ti/Au electrode disposed on the entire back surface for the LED of the n-side electrode. Experimental Example 1, Experimental Example 2, Experimental Example 3, Experimental Example 6 and Experimental Example 8 were obtained. The results shown in Figs. 7 to 9 were obtained by applying pulse currents to Experimental Example 1 and Experimental Example 6. The results shown in FIGS. 10 to 13 were obtained by applying a direct current to Experimental Example 1, Experimental Example 2, Experimental Example 3, Experimental Example 6, and Experimental Example 8. The light-emitting element of Experimental Example 8 is a light-emitting layer of a multiple quantum well structure in the structure of Experimental Example 1 as a light-emitting layer of a single quantum well structure. LED.

In Fig. 7, the symbol G2a in the figure is the result of Experimental Example 1, and the symbol G2b in the figure is the result of Experimental Example 6. In the case where the current density was small, Experimental Example 1 had an emission wavelength shorter than that of Experimental Example 6, which was consistent with the measurement results shown in Fig. 6 for the PL emission wavelength. However, in the stage where the current density is increased and the current injection is relatively high, the wavelength difference between the emission wavelength of Experimental Example 1 and the emission wavelength of Experimental Example 6 is reduced to be substantially the same. The reason for this is considered to be that the piezoelectric polarization is weakened by the current injection, and in Experimental Example 1, the probability of transition between adjacent well layers is also lowered by the screening. In addition, when the film thickness of the barrier layer is about 2.5 nm, the light-emitting element is formed on the light-emitting element on the c-plane, but the light-emitting efficiency is lowered, but it grows on a semi-polar surface such as (20-21) plane. In the case of Experimental Example 1 of the InGaN layer, the growth of the InGaN layer tends to be homogeneous and high in quality, and it is considered that the light-emitting efficiency can be maintained even if the thickness of the barrier layer is extremely thin.

In Fig. 8, the symbol G3a in the figure is the result of Experimental Example 1, and the symbol G3b in the figure is the result of Experimental Example 6. According to the measurement results shown in Fig. 8, Experimental Example 1 had a higher luminous output than Experimental Example 6. As described above, since the PL luminescence intensity of Experimental Example 1 and Experimental Example 6 are equal, there should be no large difference in the quality of the well layer. Therefore, it is considered that the difference in the light-emission output between Experimental Example 1 and Experimental Example 6 as shown in FIG. 8 by current injection is that the carrier injection efficiency of Experimental Example 1 is superior to that of Experimental Example 6.

In Fig. 9, the symbol G4a in the figure is the result of Experimental Example 1, and the symbol G4b in the figure is the result of Experimental Example 6. According to the measurement results shown in FIG. 9, Experimental Example 1 has a width half width (FWHM, Full Width) which is narrower than Experimental Example 6. Half Maximum), in particular, the difference between the half width and the width of the experimental example 1 and the experimental example 6 is significant in the stage where the current density is relatively low and the electron injection is relatively small. It is considered that in the case of Experimental Example 6, the carrier injection efficiency is poor, the carrier density between wells is not uniform, and thus the full width at half maximum is wide. When the current density is increased, the density of the carrier density is somewhat relaxed. Therefore, the difference between the half width and the width of the experimental example 1 and the experimental example 6 is small, but the level is not equal.

In Fig. 10, the symbol G5a in the figure is the result of Experimental Example 1, and the symbol G5b in the figure is the result of Experimental Example 6. In Fig. 11, the symbol G6a in the figure is the result of Experimental Example 1, and the symbol G6b in the figure is the result of Experimental Example 6. Referring to Fig. 10, the increase in the current density at which the diffusion current starts to flow in Experimental Example 1 is smaller than that in Experimental Example 6. This result also proves that the carrier injection efficiency of Experimental Example 1 is excellent. Referring to Fig. 11, the rising voltage of the current density at which the diffusion current starts to flow is 2.4 volts in the case of Experimental Example 1, and 2.6 volts in the case of Experimental Example 6.

According to the measurement results shown in FIGS. 7 to 11 above, it is understood that the film thickness of the barrier layer is relatively thin (for example, about 2.5 nm), even when the piezoelectric polarization of the well layer is negative. It is also possible to improve the injection efficiency of electrons in the light-emitting layer. This phenomenon is also reflected in the fact that the light-emitting wavelength of the weak excitation is shortened (the weak excitation is in the measurement result shown in Fig. 7 and corresponds to the current density of 0.05 kA/cm ² or less). Further, this phenomenon is also reflected in the fact that the rising voltage at which the diffusion current starts to flow is low, and for example, the rising voltage can be set to 2.5 V or less. Further, from the viewpoint of making the carrier injection efficiency and the luminous efficiency stand side by side, it is particularly preferable that the film thickness of the well layer is equal to the film thickness of the barrier layer. That is, when the light-emitting wavelength of the weak excitation is shortened, a light-emitting layer excellent in both the carrier injection efficiency and the light-emitting efficiency can be obtained.

Next, Experimental Example 2 and Experimental Example 3 were examined with reference to Figs. 12 and 13 . In Fig. 12, the symbol G7a in the figure is the result of Experimental Example 2, in which the symbol G7b is the result of Experimental Example 3, and the symbol G7c in the figure is the result of Experimental Example 8. In Fig. 13, the symbol G8a in the figure is the result of Experimental Example 2, in which the symbol G8b is the result of Experimental Example 3, and the symbol G8c in the figure is the result of Experimental Example 8. The rising voltage at which the diffusion current started to flow was 2.3 volts in Experimental Example 2, which was 2.2 volts in Experimental Example 3, and the rising voltage of Experimental Example 2 and Experimental Example 3 compared with 2.4 volts (refer to FIG. 10). It was improved to be approximately the same as 2.2 volts of Experimental Example 8 of a single quantum well structure. The results shown in Fig. 12 and the results shown in Fig. 13 suggest that the carrier injection efficiency is improved by the following effects: for Experimental Example 2, the band gap energy of the entire barrier layer is lowered; and for Experimental Example 3, The height of the barrier to the electrons is lowered by the composition of the slope to form a band structure similar to the band bending caused by the piezoelectric polarization.

Further, in Experimental Example 1 and Experimental Example 4, a cross-sectional TEM (Transmission Electron Microscopy) observation was carried out to measure misfit dislocations. When performing cross-sectional TEM observation, in Experimental Example 4, the interface between the n-InGaN layer having a film thickness of about 150 nm included in the n-side guiding layer and the n-GaN layer having a film thickness of about 200 nm was confirmed. A misfit dislocation of about 2 × 10 ⁴ cm ^-1 . On the other hand, misfit dislocations were not confirmed in the same portion in Experimental Example 1. From this, it can be seen that in Experimental Example 4, the indium composition of the n-side guiding layer is relatively high, and the thickness of the InGaN layer of about 150 nm included in the n-side guiding layer relaxes the supporting substrate. Therefore, the strain contained in the light-emitting layer is alleviated.

Next, Experimental Example 4 was examined. In the case of Experimental Example 1 in the case of LD and Experimental Example 4 in the case of LD, the laser characteristics were evaluated by applying a pulse current. The Ith (current threshold) of Experimental Example 1 was 85 mA, and the Ith of Experimental Example 4 was 60 mA. The value of Ith of Experimental Example 4 was lower than that of Experimental Example 1. In the case of Experimental Example 4, it is expected that the piezoelectric polarization of the well layer is slightly reduced by the relaxation of the n-InGaN layer of the film thickness of about 150 nm contained in the guiding layer, whereby the carrier injection efficiency is improved. Improved. It is believed that by uniformly injecting carriers in each well layer, not only the improvement of luminous efficiency but also the reduction of internal loss is achieved (in the case where the carrier injection is not uniform, the carrier density in the plurality of well layers is low rather than transparent) The well layer of the chemical acts as a source of absorption of light). Further, in the case of Experimental Example 4, it is considered that the case where the value of Ith of Experimental Example 4 is lower than the Ith of Experimental Example 1 is due to the film thickness of about 150 nm included in the guiding layer. The indium composition of the -InGaN layer is relatively high, so the light blocking effect is relatively small.

Further, in the case of Experimental Example 4, the measurement result was that the PL emission wavelength was 527 nm, whereas the oscillation wavelength was 522 nm. In the case of Experimental Example 1, the measurement result was that the PL emission wavelength was 525 nm. In contrast, the oscillation wavelength is 517 nm. In the case of a light-emitting element disposed on the main surface of a semi-polar surface such as (20-21), the piezoelectric polarization is not zero, but whether or not piezoelectric polarization is generated, the difference between the PL emission wavelength and the oscillation wavelength is Relatively small, this point means that, at least in the case of Experimental Example 1 and Experimental Example 4, the mechanism of the transition between adjacent well layers is increased due to the relatively thin film thickness of the barrier layer at the measurement of the PL emission wavelength. (Refer to the results shown in Fig. 6). When this mechanism works, the carrier injection efficiency is improved. In the case of the structure in which the light-emitting element has a structure with excellent carrier injection efficiency, the EL light-emitting wavelength (EL) at a current density of about 0.05 kA/cm ² is actually confirmed in the case of the experimental example 1 and the experimental example 4 The peak of the PL emission wavelength at the peak of the excitation density of the peak of the EL oscillation wavelength or the peak of the PL emission wavelength at the peak of the EL oscillation wavelength is 15 nm or less up to the oscillation wavelength.

According to the description of the embodiments so far, it is understood that the method of manufacturing a nitride semiconductor light-emitting element can include the following steps. In the substrate preparation step, a substrate for evaluation having a plurality of main faces including a hexagonal nitride semiconductor is prepared. The principal faces of the evaluation substrate are each inclined at an angle greater than zero with respect to the c-plane of the hexagonal nitride semiconductor. In the step of forming the diode structure, for evaluation of the nitride semiconductor light-emitting device, the evaluation quantum well including the evaluation barrier layer and the evaluation well layer is grown on the main surface of the plurality of evaluation substrates, respectively. Constructed diode structure. The barrier layers for evaluation have mutually different thicknesses. In the photoluminescence spectrum (PL) measurement step, the PL spectrum of the evaluation quantum well structure in each of the diode structures was measured. Further, since the evaluation barrier layers for the evaluation quantum well structure have mutually different thicknesses, the relationship between the peak wavelength of the PL spectrum and the thickness of the barrier layer for the evaluation quantum well structure can be obtained. An example of this relationship is shown in Figure 6. In the determining step, the thickness of the barrier layer for the nitride semiconductor light-emitting device is determined based on the dependence of the PL peak wavelength on the thickness of the barrier layer. In the forming step of the epitaxial substrate, the growth on the main surface of the substrate for the nitride semiconductor light-emitting device has a nitride semi-conductive The diode structure of the quantum well structure of the bulk light-emitting element forms an epitaxial substrate for a nitride semiconductor light-emitting element, wherein the quantum well structure comprises a barrier layer and a well layer having a determined thickness. Then, in the electrode step, an electrode is formed on the epitaxial substrate. The electrode includes, for example, at least one of an anode electrode and a cathode electrode. The main surface of the substrate can be inclined with respect to the c-plane of the hexagonal nitride semiconductor at an angle greater than zero, similarly to the main surface of the evaluation substrate. In an embodiment, the inclination angle of the main surface may be, for example, in the range of 50 degrees or more and 80 degrees or less or 130 degrees or more and 170 degrees or less.

Referring to Fig. 6, the peak wavelength of the PL spectrum temporarily decreases as the barrier layer becomes thinner, and then increases. The thickness of the barrier layer for the nitride semiconductor light-emitting device can be determined according to the dependency relationship between the PL peak wavelength and the thickness of the barrier layer. In a quantum well structure having a barrier layer of this thickness, the driving voltage for light emission is lowered. The thickness of the well layer can be, for example, in the range of 1 nm to 5 nm. In the manufacturing method, the nitride semiconductor light-emitting device can be manufactured using, for example, the embodiment described with reference to FIGS. 3 and 4. Here, the nitride semiconductor light-emitting element may include any one of a laser diode and a light-emitting diode.

According to this manufacturing method, for example, the following nitride semiconductor light-emitting elements are manufactured. The nitride semiconductor light-emitting element may comprise a support matrix and a diode structure. The support substrate has a main surface including a hexagonal nitride semiconductor. The diode structure is disposed on the main surface of the support substrate. The diode structure includes a first conductivity type group III nitride semiconductor layer provided on a main surface of the support substrate, a light emitting layer provided on the first conductivity type group III nitride semiconductor layer, and a second layer provided on the light emitting layer. A conductive type III nitride semiconductor layer. The light-emitting layer has a multiple quantum well structure including first and second well layers and a barrier layer. 1st The second well layer contains compressive strain, and the direction of piezoelectric polarization generated in the first and second well layers is the same as the direction from the p region of the diode structure toward the n region. The principal surface is inclined with respect to the c-plane of the hexagonal nitride semiconductor at an angle greater than zero. Further, the inclination angle of the main surface may be in a range of 50 degrees or more and 80 degrees or less and a range of 130 degrees or more and 170 degrees or less. The nitride semiconductor light-emitting element may include any one of a laser diode and a light-emitting diode.

The film thickness of the barrier layer is, for example, (DW - 0.50) nm or more and (DW + 0.50) nm or less. Here, the well layer may have a thickness DW. Here, the thickness DW of the well layer may range from 1 nm to 5 nm.

Further, the film thickness of the barrier layer may be equal to or less than the film thickness of the well layer. Here, the thickness of the well layer may be, for example, in the range of 1 nm to 5 nm.

Further, in the nitride semiconductor light-emitting device, the film thickness of the barrier layer may be, for example, 4.5 nm or less.

The nitride semiconductor light-emitting device may further include a strip electrode which is provided on the diode structure and extends along a reference plane defined by the c-axis and the m-axis of the hexagonal nitride semiconductor, and the strip electrode may be included in The surface of the diode configuration forms an ohmic contact ohmic electrode and comprises, for example, palladium.

The diode structure of the nitride semiconductor light-emitting device may include, for example, a ridge structure extending along a reference plane defined by the c-axis and the m-axis of the hexagonal nitride semiconductor.

In the first embodiment, the barrier to electrons can be reduced in such a manner that when the barrier layer includes an InGaN layer, the InGaN layer has an indium composition that monotonously changes from the first well layer to the second well layer. The indium composition is for example The p region from the diode structure increases in the direction of the n region.

In the second embodiment, the diode structure may further include a light guiding layer connected to the first well layer. The first well layer is connected to the barrier layer, and the barrier layer is connected to the second well layer. The barrier to electrons can be reduced in such a way that the band gap of the group III nitride semiconductor of the barrier layer is smaller than the band gap of the group III nitride semiconductor of the light guiding layer in contact with the quantum well structure.

In the third embodiment, the diode structure may further include a light guiding layer disposed between the light emitting layer and the supporting substrate. The light guiding layer includes a GaN guiding layer and an InGaN guiding layer. The GaN guiding layer is in contact with the InGaN guiding layer to form an interface. A misfit dislocation is formed at the interface: when the indium composition of the InGaN guiding layer is in the range of 0.02 or more and 0.06 or less and the thickness of the InGaN guiding layer is in the range of 100 nm or more and 500 nm or less, the light emitting layer The strain has an impact. The misfit dislocation density may be in the range of 5 × 10 ³ cm ^-1 or more and 1 × 10 ⁵ cm ^-1 or less. The strain of the light-emitting layer is lowered by the formation of the c-plane sliding surface, so that the piezoelectric field of the well layer of the light-emitting layer is lowered. By the relaxation of the strain, the barrier caused by the piezoelectric electric field becomes small. Therefore, the barrier to electrons can be lowered. The InGaN guiding layer which can achieve a mismatched transition density of less than 5 × 10 ³ cm ^-1 has an indium composition in a range of 0.01 or more and 0.02 or less, and has a thickness in a range of 50 nm or more and 200 nm or less.

The embodiments of the present invention have been illustrated and described in the preferred embodiments of the present invention. The present invention is not limited to the specific configuration disclosed in the embodiment. Therefore, all amendments and changes to the application rights are based on the scope of the patent application and its spirit.

[Industrial availability]

According to the present embodiment, it is possible to provide a nitride semiconductor light-emitting device which is provided on a semipolar surface and which suppresses an increase in a bias voltage required for light emission, and a method of manufacturing the nitride semiconductor light-emitting device.

10‧‧‧Reaction furnace

11‧‧‧Lighting elements

13‧‧‧Support matrix

13_1‧‧‧Substrate

13a‧‧‧Main face

13a_1‧‧‧Main face

13b‧‧‧Back

13b_1‧‧‧Back

15‧‧‧n type gallium nitride semiconductor layer

15a‧‧‧n-type GaN layer

15b‧‧‧n type coating

15c‧‧‧n type guiding layer

15d‧‧‧n type GaN guiding layer

15e‧‧‧n type InGaN guiding layer

15f‧‧‧ surface

15_1‧‧‧n type gallium nitride semiconductor layer

15_1a‧‧‧ surface

15a_1‧‧‧n-type GaN layer

15b_1‧‧‧n type GaN semiconductor layer

15c_1‧‧‧n type GaN-based semiconductor layer

17‧‧‧Lighting layer

17a‧‧‧ Wells

17b‧‧‧Baffle layer

17c‧‧‧ Wells

17_1‧‧‧GaN quantum well layer

17_1a‧‧‧ surface

17a_1‧‧‧GaN well layer

17b_1‧‧‧GaN barrier layer

17c_1‧‧‧GaN well layer

19‧‧‧p-type gallium nitride semiconductor layer

19a‧‧‧p type guide layer

19b‧‧‧p type coating

19c‧‧‧p type contact layer

19_1‧‧‧p-type gallium nitride semiconductor layer

19_1a‧‧‧ surface

19a_1‧‧‧p-type GaN-based semiconductor layer

19b_1‧‧‧p-type GaN-based semiconductor layer

19c_1‧‧‧p-type GaN-based semiconductor layer

21‧‧‧p side electrode

25‧‧‧n side electrode

AX‧‧‧ normal axis

CR‧‧‧Crystal coordinate system

EP‧‧‧ epitaxial substrate

EP1‧‧‧ epitaxial substrate

S‧‧‧ coordinate system

SC‧‧‧ face

VC‧‧‧c axis vector

VN‧‧ normal vector

X‧‧‧ axis

Y‧‧‧ axis

Z‧‧‧ axis

A‧‧‧Axis

C‧‧‧axis

M‧‧‧Axis

‧‧‧‧Tilt angle

Fig. 1 (a) and (b) are views showing the configuration of a light-emitting element of an embodiment.

Fig. 2 is a view for explaining the effect of the light-emitting element of the embodiment.

Fig. 3 is a view for explaining a method of manufacturing a light-emitting element of the embodiment.

4(a) to 4(c) are diagrams schematically showing products in the main steps of the method for producing a light-emitting element of the embodiment.

Fig. 5 is a view showing the configuration of an experimental example of a light-emitting element of the embodiment.

Fig. 6 is a graph showing the results of measurement of the PL emission wavelength in the experimental example.

Fig. 7 is a graph showing the measurement results of the current density dependence of the emission wavelength of the experimental example.

Fig. 8 is a graph showing the measurement results of the current density dependence of the luminescence output of the experimental example.

Fig. 9 is a graph showing the measurement results of the current density dependence of the half-height width of the emission wavelength of the experimental example.

Fig. 10 is a graph showing the results of measurement of the IV characteristics of the experimental examples.

Fig. 11 is a graph showing the results of measurement of the IV characteristics of the experimental examples.

Fig. 12 is a graph showing the results of measurement of the IV characteristics of the experimental examples.

Fig. 13 is a graph showing the results of measurement of the IV characteristics of the experimental examples.

11‧‧‧Lighting elements

13‧‧‧Support matrix

13a‧‧‧Main face

13b‧‧‧Back

13_1‧‧‧Substrate

15‧‧‧n type gallium nitride semiconductor layer

15a‧‧‧n-type GaN layer

15b‧‧‧n type coating

15c‧‧‧n type guiding layer

15d‧‧‧n type GaN guiding layer

15e‧‧‧n type InGaN guiding layer

15f‧‧‧ surface

17‧‧‧Lighting layer

17a‧‧‧ Wells

17b‧‧‧Baffle layer

17c‧‧‧ Wells

19‧‧‧p-type gallium nitride semiconductor layer

19a‧‧‧p type guide layer

19b‧‧‧p type coating

19c‧‧‧p type contact layer

19_1a‧‧‧ surface

21‧‧‧p side electrode

25‧‧‧n side electrode

AX‧‧‧ normal axis

CR‧‧‧Crystal coordinate system

EP1‧‧‧ epitaxial substrate

S‧‧‧Orthogonal coordinate system

SC‧‧‧ face

VC‧‧‧c axis vector

VN‧‧ normal vector

X‧‧‧ axis

Y‧‧‧ axis

Z‧‧‧ axis

A‧‧‧Axis

C‧‧‧axis

M‧‧‧Axis

‧‧‧‧Tilt angle

Claims (30)

A nitride semiconductor light-emitting device comprising: a support substrate comprising a hexagonal nitride semiconductor; and having a main surface inclined from a c-plane of the hexagonal nitride semiconductor in a predetermined direction; n-type nitrogen a gallium-based semiconductor layer provided on the main surface of the support substrate; a light-emitting layer provided on the n-type gallium nitride-based semiconductor layer and including a gallium nitride-based semiconductor; and a p-type gallium nitride system a semiconductor layer disposed on the light emitting layer; the light emitting layer having a multiple quantum well structure, the multiple quantum well structure comprising at least two well layers and at least one barrier layer, the barrier layer being disposed between the two well layers The two well layers include InGaN, and the two well layers have a first indium composition in a range of 0.15 or more and 0.50 or less, and the inclination angle of the main surface with respect to the c-plane is in a range of 50 degrees or more and 80 degrees or less. And in any one of a range of 130 degrees or more and 170 degrees or less, the film thickness of the barrier layer is in a range of 1.0 nm or more and 4.5 nm or less. The nitride semiconductor light-emitting device of claim 1, wherein the film thickness of the barrier layer is less than or equal to a value obtained by adding a film thickness of the well layer to 0.50 nm. The value obtained by subtracting 0.50 nm from the film thickness of the above well layer is above. The nitride semiconductor light-emitting device according to claim 1 or 2, wherein the barrier layer comprises InGaN, and the barrier layer has a second indium composition in a range of 0.01 or more and 0.10 or less. The nitride semiconductor light-emitting device according to any one of claims 1 to 3, wherein the n-type gallium nitride-based semiconductor layer includes an InGaN layer, and the light-emitting layer is provided on the InGaN layer, and the n-type gallium nitride layer is There is a misfit dislocation on the surface of the support substrate side of the InGaN layer inside the semiconductor layer, and the misfit dislocation is along a plane orthogonal to the surface of the InGaN layer and including the hexagonal nitride semiconductor The reference plane of the axis extends in a direction orthogonal to the reference axis and the c-axis shared by the surface of the InGaN layer, and the density of the misfit dislocations is 5×10 ³ cm ⁻¹ or more and 1×10 ⁵ cm ⁻¹ or less. The scope. The nitride semiconductor light-emitting device of claim 4, wherein the InGaN layer has a third indium composition in a range of 0.03 or more and 0.05 or less. The nitride semiconductor light-emitting device of claim 3, wherein the second indium composition increases from a side of the p-type gallium nitride-based semiconductor layer toward a side of the n-type gallium nitride-based semiconductor layer. The nitride semiconductor light-emitting device according to any one of claims 1 to 6, wherein the inclination angle of the main surface with respect to the c-plane is in a range of 63 degrees or more and 80 degrees or less. The nitride semiconductor light-emitting device according to any one of claims 1 to 7, wherein the first indium composition is in a range of 0.24 or more and 0.40 or less. The nitride semiconductor light-emitting device according to claim 3, wherein the second indium composition is in a range of 0.01 or more and 0.06 or less. The nitride semiconductor light-emitting device according to any one of claims 1 to 9, wherein a thickness of the barrier layer is in a range of 1.0 nm or more and 3.5 nm or less. A method for producing a nitride semiconductor light-emitting device, comprising the steps of: preparing a substrate including a hexagonal nitride semiconductor and having a principal surface inclined from a c-plane of the hexagonal nitride semiconductor in a predetermined direction; Growing an n-type gallium nitride based semiconductor layer on the main surface of the substrate; growing a light emitting layer containing a gallium nitride based semiconductor on the n-type gallium nitride based semiconductor layer; and growing p-type nitrogen on the light emitting layer a gallium-based semiconductor layer; the light-emitting layer comprising at least a first well layer, a second well layer, and at least one barrier layer, and sequentially growing on the n-type gallium nitride-based semiconductor layer in the step of growing the light-emitting layer In the first well layer, the barrier layer, and the second well layer, the first well layer and the second well layer include InGaN, and the first well layer and the second well layer have a range of 0.15 or more and 0.50 or less. The first indium composition, The inclination angle of the main surface with respect to the c-plane is in a range of 50 degrees or more and 80 degrees or less and a range of 130 degrees or more and 170 degrees or less, and the film thickness of the barrier layer is in a range of 1.0 nm or more and 4.5 nm or less. . The method for fabricating a nitride semiconductor light-emitting device according to claim 11, wherein the film thickness of the barrier layer is less than or equal to a value obtained by adding a film thickness of the well layer to 0.50 nm and a film thickness of 0.50 nm is subtracted from the film thickness of the well layer. Above the value. The method for producing a nitride semiconductor light-emitting device according to claim 11 or 12, wherein the barrier layer comprises InGaN, and the barrier layer has a second indium composition in a range of 0.01 or more and 0.10 or less. The method of manufacturing a nitride semiconductor light-emitting device according to any one of claims 11 to 13, wherein the n-type gallium nitride-based semiconductor layer includes an InGaN layer, and the light-emitting layer is provided on the InGaN layer, and the n-type nitrogen is a misfit dislocation on the surface of the substrate side of the InGaN layer inside the gallium-based semiconductor layer, the misfit dislocation line being orthogonal to the surface of the InGaN layer and including the hexagonal nitride semiconductor The reference plane of the c-axis extends in a direction orthogonal to the reference axis and the c-axis shared by the surface of the InGaN layer, and the density of the misfit dislocations is 5×10 ³ cm ⁻¹ or more and 1×10 ⁵ cm ^{− 1} range below. The method of producing a nitride semiconductor light-emitting device according to claim 14, wherein the InGaN layer has a third indium composition in a range of 0.03 or more and 0.05 or less. The method of producing a nitride semiconductor light-emitting device according to claim 13, wherein the second indium composition increases from a side of the p-type gallium nitride-based semiconductor layer toward a side of the n-type gallium nitride-based semiconductor layer. The method for producing a nitride semiconductor light-emitting device according to any one of claims 11 to 16, wherein the inclination angle of the main surface with respect to the c-plane is in a range of 63 degrees or more and 80 degrees or less. The method for producing a nitride semiconductor light-emitting device according to any one of claims 11 to 17, wherein the first indium composition is in a range of 0.24 or more and 0.40 or less. The method for producing a nitride semiconductor light-emitting device according to claim 13, wherein the second indium composition is in a range of 0.01 or more and 0.06 or less. The method for producing a nitride semiconductor light-emitting device according to any one of claims 11 to 19, wherein a thickness of the barrier layer is in a range of 1.0 nm or more and 3.5 nm or less. A method for fabricating a nitride semiconductor light-emitting device, comprising the steps of: preparing an evaluation substrate having a plurality of main faces including a hexagonal nitride semiconductor; and for evaluating the nitride semiconductor light-emitting device A diode structure having an evaluation quantum well structure including an evaluation barrier layer and an evaluation well layer is grown on the main surface of the evaluation substrate And measuring a photoluminescence spectrum of the quantum well structure for evaluation in each of the above-described diode structures, and obtaining a relationship between a peak wavelength of the photoluminescence spectrum and a thickness of the barrier layer of the quantum well structure for evaluation; The relationship determines the thickness of the barrier layer used in the nitride semiconductor light-emitting device; and the diode structure having the quantum well structure for the nitride semiconductor light-emitting device is grown on the main surface of the substrate to form an epitaxial substrate. Wherein the quantum well structure includes a barrier layer and a well layer having the thickness determined above; the evaluation substrate and the main surface of the substrate each have a c-plane with respect to the hexagonal nitride semiconductor at an angle greater than zero The semi-polarity of the inclination, the barrier layers for evaluation described above have mutually different thicknesses. The method of producing a nitride semiconductor light-emitting device according to claim 21, wherein the nitride semiconductor light-emitting device comprises any one of a laser diode and a light-emitting diode. The method for producing a nitride semiconductor light-emitting device according to claim 21, wherein the barrier layer has a thickness of (DW - 0.50) nm or more and (DW + 0.50) nm or less. Here, the well layer has a thickness DW. The method for producing a nitride semiconductor light-emitting device according to any one of claims 21 to 23, wherein a film thickness of the barrier layer is equal to or less than a film thickness of the well layer. A nitride semiconductor light-emitting device characterized by comprising: a support substrate having a host comprising a hexagonal nitride semiconductor And a diode structure provided on the main surface of the support substrate; the diode structure includes: a first conductivity type group III nitride semiconductor layer disposed on the main surface of the support substrate; a light-emitting layer provided on the first conductivity type group III nitride semiconductor layer; and a second conductivity type group III nitride semiconductor layer provided on the light-emitting layer; the light-emitting layer including the first well layer and the second layer a multiple quantum well structure of a well layer and a barrier layer, wherein the main surface has a semipolarity inclined with respect to a c-plane of the hexagonal nitride semiconductor at an angle greater than zero, and the inclination angle of the main surface is 50 degrees or more and 80 degrees or less In the range of the range of 130 degrees or more and 170 degrees or less, the film thickness of the barrier layer is in the range of 4.5 nm or less. The nitride semiconductor light-emitting device of claim 25, wherein the nitride semiconductor light-emitting device comprises any one of a laser diode and a light-emitting diode. The nitride semiconductor light-emitting device according to claim 25 or 26, further comprising a strip which is provided on the diode structure and extends along a reference plane defined by a c-axis and an m-axis of the hexagonal nitride semiconductor Electrode. The nitride semiconductor light-emitting device according to any one of claims 25 to 27, wherein the diode structure includes a ridge extending along a reference plane defined by a c-axis and an m-axis of the hexagonal nitride semiconductor structure. A nitride semiconductor light-emitting element according to any one of claims 25 to 28, The barrier layer includes an InGaN layer, and the InGaN layer has an indium composition that monotonously changes from the first well layer to the second well layer, and the indium composition is from a p region from the diode structure to n The direction of the area increases. The nitride semiconductor light-emitting device according to any one of claims 25 to 29, further comprising a light guiding layer connected to the first well layer, wherein the first well layer is connected to the barrier layer, and the barrier layer and the first layer 2 The well layer is connected, and the band gap of the group III nitride semiconductor of the barrier layer is smaller than the band gap of the group III nitride semiconductor of the light guiding layer.