TW201320310A - Memory device and method for manufacturing the same - Google Patents

Abstract

A vertical interconnect architecture for a three-dimensional (3D) memory device suitable for low cost, high yield manufacturing is described. Conductive lines (e.g. word lines) for the 3D memory array, and contact pads for vertical connectors used for couple the array to decoding circuitry and the like, are formed as parts of the same patterned level of material. The same material layer can be used to form the contact pads and the conductive access lines by an etch process using a single mask. By forming the contact pads concurrently with the conductive lines, the patterned material of the contact pads can protect underlying circuit elements which could otherwise be damaged during patterning of the conductive lines.

Description

Memory device and method of manufacturing same

The present invention relates to a high density integrated circuit device, and more particularly to an interconnect structure for a multi-level three-dimensional stacked device.

When the critical size of the device in the integrated circuit is reduced to the limit of the common memory cell technology, the designer has sought a technique for stacking multiple levels of memory cells to achieve greater storage capacity and to achieve each The lower cost of the bit. For example, thin film transistor technology is applied to Lai et al.'s charge-capture memory technology, "a multi-layer stackable thin film transistor (TFT) NAND type flash memory (A Multi-Layer Stackable Thin-Film) Transistor (TFT) NAND-Type Flash Memory), IEEE International Electronic Components Conference, December 11-13, 2006; and applied to Jung et al., "About the use of stacked monocrystalline germanium layers on ILD and TANOS structures" Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node, IEEE International Electronic Components Conference, December 11, 2006- 13th.

Also, the intersection array technique has been applied to the anti-fuse memory of Johnson et al., which provides a plurality of word lines and bit lines in which a plurality of memory elements are located at the intersection. These memory elements include a p+ polysilicon anode connected to a word line and an n-poly germanium cathode connected to a single bit line, wherein the anode and cathode are separated by an antifuse material.

Another configuration that uses charge-capture memory technology to provide vertical NAND cells is described in "A New 3D Structure for Ultra-High-Density Flash Memory with VRAT and PIPE," by Kim et al. Proceedings of the VLSI Technical Digest of the Technical Document of the Year; June 17-19, 2008; pp. 122-123.

In a three-dimensional stacked memory configuration, vertical interconnects couple the various circuit configurations of the array to overlay access lines, such as global bit lines and power lines for reading and writing memory cells.

One disadvantage of conventional three-dimensional stacked memory devices is that the vertical interconnect structures to different portions of the array are each formed in different layers overlying the array. This requires the creation of a lithographic reticle for each level, as well as an etching step for each level. The cost of implementing vertical interconnects increases with the number of lithographic steps required. In addition, key points such as reticle alignment and etch selectivity during fabrication can reduce yield.

It is desirable to provide a configuration for a three-dimensional integrated circuit memory having low manufacturing cost and high yield.

The present invention describes a vertical interconnect structure for a three-dimensional (3D) memory device that is suitable for low cost, high yield manufacturing. Conductive lines for the 3D memory array (e.g., word lines), and contact pads for vertical connectors for coupling the array to a decoding circuit or the like are formed as part of the same patterned material level. The same material layer can be used to form contact pads and conductive contacts by using one of the etch mask processes. By forming a contact pad simultaneously with the conductive line, the patterned material of the contact pad can protect the underlying circuit components that would otherwise be damaged during patterning of the conductive lines.

The contact pads provide a vertical interconnect interface for the 3D memory array. The electrically conductive contact can then be formed with a dielectric fill to contact the corresponding contact pad. Additional post-stage processing (BEOL) processing can then be performed to complete the 3D memory device.

Other embodiments and advantages of the invention can be seen in the drawings, the detailed description, and the appended claims.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

Detailed descriptions of embodiments of the invention are provided with reference to Figures 1-11.

1A and 1B are cross-sectional and plan views showing the structure after the first stage in the process for fabricating a three-dimensional stacked memory device. In this example, four levels 102, labeled 102.1, 102.2, 102.3, 102.4, are shown, which represent a structure that can include a majority of the hierarchy.

The four levels 102 are separated from the lower semiconductor substrate 140 by one or more dielectric layers 125. A top dielectric layer 126 is placed over the four levels 102.

Such levels 102 include respective layers of conductive material 134. In this embodiment, layer 134 is a semiconductor material such as polysilicon doped with impurities. Such levels 102 also include separate insulating material layers 136 separating the layers of semiconductor material 134 of the different levels 102.

This configuration also includes a first stepped connector configuration 110. The first stepped connector configuration 110 includes conductive vertical connectors 112 labeled 112.1-112.4, each of which is electrically coupled to one of the conductive layers 134 of one of the levels 102. These vertical connectors 112 are surrounded by corresponding dielectric sidewall spacers 114 labeled 114.1-114.4. The dielectric sidewall spacers 114 electrically isolate the corresponding vertical connectors 112 from the conductive layers 134 of the other layers 102, thereby causing the vertical connectors 112 to not complete electrical contact.

FIG. 1A includes a cross-sectional view through the first stepped conductor structure 110 along line A-A. As shown in FIG. 1A, the vertical connector 112.1 extends through the dielectric layer 126 to contact the conductive layer 134.1 of the first level 102.1. Similarly, the vertical connector 114.2 is electrically connected to the conductive layer 134.2 of the second level 102.2, the vertical connector 114.3 is electrically connected to the conductive layer 134.3 of the third level 102.3, and the vertical connector 114.4 is electrically connected to the fourth level 102.4. Conductive layer 134.4.

As shown in the top view of FIG. 1B, this configuration also includes a second stepped conductor construction 120. The second stepped conductor construction 120 includes a vertical connector 122, labeled 122.1-122.4, electrically coupled to one of the conductive layers 134 of one of the levels 102. These vertical connectors 122 are surrounded by corresponding dielectric sidewall spacers 124, designated 124.1-124.4. The dielectric sidewall spacers 124 electrically isolate the vertical connectors 122 from the conductive layers 134 of the other layers 102, thereby causing the vertical connectors 122 to not complete electrical contact.

This configuration also includes vertical connectors 150, 152, 154, 156 that are electrically connected to each of the conductive layers 134 of each of the levels 102. FIG. 1A includes a cross-sectional view through vertical connector 150 along line C-C. As shown in FIG. 1A, the vertical connector 150 is electrically connected to the conductive levels 134.1, 134.2, 134.3, 134.4 of each of the layers 102.1, 102.2, 102.3, 102.4.

The constructions shown in Figures 1A and 1B can be utilized in the teachings of U.S. Patent Application Serial No. 13/114,931, filed on May 24, 2011, which is incorporated herein by reference. Made out.

2A and 2B are diagrams showing the top and cross-sectional views of the structures of Figures 1A and 1B of a plurality of ridge stacks 200, 202, 204, 206 for defining a semiconductor strip after performing a lithographic patterning step. The semiconductor strips are implemented by using a material of conductive layer 134 and are separated from other strips in the same stack by a layer 136 of insulating material. As explained in more detail below, the conductive strips of stacks 200, 202, 204, 206 serve as local bit lines in various levels 102 of the device.

The lithographic patterning step is accomplished by forming a patterned photoresist mask over selected regions of the structure 100 shown in Figures 1A and 1B. Etching is then performed down to the dielectric layer 125 by using a photoresist mask as an etch mask. The photoresist mask is then removed to produce the configuration shown in Figures 2A and 2B.

As shown in Figures 2A and 2B, a lithographic patterning step is performed to place vertical connectors 150, 152, 154, 156 at the first ends of the stacks 200, 202, 204, 206 of the semiconductor strips. This patterning process also exposes the sidewall surfaces of the vertical connectors 150, 152, 154, 156.

A vertical connector located at the first end of a particular stack interconnects the conductive strips of that particular stack. For example, FIG. 2A includes a cross-sectional view of the vertical connector 150 disposed along the first end of the stack 200 along line C-C. As shown in FIG. 2A, vertical connectors 150 are connected to semiconductor strips in various levels 102 of stack 200.

The stacks 200, 202 are collectively referred to herein as the first set of stacks. Stacks 204, 206 are collectively referred to herein as a second set of stacks. As can be seen in Figure 2B, the first and second sets of stacks have opposite orientations. That is, the vertical connectors 150, 152 at the first ends of the stacks 200, 202 of the first set are in opposite positions of the vertical connectors at the first ends of the stacks 204, 206 of the second set. In addition, the stacks of the first and second groups are arranged in an alternating manner such that adjacent stacks in the first group are separated by a single stack in the second group, and adjacent stacks in the second group are first group Separated by a single stack.

Conductive extensions (not shown) within the hierarchy 102 are patterned while defining the stacks 200, 202, 204, 206. A first conductive extension within the level 102 is disposed at a second end of the stack 204, 206. The first conductive extension is achieved by using materials of conductive layers 134 of various levels 102. The first conductive extension couples the conductive strips of the stacks 204, 206 within the same level to each other and to one of the corresponding vertical connectors 112 of the first stepped connector configuration 110. For example, one of the first layers 102.1 of the first conductive extension couples the conductive strips of the stacks 204, 206 of the first level 102.1 to each other and to the corresponding vertical connector 122.1 of the first level 102.1. .

The patterning step is also formed at a second conductive extension (not shown) at the second end of the stack 200, 202. The second conductive extension is achieved by using materials of the conductive layers 134 of the various levels 102. The second conductive extension couples the conductive strips of the stacks 200, 202 within the same level to each other and to one of the corresponding vertical connectors 122 of the second stepped connector configuration 120. For example, one of the first levels 102.1 of the second conductive extension couples the conductive strips of the stacks 200, 202 of the first level 102.1 to each other and to the corresponding vertical connector 122.1 of the first level 102.1.

Figures 3A and 3B show top and cross-sectional views after a memory layer 300 is blanket deposited on the structures shown in Figures 2A and 2B.

Memory layer 300, for example, may be a programmable resistive memory material. For example, memory layer 300 can comprise a single layer of antifuse material. The antifuse material may be, for example, cerium oxide, cerium nitride, cerium oxynitride or other cerium oxide. Alternatively, other types of programmable resistive memory materials may be formed.

In alternative rather than blanket deposition, an oxidation process can be applied to form an oxide on the exposed side of the stacked conductive strips, where the oxide acts as a memory material.

The memory layer 300 may alternatively comprise a multilayer charge trapping structure comprising a tunneling layer, a charge trapping layer and a barrier layer. In one embodiment, the tunneling layer is tantalum oxide (O), the charge storage layer is tantalum nitride (N), and the barrier layer is tantalum oxide (O). Alternatively, the multi-layer charge trapping structure may comprise other charge storage structures, such as cerium oxynitride (Si _x O _y N _z ), cerium-rich nitrides, cerium-rich oxides, capture layers comprising embedded nanoparticles, and the like.

In one embodiment, a band gap engineering SONOS (BE-SONOS) charge storage structure comprising a dielectric tunneling layer is included, the dielectric tunneling layer comprising an inverted U-shaped valence band under zero bias (valence) A combination of materials of band). In one embodiment, the composite tunnel type dielectric layer includes a first layer called a hole tunneling layer, a second layer called a band offset layer, and a third layer called an isolation layer. .

Figures 4A and 4B show the results of depositing a layer of conductive material 400 (e.g., a polysilicon having an N-type or P-type doping) on the structures shown in Figures 3A and 3B. As described below, the material layer 400 is used as a lower portion of the conductive line, which will serve as a word line for the device. A high aspect ratio deposition technique such as polycrystalline germanium for low pressure chemical vapor deposition may be utilized to completely fill the open regions or trenches between the ridge stacks 200, 202, 204, 206.

5A and 5B show the etch back of layer 400 as a result of exposing portions of memory layer 300 above the upper surface of stacks 200, 202, 204, 206 and above the upper surfaces of vertical connectors 112, 122.

6A and 6B show the results after performing a planarization process to remove the exposed portions of the memory layer 300. The planarization process exposes the upper surfaces of the vertical connectors 150, 152, 154, 156 of the stacks 200, 202, 204, 206, and the upper surfaces of the vertical connectors 112, 122. The planarization process may be, for example, chemical mechanical polishing (CMP).

7A and 7B show the results of depositing a conductive material of a first layer 700 on the structures of Figs. 6A and 6B, followed by deposition of a conductive material of a second layer 710 to form a top gate material 720. In this embodiment, the top gate material 720 is a multilayer construction. Alternatively, the top gate material 720 may be a single layer of material.

As described below, the top gate material 720 is used as the upper portion of the conductive line, which will serve as the word line for the device. In addition, the top gate material 720 is used as a contact pad for the vertical connectors 150, 152, 154, 156 and as the vertical connectors 112, 122 of the first and second first stepped connector configurations 110, 120. Contact pads.

Figures 8A and 8B show the results of forming a patterned photoresist mask 800 in the structures of Figures 8A and 8B. The photoresist mask 800 includes a plurality of lines 810 extending in parallel in a first direction. These lines 810 define the location of the memory cells and conductive lines that will serve as the word lines for the device.

The photoresist mask 800 also includes a plurality of lines 820 extending in parallel in a first direction. These lines 820 define the location of the block selection transistor and the conductive line, which will serve as the ground selection line for the device.

The photoresist mask 800 also includes a plurality of lines 830 extending in parallel in a first direction. These lines 830 define the location of the common power line. As explained in more detail below, the common power line acts as a contact pad for the vertical connectors 150, 152, 154, 156. In an alternate embodiment, rather than defining a common power line extending across the stack, features defining the location of the individual contact pads may be patterned to cover each of the vertical connectors 150, 152, 154, 156.

The photoresist mask 800 also includes a plurality of features 840 that define locations for contact pads for the vertical connectors 112 in the first connector configuration 110. The photoresist mask 800 also includes a plurality of features 850 that define locations for the contact pads for the vertical connectors 122 of the second connector structure 120.

The photoresist mask 800 also includes a plurality of features 860 that define the locations of the string selection transistors disposed at the second end of the stack.

FIGS. 9A, 9B, and 9C show the results of etching the masks 800 by using the photoresist mask 800 as an etch mask to etch the structures shown in FIGS. 8A and 8B. Etching utilizes a single photoresist mask 800 without the need to etch through the ridge stack. The polysilicon on the yttrium oxide and tantalum nitride can be etched by a highly selective etch process for polysilicon, wherein the process stops on the lower dielectric layer 125.

The etching process forms a plurality of conductive lines 900 as word lines for the 3D memory array. These conductive lines 900 create a 3D array of memory cells at the intersection between the surface of the stacked semiconductor strips and the conductive lines 900. In this example, the memory cells in the semiconductor strip are arranged in a NAND string. The memory cell has a memory component within a portion of the memory layer 300 between the conductive line 900 and the semiconductor strip used as the local bit line. In the example shown here, each memory cell is a dual gate field effect transistor having active regions on both sides of the interface between the corresponding semiconductor strip and conductive line 900.

The etch process forms a first common power line 910 that is in contact with the upper surface of the vertical connectors 150, 152 of the stacks 200, 202. The first common power line 910 acts as a contact pad for the vertical connectors 150, 152.

The etch process also forms a second common power line 920 that is in contact with the upper surface of the vertical connectors 154, 156 of the stacks 204, 206. The second common power line 920 acts as a contact pad for the vertical connectors 154, 156.

The etch process also forms string select transistors 930, 932, 934, 936 disposed at the second ends of the stacks 200, 202, 204, 206. String select transistors 930, 932 are used to selectively couple the semiconductor strips of stacks 200, 202 to corresponding vertical connectors 122. String select transistors 934, 936 are used to selectively couple the semiconductor strips of stacks 204, 206 to corresponding vertical connectors 112.

The etch process also forms a first set of block select transistors underlying a first ground select line configuration 940. The etch process also forms a second set of block select transistors underlying a second ground select line structure 950.

The etch process also forms a contact pad 962 for the vertical connector 112 labeled 962.1-962.4. The etch process also forms contact pads 972 for vertical connectors 122 labeled 972.1-972.4.

During etching, the reticle features and subsequently formed contact pads protect the underlying vertical connectors 150, 152, 154, 156. If these reticle features are not present, the relatively thick polysilicon layer within the open area or trench adjacent the vertical connector is removed, and the vertical connectors 150, 152, 154, 156 are completely etched away. The memory layer, thereby allowing a portion of the vertical connectors 150, 152, 154, 156 to be etched away, will effectively destroy the device.

Next, a dielectric fill material 1000 is deposited on the structure shown in Figures 9A-9C. A lithographic patterning step is then performed to form contact openings extending through dielectric fill 1000 for contact pads 962, 972, power lines 910, 920, and string selection transistors 930, 932, 934, 936. The contact surface is exposed. Next, the contact opening portion is filled with a conductive material such as tungsten to form a corresponding conductive contact portion 1010. The resulting structure is shown in Figures 10A and 10B.

Additional post-stage processing (BEOL) processing can then be performed to complete the 3D memory device. In general, the formation formed by the BEOL process can include additional contacts, inner dielectric materials, and various metal layers for interconnection between the appropriate conductive contacts 1010 and the access circuitry for The memory unit of the 3D array is coupled to the peripheral circuit.

As a result of these processes, control circuits, bias circuits, and decoder circuits such as those shown in FIG. 11 can be formed. In some embodiments, the decoding layout described in U.S. Application Serial No. 13/078,311 is incorporated herein by reference.

Figure 11 is a simplified block diagram of an integrated circuit 1175 in accordance with one embodiment of the present technology. Integrated circuit 1175 includes a 3D stacked memory array having improved contact structures fabricated in the manner described herein. A column of decoders 1161 is coupled to a plurality of word lines 1162 and arranged along columns in the memory array 1160. A row of decoders 1163 is coupled to a plurality of string select lines 1164 for selecting rows in the memory array 1160 for reading and programming data from the memory cells in the array 1160. A planar decoder 1158 is coupled to a plurality of levels in the memory array 1160 via global bit lines 1159. The global bit line 1159 is coupled to local bit lines (not shown) that are arranged along rows in various levels of the memory array 1160. The address on bus 1165 is provided to row decoder 1163, column decoder 1161, and plane decoder 1158. In this example, the sense amplifier and data input structures in block 1166 are coupled to row decoder 1163 via data bus 1167. The data is supplied from the input/output port on the integrated circuit 1175 or from other sources inside or outside the integrated circuit 1175 via the data input line 1171 to the data input configuration in block 1166. In the illustrated embodiment, another circuit 1174 is included on an integrated circuit, such as a general purpose processor or special purpose application circuit, or provides a system-on-a-system supported by the array (system-on-a- Chip) A combination of functional modules. The data is provided from the sense amplifiers in block 1166 to the input/output ports on integrated circuit 1175 via data output line 1172, or to other data objects internal or external to integrated circuit 1175.

In this example, the controller implemented by using the bias configuration state machine 1169 controls the application of the bias configuration power supply voltage generated or provided via the voltage source, or supplies, for example, the read and program voltages in block 1168. The controller can be implemented by using a special purpose logic circuit as is known in the art. In an alternate embodiment, the controller includes a general purpose processor that may be implemented on the same integrated circuit that executes a computer program to control the operation of the device. In still other embodiments, a combination of special purpose logic circuitry and a general purpose processor may be used for the implementation of the controller.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100. . . structure

102, 102.1-102.4. . . Class

110. . . First stepped connector construction

112, 112.1-112.4. . . Vertical connector

114. . . Dielectric sidewall spacer

114.2, 114.3, 114.4. . . Vertical connector

120. . . Second stepped connector construction

122. . . Vertical connector

124, 124.1-124.4. . . Dielectric sidewall spacer

125. . . Dielectric layer

126. . . Dielectric layer

134. . . Semiconductor material layer

134.1-134.4. . . Conductive layer

136, 136.1-136.4. . . Insulating material layer

140. . . Lower semiconductor substrate

150, 152, 154, 156. . . Vertical connector

200, 202, 204, 206. . . Stacking

300. . . Memory layer

400. . . Conductive material layer

700. . . level one

710. . . Second floor

720. . . Top gate material

800. . . Photoresist mask

810, 820, 830. . . line

840, 850, 860. . . Characteristic department

900. . . Conduction line

910. . . First common power cord

920. . . Second common power cord

930, 932, 934, 936. . . String selection transistor

940. . . First ground selection line construction

950. . . Second ground selection line construction

962, 962.1-962.4. . . Contact pad

972, 972.1-972.4. . . Contact pad

1000. . . Dielectric fill material / dielectric fill

1010. . . Conductive contact

1158. . . Planar decoder

1159. . . Global bit line

1160. . . Memory array

1161. . . Column decoder

1162. . . Word line

1163. . . Row decoder

1164. . . String selection line

1165. . . Busbar

1166. . . Square

1167. . . Data bus

1168. . . Square

1169. . . Bias configuration state machine

1171. . . Data input line

1172. . . Data output line

1174. . . Circuit

1175. . . Integrated circuit

1A and 1B are cross-sectional and plan views showing the structure after the first stage in the process for fabricating a three-dimensional stacked memory device.

2A and 2B are cross-sectional and plan views showing the structure after the second stage in the process for fabricating the three-dimensional stacked memory device.

3A and 3B are cross-sectional and plan views showing the structure after the third stage in the process for fabricating the three-dimensional stacked memory device.

4A and 4B are cross-sectional and plan views showing the structure after the fourth stage in the process for fabricating the three-dimensional stacked memory device.

5A and 5B are cross-sectional and plan views showing the structure after the fifth stage in the process for fabricating the three-dimensional stacked memory device.

6A and 6B are cross-sectional and plan views showing the structure after the sixth stage in the process for fabricating the three-dimensional stacked memory device.

7A and 7B are cross-sectional and plan views showing the structure after the seventh stage in the process for fabricating the three-dimensional stacked memory device.

8A and 8B are cross-sectional and plan views showing the structure after the eighth stage in the process for fabricating the three-dimensional stacked memory device.

Figures 9A, 9B, and 9C show cross-sectional and top views of the structure after the ninth stage in the process for fabricating a three-dimensional stacked memory device.

10A and 10B are cross-sectional and plan views showing the structure after the tenth stage in the process for fabricating a three-dimensional stacked memory device.

Figure 11 is a simplified block diagram of an integrated circuit in accordance with an embodiment of the present technology.

910. . . First common power cord

1000. . . Dielectric fill material / dielectric fill

1010. . . Conductive contact

Claims (26)

A method of fabricating a memory device, the method comprising: forming a plurality of conductive strip stacks separated by an insulating material, wherein a first end of each of the conductive strip stacks in the stacks is by a plurality of corresponding vertical lines Forming a connector to be interconnected; forming a memory layer on the surface of the plurality of conductive strip stacks; forming a conductive material over the stacks and on the upper surface of the vertical connectors; and patterning the conductive material to form a plurality of strips Conducting a line and forming a plurality of contact pads extending across the stack and the contact pads on the upper surfaces of the vertical connectors, and the conductive lines have a plurality of Stacking the surfaces of the contact pads on the upper surfaces of the vertical connectors such that a plurality of memory elements in the memory layer are defined on the side surfaces of the conductive strips and the conductive lines To establish a memory cell of a 3-dimensional array that is easily accessible to the contact pads via the conductive lines. The method of claim 1, wherein the forming the memory layer comprises: forming the memory layer on a surface above the insulating material layer on the stack and on the upper surface of the vertical connectors And exposing the conductive material; and forming a layer of the first conductive material between adjacent stacks of the stacks; removing portions of the memory layer to expose the vertical connectors The upper surface and the stacked upper surface; depositing a second conductive material layer on the plurality of residual portions of the first conductive material, the exposed upper surfaces of the vertical connectors, and the stacked Upper surfaces; and patterning the first and second layers of conductive material to form the conductive lines and the contact pads. The method of claim 2, wherein the first conductive material layer is different from the second conductive material layer. The method of claim 1, wherein the step of forming the stack of conductive strips exposes sidewalls of the vertical connectors; the step of forming the memory layer includes forming the memory layer at the vertical connectors And exposing the conductive material; and forming a plurality of memory layer sidewall spacers on the sidewalls of the vertical connectors and contacting the lower surfaces of the contact pads, the sidewalls The separator separates the residual conductive material under the contact pads from the vertical connectors. The method of claim 1, further comprising: forming a dielectric filling material over the conductive lines and the contact pads; forming a plurality of contact openings in the dielectric filling material, Exposing the contact surfaces of the corresponding contact pads; and filling the contact openings with the conductive material to form a corresponding plurality of conductive contacts. The method of claim 1, wherein the forming the stacking comprises forming a plurality of conductive extensions in a plurality of levels of the conductive strips, each of the conductive extension interconnects being at each of the specific layers a second end of the plurality of conductive strips, and further comprising a plurality of second vertical connectors that contact the corresponding conductive extensions of the particular ones of the layers and extend through the plurality of layers in the coverage Opening. The method of claim 6, wherein the forming the conductive material comprises forming the conductive material on the upper surface of the second vertical connectors; and the step of patterning the conductive material further forms a plurality A second contact pad is on the upper surface of the second vertical connectors. The method of claim 7, further comprising: forming a dielectric filling material over the conductive lines, the contact pads, and the second contact pads; forming a plurality of contact openings a contact surface of the dielectric filling material for exposing the corresponding contact pads and the corresponding second contact pads; and filling the contact openings with the conductive material to form a corresponding plurality of conductive portions Contact part. The method of claim 1, wherein the forming the conductive strips of the stack comprises forming a first set of stacks and forming a second set of stacks, the first and second sets being arranged in an alternating manner So that the adjacent stacks in the first group are separated by a single one of the stacks, and the adjacent stacks in the second set are the first set The stack of the single stack is separated, and the first ends of the conductive strips in the stacks of the first set are located at the first ends of the conductive strips in the second set opposite. The method of claim 1, wherein the memory layer comprises an antifuse material layer. The method of claim 1, wherein the memory layer comprises a multilayer charge storage structure. The method of claim 1, wherein the conductive strips comprise a doped semiconductor material such that the conductive strips are configured for operation of the memory cells to serve as a plurality of charge storage transistors. The method of claim 1, wherein the patterning the conductive material forms a plurality of string selection transistors disposed at the second ends of the stacks. A memory device comprising: a plurality of conductive strip stacks separated by an insulating material; a plurality of vertical connectors interconnecting the first ends of the conductive strip stacks in the stacks; a plurality of conductive lines extending across Passing over the stacks and having a plurality of surfaces compliant with the stacks such that a plurality of interface regions of a 3-dimensional array are established at intersections between the surfaces of the conductive strips and the conductive lines; a plurality of contact welds a pad on the upper surface of the vertical connectors, wherein the contact pads and the conductive materials of the conductive lines are part of the same patterned material level; and a plurality of memory elements are located In the interface region, a plurality of memory cells of a three-dimensional array that are easily connected to the contact pads via the conductive lines are established. The memory device of claim 14, wherein the conductive lines comprise: a first conductive material within a plurality of trenches between adjacent stacks of the stacks; and a second conductive A material extending across the plurality of upper surfaces of the plurality of stacked and within the trenches of the first conductive material. The memory device of claim 15, wherein the first conductive material is different from the second conductive material. The memory device of claim 14, further comprising a plurality of sidewall spacers on the sidewalls of the vertical connectors and in contact with the lower surfaces of the contact pads, the sidewall spacers The residual conductive material under the contact pads is separated from the vertical connectors. The memory device of claim 14, further comprising: a dielectric fill covering the conductive lines and the contact pads; and a plurality of conductive contacts from which the upper surface is filled Extending to contact the corresponding conductive lines and the contact pads. The memory device of claim 14, further comprising: a plurality of conductive extensions located in a plurality of layers of the conductive strips, each of the conductive extension interconnections being within each of the specific layers a second end of the plurality of conductive strips; a plurality of second vertical connectors contacting the corresponding conductive extensions of the respective ones of the layers and extending through a plurality of openings in the layers covered; and a plurality of The two contact pads are located on the upper surface of the second vertical connectors, wherein the second contact pads and the conductive materials of the conductive lines are part of the same patterned material level. The memory device of claim 19, further comprising: a dielectric fill covering the conductive lines, the contact pads and the second contact pads; and a plurality of conductive contacts, Extending from the upper surface of the dielectric fill to contact the corresponding contact pads and the second contact pads. The memory device of claim 14, wherein the stacked conductive strips comprise a first set of stacks and a second set of stacks, the first and second sets being arranged in an alternating manner such that The adjacent stacks in the first group are separated by a single one of the stacks in the second group, such that the adjacent stacks in the second group are stacked by the second assembled single stack Separating and spacing adjacent stacks in the second set by a single stack in the first set, and the first ends of the conductive strips in the stacks of the first set are Opposite to the first ends of the plurality of conductive strips in the second group. The memory device of claim 21, further comprising: a first interconnecting region, comprising: a plurality of first conductive extensions, located in a plurality of layers of the conductive strips, each of the first conductive layers Extending the second ends of the plurality of conductive strips of the first set of stacks within each of the particular levels; and a plurality of second vertical connectors contacting the corresponding ones of the respective ones of the levels a conductive extending and extending through the plurality of openings in the plurality of layers covered; and a second interconnecting region comprising: a plurality of second conductive extensions, located in a plurality of layers of the conductive strips, each The second conductive extension interconnects the second ends of the plurality of conductive strips of the second set of stacks within each of the specific levels; and a plurality of third vertical connectors that contact the respective ones of the plurality of levels The second conductive extensions extend through the plurality of openings in the plurality of layers covered. The memory device of claim 14, wherein the memory layer comprises an antifuse material layer. The memory device of claim 14, wherein the memory layer comprises a multi-layer charge storage structure. The memory device of claim 14, wherein the conductive strips comprise a doped semiconductor material such that the conductive strips are configured for operation of the memory cells to serve as a plurality of charge storage devices. Crystal. The memory device of claim 14, further comprising a plurality of string selection transistors disposed at the second ends of the stacks, the string selection transistors having a plurality of gates, the gates The poles have a plurality of upper surfaces that are coplanar with the upper surfaces of the conductive lines.