TW201320089A - Self-test driver circuit - Google Patents

Abstract

A self-test driver circuit includes a first register, a second register and a comparator. The first register stores first programmable data. The second register stores second programmable data that are preconfigured to be the same as the first programmable data. The comparator compares the first and the second programmable data after a programming process, and generates an error signal when the first and the second programmable data are different. A test method applied in a self-test driver circuit is also disclosed herein.

Description

Self test drive circuit

SUMMARY OF THE INVENTION The present invention is directed to a drive circuit and, more particularly, to a programmable drive circuit.

Liquid crystal displays have the advantages of being thin and light, and low in power consumption, and have been widely used in modern information devices such as notebook computers, mobile phones, and personal digital assistants (PDAs) in recent years.

Since liquid crystal displays are compatible with semiconductor process technology, they have rapidly expanded to a wide range of application levels and have even become mainstream in flat panel displays. In a liquid crystal display, driving an integrated circuit (IC) is one of the important components, which accounts for a relatively high cost of the liquid crystal display. Therefore, how to ensure the quality of the driver IC is a key to determining the pros and cons of the flat panel display.

In the current process of programming (or burning) the driver IC, it mainly programs the required parameters such as ID code, common voltage value (VCOM), etc. (or The method of burning is written into the driver IC, and then the required parameters are read from the driver IC through the corresponding transmission interface. The foregoing transmission interface may be a corresponding transmission of a Serial Peripheral Interface (SPI), a Mobile Industry Processor Interface (MIPI), or a Mobile Display Digital Interface (MDDI), etc. interface.

However, since the above-mentioned MIPI and MDDI transmission interfaces are all high-speed serial transmission interfaces, it is usually necessary to first read out the required parameters by using an interface conversion device (for example, bridge IC), and then data transmission is performed. This determines whether the written parameters are correct. As a result, the test process that determines whether the parameters written correctly are correct is quite complicated.

For this reason, it is necessary to propose a driving circuit or a test method for conveniently and easily testing whether the parameters of the stylized (or burned) are correct.

One aspect of the present invention is to provide a self test drive circuit whereby the process of testing the drive circuit is simplified.

One embodiment of the present invention is directed to a self test drive circuit including a first register, a second register, and a comparator. The first register is configured to store a first programmable data. The second register is configured to store one of the second programmable data that is the same as the first programmable data preset. The comparator is configured to compare the first programmable data and the second programmable data after a stylization process, and generate an error signal when the first programmable data and the second programmable data are different.

In an embodiment of the invention, the self test drive circuit further includes a memory. The memory is programmed to store a third executable data that is identical to the first programmable data or the second programmable data preset during the stylization process, and load the third programmable data The second register.

The comparator can generate an error signal when the third programmable data stored in the memory is not the same as the first programmable data or is different from the second programmable data.

In another embodiment of the invention, the comparator generates a correct signal when the first programmable data is identical to the second programmable data. The error signal can be a clock signal having a duty cycle ratio of N:1 or a low level signal, and the correct signal can be a clock signal having a duty cycle ratio of 1:1 or a high level signal, wherein N is a positive integer greater than one.

In an embodiment of the invention, the self test drive circuit further includes a multiplexer. The multiplexer is configured to process the error signal and a data transmission enable signal to selectively output one of the error signal and the data transmission enable signal.

Another aspect of the present invention is to provide a test method in a self test drive circuit whereby the process of testing the data written to the drive circuit is simplified.

Another embodiment of the present invention is directed to a test method in a self test drive circuit that includes the following steps. Writing a first programmable data and storing a second programmable data that is the same as the first programmable data preset. In addition, after the stylization process, the first programmable data and the second programmable data are compared. When the first programmable data is different from the second programmable data, an error signal is generated. When the first programmable data is identical to the second programmable data, a correct signal is generated.

In an embodiment of the invention, the step of storing the second programmable material further comprises the following steps. First, a memory is programmed to store a third programmable data that is identical to the first programmable data or the second programmable data. Next, the third programmable data is loaded as the second programmable data. An error signal is generated when the third programmable data is different from the first programmable data or different from the second programmable data.

In another embodiment of the present invention, the error signal is a clock signal having a duty cycle ratio of N:1 or a low level signal, and the correct signal is a clock signal having a duty cycle ratio of 1:1. Or a high level signal, where N is a positive integer greater than one.

According to the technical content of the present invention, the self-test driving circuit and the testing method thereof are applied, and no error occurs in the process of programming the driving circuit, or an error occurs in the data reading process in the driving circuit, and the self-test can be directly passed. The signal outputted by the driving circuit determines whether the driving circuit is correct during the stylization process, and can simultaneously know whether the stylized data is correct.

The embodiments are described in detail below with reference to the accompanying drawings, but the embodiments are not intended to limit the scope of the invention, and the description of the structure operation is not intended to limit the order of execution, any component recombination The structure, which produces equal devices, is within the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to the original dimensions.

As used herein, "about", "about" or "substantially" generally means that the error or range of the index value is within 20%, preferably within 10%, and more preferably It is within 5 percent. In the text, unless otherwise stated, the numerical values referred to are regarded as approximations, that is, the errors or ranges indicated by "about", "about" or "roughly".

In addition, as used herein, "coupled" and "connected" may mean that two or more elements are in direct physical or electrical contact with each other, or indirectly in physical or electrical contact with each other. It can also mean that two or more components operate or act in each other.

FIG. 1 is a schematic diagram of a self-test driving circuit according to an embodiment of the invention. The self-test driving circuit 100 can be programmed (or burned) into a required data (including identification code, common voltage, ..., etc.) or a desired value in a programming (or burning) process. Then, it is self-aligned or tested whether the programmed data is incorrect, so the programmed data can be directly determined in the self-test driving circuit 100, and it can be determined whether it is correct without being read first.

As used herein, "programming", which can also be referred to as "burning", can refer to a stylized approach that includes an action or step of encoding a data program.

In practice, the self-test driving circuit 100 may be a driving integrated circuit (IC) applied to a liquid crystal display, or may be a driving integrated circuit applied to other devices; in other words, the self-test driving circuit 100 may be The actual needs are applied to any electronic device.

As shown in FIG. 1 , the self test drive circuit 100 includes a first register 110 , a second register 120 , and a comparator 130 . The input end of the comparator 130 is coupled to the output ends of the first register 110 and the second register 120. The first register 110 is configured to store a first programmable data D1. The second register 120 is configured to store a second programmable data D2 that is the same as the preset of the first programmable data D1. The comparator 130 is configured to compare the first programmable data D1 and the second programmable data D2 after a stylization process, and accordingly generate a determination signal MTR.

The above and the following "programmable data" may be data written during the stylization process, or may be pre-stored before the stylization process. Specifically, the stylized data may be pre-stored by the temporary register. data. For example, the first programmable data D1 may be data stored in the first temporary storage unit 110 in advance. Therefore, the above-mentioned "programmable data" may also be referred to as "storage data", that is, the first register 110 is used to store the first register data, and the second register 120 is Used to store the second register data.

In other words, the above-mentioned and the following "programmable materials" are merely illustrative and are not intended to limit the invention, and those skilled in the art can use the temporary storage device according to actual needs without departing from the spirit and scope of the present invention. Store the corresponding information.

In practice, the first register 110 and the second register 120 may be the same or different, and the first programmable data D1 and the second programmable data D2 include an identification code, a common voltage, ... Wait for the required parameters or set values.

In operation, the first programmable data D1 can be written into the first temporary register from a multiple-time programming (MTP) device (not shown) outside the driving circuit 100 during the stylization process. 110. In addition, the second programmable data D2 can be programmed (or burned) from the plurality of programmable devices into the self-test drive circuit 100 and then loaded into the second register 120. Then, after the stylization process, the comparator 130 compares the first programmable data D1 and the second programmable data D2, and outputs a determination signal MTR from the hardware pin of the test driving circuit 100. It is determined whether the first programmable data D1 and the second programmable data D2 are the same. In this way, the signal output from the test drive circuit 100 can be directly determined whether the drive circuit 100 is correct during the stylization process, and at the same time, whether the stylized data is correct.

In an embodiment, when the first programmable data D1 and the second programmable data D2 are different, the determination signal MTR is an error signal. When the first programmable data D1 is identical to the second programmable data D2, the determination signal MTR is a correct signal.

In an embodiment, when the determination signal MTR is an error signal, the error signal may be a clock signal having a duty cycle ratio of N:1 or a low level signal, where N is greater than 1 A positive integer; and when the decision signal MTR is a correct signal, the correct signal can be a clock signal having a duty cycle ratio of 1:1 or a high level signal. The above error signals and correct signals are merely examples and are used for convenience determination, and are not intended to limit the present invention. In other words, those skilled in the art can use various signals that can be distinguished or determined according to actual needs, thereby distinguishing between an error signal and a correct signal.

2 is a schematic diagram of a self-test driving circuit according to another embodiment of the present invention. In the present embodiment, the self test drive circuit 200 includes a first register 210, a second register 220, a comparator 230, and a memory 240. The input end of the comparator 230 is coupled to the output of the first register 210 and the second register 220, and the input of the second register 220 is coupled to the output of the memory 240.

Similarly, the first register 210 and the second register 220 are respectively configured to store the first programmable data D1 and the second programmable data D2, and the comparator 230 is used to compare the first after the stylization process. The data D1 and the second programmable data D2 can be programmed and the decision signal MTR is generated accordingly. In addition, the memory 240 is configured to be programmed to store a third programmable data D3 that is identical to the first programmable data D1 or the second programmable data D2 during the stylization process. The third programmable data D3 is loaded into the second register 220 after the process, so that the third programmable data D3 can be used as the second programmable data D2.

In practice, the first register 210 and the second register 220 can be the same or different, and the memory 240 can be a non-volatile memory (NVM), and the first programmable data D1, the second programmable data D2 and the third programmable data D3 include required parameters or set values such as identification code, common voltage, and the like.

In operation, the first programmable data D1 can be written into the first temporary memory 210 from a plurality of programmable devices (not shown) external to the driving circuit 200 during the stylization process, or can be first programmable. The data D1 can be pre-stored in the first register 210, and the third programmable data D3 can be programmed (or burned) from the plurality of programmable devices simultaneously during the programming of the memory 240. Into the memory 240. For example, the data can be programmed (or burned) from the first register 210 into the memory 240 such that the memory 240 stores the third programmable data D3.

Then, after the stylization process, the third programmable data D3 can be loaded into the second register 220 by the memory 240, so that the second register 220 can store the second programmable data D2. Then, the comparator 230 compares the first programmable data D1 and the second programmable data D2, and outputs a determination signal MTR from the hardware pin of the test driving circuit 200, thereby determining the first programmable Whether the data D1 is the same as the second programmable data D2 or the third programmable data D3.

For example, in the case where the data D3 is preset to be the same as the data D1, when the stylization process or the data reading process is correct, the data D3 programmed (or burned) into the memory 240 is of course related to the data D1. The same, and the data D3 will be the same as the data D2, so that the data D1 is the same as the data D2, and the determination signal MTR generated by the comparator 230 is the correct signal.

Secondly, when an error occurs in the stylization process, so that the data D3 programmed (or burned) into the memory 240 is different from the data D1, even if the data reading process is correct and the data D3 is the same as the data D2, the data D1 Still different from the data D2, the decision signal MTR generated by the comparator 230 is an error signal.

Moreover, when the stylization process is correct, if the data reading process is incorrect and the data D3 is different from the data D2, the data D1 and the data D2 are still different, so the determination signal MTR generated by the comparator 230 is still Error signal.

In this way, whether the programming of the driver circuit 200 by the programmable device is wrong, or an error occurs in the data reading process of the driving circuit 200, the signal output from the driving circuit 200 can be directly transmitted to determine the driving. The circuit 200 is correct during the stylization process, and at the same time, it is known whether the stylized data is correct.

In this embodiment, when the determination signal MTR is an error signal, the error signal may be a clock signal having a duty cycle ratio of N:1 or a low level signal, where N is greater than 1 A positive integer; and when the decision signal MTR is a correct signal, the correct signal can be a clock signal having a duty cycle ratio of 1:1 or a high level signal. The above error signals and correct signals are merely examples and are used for convenience determination, and are not intended to limit the present invention. In other words, those skilled in the art can use various signals that can be distinguished or determined according to actual needs, thereby distinguishing between an error signal and a correct signal.

FIG. 3 is a schematic diagram of a self-test driving circuit according to another embodiment of the present invention. In the present embodiment, the self test drive circuit 300 includes a first register 310, a second register 320, a comparator 330, a memory 340, and a multiplexer 350. The input end of the comparator 330 is coupled to the output of the first register 310 and the second register 320, and the input of the second register 320 is coupled to the output of the memory 340. The input end of the multiplexer 350 is coupled to the output of the comparator 330 for receiving the decision signal MTR output by the comparator 330 and additionally receiving a data transmission enable signal TE.

Similarly, the first register 310 and the second register 320 are respectively configured to store the first programmable data D1 and the second programmable data D2, and the comparator 330 is used to compare the first after the stylization process. The data D1 and the second programmable data D2 can be programmed and the decision signal MTR is generated accordingly. In addition, the memory 340 is used to programmatically store the third programmable data D3 that is the same as the preset of the first programmable data D1 or the second programmable data D2 during the stylization process, and is programmed. The third programmable data D3 is loaded into the second register 220 after the process, so that the third programmable data D3 can be used as the second programmable data D2. In addition, the multiplexer 350 is configured to process the determination signal MTR and the data transmission enable signal TE to selectively output one of the two signals in a corresponding situation; in other words, the multiplexer 350 is switched. The output determination signal MTR or the output data transmission enable signal TE.

In practice, the first register 310 and the second register 320 may be the same or different, and the memory 340 may be a non-volatile memory (NVM), and the first programmable The data D1, the second programmable data D2, and the third programmable data D3 include required parameters or set values such as identification code, common voltage, and the like.

In operation, the first programmable data D1 can be written into the first temporary register 310 from a plurality of programmable devices (not shown) external to the driving circuit 300 during the stylization process, or can be first programmable. The data D1 can be pre-stored in the first register 310, while the third programmable data D3 can be programmed (or burned) into the memory 340 from the plurality of programmable devices via a stylization process. For example, the data can be programmed (or burned) from the first register 310 into the memory 340 such that the memory 340 stores the third programmable data D3.

Then, after the stylization process, the third programmable data D3 can be loaded into the second register 320 by the memory 340, so that the second register 320 can store the second programmable data D2. Then, the comparator 330 compares the first programmable data D1 in the first temporary register 310 with the second programmable data D2 in the second temporary storage 320, and the hardware of the self-test driving circuit 300 The pin outputs a decision signal MTR, thereby determining whether the first programmable data D1 is identical to the second programmable data D2 or the third programmable data D3.

As described above, in the case where the data D3 is preset to be the same as the data D1, when the stylization process or the data reading process is correct, the determination signal MTR generated by the comparator 330 is a correct signal; when an error occurs in the stylization process, When the data D3 programmed (or burned) into the memory 340 is different from the data D1, the determination signal MTR generated by the comparator 330 is an error signal; when an error occurs in the data reading process, the data D3 and the data D2 are caused. When not the same, the decision signal MTR generated by the comparator 330 is still an error signal.

In this way, whether the programming of the driver circuit 300 by the programmable device is wrong, or an error occurs in the data reading process of the driving circuit 300, the signal output from the driving circuit 300 can be directly transmitted to determine the driving. The circuit 300 is correct during the stylization process, and at the same time, it is known whether the stylized data is correct.

Secondly, the data transmission enable signal TE can be generally output through the hardware pin inherent to the drive circuit 300, thereby determining whether the drive circuit 300 starts or stops the data transmission cycle. Therefore, if the determination signal MTR and the data transmission enable signal TE are processed by the multiplexer 350 so that one of the determination signal MTR and the data transmission enable signal TE can be output through the switching of the multiplexer 350, the determination signal MTR and The data transmission enable signal TE can be output through the original hardware pin, thereby preventing the drive circuit 300 from having to configure different pins for the signal MTR and TE output, and further saving cost.

The circuit structure features in the self-test driving circuit in the above embodiments may be formed separately or in combination with each other. Therefore, the above embodiments are merely for convenience of description, and all the embodiments can be selectively matched with each other according to actual needs to fabricate the self-test driving circuit in the present disclosure, which is not used for The invention is defined.

4 is a flow chart of a test method in a self test drive circuit according to an embodiment of the invention. First, the first programmable data is written, and the second programmable data is the same as the first programmable data preset (step 402). Next, the first programmable data and the second programmable data are compared (step 404). Then, it is determined whether the first programmable material is identical to the second programmable data (step 406). When the first programmable data is different from the second programmable data, an error signal is generated (step 408). When the first programmable data is identical to the second programmable data, a correct signal is generated (step 410).

In an embodiment, the step of storing the second programmable data may further comprise the following steps. First, a memory is programmed to store a third programmable data that is identical to the first programmable data or the second programmable data. Then, the third programmable data is loaded as the second programmable data.

In another embodiment, the above testing method may further comprise the following steps. An error signal is generated when the third programmable data is different from the first programmable data or different from the second programmable data.

In this embodiment, when the determination signal MTR is an error signal, the error signal may be a clock signal having a duty cycle ratio of N:1 or a low level signal, where N is greater than 1 A positive integer; and when the decision signal MTR is a correct signal, the correct signal can be a clock signal having a duty cycle ratio of 1:1 or a high level signal. The above error signals and correct signals are merely examples and are used for convenience determination, and are not intended to limit the present invention. In other words, those skilled in the art can use various signals that can be distinguished or determined according to actual needs, thereby distinguishing between an error signal and a correct signal.

FIG. 5 is a flow chart of a test method in a self test drive circuit according to another embodiment of the invention. For the sake of clarity, please refer to Figures 2 and 5 at the same time. First, the programmable data D1 is written to the first register 210 (step 502). Next, while writing the programmable data D1, the memory 240 is programmed (or burned) to program (or burn) the programmable data D3 that is the same as the preset of the programmable data D1. Memory 240 (step 504). Then, the programmable data D3 is loaded from the memory 240 to the second temporary memory 220, so that the programmable data D3 is additionally stored in the second temporary storage 220 as the programmable data D2 (step 506). Then, the programmable data D1 and the programmable data D2 are compared (step 508).

Next, it is determined whether the programmable data D1 is identical to the programmable data D2 (step 510). When the programmable data D1 is different from the programmable data D2, an error signal is generated (step 512). When the programmable data D1 is identical to the programmable data D2, a correct signal is generated (step 514).

In this embodiment, when the determination signal MTR is an error signal, the error signal may be a clock signal having a duty cycle ratio of N:1 or a low level signal, where N is greater than 1 A positive integer; and when the decision signal MTR is a correct signal, the correct signal can be a clock signal having a duty cycle ratio of 1:1 or a high level signal. The above error signals and correct signals are merely examples and are used for convenience determination, and are not intended to limit the present invention. In other words, those skilled in the art can use various signals that can be distinguished or determined according to actual needs, thereby distinguishing between an error signal and a correct signal.

The steps mentioned in this embodiment can be adjusted according to actual needs, except that the order is specifically described, and even can be performed simultaneously or partially simultaneously. The flowcharts shown in FIG. 4 and FIG. It is merely an example and is not intended to limit the invention.

According to the above, the self-test driving circuit and the testing method thereof are applied, and the error occurs in the process of programming the driving circuit, or the data reading process in the driving circuit is in error, and can be directly output through the self-test driving circuit. The signal determines whether the driver circuit is correct during the stylization process, and can also know whether the stylized data is correct.

In addition, the application of the self-test driving circuit and the testing method thereof can not only directly know whether the stylized process is correct by the hardware pin of the driving circuit, but also facilitate the testing of the driving circuit, and save the detection time. Improve the accuracy of the test.

The present invention has been disclosed in the above embodiments, but it is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

100, 200, 300. . . Self test drive circuit

110, 210, 310. . . First register

120, 220, 320. . . Second register

130, 230, 330. . . Comparators

240, 340. . . Memory

350. . . Multiplexer

402-410, 502-514. . . step

FIG. 1 is a schematic diagram of a self-test driving circuit according to an embodiment of the invention.

2 is a schematic diagram of a self-test driving circuit according to another embodiment of the present invention.

FIG. 3 is a schematic diagram of a self-test driving circuit according to another embodiment of the present invention.

4 is a flow chart of a test method in a self test drive circuit according to an embodiment of the invention.

FIG. 5 is a flow chart of a test method in a self test drive circuit according to another embodiment of the invention.

300. . . Self test drive circuit

310. . . First register

320. . . Second register

330. . . Comparators

340. . . Memory

350. . . Multiplexer

Claims (11)

A self-test driving circuit includes: a first register for storing a first programmable data; and a second register for storing the same one of the first programmable data preset a second programmable data; and a comparator for comparing the first programmable data and the second programmable data after a stylization process, and the first programmable data and the second An error signal is generated when the stylized data is different. The self-test drive circuit of claim 1, further comprising: a memory for being programmed to store the first programmable data or the second programmable data preset during the stylization process The same one of the third programmable data, and the third programmable data is loaded into the second temporary register. The self-test drive circuit of claim 2, wherein the third programmable data stored in the memory is not the same as the first programmable data or the second programmable data The comparator generates the error signal when it is not the same. The self test drive circuit of claim 1, wherein the comparator generates a correct signal when the first programmable data is identical to the second programmable data. The self-test driving circuit of claim 4, wherein the error signal is a clock signal having a duty cycle ratio of N:1 or a low level signal, and the correct signal is a duty cycle ratio of 1 The clock signal of :1 or a high level signal, where N is a positive integer greater than one. The self-test driving circuit of claim 1, further comprising: a multiplexer for processing the error signal and a data transmission enable signal to selectively output one of the error signal and the data transmission enable signal By. A test method in a self-test drive circuit, comprising: writing a first programmable data; storing a second programmable data that is identical to the first programmable data preset; and after a stylization process Comparing the first programmable data with the second programmable data. The test method of claim 7, further comprising: generating an error signal when the first programmable data is different from the second programmable data; and when the first programmable data and the first When the two programmable data are the same, a correct signal is generated. The method of claim 7, wherein the storing the second programmable data further comprises: programming a memory to store the first programmable data or the second programmable data preset One of the same third programmable data; and the third programmable data is loaded as the second programmable data. The test method of claim 9, further comprising: generating the error signal when the third programmable data is different from the first programmable data or different from the second programmable data. The test method of claim 8, wherein the error signal is a clock signal having a duty cycle ratio of N:1 or a low level signal, and the correct signal is a duty cycle ratio of 1:1. The clock signal is either a high level signal, where N is a positive integer greater than one.