TW201320071A - Self-refresh control circuit and memory including the same - Google Patents

Abstract

An self-refresh control circuit for controlling a self-refresh operation of a memory device includes a self-refresh control logic block configured to control the memory device to perform the self-refresh operation and an initial refresh control block configured to activate the self-refresh control logic block in an initialization period of the memory device.

Description

Self-renew control circuit and memory including the same

Illustrative embodiments of the present invention relate to a memory and, more particularly, to a self-renew operation of a memory.

The present application claims priority to Korean Patent Application No. 10-2011-0063, filed on Jun. 29, 2011, the entire disclosure of which is hereby incorporated by reference.

The memory device receives different set values and sets the operational timing to begin its operation after being powered, and then a certain period of time elapses until the power supply is stable.

Figure 1 illustrates an initialization process for a dual data rate 3 (DDR3) synchronous dynamic random access memory (SDRAM) device.

Referring to Figure 1, the power supply voltages VDD and VDDQ are supplied, and the reset signal RESETB, which is a signal for resetting different circuits in the wafer, is enabled to a logic low level to initialize various internal circuits of the memory device (such as , the value of the latch circuit). After the initialization process is completed, that is, at time "101", the clock enable signal CKE is enabled to a logic high level to start the synchronous operation of the memory device, and based on the command COMMAND and the memory address BA. Various values MRS and MR are set for the value.

In FIG. 1, "CK" represents a clock, "CK#" represents an inverted clock, and "CKE" represents a clock enable signal, which is a signal indicating a period in which the memory device will operate in synchronization with the clock. In addition, "MRS" And "MR#" indicates different set values set in the memory device. The portion marked with a slash indicates the "arbitrary" period. In Figure 1, "tXPR" indicates the reset CLE exit time; "tMRD" indicates the cycle time of the mode register set (MRS) command; "tMOD" indicates the delay time from the MRS command to the non-MRS command; and "tZQinit "Indicates the initial ZQ calibration time. tXPR, tMRD, tMOD, and tZQinit may be parameters defined in the standard memory specification (ie, the Joint Electron Devices Engineering Council (JEDEC) specification).

Since the memory device does not perform any other operations therein during the initialization operation, the operation of the internal circuitry in the memory device may be unstable. That is, when the power supply of the system using the memory device is relatively fast or the power supply voltage is undesirably unstable, the internal circuit of the memory device may be unstable at the time of power-on, which may cause the operation of the memory device to malfunction.

An exemplary embodiment of the present invention is directed to stabilizing the operation of internal circuitry of a memory device in a process of initializing a memory device.

According to an exemplary embodiment of the present invention, a self-renew control circuit for controlling a self-renew operation of a memory device includes: a self-renew control logic block configured to control the memory The device performs the self-renew operation; and an initial renew control block configured to initiate the self renew control logic block during an initialization cycle of the memory device.

In accordance with another exemplary embodiment of the present invention, a method for controlling a self-renew operation of a memory device includes initiating a self-renew in response to a reset signal for an initialization operation of the memory device Fuck And ending the self-renew operation in response to a clock enable signal for one of the memory devices being synchronized.

According to still another exemplary embodiment of the present invention, a memory device includes: a memory cell array including a plurality of memory cells; and a column of circuits configured to control a column operation of the memory cell array; a command decode block configured to generate a self-renew start signal and a self-renew stop signal by decoding a command; an initial renew control block configured to be generated in the memory a self-renewing cycle signal initiated during one of the initialization cycles of the device; and a self-renew control logic block configured to control the column circuit during a start cycle of the self-renew cycle signal and self-starting the self A self-renew operation is performed in one cycle from the moment of the new start signal to the moment when one of the self-renewal signals is started.

Exemplary embodiments of the present invention are described in more detail below with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and the scope of the invention will be fully conveyed to those skilled in the art. Throughout the invention, the same reference numerals refer to the same parts throughout the various figures and embodiments of the invention.

According to an exemplary embodiment of the invention, the memory performs a self-renew operation during an initialization operation of the memory device. Hereinafter, the self-renew operation will be described in detail.

A memory device includes: a capacitor as a unit device for storing data; and an access transistor. Here, the capacitor is called a note Recall the body cell. When the data "1" is stored in the memory cell, a high voltage level is applied to the memory cell. When the data "0" is stored in the memory cell, a low voltage level is applied to the memory cell. Ideally, the capacitor always maintains the charge previously accumulated therein as long as the voltage level of the coupling terminal of the capacitor does not change. However, in practice, the capacitor loses the charge previously stored therein in the form of leakage current over time, and the data stored in the capacitor is not distinguished between the data "1" and "0". Therefore, the processing of sensing the data stored in the memory cell and the processing of storing the data again periodically will be performed to continuously maintain the data. A series of such handlers is referred to as a new operation. The new processing program includes automatic re-operation and self-renew operation. The automatic re-operation is a re-operation that is performed in response to a command applied from the memory controller (the operation of the memory device is performed once for one command). The self-renew operation is a re-execution operation performed by the memory device on itself when the memory controller notifies the memory of the self-renew cycle (the memory device performs an action operation on itself several times in the self-renew mode).

2 is a block diagram illustrating a self-renew control circuit of a memory device in accordance with an exemplary embodiment of the present invention.

Referring to FIG. 2, the self-renew control circuit includes an initial re-control block 210 and a self-renew control logic block 220.

The self-renew control logic block 220 controls the memory device to perform a self-renew operation in the self-renew cycle. The self-renew cycle includes 1) a period from the moment when the self-renew start signal SREF_ENTRY is enabled to the moment when the self-renew termination signal SREF_EXIT is enabled (which is substantially similar to the conventional technique) And 2) enabling the period of the self-renewing periodic signal SELF (which is described as an exemplary embodiment of the invention). Controlling the memory device to perform a self-renew operation means controlling the memory device to perform an action operation by internally changing the column address. Performing the operation by changing the column address means sequentially enabling a plurality of word lines in the memory device and amplifying the data of the memory cells controlled by the enabled word line via the bit line sense amplifier. Since this self-renew operation control of the self-re-control logic block 220 is well known to those skilled in the art, further description thereof is omitted herein.

The initial renew control block 210 controls the self renew control logic block 220 to be enabled during the initialization cycle of the memory device such that the self renew control logic block 220 can control the memory device to safely perform the self renew operation. Here, the initialization period of the memory device may be included in a period from the time when the memory device is powered to the time when the memory starts to synchronize with the clock. Specifically, the initial renew control block 210 enables the self-renew cycle signal SELF from the time when the reset signal RESETB is deactivated during the initialization operation of the memory device to the time when the clock enable signal CKE is enabled, so that the memory device executes the self. New operation.

When self-renewing operations are performed during the initialization operation, the various circuits in the memory device also operate, thereby stabilizing the operation of the circuit and the voltage used by the internal circuitry of the memory device. Therefore, it is possible to prevent the memory device from malfunctioning after the initialization operation.

Here, the reset signal RESETB is a signal for initializing an initial value of an internal circuit (such as a latch circuit) of the memory device, and the clock enable signal CKE represents a period in which the memory device operates in synchronization with the clock.

3 is a block diagram of the initial renew control block 210 shown in FIG.

Referring to FIG. 3, the initial re-control block 210 includes a pulse generating unit 310 and a self-renewing period signal generating unit 320.

The pulse generating unit 310 generates a reset pulse RSTP, and when the reset signal RESETB transitions from the enabled state to the deactivated state, the reset pulse RSTP is enabled. Since the reset signal RESETB is a signal enabled to a logic low level, when the reset signal RESETB transitions from a logic low level to a logic high level, the pulse generation unit 310 enables the reset pulse RSTP to a logic high level.

The self-renew cycle signal generation unit 320 activates/initiates the self-renew cycle signal SELF in response to the enable of the reset pulse RSTP, and deactivates/deactivates the self-renew cycle signal SELF in response to the enable of the clock enable signal CKE.

4 is a block diagram of the pulse generation unit 310 shown in FIG.

Referring to FIG. 4, the pulse generating unit 310 includes an inverted delay line 410 for inverting and delaying the reset signal RESETB, and a reset pulse generating unit 420 for logically combining the inverted delay line 410. The output signal and the reset signal RESETB generate a reset pulse RSTP.

The inverted delay line 410 delays the reset signal RESETB by the delay line 411, and inverts the delayed reset signal by the inverter 412.

The reset pulse generating unit 420 includes a "NAND" gate 421 and an inverter 422. When the output signal of the inverted delay line 410 and the reset signal RESETB are both at the logic high level, the reset pulse generating unit 420 enables the reset pulse RSTP to the logic high level, and outputs the enabled reset pulse. Rush RSTP. In summary, the reset pulse RSTP becomes a pulse signal that is enabled when the reset signal RESETB transitions from a logic low level to a logic high level.

FIG. 5 is a block diagram of the self-renew cycle signal generating unit 320 shown in FIG.

Referring to FIG. 5, the self-renewing period signal generating unit 320 includes a first signal generator 510, a second signal generator 520, and a set-reset (SR) latch 530.

The first signal generator 510 includes an inverter 511 and a "reverse" gate 512. The first signal generator 510 enables the first signal A to a logic low level during a period in which the reset pulse RSTP is enabled to a logic high level and the clock enable signal CKE is deactivated to a logic low level.

The second signal generator 520 includes an inverter 521 and an "NOR" gate 522. When the reset signal RESETB is enabled to a logic low level or the clock enable signal CKE is enabled to a logic high level, the second signal generator 520 enables the second signal B to a logic low level.

When the first signal A is enabled to a logic low level, the SR latch 530 enables the self-renew cycle signal SELF to a logic high level, and when the second signal B is enabled to a logic low level, the SR latch 530 will self The new cycle signal SELF is deactivated to a logic low level.

Figure 6 is a timing diagram illustrating the operation of the circuits shown in Figures 2 through 5.

Referring to Figure 6, the reset signal RESETB of the memory device is enabled to a logic low level and, therefore, the initial value of the internal circuitry of the memory device is set. When the reset signal RESETB enabled to the logic low level is deactivated to the logic high level, the pulse RSTP will be reset in response to the deactivation of the reset signal RESETB. Enable to logic high level. In response to the reset pulse RSTP enabled to logic high level, the self-renew cycle signal SELF is enabled to a logic high level, and when the self-renew cycle signal SELF is enabled, the self-renew operation of the memory device is re-newed by the self. Logic block 220 is executed.

Subsequently, when the clock enable signal CKE is enabled to the logic high level, the self-renew cycle signal SELF is deactivated to a logic low level in response to the enable of the clock enable signal CKE. As a result, the self-renew operation is ended. After the clock enable signal CKE is enabled to the logic high level, the memory device operates in synchronization with the clock, receives the command, and performs an operation corresponding to the command.

7 is a block diagram illustrating a memory device including one of the self-renew control circuits shown in FIG. 2, in accordance with an embodiment of the present invention. The figure shows the structure associated with the operation of the memory device, which includes the operation and the re-operation.

Referring to FIG. 7, the memory device includes a memory cell array 710, a column of circuits 720, a command decode block 730, an initial renew control block 210, and a self-renew control logic block 220. The memory cell array 710 includes a plurality of memory cells, and the column circuit 720 controls the column operations of the memory cell array 710. The command decode block 730 generates a self-renew start signal SREF_ENTRY and a self-renew stop signal SREF_EXIT by the decode command COMMAND. The initial regeneration control block 210 generates a self-renew cycle signal SELF that is enabled during the initialization operation of the memory device. The self-renew control logic block 220 controls the period of the column circuit 720 during the enable period of the self-renew cycle signal SELF and the time from the activation of the self-restart signal SREF_ENTRY to the time when the self-renew termination signal SREF_EXIT is enabled. Perform self-renewing operations.

The command decode block 730 controls the operation of the column circuit 720 by decoding the command COMMAND applied to the memory device via the command buffer 701. When a command to initiate a self-renew operation is applied to the memory device, the command decode block 730 decodes the command and enables the self-renew start signal SREF_ENTRY. When a command for ending the self-renew operation is applied to the memory device, the command decode block 730 decodes the command and enables the self-renew termination signal SREF_EXIT. In addition to this, as is well known, the command decode block 730 decodes different commands (such as read commands, write commands, and action commands) applied to the memory device and controls the internal circuitry of the memory device.

The initial renew control block 210, as described with reference to FIGS. 2 through 6, generates a self-renew cycle signal SELF based on the reset signal RESETB and the clock enable signal CKE applied from the outside of the memory device via the buffers 703 and 704.

The self-renew control logic block 220 controls the column circuit 720 during the period of the self-renew cycle signal SELF enable period and the time from the activation of the self-restart signal SREF_ENTRY to the time when the self-renew termination signal SREF_EXIT is enabled, so as to The new data stored in the memory cell array 710.

Outside the renew cycle, column circuit 720 performs column operations on selected memory cells in the memory cells of memory cell array 710 based on address ADD input via address buffer 702 under control of command decode block 730 ( For example, action operation). In the self-renew cycle, the column circuit 720 is sequentially stored in the memory cell array 710 under the control of the self-re-control logic block 220. data.

In accordance with the teachings of the present invention, a self-renew operation is performed during an initial operational cycle of the memory device. Therefore, various internal circuits of the memory device operate in the initialization period, and as a result, the internal circuit is stable.

While the invention has been described with respect to the specific embodiments of the present invention, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined in the appended claims.

101‧‧‧ moments

210‧‧‧Initial re-control block

220‧‧‧ Self-renew control logic block

310‧‧‧pulse generating unit

320‧‧‧ Self-renew cycle signal generation unit

410‧‧‧Inverted delay line

411‧‧‧delay line

412‧‧‧Inverter

420‧‧‧Reset pulse generation unit

421‧‧‧"Reverse" brake

422‧‧‧Inverter

510‧‧‧First signal generator

511‧‧‧Inverter

512‧‧‧"Reverse" gate

520‧‧‧Second signal generator

521‧‧‧Inverter

522‧‧‧"Anti-or" gate

530‧‧‧Set-Reset (SR) Latch

701‧‧‧Command buffer

702‧‧‧ address buffer

703‧‧‧buffer

704‧‧‧buffer

710‧‧‧ memory cell array

720‧‧‧ column circuit

730‧‧‧Command decoding block

1 is a timing diagram showing an initialization process of a dual data rate 3 (DDR3) synchronous dynamic random access memory (SDRAM) device.

2 is a block diagram illustrating a self-renew control circuit of a memory device in accordance with an exemplary embodiment of the present invention.

3 is a block diagram of the initial renew control block shown in FIG. 2.

4 is a block diagram of the pulse generation unit shown in FIG.

FIG. 5 is a block diagram of the self-renew cycle signal generating unit shown in FIG.

Figure 6 is a timing diagram illustrating the operation of the circuits shown in Figures 2 through 5.

FIG. 7 is a block diagram illustrating a memory device including one of the self-renew control circuits shown in FIG. 2, in accordance with an exemplary embodiment of the present invention.

210‧‧‧Initial re-control block

220‧‧‧ Self-renew control logic block

Claims (14)

A self-renew control circuit for controlling a self-renew operation of a memory device, comprising: a self-renew control logic block configured to control the memory device to perform the self-renew operation; An initial re-control block configured to initiate the self-renew control logic block during an initialization cycle of the memory device. The self-renew control circuit of claim 1, wherein the initial renew control block is configured to initiate the self renew control logic block in response to one of the reset signals being deactivated, and responsive to a clock enable signal One of them starts to undo the startup of the self-re-control logic block. The self-renew control circuit of claim 2, wherein the initial re-control block comprises: a pulse generating unit configured to generate a reset pulse, wherein the reset pulse is initiated when the reset signal is deactivated And a self-renewing cycle signal generating unit configured to activate a self-renewing cycle signal in response to activation of one of the reset pulses, and to initiate activation of the self in response to the activation of the clock enable signal A new periodic signal in which the self-renew control logic block is initiated during one of the cycles of initiating the self-renew cycle signal. The self-renewing control circuit of claim 3, wherein the self-renewing period signal generating unit comprises: a first signal generator configured to activate the reset pulse and Activating a first signal when the clock enable signal is deactivated; and a second signal generator configured to activate a second signal when the reset signal is activated or the clock enable signal is deactivated; and a set-weight A (SR) latch is provided that is configured to initiate the self-renew cycle signal in response to the first signal and to initiate activation of the self-renew cycle signal in response to the second signal. The self-renew control circuit of claim 3, wherein the pulse generating unit comprises: an inverted delay line configured to invert and delay the reset signal to generate an inverted and delayed reset signal; And a reset pulse generating unit configured to generate and output the reset signal by logically combining the inverted and delayed reset signal with the reset signal. The self-renew control circuit of claim 1, wherein the initialization period of the memory device comprises a period from a power supply time of the memory device to a time when the memory device begins to perform a synchronization operation. The self-renew control circuit of claim 1, wherein the self-renew control logic block is configured to control the memory device after supplying a power to the memory device and setting an initial value of the memory device. The self-renew operation is performed before the memory device operates in synchronization with a reference clock. A method for controlling a self-renew operation of a memory device, comprising: responding to a reset signal for an initialization operation of the memory device The number begins with a self-renew operation; and ends the self-renew operation in response to a clock enable signal for one of the memory devices' synchronization operations. The method of claim 8, wherein the reset signal includes a signal that is activated to set an initial value of the memory device and is deactivated for use in the initialization operation, and the clock enable signal includes a supply to the memory device A signal for the synchronization operation. A memory device comprising: a memory cell array comprising a plurality of memory cells; a column of circuits configured to control a column operation of the memory cell array; a command decoding block configured Generating a self-renew start signal and a self-renew stop signal by decoding a command; an initial re-control block configured to generate a start-up in an initialization cycle of the memory device a self-renewing cycle signal; and a self-renew control logic block configured to control the column circuit during a start-up period of the self-renew cycle signal and a time from the initiation of the self-restart signal A self-renew operation is performed in a cycle at which one of the self-renewal signals is initiated. The memory device of claim 10, wherein the initial renew control block is configured to initiate the self renew cycle signal in response to one of the reset signals being deactivated, and in response to activation of one of the clock enable signals Undo the self-renew cycle signal. The memory device of claim 11, wherein the initial re-control block package And a pulse generating unit configured to generate a reset pulse, wherein the reset pulse is activated when the reset signal is deactivated; and a self-renew cycle signal generating unit configured to respond to the One of the reset pulses is activated to activate the self-renew cycle signal and to initiate the self-renew cycle signal in response to the activation of the clock enable signal. The memory device of claim 10, wherein the initialization period of the memory device comprises a period from a time when the memory device is powered to a time when the memory device begins to perform a synchronization operation. The memory device of claim 10, wherein after a power is supplied to the memory device and an initial value of the memory device is set, the self-renew control logic block is configured to respond to the initial regeneration One of the control blocks outputs the self-renew operation prior to synchronization with a reference clock.