TW201318328A - Dual loop control circuit with capacitor multiplier - Google Patents

Abstract

An exemplary embodiment of the present disclosure illustrates a dual loop control circuit with capacitor multiplier. The dual loop control circuit includes a first error amplifying unit, a second error amplifying unit, and a delay unit. The first and the second amplifying units respectively output a first and a second error current respectively to a first capacitor according to an inputted first voltage signal and an inputted second voltage signal. The delay unit is coupled between the first and the second error amplifying units and is used to delay either the first or the second error current for a predetermined duration before flow into the first capacitor. Consequently, the first and the second error amplifying units alternatively outputting error current to charge the first capacitor thereby enlarge the equivalent capacitance of the first capacitor. Further by having the first capacitor constantly charge and discharge shorten the transient response time.

Description

Capacitor multiplication dual-loop control circuit

The present invention relates to a capacitance multiplying circuit, and more particularly to a dual loop control circuit having a capacitance multiplication.

In recent years, portable electronic products such as mobile phones, walkmans, and digital cameras have continued to evolve in light, thin, short, and small sizes to meet the needs of consumers for portability. At the same time, portable electronic products continue to add new features to increase the usability and convenience of portable electronic products, and then become a living device for consumers.

However, the basic power source of portable electronic products comes from reusable rechargeable batteries, and as the function continues to expand, the number of built-in circuits continues to increase, and the required operating time increases and the power consumed. The relative increase, and thus the larger the battery, makes the portable electronic products more cumbersome. Therefore, the miniaturization and operation time of portable electronic products are therefore limited due to the large battery. In order to effectively utilize limited battery functions and reduce the power consumption of portable electronic products to prolong battery operation time, portable electronic products generally use DC/DC converters with rise and fall functions in the circuit architecture.

The DC/DC converter is a conventional technology for switching the operation mode of the portable electronic product, that is, when the load changes, for example, when the portable electronic product is not in operation, it is in a standby state (light load operation) When switching to the operating state (heavy duty operation) due to the use of the operation, the voltage required for the circuit at the time of operation is stably supplied. Generally, the conversion efficiency of the DC/DC converter switching converter can be improved, for example, switching from light load to heavy load or from heavy load to light load, which can extend the operation time of the portable electronic product, thereby prolonging the portability Operating time of electronic products.

However, the DC/DC converter needs to provide a stable voltage to the portable electronic product due to the load change. Therefore, it is often necessary to add a large amount of compensation capacitor and compensation resistor to compensate to suppress the output voltage of the transient DC/DC converter. The amount of change. However, the compensation capacitor cannot be integrated due to its bulky volume and is often connected to the circuit in an external connection mode, thereby increasing the additional manufacturing cost while occupying a large amount of wafer circuit area, which in turn hinders the system-on-chip (SOC). The use and miniaturization trend. Therefore, integrating the circuit architecture in portable electronic products without affecting the operation of portable electronic products has become one of the main research directions in the industry.

In view of this, the embodiment of the present invention provides a dual-loop control circuit with capacitance multiplication that can be used in any circuit architecture that requires a capacitance multiplication technique, and can be integrated with a circuit of the system at the same time, thereby achieving circuit integration. The goal is to comply with the trend of miniaturization of portable electronic products.

Embodiments of the present invention provide a dual loop control circuit with capacitance multiplication, the dual loop control circuit including a first error amplification unit, a second error amplification unit, and a delay unit. The first error amplifying unit receives the first voltage signal and the second voltage signal, and outputs the first error current according to the first and second voltage signal differences. The second error amplifying unit receives the first and second voltage signals, and outputs the second error current according to the first and second voltage signal differences. The delay unit is coupled between the first and second error amplifying units for injecting one of the first error current and the second error current into the first capacitor after a preset delay time. The first capacitor is coupled between the output end of the second error amplifying unit and the ground, and the first error amplifying unit and the second error amplifying unit alternately charge the first capacitor, and the first capacitor is outputted during the discharging period. Voltage. Accordingly, the first capacitor continuously performs charging and discharging operations, thereby amplifying the equivalent capacitance value of the first capacitor and effectively shortening the transient reaction time.

In one embodiment of the present invention, the delay unit is coupled between the first error amplifying unit and the output end of the second error amplifying unit, so that the first error current is injected into the first capacitor after the preset delay time. Even if the second error amplifying unit charges the first capacitor prior to the first error amplifying unit.

In one embodiment of the present invention, the delay unit is coupled between the input terminals of the first error amplifying unit and the second error amplifying unit for inputting the first voltage signal and the second voltage signal at a preset delay time. The second error amplifying unit further causes the second error amplifying unit to delay outputting the second error current to the first capacitor, and even if the first error amplifying unit charges the first capacitor before the second error amplifying unit.

In one embodiment of the present invention, the delay unit may be a capacitive switch array. By switching the on and off switches, the output delay time and the equivalent power group form a low pass filter with the first capacitor.

In one embodiment of the present invention, the capacitive switch array can be operated by an oscillating unit to generate a fixed frequency control switch to produce a fixed delay time and an equivalent resistance value.

In one embodiment of the present invention, the capacitive switch array can adjust the frequency of the control switch operation by adjusting the oscillating unit circuit to generate a variable delay time and an equivalent resistance value.

In summary, the embodiments of the present invention provide a dual-loop control circuit with capacitance multiplication, which can be applied to any circuit architecture that requires capacitance multiplication, such as a linear voltage conversion regulator circuit or DC/DC conversion. And so on. In addition, the dual-loop control circuit can increase the equivalent capacitance value of the compensation capacitor due to the effect of capacitance multiplication, so that it can achieve the same benefit without externally adding a large amount of bulky compensation capacitors, and stabilize the output voltage, thereby saving power and reducing the portable type. The cost of electronic product manufacturing can also effectively shorten the transient response time and improve the voltage regulation efficiency of portable electronic products. In addition, the dual-loop control circuit can further integrate the compensation circuit integrated with the power supply circuit on a single wafer, thereby making the circuit process environment the same, thereby reducing process variability and error. In addition, integrated circuit can also reduce the area occupied by the circuit, which is in line with the trend of miniaturization of portable electronic products.

The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.

[Embodiment of Dual Loop Control Circuit Architecture with Capacitor Multiplication]

Please refer to FIG. 1. FIG. 1 is a schematic diagram of a dual loop control circuit 1 with capacitance multiplication according to an embodiment of the present invention. The dual loop control circuit 1 includes a first error amplifying unit 11, a second error amplifying unit 13, a delay unit 15, and a capacitor C1 (first capacitor). The delay unit 15 is electrically connected between the first error amplifying unit 11 and the output end of the second error amplifying unit 13 (end points T1, T2), and the capacitor C1 is electrically connected to the output end of the second error amplifying unit 13. Between the ground and GND.

The first error amplifying unit 11 and the second error amplifying unit 13 respectively generate a first voltage and a second voltage according to the received feedback signal V_FB (first voltage signal) and the reference signal V_REF (second voltage signal). In addition, the first error amplifying unit 11 and the second error amplifying unit 13 respectively output the first error current Ie1 and the second error current Ie2 according to the received feedback signal V_FB and the reference signal V_REF, and inject the capacitor C1 into the pair. The capacitor C1 is charged, thereby forming a constant voltage Ve at both ends of the capacitor C1 while increasing the equivalent capacitance value of the capacitor C1.

In detail, the feedback signal V_FB is input to the negative input terminal of the first error amplifying unit 11 and the positive input terminal of the second error amplifying unit 13. The reference signal V_REF is input to the positive input terminal of the first error amplifying unit 11 and the negative input terminal of the second error amplifying unit 13. It is generally known in the art that the voltage at the output of the error amplifying unit corresponds to the voltage level difference between the positive input terminal and the negative input terminal. Further, the first voltage and the second voltage are different from the voltage level of the feedback signal V_FB reference signal and V_REF. Accordingly, the first voltage output by the first error amplifying unit 11 and the second error amplifying unit 13 respectively is opposite to the second voltage level.

For example, if the voltage level of the feedback signal V_FB is greater than the reference signal V_REF, the first voltage output by the first error amplifying unit 11 may be a preset low level voltage. In actual implementation, the first voltage may be the voltage of the negative power supply terminal of the first error amplifying unit 11 or zero voltage. The second voltage output by the second error amplifying unit 13 is a preset high level voltage. In actual implementation, the second voltage may be the difference between the feedback signal V_FB and the reference signal V_REF multiplied by the gain parameter of the second error amplifying unit 13 or when the output second voltage is greater than the voltage of the positive power terminal of the second error amplifying unit 13. The voltage of the positive power supply terminal of the second error amplifying unit 13 is set.

Similarly, if the voltage level of the feedback signal V_FB is smaller than the reference signal V_REF, and the voltage difference between the feedback signal V_FB and the reference signal V_REF is smaller than the voltage of the positive power terminal of the first error amplifying unit 11, the first error amplifying unit 11 outputs The first voltage may be a preset high level voltage, and the second voltage output by the second error amplifying unit 13 may be a preset low level voltage. As described above, in actual implementation, the second voltage output by the second error amplifying unit 13 may be the voltage or zero voltage of the negative power terminal of the second error amplifying unit 13. The first voltage outputted by the first error amplifying unit 11 may be the voltage of the positive power terminal of the first error amplifying unit 11 or the gain parameter of the first error amplifying unit 11 by the difference between the feedback signal V_FB and the reference signal V_REF.

Further, when the circuit is running, the voltage level of the feedback signal V_FB is greater than the reference signal V_REF, and the second error amplifying unit 13 outputs the second error current Ie2 to charge the capacitor C1 and form a constant voltage Ve. The first error amplifying unit 11 does not operate because the output is a low level voltage. The capacitor C1 then discharges the stored energy by electrically disconnecting the output of the second error amplifying unit 13 and the capacitor C1, and discharging the formed constant voltage Ve to the back end circuit.

When the voltage level of the feedback signal V_FB is smaller than the reference signal V_REF, the second error amplifying unit 13 does not operate, and the first error amplifying unit 11 outputs the first error current Ie1. At this time, the first error current Ie1 is injected into the capacitor C1 via the delay unit 15 after being separated by a predetermined delay time DELTA_T to charge it and form a constant voltage Ve. In the delay time DELTA_T, the capacitor C1 discharges the second error current Ie2 injected by the previous second error amplifying unit 13 to the back-end circuit while outputting the formed constant voltage Ve to the back-end circuit. Thus, the first error amplifying unit 11 and the second error amplifying unit 13 alternately charge the capacitor C1 during the circuit operation to increase the equivalent capacitance value of the capacitor C1. In other words, the operation modes of the first error amplifying unit 11 and the second error amplifying unit 13 amplify the equivalent capacitance value of the capacitor C1 in the same manner as the capacitance multiplication mode of the current mode in Miller Theorem. At the same time, since the capacitor C1 alternately continues to charge and discharge during the operation of the circuit, the charging and discharging time of the capacitor C1 is shortened, and the transient response time of the circuit is effectively shortened.

Incidentally, the predetermined voltage Ve corresponds to the error currents output by the first error amplifying unit 11 and the second error amplifying unit 13 (ie, the first and second error currents Ie1, Ie2), and thus corresponds to The difference between the feedback signal V_FB and the reference signal V_REF can be used to stabilize the voltage supplied by the system to the load. For example, the constant voltage Ve can be discharged by the capacitor C1 and input to a back-end circuit, such as a comparison unit, to generate a control pulse width modulation (PWM), thereby controlling the DC/DC converter operation. The cycle, in turn, can stably supply the power required by the load when the load changes. It should be noted that the present invention does not limit the use of the first voltage, the second voltage, and the constant voltage Ve output by the first error amplifying unit 11 and the second error amplifying unit 13, and the prior art should have Other uses of the first voltage, the second voltage, and the constant voltage Ve are inferred, and thus are not described herein again.

Please refer to FIG. 2. FIG. 2 is a schematic diagram showing the circuit structure of the delay unit 15 of the dual loop control circuit 1 according to an embodiment of the present invention. The delay unit 15 in this embodiment is a capacitive switch array. The delay unit 15 includes a capacitive switch array 151, an oscillating unit 153, and a reverse unit 155. The capacitive switch array 151 includes switches 1511, 1513, 1515, 1517 and a capacitor Cs1 (second capacitor) and Cs2 (third capacitor).

Briefly, the second end of the switch 1511 (first switch) is electrically connected to the first end of the switch 1513 (second switch) and the second end of the switch 1513 is electrically connected to the first end of the switch 1515 (third switch) . The second end of the switch 1515 is electrically connected to the first end of the switch 1517 (fourth switch), and the second end of the switch 1517 is electrically connected to the first end of the switch 1511.

In addition, one end of the capacitor Cs1 is electrically connected to the contact between the switch 1511 and the switch 1513 and the other end is electrically connected to the ground GND. Similarly, one end of the capacitor Cs2 is electrically connected to the junction between the switch 1515 and the switch 1517 and the other end is electrically connected to the ground GND. Thereby, the switches 1511, 1513, 1515, 1517 and the capacitors Cs1, Cs2 form a capacitive switch array and can generate a delay time by controlling the opening and closing frequencies of the switches 1511, 1513, 1515, 1517. DELTA_T and equivalent resistance value REQ.

As described above, the delay unit 15 is coupled between the output of the first error amplifying unit 11 and the output of the second error amplifying unit 13 and the contact of the capacitor C1. That is, the output of the first error amplifying unit 11 is connected between the second end of the switch 1513 and the first end contact of the switch 1515, that is, the end point T1. The capacitor C1 is connected between the second end of the switch 1517 and the first end contact of the switch 1511, that is, the end point T2.

In addition, the switches 1511, 1515 in the capacitive switch array 151 are electrically connected to the control terminals (eg, the gates of the power transistors). Similarly, the switches 1513, 1517 in the capacitive switch array 151 are electrically connected to the control terminals (eg, the gates of the power transistors).

Further, the oscillating unit 153 is electrically connected to the capacitive switch array 151. The oscillating unit 153 can be used to generate a clock control signal that periodically switches the operation (ie, opening and conducting) of the switches 1511, 1513, 1515, 1517 of the capacitive switch array 151. In other words, the switches 1511, 1515 and the switches 1513, 1517 switch between on and off during a switching cycle. Briefly, when the switches 1511, 1515 are turned on, the switches 1513, 1517 are turned on and when the switches 1513, 1517 are turned on, the switches 1511, 1515 are turned on.

For example, as shown in the circuit design of FIG. 2, when the oscillating unit 153 outputs a clock signal of a high-level amplitude during the first half switching period, 1511 and 1515 are turned on, and the switches 1513 and 1517 are turned on. Similarly, when the oscillating unit 153 outputs a clock signal of a low level amplitude in the second half switching period, the switches 1513, 1517 are turned on, and the switches 1511, 1515 are turned on. That is to say, the switches 1511, 1515 are opposite to the control signals received by the switches 1513, 1517 at the same time, and thus the actions of the two sets of switches are reversed.

In the above, when the first error amplifying unit outputs the first error current Ie1, the first error current Ie1 is injected into the capacitor Cs1 or the capacitor Cs2 according to the on state of the switches 1511, 1513, 1515, and 1517. In detail, if the switches 1511, 1515 are turned on and the switches 1513, 1517 are turned on, the first error current Ie1 is first injected into the capacitor Cs2 to charge the capacitor Cs2. Then, when the switch is switched (ie, the switches 1513 and 1517 are turned on, and the switches 1511 and 1515 are turned on), the switch 1517 is discharged and injected into the capacitor C1 to form a constant voltage Ve across the capacitor C1.

Similarly, if the switches 1513, 1517 are turned on and the switches 1511, 1515 are turned on, the first error current Ie1 is first injected into the capacitor Cs1 to charge the capacitor Cs1. Then, when the switch is switched (ie, the switches 1511 and 1515 are turned on, and the switches 1513 and 1517 are turned on), the switch 1511 is discharged and injected into the capacitor C1, and a constant voltage Ve is formed across the capacitor C1.

In actual implementation, as shown in FIG. 2, a reverse unit 155 may be added between the oscillating unit 151 and one of the switches (ie, the switches 1511, 1515 or the switches 1513, 1517) to switch on the two sets of switches. The switches 1511, 1513, 1515, 1517 can be implemented by a power transistor such as a power MOS field power transistor (Power MOSFET). For example, the oscillating unit 153 can turn on or off the power transistor by controlling the power transistor gate voltage, thereby achieving the same effect as the switch. The oscillating unit 153 can be implemented, for example, by a comparison unit, a capacitive element, a latch, and a reference voltage combining circuit. Briefly, the oscillating unit 153 can generate a desired oscillation frequency by capacitive charging and discharging operations.

It is worth mentioning that the frequency generated by the oscillating unit 153 can be adjusted by the actual circuit design. Therefore, the frequency generated by the oscillating unit 153 can be fixed or frequency-converted, so the frequency generated by the oscillating unit 153 depends on the actual circuit architecture of the oscillating unit 153. It should be noted that the present invention does not limit the actual circuit architecture and/or design of the oscillating unit 153 as long as the required frequency can be generated to control the capacitive switch array. Similarly, the actual circuit architecture of the delay unit 15 is merely an exemplary embodiment, and is not intended to limit the present invention, that is, the actual circuit architecture of the delay unit 15 can be implemented in other manners as long as the delay required for the circuit can be generated. The time DELTA_T and the equivalent resistance value REQ can be. In summary, FIG. 2 is only a schematic diagram of the circuit structure of the capacitor delay unit 15, which is not intended to limit the present invention. Furthermore, the embodiments, connections and/or physical architecture of the switches 1511, 1513, 1515, 1517 and the oscillating unit 153 are not intended to limit the invention.

Referring to FIG. 3, FIG. 3 is an equivalent circuit diagram of the capacitive switch array 151 of the delay unit 15 according to the embodiment of the present invention. As shown in FIG. 3, the capacitive switch array 151 can generate a delay time DELTA_T by switching switches 1511, 1513, 1515, 1517, and can generate an equivalent resistance value REQ as previously described. Therefore, the capacitive switch array 151 can be represented as an equivalent resistor 151' as shown in Fig. 3, which has a resistance value REQ. As shown in FIG. 3, one end of the equivalent resistor 151' (ie, the end point T1) is electrically connected to the output end of the first error amplifying unit 11 and the other end (ie, the end point T2) is electrically connected to one end of the capacitor C1. In other words, the equivalent resistor 151' is connected in series with the capacitor C1 to form a low pass filter (LPF), which can be used to eliminate the first voltage and the second voltage output by the first and second error amplifying units 11, 13. The chopping voltage (ripple) stabilizes the voltage level of the constant voltage Ve formed by the capacitor C1 to facilitate the operation of the back-end circuit.

Further, the resistance value REQ of the equivalent resistor 151' can be expressed as REQ = ( f _REF * C _s ) ^-1 , where f _REF is the clock control of the control switches of the switches 1511, 1515 and the switches 1513, 1517 The frequency of the signal. In this embodiment, the capacitors Cs1, Cs2 have the same capacitance value C _s . In other words, the resistance value REQ of the required equivalent resistance 151' can be achieved by adjusting at least one of the frequency of the clock control signal and the capacitance of the capacitances Cs1, Cs2. In view of the above, those skilled in the art should be able to infer the adjustment and design of the equivalent resistance 151' and the delay time DELTA_T, and therefore will not be described herein.

It is worth mentioning that the transfer function of this dual-loop circuit 1 architecture can be expressed as

Alternatively, I _{e 1} = -α I _{e 2} , then the transfer function can be seen that the equivalent capacitance of the capacitor C1 is amplified (1-α) ^{- 1} times. In addition, by calculating the transfer function, you can get a zero point as follows.

It will be appreciated by those of ordinary skill in the art that this feedback system can be stabilized by adjusting ω( z ). When the set parameter a is closer to 1, the closer ω( z ) will be to zero, the more the capacitance C1 is multiplied. Therefore, the capacitor C1 can be amplified (1-α) ^-1 times using this double loop circuit 1. At the same time, the closer the ω( z ) is to the zero point, the more stable the double loop circuit 1 is. The other zero point has nothing to do with the process and temperature, so the dual loop circuit 1 architecture can reduce the error and variability of the overall control circuit. It should be noted that those skilled in the art should be able to deduce that the above-mentioned transfer function and the derivation of the zero point should be inferred, and therefore will not be described herein.

[Another embodiment of a dual loop control circuit architecture with capacitance multiplication]

Next, please refer to FIG. 4. FIG. 4 illustrates another embodiment of the present invention to provide a dual loop control circuit 2 architecture with capacitance multiplication. The architecture of the dual loop control circuit 2 similar to the dual loop control circuit 1 (FIG. 1) includes a first error amplifying unit 11, a second error amplifying unit 13, and a delay unit 21. The feedback signal V_FB and the reference signal V_REF are input to the first error amplifying unit 11 and the second error amplifying unit 13, respectively. The first error amplifying unit 11 and the second error amplifying unit 13 respectively output the first voltage and the second voltage according to the feedback signal V_FB and the reference signal V_REF. In addition, the first error amplifying unit 11 and the second error amplifying unit 13 respectively output the first and second error currents Ie1 and Ie2 according to the feedback signal V_FB and the reference signal V_REF to the capacitor C1 to alternately charge the capacitor C1. The constant voltage Ve is formed, and the equivalent capacitance value of the capacitor C1 is amplified, and the capacitor C1 effectively shortens the transient reaction time by continuously performing the charging and discharging operations.

However, the difference between the dual loop control circuit 2 and the dual loop control circuit 1 is that the delay unit 21 of the dual loop control circuit 2 is electrically connected between the input terminals of the first error amplifying unit 11 and the second error amplifying unit 13. Briefly, the delay unit 21 of the dual loop control circuit 2 is electrically connected between the feedback signal V_FB and the reference signal V_REF (end points A1, A2) and the input end of the second error amplifying unit 13 (end points B1, B2). . In other words, the feedback signal V_FB and the reference signal V_REF are delayed by the delay unit 21 and input to the second error amplifying unit 13. In detail, the first error amplifying unit 11 receives the feedback signal V_FB and the reference signal V_REF before the second error amplifying unit 13 and outputs the first error current Ie1 to the capacitor C1 to form a constant voltage Ve. Then, the second error amplifying unit 13 receives the feedback signal V_FB and the reference signal V_REF after the interval one delay time DELTA_T, and outputs the second error current Ie2 to the capacitor C1 to form a constant voltage Ve.

It is to be noted that the specific operation mode of the dual-loop control circuit 2 can be as described in the above embodiments. Therefore, those skilled in the art should be able to infer the operation mode of the circuit and the capacitance multiplication mode, and therefore will not be described herein. . FIG. 4 is only a schematic diagram of a dual loop circuit architecture, and is not intended to limit the present invention.

In addition, the transfer function of the dual loop control circuit 2 of FIG. 4 can be expressed as follows.

Also assume that I _{e 2} =-α I _{e 1} , through the calculation of this transfer function, you can get a zero point as follows

It is known to those skilled in the art that this feedback system can be stabilized by adjusting ω( z ). When the set parameter α is closer to 1, the closer ω( z ) will be to zero, and the more the capacitance C1 is multiplied. It should be noted that those skilled in the art should be able to infer the above-mentioned transfer function and the derivation of the zero point, and therefore will not be described herein.

In addition, if the delay unit 21 uses the circuit architecture of the delay unit 15, it needs to be composed of two delay units 15 to delay the input of the feedback signal V_FB signal and the reference signal V_REF, respectively. However, the delay unit 21 can also be implemented by other circuit designs, such as RC delay circuits.

It should be noted that the dual loop control circuit 1 of FIG. 1 is a better embodiment than the dual loop control circuit 2 of FIG. As shown in FIG. 4, the dual-loop control circuit 2 needs to delay the input feedback signal V_FB and the reference signal V_REF to the second error amplifying unit 13 at the same time. The dual-loop control circuit 1 of FIG. 1 and the delay unit 15 only The first error current Ie1 outputted by the first error amplifying unit 11 is required to be injected into the capacitor C1. Therefore, the variability and error of the dual loop control circuit 1 of FIG. 1 are relatively small. Further, the delay time DELTA_T required by the dual loop control circuit 2 of FIG. 4 is technically great, and the delay time DELTA_T and the bandwidth are mutually exchanged, and the delay time DELTA_T of the dual loop control circuit 2 of FIG. Compared with the dual loop control circuit 1 of FIG. 1, it is also possible to consider the variability of the process, ambient temperature and the like.

[Application example of a dual loop control circuit architecture with capacitance multiplication]

Please refer to FIG. 5. FIG. 5 is a circuit diagram of a step-down DC/DC converter 3 having a dual loop control mechanism and a conventional feedback control circuit. The DC/DC converter 3 includes an input voltage V _in , an output voltage V _out , a P-MOS power transistor Q1, an N-MOS power transistor Q2, a dual loop control circuit 1, a third error amplifying unit 31, and a buffer 37. Pulse wave modulation signal generating unit 35, multiplexer 33a, 33b, inductor L, voltage dividing resistors R1, R2, R3, R4, capacitor C, output capacitor CL, equivalent parasitic resistance RESR of output capacitor CL, and load 39 . The pulse wave modulation signal generating unit 35 includes a ramp generator 351 and a comparator 353.

The dual loop control mechanism and the conventional feedback control circuit can adjust the duty cycle of the reference voltage V_REF and the feedback voltages V_FB1, V_FB2 by adjusting the duty cycle of the P-MOS power transistor Q1 and the N-MOS power transistor Q2. voltage to the input voltage V _out V _out 39 which has one or any load change, the output voltage V _out can be pulled back to a certain voltage level in a short time.

The input voltage V _{in is} connected to the source of the P-MOS power transistor Q1, and the drain of the P-MOS power transistor Q1 is electrically connected to one end of the inductor L, and the other end of the inductor L is electrically connected to the voltage dividing resistor. R1, R3, output capacitor CL and one end of load 39. The voltage dividing resistor R2 is electrically connected between the voltage dividing resistor R1 and the ground GND. The voltage dividing resistor R4 is electrically connected between the voltage dividing resistor R3 and the ground GND. The equivalent parasitic resistance RESR is connected in series between the output capacitor CL and the ground GND. The other end of the load 39 is connected between the ground terminal GND, and the output voltage V _out of the voltage across the load 39 at both ends. In other words, the series-divided voltage dividing resistors R1, R2, the series-connected voltage dividing resistors R3, R4, the series-connected output capacitor CL, and the output capacitor CL are connected in parallel with the load 39.

The first feedback line is electrically connected to the junction of the voltage dividing resistors R1 and R2 and the input end of the multiplexer 33a. The second feedback line is electrically connected to the junction of the voltage dividing resistors R3 and R4 and to the input end of the multiplexer 33a. The output of the multiplexer 33a is electrically connected to the dual loop control circuit 1. At the same time, the output end of the multiplexer 33a is electrically connected to the negative input terminal of the third error amplifying unit 31. Therefore, the reference voltage V_REF is simultaneously input to the positive input terminals of the dual loop control circuit 1 and the third error amplifying unit 31. In addition, the capacitor C is electrically connected between the output end of the third error amplifying unit 31 and the ground GND. The outputs of the dual loop control circuit 1 and the third error amplifying unit 31 are electrically connected to the multiplexer 33b. The output of the multiplexer 33b is electrically coupled to the negative input of the comparator 353. The output of the ramp generator 351 is electrically coupled to the positive input of the comparator 353.

Furthermore, the output of the comparator 353 is electrically connected to the negative input of the buffer 37, and the positive input of the buffer 37 is electrically connected to the output. The output of the buffer 37 is electrically connected to the gates of the P-MOS power transistor Q1 and the N-MOS power transistor Q2. The drain of the N-MOS power transistor Q2 is electrically connected to the drain of the P-MOS power transistor Q1 and the inductor L junction. The source of the N-MOS power transistor Q2 is electrically connected to the ground GND.

The basic operation of the step-down DC/DC converter 3 is the same as that of the conventional typical step-down DC/DC converter. Therefore, those skilled in the art should be able to infer the basic operation mode of the step-down DC/DC converter 3, This is not mentioned here. However, the difference is that the step-down DC/DC converter 3 is provided with a dual loop control circuit 1 in addition to the conventional feedback circuit (i.e., the third error amplifying unit 31 and the capacitor C).

In detail, the output voltage V _out is divided by the voltage dividing resistors R1 and R2 to generate the first feedback voltage V_FB1 and the voltage dividing resistors R3 and R4 are divided to generate the second feedback voltage V_FB2, and then fed back to the multiplexer 33a. That is, the output voltage V _out can be expressed as .

The multiplexer 33a can be used to selectively input the first feedback voltage V_FB1 or the second feedback voltage V_FB2 to be compared with the reference voltage V_REF. The first feedback voltage V_FB1 corresponds to a voltage across the voltage dividing resistor R2. Similarly, the second feedback voltage V_FB2 corresponds to a voltage across the voltage dividing resistor R4. The first feedback voltage V_FB1 or the second feedback voltage V_FB2 is subjected to a conventional feedback circuit or a dual loop control circuit 1 mechanism to obtain a constant voltage Ve. The multiplexer 33b can be used to select a predetermined voltage Ve detected by the mechanism of the conventional feedback circuit or the dual loop control circuit 1 to be compared with the ramp generator 351 to obtain a switching period of the power transistors Q1 and Q2 (ie, a pulse wave). The duty cycle of the width modulation signal). Then, the operation mode of the P-MOS power transistor Q1 and the N-MOS power transistor Q2 is controlled via the buffer unit 37 until the output voltage V _{out is} equal to the desired value (ie, the reference voltage V_REF).

For example, if the output voltage V _{out is} too small (for example, the first feedback voltage V_FB1 or the second feedback voltage V_FB2 is smaller than the reference voltage V_REF), the output constant voltage Ve may be too large, and the pulse width modulation obtained may be obtained. The duty cycle of the signal will increase to increase the on-time of the P-MOS power transistor Q1 and the off-time of the N-MOS power transistor Q2 to increase the output voltage V _out . On the other hand, if the output constant voltage Ve is too small (for example, the first feedback voltage V_FB1 or the second feedback voltage V_FB2 is greater than the reference voltage V_REF), the constant voltage Ve becomes smaller, and the duty cycle of the pulse width modulation signal obtained is subsequently obtained. The ON time of the P-MOS power transistor Q1 and the off time of the N-MOS power transistor Q2 are reduced, and the output voltage V _{out is} lowered.

Accordingly, the output voltage V _out can be controlled to a desired voltage level, and when there is any change in the input voltage Vin or the load 39, the output voltage V _out can be pulled back to the desired voltage level in a short time. . As described in the previous embodiment, the dual loop control circuit 1 provided by the embodiment of the present invention can shorten the transient response time of the circuit and increase the output voltage by increasing the equivalent capacitance value of the compensation capacitor (ie, the capacitor C1 of FIG. 1). V _{out is} pulled back to the desired voltage level.

Incidentally, the third error amplifying unit 31 may be implemented by an operational transconductance amplifier in this embodiment. The buffer 37 and the comparator 353 can be implemented by an operational amplifier and other electronic components (eg, resistors, capacitors, etc.) in this embodiment. It should be noted that the present invention does not limit the third error amplifying unit 31, the buffer 37, the pulse wave modulation signal generating unit 35, the multiplexers 33a and 33b, the types of the power transistors Q1 and Q2, the physical architecture, and / or implementation. FIG. 5 is only a schematic diagram of an application circuit of the dual loop control circuit 1 provided by the embodiment of the present invention, and is not intended to limit the present invention. Those skilled in the art should be able to infer the application of other dual-loop control circuits, and therefore will not be described herein.

It should be noted that the coupling relationship between the components in the above embodiments includes direct or indirect electrical connection, as long as the required electrical signal transmission function can be achieved, and the present invention is not limited. The technical means in the above embodiments may be combined or used alone, and the components may be added, removed, adjusted or replaced according to their functions and design requirements, and the invention is not limited. After the description of the above embodiments, those skilled in the art should be able to deduce the embodiments thereof, and no further details are provided herein.

[Possible efficacy of the embodiment]

Please refer to FIG. 6. FIG. 6 is a schematic diagram showing the comparison of the output voltage waveforms of the boost DC/DC voltage regulator circuit with the dual loop control mechanism provided by the embodiment of the present invention. As shown in FIG. 6, curve 41 is the output current value when the boost DC/DC voltage regulator switches the load. Curve 43 is a transient waveform diagram of the output voltage of the conventional boost DC/DC voltage regulator when the load current changes. Curve 45 is a transient waveform diagram of the output voltage when the load current is changed by the boost DC/DC voltage regulator with dual-loop control mechanism provided by the present invention.

As shown in FIG. 6, when the load current (curve 41) changes (eg, instantaneously increases), it is known to those skilled in the art that the load will draw a large amount of current from a DC/DC voltage regulator (not shown). When the step-up DC/DC voltage regulator is too late to respond, it is unable to supply sufficient current in time, so the output voltage will be as shown in Figure 6, and the curves 47 and 45 in the object 47 will produce a small step-down. The boost DC/DC voltage regulator adjusts the switching voltage for a short period of time by adjusting the switching period, such as increasing the power transistor (not shown) duty cycle. During this time, the output capacitor CL temporarily provides a large amount of current required for the load.

It should be noted that, as can be seen from FIG. 6, the transient response time of the output voltage of the boost DC/DC voltage regulator with the dual loop control mechanism (curve 45) is only 8.1 μs, while the conventional The required transient state response time for the output voltage of the step-up DC/DC voltage regulator (curve 43) is 152 μs.

Next, please refer to FIG. 7. FIG. 7 is a schematic diagram showing a voltage waveform of a buck DC/DC voltage regulator circuit having a dual loop control mechanism according to an embodiment of the present invention. As shown in FIG. 7, curve 51 is the output current value when the buck DC/DC voltage regulator switches the load variation. Curve 53 is a transient waveform diagram of the output voltage of the conventional buck DC/DC voltage regulator when the load current changes. Curve 55 is a transient waveform diagram of the output voltage when the load current is changed by the buck DC/DC voltage regulator with dual-loop control mechanism provided by the present invention.

As shown in FIG. 7, when the load current (curve 51) changes (for example, instantaneously decrements), it is known to those skilled in the art that the buck DC/DC voltage regulator (not shown) reacts at this time. As a result, the output voltage will produce a small boost as shown by curves 53 and 55 in Figure 57, and the buck DC/DC voltage regulator will adjust the switching period for a short period of time, for example Shorten the duty cycle of the power transistor (not shown) and adjust the output voltage.

It should be noted that, as can be seen from FIG. 7, the transient response time of the output voltage of the buck DC/DC voltage regulator with the dual loop control mechanism (curve 55) is only 8.2 μs, while the conventional The required transient state response time for the output voltage of the buck DC/DC voltage regulator (curve 53) is 160 μs.

Accordingly, it can be seen that the transient state response time of the DC/DC voltage regulator with dual-loop control mechanism provided by the present invention is higher than that of the conventional DC/, regardless of whether the load current is transferred from heavy load to light load or from light load to heavy load. The transient state reaction time of the DC voltage regulator, that is, the dual loop control mechanism provided by the invention can effectively shorten the transient reaction time of the DC/DC voltage regulator, improve the switching efficiency, and stably provide the output voltage to the load. It should be noted that FIG. 6 and FIG. 7 are only schematic diagrams of the voltage waveforms of the DC/DC voltage regulator circuit, and are not intended to limit the present invention.

In summary, the dual-loop control circuit with capacitance increase provided by the embodiment of the present invention, the dual-loop control circuit alternately outputs error currents by two error amplifying units to charge a compensation capacitor, using Miller's theorem The medium current mode increases the equivalent capacitance of this compensation capacitor. The dual-loop control circuit with capacitance increase provided by the embodiment of the invention can shorten the transient reaction time when the voltage device is switched in the power supply circuit, and improve the voltage regulation efficiency.

In addition, the dual loop control circuit with capacitance increase provided by the embodiments of the present invention can be applied to any circuit that requires capacitance multiplication, such as a DC/DC converter. As described in the above embodiments, the dual-loop control circuit with capacitance increase provided by the embodiment of the present invention can make the circuit of the application not need to be connected with a bulky compensation capacitor due to the characteristics of its own capacitance multiplication, and thus can be integrated on a single chip. In turn, the effect of circuit integration is achieved.

The above description is only an embodiment of the present invention, and is not intended to limit the scope of the invention.

1, 2. . . Capacitor multiplication dual-loop control circuit

11. . . First error amplifying unit

13. . . Second error amplifying unit

15, 21. . . Delay unit

151. . . Capacitive switch array

151’. . . Equivalent resistance of capacitive switch array

1511, 1513, 1515, 1517. . . switch

153. . . Oscillation unit

155. . . Reverse unit

3. . . DC/DC voltage regulator circuit

31. . . Third error amplifying unit

33a, 33b. . . Multiplex unit

35. . . Pulse wave modulation signal generating unit

351. . . Slope generator

353. . . Comparators

37. . . buffer

39. . . load

41, 43, 45, 51, 53, 55. . . curve

47, 57. . . object

V _in . . . Input voltage

V _out . . . The output voltage

Ve. . . Constant voltage

V_FB, V_FB1, V_FB2. . . Feedback signal

V_REF. . . Reference signal

Ie1. . . First error current

Ie2. . . Second error current

L. . . inductance

Q1. . . PMOS power transistor

Q2. . . NMOS power transistor

CL. . . Output capacitor

C, C1, Cs1, Cs2. . . capacitance

R1~R4, RESR. . . resistance

T1, T2, A1, A2, B1, B2. . . Electrical endpoint

FIG. 1 is a circuit diagram of a dual loop with capacitance multiplication according to an embodiment of the present invention.

2 is a circuit diagram of a delay unit according to an embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram of a capacitive switch according to an embodiment of the present invention.

4 is a circuit diagram of a dual loop with capacitance multiplication according to another embodiment of the present invention.

FIG. 5 is a schematic diagram of a DC/DC voltage regulator circuit with a conventional feedback control circuit of a dual loop control mechanism according to an embodiment of the present invention.

6 is a schematic diagram showing a comparison of output voltage waveforms of a boosted DC/DC voltage regulator circuit having a dual loop control mechanism according to an embodiment of the present invention.

7 is a schematic diagram showing a comparison of output voltage waveforms of a buck DC/DC voltage regulator circuit having a dual loop control mechanism according to an embodiment of the present invention.

1. . . Double loop circuit

11. . . First error amplifying unit

13. . . Second error amplifying unit

15. . . Delay unit

C1. . . capacitance

Ie1. . . First error current

Ie2. . . Second error current

Ve. . . Constant voltage

V_FB. . . Feedback signal

V_REF. . . Reference signal

T1, T2. . . Electrical endpoint

Claims (10)

A double-loop control circuit for capacitor multiplication includes: a first capacitor; a first error amplifying unit having a positive input receiving a first voltage signal and a negative input receiving a second voltage signal, and The first error amplifying unit is configured to compare a voltage level difference between the first voltage signal and the second voltage signal, and output a first error current according to the comparison result and inject the first capacitor to the first capacitor Charging; a second error amplifying unit having a positive input terminal for receiving the second voltage signal, and a negative input terminal for receiving the first voltage signal, and the second error amplifying unit is configured to compare the first voltage And a voltage difference between the signal and the second voltage signal, and outputting a second error current according to the comparison result and injecting the first capacitor to charge the first capacitor; and a delay unit coupled to the first An error amplifying unit and the second error amplifying unit are configured to inject one of the first error current and the second error current after the predetermined delay time A capacitor; wherein the capacitance value of the first error amplifying unit amplifies the second error unit through the first capacitor is alternately charged to the first capacitor increases. The dual-loop control circuit of claim 1, wherein the delay unit is coupled between the output end of the first error amplifying unit and the output end of the second error amplifying unit to enable the first error current The first capacitor is injected after the preset delay time. The dual-loop control circuit of claim 1, wherein the delay unit is coupled between the input end of the first error amplifying unit and the input end of the second error amplifying unit to enable the first voltage signal And inputting the second voltage signal to the second error amplifying unit at the preset delay time, so that the second error amplifying unit delays outputting the second error current to the first capacitor. The dual-loop control circuit of claim 1, wherein if the current ratio of the first error current to the second error current is 1:-α, and the capacitance of the first capacitor is C, the first The equivalent capacitance of the capacitor is (1-α) ^-1 ‧C. The dual-loop control circuit of claim 1, wherein the first error amplifying unit and the second error amplifying unit respectively comprise an operational amplifier and a plurality of resistors and capacitors. The dual loop control circuit of claim 1, wherein the delay unit comprises a capacitive equivalent switch circuit for generating the preset delay time and an equivalent resistance value, the capacitive equivalent switch circuit is Controlling a clock control signal outputted by an oscillating unit, the capacitive equivalent switching circuit includes: a first switch having a first end and a second end; and a second switch having a first end coupled The second end of the first switch and the second end; a third switch having a first end coupled to the second end and the second end of the second switch; a fourth switch having a second end is coupled to the second end of the third switch, and a first end of the fourth switch is coupled to the first end of the first switch; a second capacitor is coupled to the first end a switch between the switch and the ground of the second switch; and a third capacitor coupled between the contact of the third switch and the fourth switch and the ground; wherein the first switch Synchronizing with the third switch is controlled by the clock control signal, and the second switch and the fourth switch The off synchronization is controlled by the reverse signal of the clock control signal, and when the second capacitor is charged, the third capacitor is discharged, and when the third capacitor is charged, the second capacitor is discharged. The dual loop control circuit of claim 6, wherein the first switch, the second switch, the third switch, and the fourth switch are respectively implemented by a power transistor. The dual loop control circuit of claim 6, wherein the frequency of the clock control signal output by the oscillating unit is a fixed frequency. The dual loop control circuit of claim 6 wherein the frequency of the clock control signal output by the oscillating unit is a variable frequency. For example, in the dual-loop control circuit of claim 1, wherein the dual-loop control circuit is built in a power integrated circuit.