TW201316698A - A dual mode sigma delta analog to digital converter and circuit using the same - Google Patents

Abstract

The present invention provides a dual mode sigma delta analog to digital converter (ADC), which only in one hardware implementation, used for low IF and near zero IF receiver. The dual mode sigma delta ADC comprises a first switched-capacitor integrator, for integrating a sum of an input signal and a first feedback signal; a second switched-capacitor integrator, for integrating a sum of an output of the first switched-capacitor integrator and a second feedback signal; a quantizer, for providing an output signal of the ADC in at least first and second logic state in response to an output of the second switched-capacitor integrator; a feedback circuit, for providing the first feedback signal to the first switched-capacitor integrator and the second feedback signal to the second switched-capacitor integrator and an operation of the second switched-capacitor integrator. By switching the mode device on or off, one could easily change the configuration of the disclosed ADC to decide the receiving signal falling in low-IF or near zero IF.

Description

Bimodal δ-Δ analog to digital converter and its circuit

The present invention relates to a bimodal delta-delta analog to digital converter (ADC), and more particularly to a dual mode for operating at a low intermediate frequency and/or near zero intermediate frequency near zero intermediate frequency. State δ-Δ analog to digital converter.

Since 1960, δ-Δ analog to digital converters have been widely used in the electronics industry. This delta-delta technique is attractive because it achieves high resolution by precise time control without the need to precisely match the components on the wafer. Therefore, the delta-delta technique is one of the choices of many integrated circuit applications.

A basic delta-delta analog to digital converter receives an analog input signal and subtracts a feedback signal to provide an error signal. The error signal is processed through a low pass filter and then quantized to form a digital output signal. The digital output signal is fed back to the digital to analog converter (DAC) to convert the feedback digital signal output to the analog signal, and is subtracted from the front end receiving analog signal. In addition to the feedback digital to analog converter, the basic delta-delta analog to digital converter can be implemented with conventional analog components such as operational amplifiers, comparators, and switched capacitor filters. Since the integrated circuit clock speed allows for a higher sampling rate, a typical delta-delta analog to digital converter typically provides high resolution. The basic δ-Δ analog-to-digital converter shifts the quantized noise to the high frequency band by feedback technology, so it can have a very high signal-to-noise ratio (SNR), and the extra-band quantization noise can also be traditional. The filtering technique is fully eliminated.

U.S. Patent No. 5,461,381, issued to Seaberg, entitled "with feedback compensation δ-Δ analog to digital converter (ADC) and method of making the same." It is disclosed that a delta-delta analog to digital converter includes a first and second integrator, a quantizer coupled to one of the outputs of the second integrator, and a feedback circuit coupled to the output of the quantizer. In order to avoid the effects of delay through the actual circuit components, the feedback circuit maintains the feedback signal to the first integrator in a high impedance state until the quantizer resolves the output of the second integrator. Therefore, the first integrator avoids temporarily summing up a possibly incorrect feedback signal. In addition, the feedback circuit also prevents the first integrator from integrating an input signal and the feedback signal until the feedback signal is driven to correct to the correct state to return to the output of the quantizer. In order to accomplish these results, the feedback circuit includes a compensation circuit for continuously determining when the quantizer has a solution.

Referring to U.S. Patent No. 6,225,928, to Green, entitled "Multiple Bandpass Modulators and Methods for Delta-Delta Analog to Digital Converters (ADC)". It discloses a discrete-time cross-coupling to complex bypass by providing a cross-coupled discrete-time complex loop filtering structure that is insensitive to component matching and by providing a simple architecture to correct the effects of modulator mismatch The transformer is implemented to achieve bandpass delta-delta conversion. The plurality of band pass modulators includes a plurality of nonlinear resonators coupled together and acting as a linear complex operator. Each resonator will act as a linear complex operator, with an imaginary input signal being delayed in half the sample interval and an imaginary output signal being enhanced in half the sample interval. In addition, the effect of the reduction of the adapter mismatch is eliminated by digitally adjusting the correlation gain of the real and imaginary paths and adjusting the correlation gain of the real and imaginary input signals, and the real and imaginary paths are coupled to the analog to digital conversion. After the output of the device.

Referring to U.S. Patent No. 6,954,628, to Minnis et al., entitled "Radio Receiver". It reveals that a radio receiver architecture operates in a low-IF and near zero IF mode with maximum reusability of analog-to-analog and digital loops. The receiver includes a quadrature downconverter for generating phase (I) and quadrature (Q) signals and a complex filter at an intermediate frequency to cancel the image frequency. In the low intermediate frequency mode, one end of the output (Q) of the filter is unused, while the other (I) is digitized by a non-complex analog to digital converter, and then the digital signal passes through Digital filter processing, thus generating orthogonal IF signals. In the near zero intermediate frequency mode, the digitization is performed in parallel using two non-complex digital to analog converters. By performing channel filtering and non-complex analog to digital conversion, it is possible to avoid repeated loops and provide significant energy savings.

Referring to U.S. Patent No. 7,176,817, issued to Jensen, entitled "Continuous Time Delta-Delta Analog to Digital Converter with Jitter". It discloses a hybrid application of digital signal processing and analog loops to reduce residual noise in a continuous time delta-delta analog to digital converter. By adding a small amount of random noise, the quantization noise associated with the input signal is removed without significantly reducing the signal-to-noise ratio (SNR) characteristics. In each of the embodiments, the digital loop is utilized to generate the desired randomness, de-correlation and jitter specific spectrum and simple analog loop blocks for modest planning and interpolation of the jitter signal to continuous time δ- Delta analog to digital converter loop. In an embodiment of the invention, random noise is added to the quantizer input. In another embodiment of the invention, a small amount of current is randomly added to remove the quantized noise from the input signal. The original signal noise ratio.

Today, the Bluetooth standard expands applications from high speed to low power consumption. At the same time, different RF receiver architectures have been developed to meet the RF link requirements. However, design engineers should provide different designs to meet the diversity of design specifications, which can be time consuming and lose the point in time to win market opportunities. For example, a design engineer should design two different analog-to-digital converter hardware to individually support low-IF and near-zero IF receivers.

Therefore, it is necessary to provide a bimodal delta-delta analog to digital converter that can implement low intermediate frequency and near zero intermediate frequency receivers as long as one hardware is implemented.

The main object of the present invention is to provide a bimodal delta-delta analog to digital converter (ADC) that can be implemented in low intermediate frequency and near zero intermediate frequency receivers as long as one hardware is implemented. By switching the "modal" component on or off, the operator can easily change the state of the analog to digital converter disclosed in the present invention; it can be decided to receive low intermediate frequency (Low-IF) or near zero intermediate frequency (near). Zero IF) signal.

To achieve the above objective, the present invention provides a bimodal delta-delta analog to digital converter comprising a first switched capacitor integrator for integrating an input signal and a first feedback signal; a second switched capacitive integrator coupled to the first switched volume divider for integrating the output signal of the first switched capacitive integrator with a second feedback signal; a quantizer having a The input end is coupled to the second switched capacitor integrator and an output terminal for providing an output signal of the digital converter, at least the first and second logic states, corresponding to the second switched capacitor integral One of the outputs, a feedback circuit coupled to the first switched capacitive integrator and the second switched capacitive integrator for providing the first feedback signal to the first switched capacitive integrator and the a second feedback signal to the second switched capacitor integrator; and a modal element coupled to one of the input of the first switched capacitive integrator and one of the output of the second switched capacitive integrator , A system for providing a signal to the control mode of the first switched capacitor integrator operation and one of the second switched capacitor integrator one operation. According to the above invention, the modal element includes a first switching element having a first end coupled to the input of the first switched capacitive integrator and a second end coupled to the second switched capacitive integrator An input end; a second switching element having a first end coupled to the input end of the first switched capacitive integrator and a second end; and a third switching element having a first end coupled to the modal The second end and the second end of the second switching element of the component are coupled to the output of the second switched capacitive integrator; wherein the modal element controls the first switching component, the second switching The element and the third switching element are in a state of being on or off.

Furthermore, the present invention further proposes a receiver circuit using the disclosed bimodal delta-delta analog to digital converter.

The above and other objects, features, and advantages of the present invention will become more apparent and understood.

While the invention may be embodied in various forms, the embodiments illustrated in the drawings It is not intended to limit the invention to the particular embodiments illustrated and/or described.

In order to understand the spirit of the present invention, please refer to FIG. 1, which shows a delta-delta analog to digital converter (ADC) according to the prior art, which includes a first switched capacitor integral. The device 50 is configured to perform an integral operation on an input signal and a first feedback signal. A second switched capacitive integrator 60 is coupled to the first switched capacitive integrator 50 for the first switching. The output signal of the capacitive integrator is integrated with a second feedback signal; a quantizer 70 having an input coupled to the second switched capacitive integrator 60 and an output for providing the digital conversion The output signal (DOUT) of the device has at least first and second logic states corresponding to one of the outputs of the second switched capacitor integrator 60; a feedback circuit 170, 180 coupled to the first switched capacitor integrator and the a second switched capacitor integrator for providing the first feedback signal to the first switched capacitor integrator 50 and the second feedback signal to the second switched capacitor integrator 60; the integrators 50, 60 and the back 170, 180 form a circuit to filter out noise transfer function within its band quantized from the quantizer 70 of the noise. By means of a general switched capacitor operation loop method, the switched element exhibits a non-overlapping clock control switch together with a capacitor to form an integrator, the delta-delta analog to digital converter signal transfer function being a low pass type and a noise transfer function It is a high-pass type. This type of analog to digital converter has the advantages of oversampling rate and high-pass noise shape function, which can achieve extremely high signal-to-noise ratio for general communication applications. However, design engineers should require two different analog-to-digital converter hardware to individually support low-IF (low IF) and near-zero intermediate frequency (NZIF) receivers. This is a time-consuming and easy opportunity to lose the market.

Referring now to FIG. 2, a dual mode delta-delta analog to digital converter is disclosed in accordance with the present invention. The bimodal delta-delta analog to digital converter 100 includes a first switched capacitor integrator 50; A second switched capacitive integrator 60; a quantizer 70; a feedback circuit 170; a modal element 190.

The first switched capacitive integrator 50 is configured to integrate an input signal and a first feedback signal; the second switched capacitive integrator 60 is coupled to the first switched capacitive integrator 50. For integrating the output signal of the first switched capacitor integrator 50 with a second feedback signal; the quantizer 70 has an input coupled to the second switched capacitor integrator 60 and an output Providing an output signal (DOUT) of the digital converter, having at least a first and a second logic state corresponding to an output of the second switched capacitor integrator; the feedback circuit 170 is coupled to the first The switched capacitor integrator 50 and the second switched capacitor integrator 60 are configured to provide the first feedback signal to the first switched capacitor integrator 50 and the second feedback signal to the second switched capacitor integral The modal element 190 is coupled to an input of the first switched capacitive integrator 50 and an output of the second switched capacitive integrator 60 for providing a modal signal for control The first cut One integrator capacitor 50 and the operation of the second one of the switched capacitor integrator 60 is operated.

The feedback circuit 170 includes a first digital to analog converter (DAC) 171, a second digital to analog converter (DAC) 172, nine switched elements 116-119, 156-159 and two capacitors 112, 152. The first digital to analog converter 171 has a first end coupled to the output of the quantizer 70 and a second end coupled to the input of the first switched capacitive integrator 50, through the switching element 116 ～119 and the capacitor 112 are configured to provide the first feedback signal to the first switched capacitor integrator 50.

The second digit to analog converter 172 has a first terminal coupled to the output of the quantizer 70 and a second terminal coupled to the input of the second switched capacitor integrator 60, through the switching component 156 ～159 and the capacitor 152 are configured to provide the second feedback signal to the second switched capacitor integrator 60.

The switching element 116 has a first end coupled to the first digit to the output of the analog converter 171 and a second end. The switching element 117 has a first end coupled to the second end of the switching element 116 and a second end coupled to ground. The capacitor 112 has a first end coupled to the first end and a second end of the switching element 117. The switching element 118 has a first end coupled to the second end of the capacitor 112 and a second end coupled to ground. The switching element 119 has a first end coupled to the second end of the capacitor 112 and a second end coupled to the bimodal delta-delta analog to the fully differential operating amplifier 110 of the digital converter 50. Output. The switching element 156 has a first end coupled to the output of the second digit to the analog converter 172 and a second end. The switching element 157 has a first end coupled to the second end of the switching element 156 and a second end coupled to ground. The capacitor 152 has a first end coupled to the first end and a second end of the switching element 157. The switching element 158 has a first end coupled to the second end of the capacitor 152 and a second end coupled to ground. The switching element 159 has a first end coupled to the second end of the capacitor 152 and a second end coupled to the bimodal delta-delta analog to the fully differential operating amplifier 150 of the digital converter 60. Output.

The modal element 190 includes three switching elements 132-134, a capacitor 115, four switching elements 128-131, and two inverters 191-192. The switching element 132 has a first end coupled to the output of the first switched capacitive integrator 50 through a plurality of capacitors 113 and four switching elements 120-123, and a second end coupled to the first The input of the switched capacitor integrator 50 is coupled through a plurality of capacitors 114 and four switching elements 124-127. The switching element 133 has a first end coupled to the input of the first switched capacitive integrator 50 and a second end. The switching element 134 component has a first end and a second end. The inverter 191 has a first end coupled to the input of the second switched capacitor integrator 60 and a second end coupled to the switching element 134. The inverter 192 has a first end coupled to the switching element 132 element and a second end coupled to the switching element 133, 134. The switching element 128 has a first end coupled to the switching element 134 element and a second end. The switching element 129 has a first end coupled to the second end and a second end of the switching element 128. The capacitor 115 has a first end coupled to the second end and a second end of the switching element 129. The switching element 130 has a first end coupled to the second end of the capacitor 115 and a second end coupled to ground. The switching element 131 has a first end coupled to the second end of the capacitor 152 and a second end coupled to the second end of the switching element 133. The modal element 190 controls the first switching element 132, the second switching element 133 and the third switching element 134 to determine an on or off state.

The first switched capacitive integrator 50 includes a fully differential operational amplifier 110, a capacitor 111, eight switching elements 120-123, 124-127, and two capacitors 113,114.

The fully differential operating amplifier 110 has a first input coupled to the second switching component 119, 133 of the modal component, a second terminal coupled to the ground and an output. The first capacitor 111 has a first end coupled to the first end of the fully differential operating amplifier 110 of the first switched capacitive integrator 50, and a second end coupled to the first switched capacitive integrator 50. The fully differential operates the output of the amplifier 110.

The switching element 120 has a first end coupled to the first end and a second end of the switching element 102. The switching element 121 has a first end coupled to the second end and a second end of the switching element 120. The capacitor 113 has a first end coupled to the second end and a second end of the switching element 113. The switching element 114 has a first end coupled to the second end of the capacitor 113 and a second end coupled to ground. The switching element 123 has a first end coupled to the second end of the capacitor 113 and a second end coupled to the first output of the fully differential operating amplifier 110.

The switching element 124 has a first end coupled to the second end and a second end of the switching element 102. The switching element 125 has a first end coupled to the second end and a second end of the switching element 124. The switching element 114 has a first end coupled to the second end and a second end of the switching element 125. The switching element 126 has a first end coupled to the second end of the capacitor 114 and a second end coupled to ground. The switching element 127 has a first end coupled to the second end of the capacitor 114 and a second end coupled to the first output of the fully differential operating amplifier 110.

The second switched capacitor integrator 60 includes a fully differential operating amplifier 150, a capacitor 151, four switching switches 160-163 and a capacitor 153.

The differential sub-operating amplifier 150 has a first input coupled to the switching element 159, 163 and a second input coupled to the ground and an output. The capacitor 151 has a first end coupled to the first output of the fully differential operating amplifier 150 of the second switched capacitive integrator 60 and the input of the quantizer 70.

The switching element 160 has a first end coupled to the first output and a second end of the fully differential operating amplifier 110. The switching element 161 has a first end coupled to the second end and a second end of the switching element 160. The capacitor 153 has a first end coupled to the second end and a second end of the switching element 161. The switching element 162 has a first end coupled to the second end of the capacitor 153 and a second end coupled to ground. The switching element 163 has a first end coupled to the second end of the capacitor 153 and a second end coupled to the first output of the fully differential operating amplifier 150.

According to the present invention, the dual input AIN and BIN nodes are provided for transmitting signals to the bimodal delta-delta analog to digital converter 100 and other input modal signals from the modal element 190 to determine the dual mode. The state of the delta-delta analog to the state of the digital converter 100. When the modal signal is equal to 0, the bimodal δ-Δ analog to digital converter 100 operates in a near zero intermediate frequency (NZIF) mode; when the modal signal is equal to 1, the bimodal δ-Δ analog to digital conversion The device 100 operates in a low intermediate frequency mode (low IF).

Referring now to Figure 3, there is shown a block diagram of a receiver circuit 200 operating at a near zero intermediate frequency bimodal delta-delta analog to digital converter. This RF receiver architecture is widely used today. The receiver circuit 200 includes a low noise amplifier 210; a frequency synthesizer 240; a first mixer 220; a second mixer 221; a low pass filter 231, a first bimodal δ- The delta analog to digital converter 100 and a second bimodal delta-delta analog to digital converter 100. It should be noted that although the modal element 190 is in the bimodal delta-delta analog to digital converter 100, the modal element 190 is shown separately in the figure for clarity of the receiver circuit 200.

The low noise amplifier (LNA) 210 amplifies a received weak signal, which then passes through the mixer 220, 221 stage, and then filters out the interference beyond the frequency band by a low pass filter (LPF) 230. The frequency synthesizer 240 has a first output to provide a first signal to the mixer 220 and a second output to provide a second signal to the mixer 221. The mixer 220 has a first input coupled to the output of the low noise amplifier 210, and a second input coupled to the first input and an output of the frequency synthesizer 240. The second mixer 221 has a first input coupled to the output of the low noise amplifier 210, a second input coupled to the second input of the frequency synthesizer 240, and an output. The low pass filter 230 has a first input coupled to the output of the first mixer 220, a second output coupled to the output of the second mixer 221, and a first output coupled The first bimodal delta-delta analog to digital converter 100 (above) and a second output are coupled to a second bimodal delta-delta analog to digital converter 100 (below). The down-converted I and Q signals from the low pass filter (LPF) 230 are transmitted to the input nodes "AIN" and "BIN", and the individual passes analogy to the digital converter 100, but only the input "AIN" is required at this time. A node. Here, the two digit-to-analog converters (disclosed below the figure 3) are identical, that is, one digit to the analog converter performs the I signal and the other digit to the analog converter performs the Q signal.

Referring now to Figure 4, there is disclosed a signal flow diagram of the bimodal delta-delta analog to digital converter 100 operating at near zero intermediate frequency. When the modal signal of the modal element 190 is equal to zero, the δ-Δ analog to the digital converter 100 operates in a near zero intermediate frequency (NZIF) mode, the switching elements 133, 134 should be turned off, and The upper feedback path should be broken, as shown in Figure 4. At the same time, the switching element 132 should be turned "on" and the input signal AIN is equal to BIN. So when the signal is fed, we can use one of its input nodes. Under this architecture, the delta-delta analog to digital converter 100 has a high pass noise transfer function whose zero position is located at the original frequency.

Referring now to Figure 5, there is shown a block diagram of a receiver circuit 201 operating at a low intermediate frequency bimodal delta-delta analog to digital converter. The same receiver architecture includes the low noise amplifier 210 and the mixers 220, 221 but coupled to a bandpass filter (BPF) 232 and the bimodal delta-delta analog to digital converter 100 of the present invention. It should be noted that although the modal element 190 is in the bimodal delta-delta analog to digital converter 100, the modal element 190 is shown separately in the figure for clarity of the receiver circuit 200.

The frequency synthesizer 240 has a first input terminal to provide a first signal to the mixer 220 and a second output terminal to provide a second signal to the mixer 221 . The first mixer 220 has a first input coupled to the output of the low noise amplifier 210, and a second input coupled to the first input and an output of the combiner 240. The second mixer 221 has a first input coupled to the output of the low noise amplifier 210 and a second input coupled to the second output and an output of the combiner 240. The bandpass filter 232 has a first input coupled to the output of the first mixer 220, a second input coupled to the output of the second mixer 221, and a first output coupled to the output A first bimodal delta-delta analog to digital converter 100 (above the fifth figure) and a second output coupled to a second bimodal delta-delta analog to digital converter 100 (in the fifth diagram) Below).

The down-converted signal preceding the bandpass filter 232 may have interference energy and can be interpreted by the second bimodal delta-delta analog to the digital converter 100 (below the fifth figure). The second bimodal delta-delta digital to analog converter 100 has the detection to monitor the interference signal. Once the signal is too large and exceeds the linear range of the bandpass filter 232, the low noise amplifier 210 is alerted to reduce the gain. To avoid interference signals, the bandpass filter (BPF) 232 is saturated. At this time, the first δ-Δ analog to digital converter 100 (on) should receive a signal from the bandpass filter (BPF) 232 that the normal I and Q paths are down-converted, and then transferred to a digital code of the data (Data). Stream), read by the baseband processor. That is, even if the first bimodal δ-Δ analog to the digital converter 100 (on) and the second bimodal δ-Δ analog to the digital converter 100 (below) are the same components, they receive different The signal, when the modal signal of the modal element 190 is equal to 1 and the bimodal δ-Δ analog to the digital converter 100 operates in a low intermediate frequency mode.

Referring now to Figure 6, there is disclosed the signal flow diagram of the bimodal delta-delta analog to digital converter 100 operating at a low intermediate frequency. When the modal signal of the modal element 190 is equal to 1 and the bimodal δ-Δ analog to the digital converter 100 is operating in a low intermediate frequency mode, the switching elements 133, 134 should be turned "on" and the switching The element 132 should now be turned off, as shown in FIG. The upper layer feedback path is now coupled, in which case the delta-delta analog to digital converter 100 has a high pass noise transfer function in which the zero position falls on the intermediate frequency. In this architecture, the "AIN" and "BIN" nodes process individual signals and use the switched capacitor operation to add input signals such as "AIN+BIN".

While the present invention has been described in its preferred embodiments, it is not intended to limit the scope of the invention, and various modifications and changes can be made without departing from the spirit and scope of the invention. As explained above, all types of corrections and changes can be made without destroying the spirit of this creation. Therefore, the scope of the invention is defined by the scope of the appended claims.

50. . . First switched capacitive integrator

60. . . Second switched capacitive integrator

70. . . Quantizer

100. . . Bimodal delta-delta analog to digital converter

102. . . Switching component

110. . . Fully differential operating amplifier

111～115. . . Capacitor

116～134. . . Switching component

150. . . Fully differential operating amplifier

151~153. . . Capacitor

156~159. . . Switching component

160～163. . . Switching component

170. . . Feedback circuit

171,172. . . Digital to analog converter

180. . . Feedback circuit

190. . . Modal component

191,192. . . inverter

200,201. . . Receiver circuit

210. . . Low noise amplifier (LNA)

220,221. . . Mixer

230. . . Low pass filter (LPF)

232. . . Bandpass filter (BPF)

240. . . Frequency synthesizer

Figure 1 is a delta-delta analog to digital converter in accordance with the prior art.

Figure 2 is a diagram showing a bimodal delta-delta analog to digital converter in accordance with the prior invention.

Figure 3 is a block diagram showing the receiver circuit operating a bimodal delta-delta analog to digital converter operating at near zero intermediate frequency.

Figure 4 is a diagram showing the signal flow diagram of the bimodal delta-delta analog to digital converter operating at near zero intermediate frequency.

Figure 5 is a block diagram showing the receiver circuit of a bimodal delta-delta analog to a digital converter ADC operating at low intermediate frequencies.

Figure 6 is a diagram showing the flow of signals at a low intermediate frequency operating from a bimodal delta-delta analog to digital converter.

50. . . First switched capacitive integrator

60. . . Second switched capacitive integrator

70. . . Quantizer

110. . . Fully differential operating amplifier

111～115. . . Capacitor

116～134. . . Switching component

150. . . Fully differential operating amplifier

151~153. . . Capacitor

156~159. . . Switching component

160～163. . . Switching component

170. . . Feedback circuit

171,172. . . Digital to analog converter

190. . . Modal component

191,192. . . inverter

Claims (14)

A bimodal delta-delta analog to digital converter (ADC) comprising: a first switched capacitive integrator for integrating an input signal and a first feedback signal; and a second switching capacitor An integrator coupled to the first switched volume divider for integrating the output signal of the first switched capacitive integrator with a second feedback signal; a quantizer having an input coupled The second switched capacitor integrator and an output terminal are configured to provide an output signal of the digital converter, and have at least a first and a second logic state corresponding to an output of the second switched capacitor integrator; a feedback circuit coupled to the first switched capacitive integrator and the second switched capacitive integrator for providing the first feedback signal to the first switched capacitive integrator and the second feedback signal to the a second switched capacitor integrator; and a modal element coupled to one of the input of the first switched capacitive integrator and one of the output of the second switched capacitive integrator for providing a modal signal No. to control one of the action of the first switched capacitor integrator and one of the second switched capacitor integrators. The bimodal delta-delta analog to digital converter of claim 1, wherein the feedback circuit comprises: a first digital to analog converter (DAC) coupled to the first switched capacitive integrator The input end is configured to provide the first feedback signal to the first switched capacitive integrator; and a second digital to analog converter (DAC) coupled to the input end of the second switched capacitive integrator, The second feedback signal is provided to the second switched capacitor integrator. The bimodal delta-delta analog to digital converter of claim 1, wherein the modal element comprises: a first switching element having a first end coupled to the first switched capacitive integrator The input end and a second end are coupled to the input end of the second switched capacitor integrator; a second switching element has a first end coupled to the input of the first switched capacitive integrator and a second And a third switching element having a first end coupled to the second end of the second switching element of the modal element and a second end coupled to the output of the second switched capacitive integrator And wherein the modal element controls the first switching element, the second switching element and the third switching element to determine a state of being on or off. The bimodal δ-Δ analog to digital converter according to claim 3, wherein between the second switching element and the third switching element, the modality further comprises: a fourth switching The first component is coupled to the second terminal and the second terminal of the third switching component; and the fifth switching component has a first terminal coupled to the fourth switching component The second terminal and the second terminal are coupled to the ground; a first capacitor has a first end coupled to the first end and a second end of the fifth switching element; and a sixth switching element has a first a second end coupled to the first capacitor and a second end coupled to the ground; and a seventh switching element having a first end coupled to the first end of the sixth switching element and a first The two ends are coupled to the second end of the second switching element. The bimodal delta-delta analog to digital converter of claim 1, wherein the first switched capacitive integrator comprises: a fully differential operational amplifier having a first input coupled to the mode The first end of the second switching element of the state element; and a first capacitor having a first end coupled to the first end of the fully differential operating amplifier of the first switched capacitive integrator, A second end is coupled to the output of the fully differential operating amplifier of the first switched capacitive integrator. The bimodal delta-delta analog to digital converter of claim 5, wherein the first switched capacitive integrator further comprises: a first switching element having a first end coupled to the first The first switching end of the switching element has a first end coupled to the second end of the first switching element and a second end coupled to the ground; The second capacitor has a first end coupled to the first end and a second end of the second switching element; a third switching element having a first end coupled to the second end of the second capacitor and The second end is coupled to the ground; the fourth switching element has a first end coupled to the second end of the third switching element and a second end coupled to the fully differential of the first switched capacitive integrator An input terminal of the operational amplifier; a fifth switching element having a first end coupled to the second end and a second end of the first switching element; a sixth switching element having a first end coupled to The second switching terminal is coupled to the ground by the second end and the second end; The third capacitor has a first end coupled to the second end and a second end of the sixth switching element; a seventh switching element having a first end coupled to the second end of the third capacitor and a first end The two ends are coupled to the ground; the eighth switching element has a first end coupled to the second end of the seventh switching element and a second end coupled to the first switched capacitive integrator. The input of the amplifier; The bimodal delta-delta analog to digital converter according to claim 1, wherein the second switched capacitive integrator comprises: a fully differential operational amplifier having a first input terminal and a second An input coupled to the ground and an output coupled to the output of the quantizer; and a first capacitor having the first end coupled to the second differentially operated amplifier of the second switched capacitive integrator An input end, a second end coupled to the output of the fully differential operating amplifier; The bimodal δ-Δ analog to digital converter according to claim 7, wherein the second switched capacitor integrator further comprises: a first switching element having a first end coupled to the total difference The first switching end of the first switching element has a first end coupled to the second end of the first switching element and a second end coupled to the ground; a second The capacitor has a first end coupled to the first end and a second end of the second switching element; a third switching element having a first end coupled to the second end of the second capacitor and a first end a second end is coupled to the ground; a fourth switching element having a first end coupled to the second end of the third switching element and a second end coupled to the second differential capacitive integrator Operating the input of the amplifier; The bimodal delta-delta analog to digital converter of claim 3, wherein the first switching element of the modal element is switched to on, the second switching of the modal element The mode element and the third switching element are switched to off, for operating the bimodal delta-delta analog-to-digital converter in a near zero intermediate frequency (NZIF); The bimodal delta-delta analog to digital converter of claim 3, wherein the first switching element of the modality is switched to off, the second switching of the modal element Switching the component and the third switching element to on is used to operate the bimodal delta-delta analog-to-digital converter at a low intermediate frequency (LIF); A receiver circuit includes: a low noise amplifier having an output; a frequency synthesizer having a first output for providing a first signal and a second output for providing a second output a first mixer having a first output coupled to the output of the low noise amplifier, a second input coupled to the first output of the frequency synthesizer, and an output; a second mixer having a first output coupled to the output of the low noise amplifier, a second input coupled to the second input of the frequency synthesizer, and an output; a low a pass filter having a first input coupled to the output of the first mixer, a second input coupled to the output of the second mixer, and a first output coupled to the application range One of the first bimodal delta-delta analog to digital converters and a second output coupled to one of the second bimodal delta-delta analog to digital converters as recited in claim 1 . The δ-Δ analog-to-digital circuit of claim 11, wherein the first bimodal δ-Δ analog to digital converter and the second bimodal δ-Δ analog to digital converter The first switching element of the modal element is switched to on, the first bimodal δ-Δ analog to digital converter and the second bimodal δ-Δ analog to modal of the digital converter The second switching element of the component and the third switching component will switch to off for the first bimodal delta-delta analog to digital converter and the second bimodal delta-delta The analog to digital converter operates in the near zero intermediate frequency (NZIF) mode. A receiver circuit includes: a low noise amplifier having an output; a frequency synthesizer having a first output for providing a first signal and for providing a second output and a second output a first mixer having a first output coupled to the output of the low noise amplifier, a second input coupled to the first output of the frequency synthesizer, and an output; a second mixer having a first output coupled to the output of the low noise amplifier, a second input coupled to the second input of the frequency synthesizer, and an output; a bypass a filter having a first input coupled to the output of the first mixer, a second input coupled to the output of the second mixer, and a first output coupled to the first application range The first bimodal delta-delta analog to digital converter and a second output are coupled to a second bimodal delta-delta analog to digital converter as described in claim 1. The δ-Δ analog-to-digital circuit of claim 13, wherein the first bimodal δ-Δ analog to digital converter and the second bimodal δ-Δ analog to digital converter The first switching element of the modal element is switched to (off), the first bimodal δ-Δ analog to digital converter and the second bimodal δ-Δ analog to the modal element of the digital converter Switching the second switching element and the third switching element to on, such that the first bimodal δ-Δ analog to digital converter and the second bimodal δ-Δ analog to digital conversion The device operates in a low intermediate frequency (Low IF) mode.