TW201316426A - System and method for semiconductor wafer processsing with side/bevel protection - Google Patents

Abstract

A system is provided that includes a power supply connectable to a semiconductor wafer including opposing, major front and back surfaces joined by a circumferential side, with the wafer undergoing processing including electroplating a damascene layer on the wafer. The system also includes an arrangement configured to apply a polymer coating to the side of the wafer before electroplating the damascene layer, with the system being configured to apply a polymer coating in accordance with an electrophoresis technique driven by the power supply. In this regard, the polymer coating is applied to the side but not at least a portion of the front and back surfaces of the wafer, and the polymer coating provides a barrier to formation of the damascene layer on the side of the wafer.

Description

Semiconductor wafer processing method and system with side protection

Example embodiments of the present invention relate to processes for semiconductor wafers and, more particularly, to methods and systems for protecting wafer sides in a process.

In the semiconductor industry, the fabrication of a semiconductor device includes a process for a wafer that includes a front-end process and a back-end process to pattern electronic components (eg, transistors, resistors, capacitors, etc.) into the crystal and form interconnects. Form the integrated circuit. After the wafer process is completed, the wafer is diced into individual dies and then packaged.

In a portion of the front-end process, the wafer can be embedded to form an electronic interconnect such as a wire, a contact window, or a via. To form the damascene structure, a dielectric layer is formed over a substrate having a conductive region therein. An opening is then formed in the dielectric layer. The opening can be a contact window opening, a via opening, a wire trench or a mosaic opening. This opening exposes a portion of the conductive area in the substrate. A layer of metal is then formed over the substrate and completely covers the opening. Many suitable metallic materials are used as the metal layer, but as described herein, according to an example, the metal layer is copper or a copper alloy (commonly referred to as copper). In one example, the metal layer may first form a thin layer of copper seed and then form a thick layer of metal, commonly referred to as a "mosaic layer." In one example, the thin copper seed layer can be formed using physical vapor deposition (PVD) or chemical vapor deposition (CVD), and the copper inlay can be formed using electrochemical plating (ECD).

After applying the metal layer on the substrate, the wafer can be cleaned by immersing it in a solution to remove particles generated when the copper layer is applied. The cleaned wafer can also be dried, for example, by rotating the wafer. Finally, annealing and chemical mechanical polishing (CMP) are performed to remove excess metal material outside the opening.

The wafer typically includes opposing major front and back surfaces joined together by one side, which is generally inclined. In a damascene process, it is often desirable to have a metal layer deposited by electroplating close to the sides of the wafer but not to the sides. Similarly, it is generally undesirable to have a metal layer of electroplated deposition extending over the sides of the wafer. Therefore, certain techniques have been developed to remove portions of the electroplated deposited metal layer formed on the sides of the wafer, but further improvements to existing technologies are still desired.

Exemplary embodiments of the present invention provide methods and systems for protecting the sides of a wafer in a process for forming a plating layer, as described in the preceding paragraphs. SUMMARY OF THE INVENTION According to one aspect of the present invention, an integrated circuit manufacturing system includes: a power supply connectable to a semiconductor wafer having opposing major front and back surfaces joined together by one side, The wafer can be subjected to a front-end process including plating an inlay on the wafer. The system also includes an arrangement configured to apply a polymer to the side of the wafer prior to electroplating the inlay layer, the polymer coating applied to the major front and back surfaces of the wafer A portion and the side, wherein the system is configured to apply the polymeric coating layer by an electrophoresis technique driven by a power source. The polymer coating system serves as a barrier layer for preventing the mosaic layer from being formed on one side of the wafer.

More specifically, a polymer coating is applied to one of the main front and back surfaces of the wafer and the side, that is, a polymer coating system is applied to the side of the wafer, and may be selectively Applied to a portion of the major front and back surfaces of the wafer, rather than being applied to the major front and back surfaces of the wafer. In one example, the polymer applied to the major front and back surfaces of the wafer has a width of between 3 and 5 mm, and the major front and back surfaces have a radius greater than 3 to 5 mm.

In one example, the arrangement includes a pedestal and a heat source. The susceptor is configured to contact the wafer with a polymeric liquid such that the polymer is applied outside of the major front and back surfaces of the wafer and to the sides. And the heat source is configured to thermally cure the polymer liquid on the side of the wafer to form the polymer coating.

In one example, the arrangement includes being configured to apply the polymeric coating after the formation of a thin copper seed layer and prior to electroplating to form the mosaic layer. In this example, the system further includes a reaction chamber in which the wafer can be sealed for thermal curing of the heat source. Also in this example, the reaction chamber has an environment of reduced pressure or inert gas to at least reduce the oxidation of the seed layer upon solidification of the polymeric liquid.

In one example, the arrangement further includes a carrier container filled with a polymeric liquid. In this example, the carrier container has a plurality of rollers configured to support the wafer on the carrier container such that the major front and back surfaces of the wafer are substantially parallel to the upper surface of the polymer liquid. The plane is vertical and such that at least a portion of the side and a portion of the major front and back surfaces are immersed in the polymeric liquid; and wherein the one or more rollers are configured to substantially surround the wafer with the major front surface and One of the rear surfaces is vertically rotated to allow the side continuous contact portion of the wafer to be immersed and removed from the polymer liquid.

Another object of the present invention is to provide an integrated circuit plating system comprising a first machine configured to apply a polymer onto a semiconductor wafer. In various embodiments, the first machine can be the system described above or comprise the elements of the aforementioned system. In this example, the integrated circuit plating system further includes a second machine configured to receive the wafer from the first machine. The second machine is configured to receive the wafer from the first machine, and the second machine is configured to plate an insert layer on the wafer, the polymer coating system is used to prevent the formation of the mosaic layer a barrier layer on the side of the wafer. In this example, the integrated circuit plating system further includes a robot arm to transfer the wafer from the first machine to the second machine.

In an example, the integrated circuit plating system further includes a third machine configured to receive the wafer from the second machine, the third machine for cleaning and drying the wafer after the plating; And a fourth device configured to receive the wafer from the third machine, the fourth machine being used to anneal the wafer. In this example, the integrated circuit plating system further includes the robot arm to transfer the wafer from the second machine to the third machine and from the third machine to the fourth machine.

Certain embodiments of the invention are described in the following description of the embodiments of the invention, in which only some, but not all, embodiments are shown. However, the various embodiments of the present invention may have different types and should not be construed as limiting the present invention; rather, these embodiments are provided so that the disclosure of the present specification satisfies the requirements of the patent law.

Referring to FIG. 1, there is shown a top view and a cross-section (along the dashed line) of a semiconductor wafer 10 in accordance with an exemplary embodiment of the present invention. As shown in the figures, the wafer includes opposing major front and rear surfaces 12, 14 that are joined together by one side 16 that may or may not be inclined (the side of the slope is shown) . This side is therefore sometimes referred to as a slanted side, a slanted edge, a beveled edge or a side. The wafer can be subjected to a front-end process or a back-end process to pattern electronic components (eg, transistors, resistors, capacitors, etc.) in the crystal and form interconnects to form an integrated circuit.

In a manner similar to that explained in the background paragraph, the wafer 10 can be embedded in a portion of the front-end process to form an electronic interconnect such as a wire, a contact or a via. To form the damascene structure, a dielectric layer is formed over a substrate having a conductive region therein. An opening is then formed in the dielectric layer. The opening can be a contact window opening, a via opening, a wire trench or a mosaic opening. This opening exposes a portion of the conductive area in the substrate. A layer of metal is then formed over the substrate and completely covers the opening. Many suitable metallic materials are used as the metal layer, but as described herein, according to an example, the metal layer is copper or a copper alloy (commonly referred to as copper). In one example, the metal layer may first form a thin layer of copper seed and then form a thick layer of copper inlay. In one example, the thin copper seed layer can be formed using physical vapor deposition (PVD) or chemical vapor deposition (CVD), and the copper inlay can be formed using electrochemical plating (ECD).

After applying the metal layer on the substrate, the wafer 10 can be cleaned by immersing it in a solution to remove particles generated when the copper layer is applied. The cleaned wafer can also be dried, for example, by rotating the wafer. Finally, annealing and chemical mechanical polishing (CMP) are performed to remove excess metal material outside the opening.

As explained in the background paragraph, it is generally undesirable to have a layer of electroplated deposition extending over the side edges 16 of the wafer 10. In accordance with certain exemplary embodiments of the present invention, a non-conductive polymer layer 18 may then be applied or otherwise applied to the periphery of the wafer prior to forming the inlay layer. In one embodiment, the non-conductive polymer layer can be applied to the periphery of the wafer after forming a thin copper seed layer and before forming the inlay layer. The polymeric layer may have one or more properties such as compatibility with the plating solution, and/or may be soluble in certain chemicals but is generally insoluble in the plating solution.

The polymer layer 18 can cover the side edges 16 of the wafer 10 and can be additionally coated on the surface of the respective annular peripheral regions of the major front surface 12 and the back surface 14. In a wafer having a main front surface 12 and a rear surface 14 having a diameter of 150 to 450 millimeters (mm), the polymer layer is additionally coated with a front surface 12 and a rear surface of 3 to 5 millimeters (mm) in one example. 14. When the insert layer is formed, the polymer layer can serve as a barrier layer for preventing the insert layer from being formed on the side and partially covered by the polymer on the main front surface 12 and the back surface 14 of the wafer. The polymer layer can then be removed, for example, by some solution or slurry during, during or after chemical mechanical polishing (CMP), so that the embedded layer is not left on the side and the polymer is coated on the wafer. The front surface 12 and the rear surface 14 are partially formed.

This polymeric layer 18 can be applied to the wafer 10 in a number of different ways. As shown in FIG. 2, a system 20 is used to apply a polymer layer 18 over wafer 10, in accordance with an exemplary embodiment. The system includes a container 22 carrying a solution which is filled with a polymeric liquid 24. The system also includes a susceptor to support the wafer and to contact the polymer liquid 24 to coat the polymer liquid 24 at the side 16 of the wafer 10 and to be selectively coated on the primary front surface 12 The edge portions of the peripheral surface of the rear surface 14 are not partially coated on the inner edge portions of the peripheral surfaces of the main front surface 12 and the rear surface 14. As shown in the figure, the system also includes a roller 26 for supporting the side 16 of the wafer 10 to coat the polymer liquid carrying container such that the main front surface 12 and the rear surface 14 of the wafer are substantially associated with the polymer liquid. The plane of the upper surface is perpendicular and such that at least a portion of the sides (if not also including a portion of the major front surface 12 and the back surface 14) is immersed in the polymeric liquid. As shown in the figure, in this example, the roller 26 supports the wafer such that the respective sections of the main front surface 12 and the rear surface 14 of the wafer and the side portions connected to the respective sections are immersed in the polymer. In the liquid. In this example, the depth at which the wafer is immersed in the polymer liquid can be set such that the edge portions of the main front surface 12 and the rear surface 14 can be coated with the polymer liquid.

The roller 26 in this example can further be used to rotate the wafer in an axial direction generally perpendicular to the major front surface 12 and rear surface 14. As shown in Figures 3A-3D (only a portion of this system 20 is shown), as the roller 26 rotates the wafer, the continuous contact portion of the side 16 can be immersed and removed from the polymer liquid 24. Similarly, for any portion of the primary front surface 12 and rear surface 14 that need to be covered by the polymeric liquid, the continuous contact portions 28 of their respective edges can be immersed and removed from the polymeric liquid 24. When the respective sections of the main front surface 12 and the rear surface 14 of the wafer and the side portions joined to the respective sections are immersed in the polymer liquid, the polymer solution covers the respective sections. In one example, the system can be implemented in accordance with an electrophoresis technique driven by a power source 30 coupled to the wafer.

When the respective peripheral sections of the main front surface 12 and the rear surface 14 of the wafer and the side portions connected to the respective sections are extracted from the polymer liquid 24, the coating on the respective sections is high. The molecular liquid can be cured to form the polymer layer 18. In one example, the polymeric layer can be thermally cured using a heat source such as bulb 32 or an ultraviolet light source system. In an exemplary implementation, the polymeric layer 18 is applied after forming a thin copper seed layer and prior to forming the inlay layer, at least the wafer and many of the components typically included in the system are placed with reduced pressure and inert gas In the reaction chamber 34, these inert gases may be, for example, nitrogen, argon or the like. The pressure in the reaction chamber can be at least reduced or to prevent oxidation of the seed layer upon application of the polymeric liquid.

Furthermore, the polymer layer may be applied to the periphery of the wafer 10 prior to electroplating to form an inlay layer to form a damascene structure on the wafer. In the subsequent electroplating step, the polymer layer 18 can serve as a barrier layer for preventing the embedding layer from being formed on the side and a portion of the main front surface 12 and the back surface 14 of the wafer.

4 shows a cross-sectional view of a system 36 for electroplating a wafer 10 in accordance with an exemplary embodiment of the present invention. The system includes a container 38 carrying a solution filled with a plating solution 40 such as copper sulfate. The wafer and a copper metal 42 are immersed in the solution - the wafer serves as a cathode and the copper metal 42 serves as an anode. The wafer cathode and copper metal anode are connected to a power source 44 which creates a potential difference between the cathode of the wafer and the copper metal anode and applies a direct current to the copper metal anode. This current causes the copper atoms in the copper metal anode to oxidize and dissolve in the solution. The potential difference between the wafer cathode and the copper metal anode drives the dissolved copper atoms in the solution toward the wafer cathode. Generally, the junction between the dissolved copper atomic wafer cathode and the copper metal anode is gradually reduced, thus forming a copper plating layer on the wafer cathode surface. However, in the periphery of the wafer including the polymer 18, the polymer layer can serve as a barrier layer to prevent copper from being plated on the side edges 16 and coated with a polymer on one of the major front surface 12 and the back surface 14 of the wafer.

Referring to FIG. 5, an exemplary embodiment of the present invention may further provide an integrated plating system 46 for performing many different operations of the wafer 10 plating and associated processes in the damascene process. System 46 can include a carrier base 48 for feeding wafers in and out of the system. The system also includes a plurality of machines for performing processes in electroplating and inlay processes, and a robotic arm 50 or other electromechanical machine to transfer wafers from one first machine to another and subsequent machines, and Continue to the last machine.

As shown in the figure, the machine in this system may include a first machine 52 to apply a polymer layer 18 on the wafer; and for this purpose, the first machine may include as shown in FIG. A system of system 20. The machine in this system may also include a second machine 54 to electroplate the wafer containing the polymer layer 18. This second machine can include a system of system 36 as shown in FIG. In addition, the machine in the system may also include a third machine 56 including a cleaning solution and drying device to clean and dry the wafer after plating, and a fourth machine 58 to anneal the wafer. .

Referring to Figures 6 and 7, there are shown process flow diagrams for many different operations in accordance with an exemplary embodiment of the present invention. The method includes providing a wafer comprising opposing major front and back surfaces joined together by one side, the wafer being capable of performing a front-end process including plating a layer on the wafer. As shown in block 60, the method can include applying a polymeric coating layer over the sides of the wafer prior to electroplating, but without coating at least a portion of the major front and back surfaces of the wafer. The polymer coating layer can be used as a barrier layer to prevent the side layer from being formed on the side when the electrophoresis technique is driven by a power source.

Applying the polymer coating layer may include immersing the wafer in the polymer liquid to form a polymer coating layer covering the side of the wafer, but not covering at least the main front surface and the back surface of the wafer A portion is then thermally cured to form a polymer coating layer. More specifically, for example, applying the polymer coating layer may include supporting the wafer on a polymer liquid carrying container such that the main front surface and the back surface of the wafer substantially correspond to the upper surface of the polymer liquid The plane is vertical and at least a portion of the sides and a portion including the major front and back surfaces are immersed in the polymeric liquid. In this example, the wafer can be rotated in an axial direction substantially perpendicular to the major front and back surfaces to allow the side continuous contact portions of the wafer to be immersed and removed from the polymeric liquid. Further, in this example, the polymer layer may be thermally cured after the continuous contact portion of the side of the wafer is removed from the polymer liquid.

In one example, the polymeric layer is applied after forming a thin copper seed layer and prior to forming the inlay layer. In this example, the polymer layer coating can be carried out in a reaction chamber having a reduced pressure or inert gas to at least reduce or prevent oxidation of the seed layer upon application of the polymer liquid.

Regardless of the manner in which the polymer layer is applied, the method also includes electroplating to form an inlay layer on the wafer after applying the polymer layer, the inlay layer covering the wafer not covered by the polymer. Portions of the front and back surfaces are as shown in block 62. The method also includes removing the polymeric coating layer after electroplating to form the inlay layer. The subsequent process also includes chemical mechanical polishing (CMP) of the wafer. As shown in block 64, the polymeric coating layer can be removed by chemical mechanical polishing (CMP). Alternatively, as shown in block 66 of Figure 7, the polymer coating layer can be removed prior to chemical mechanical polishing (CMP) by solvent or slurry, followed by chemical mechanical polishing (CMP) at block 68. ).

Although the present invention has been described with reference to the embodiments, the present invention is not limited by the detailed description thereof. Alternatives and modifications are suggested in the foregoing description, and other alternatives and modifications will be apparent to those skilled in the art. In particular, all combinations of components that are substantially identical to the invention can achieve substantially the same results as the present invention without departing from the spirit of the invention. Therefore, all such alternatives and modifications are intended to be within the scope of the invention as defined by the appended claims and their equivalents.

10. . . Semiconductor wafer

12. . . Main front surface

14. . . Back surface

16. . . Side

18. . . Polymer layer

20. . . Polymer coating system

twenty two. . . Container for carrying solution

twenty four. . . Polymer liquid

26. . . Wheel

30. . . power supply

32. . . Heat source

34. . . Reaction chamber

36. . . Plating wafer system

38. . . Container for carrying solution

40. . . Plating solution

42. . . anode

44. . . cathode

46. . . Plating system

48. . . Carrying base

50. . . Robotic arm

52. . . First machine

54. . . Second machine

56. . . Third machine

58. . . Fourth machine

The invention is defined by the scope of the patent application. These and other objects, features, and embodiments are described in the following sections of the accompanying drawings, in which:

1 shows a top view and a cross section (along a broken line) of a semiconductor wafer in accordance with an exemplary embodiment of the present invention.

2 is a schematic diagram of a system for applying a polymer layer on a wafer in accordance with an exemplary embodiment of the present invention.

Figures 3a to 3d show schematic views of a portion of the system according to an exemplary embodiment of the present invention in Figure 2 when the wafer is rotated.

4 is a cross-sectional view showing a system for plating a wafer in accordance with an exemplary embodiment of the present invention.

Figure 5 shows a block diagram of an exemplary embodiment of the present invention that may further provide an integrated plating system for performing many different operations in the wafer plating and inlay process.

Figures 6 and 7 show a process flow diagram for many different operations in accordance with an exemplary embodiment of the present invention.

20. . . Polymer coating system

twenty two. . . Container for carrying solution

twenty four. . . Polymer liquid

26. . . Wheel

30. . . power supply

32. . . Heat source

34. . . Reaction chamber

Claims (23)

An integrated circuit manufacturing method comprising: providing a semiconductor wafer having opposite major front and back surfaces, which are connected by one side, and the wafer can be plated to include an inlay layer thereon a process on the wafer; before plating the inlay layer, applying a polymer to the side of the wafer, the polymer coating is applied to the side but not to the main front surface of the wafer And at least a part of the rear surface, the polymer coating system is formed as a barrier layer for preventing the mosaic layer from being formed on the side of the wafer; wherein the polymer coating layer is driven by a power source Technology to implement. The method of claim 1, wherein the polymer coated on the main front surface and the back surface of the wafer has a width of 3 to 5 mm, and the main front surface and the back surface have a larger diameter. Radius of 3~5mm. The method of claim 1, wherein applying the polymer coating comprises: contacting the wafer with a polymer liquid such that the polymer is coated on the side of the wafer but not in the crystal At least a portion of the major front and back surfaces of the circle; and the polymeric liquid that thermally cures the side of the wafer is coated to form the polymer coating. The method of claim 3, wherein applying the polymer coating is performed after forming a thin copper seed layer and before plating to form the mosaic layer, and the polymer coated application system It is carried out under a reduced pressure or inert gas to at least reduce the oxidation of the seed layer upon solidification of the polymer liquid. The method of claim 3, wherein applying the polymer coating comprises: supporting the wafer on a carrier of the polymer liquid such that the main front surface and the back surface of the wafer are substantially And the polymer liquid is perpendicular to a plane of the upper surface, and at least a portion of the side but not at least a portion of the main front and back surfaces of the wafer is immersed in the polymer liquid; and the wafer is One of the portions perpendicular to the major front surface and the rear surface is axially rotated to continuously contact the side of the wafer to be immersed in and removed from the polymer liquid. The method of claim 5, wherein thermally curing the polymer liquid comprises thermally curing the polymer liquid when the continuous contact portion of the side of the wafer is removed from the polymer liquid. The method of claim 1, further comprising: after applying the polymer coating, electroplating to form the mosaic layer on the wafer, the cladding layer covering is not coated with the polymer The portion of the major front and back surfaces that are coated. The method of claim 1, further comprising: removing the polymer coating after electroplating to form the mosaic layer. The method of claim 8, wherein the process further comprises chemical mechanical polishing of the wafer, and wherein the polymer coating is removed by the chemical mechanical polishing. The method of claim 8, wherein the process further comprises chemical mechanical polishing of the wafer, and wherein the polymer coating is removed by a solvent or a slurry prior to the chemical mechanical polishing. An integrated circuit manufacturing system comprising: a power supply connectable to a semiconductor wafer having opposite major front and back surfaces, connected by one side, the wafer can be electroplated a process of inserting a layer on the wafer; a configuration configured to apply a polymer to the side of the wafer before plating the inlay layer, the polymer coating being applied to the wafer The side layer is not at least a portion of the main front surface and the back surface of the wafer, and the polymer coating system serves as a barrier layer for preventing the mosaic layer from being formed on the side of the wafer; The system is configured to apply the polymer coating layer by an electrophoresis technique driven by a power source. The system of claim 11, wherein the polymer coated on the main front surface and the back surface of the wafer has a width of 3 to 5 mm, and the main front surface and the rear surface have a larger diameter. Radius of 3~5mm. The system of claim 11, wherein the arrangement comprises: a susceptor configured to contact the wafer with a polymeric liquid such that the polymer is applied to the side of the wafer but not At least a portion of the major front and back surfaces of the wafer; and a heat source configured to thermally cure the polymeric liquid on the side of the wafer to form the polymer coating. The system of claim 13, wherein the arrangement is configured to apply the polymer coating after the formation of a thin copper seed layer and before plating to form the mosaic layer, and the system is further The invention comprises: a reaction chamber in which the wafer can be sealed for thermal curing of the heat source, and the reaction chamber has an environment for reducing pressure or an inert gas to at least reduce the seed layer to the polymer liquid It is oxidized when it is cured. The system of claim 13, wherein the arrangement further comprises: a carrying container filled with a polymer liquid, wherein the carrying container has a plurality of rollers configured to support the wafer in the carrying container The main front surface and the rear surface of the wafer are substantially perpendicular to a plane of the upper surface of the polymer liquid, and at least a portion of the side surface is not at least the main front surface and the back surface of the wafer Partially immersed in the polymeric liquid; and wherein the one or more rollers are configured to rotate the wafer axially about one of the major front and back surfaces to continuously contact the side of the wafer It is immersed in and removed from the polymer liquid. The system of claim 15, wherein the heat source is configured to thermally cure the polymer liquid when the continuous contact portion of the side of the wafer is removed from the polymer liquid. An integrated circuit plating system comprising: a first machine configured to apply a polymer coated on a semiconductor wafer, the wafer having opposite major front and back surfaces, connected by one side Together, the polymer coating is applied to the side of the wafer but not to at least a portion of the major front and back surfaces of the wafer; and a second machine is configured to receive from the first machine The wafer is configured to plate an inlay layer on the wafer, the polymer coating being a barrier layer that prevents the inlay layer from being formed on the side of the wafer. The integrated circuit plating system according to claim 17, wherein the polymer coated width applied to the main front surface and the rear surface side of the wafer is between 3 and 5 mm, and the main front The surface and the back surface have a radius greater than 3 to 5 mm. The integrated circuit plating system of claim 17, wherein the first machine comprises: a base configured to contact the polymer with a polymer liquid such that the polymer is coated on the crystal The side of the circle but not at least a portion of the major front and back surfaces of the wafer; and a heat source configured to thermally cure the polymer liquid on the side of the wafer to form the polymer Coating. The integrated circuit plating system of claim 17, wherein the first machine is configured to apply the polymer coating after forming a thin copper seed layer and before plating to form the mosaic layer. Applied, and the first machine further comprises: a reaction chamber in which the wafer can be sealed for thermal curing of the heat source, the reaction chamber having an environment for reducing pressure or inert gas, At least the seed layer is reduced to be oxidized when the polymer liquid is cured. The integrated circuit plating system according to claim 19, wherein the first machine further comprises: a carrying container filled with a polymer liquid, wherein the carrying container has a plurality of rollers configured to the crystal a circular support on the carrier such that the major front and back surfaces of the wafer are substantially perpendicular to a plane of the upper surface of the polymer liquid, and such that at least a portion of the side but not the primary of the wafer At least a portion of the front surface and the back surface are immersed in the polymeric liquid; and wherein the one or more rollers are configured to rotate the wafer axially about one of the major front and back surfaces to substantially The side continuous contact portion can be immersed in and removed from the polymer liquid. The integrated circuit plating system of claim 21, wherein the heat source is configured to thermally cure the polymer liquid when the continuous contact portion of the side of the wafer is removed from the polymer liquid. The integrated circuit plating system of claim 17, further comprising: a third machine configured to receive the wafer from the second machine, the third machine being used for cleaning after the plating And drying the wafer; and a fourth station configured to receive the wafer from the third machine, the fourth machine for annealing the wafer.