TW201312578A - System and method of distributive ECC processing - Google Patents

Abstract

Systems and methods to perform distributive ECC operations are disclosed. A method includes, in a controller of a memory device, receiving data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and first ECC data corresponding to the first sub-block. The method includes initiating a data block ECC operation to process the data block using the main ECC data and initiating a sub-block ECC operation to process the first sub-block using the first ECC data. The method also includes selectively initiating an error location search of the data block ECC operation based on a result of the sub-block ECC operation.

Description

System and method for assigning error correction coding processing

The present invention is generally directed to error correction coding (ECC) processing.

During the processing of writing data into the memory, the data is typically encoded with extra bits ("co-located bits") to form a codeword. In the presence of noise, some of the bits representing the bits of the codeword can be changed, thus causing the original codeword to be erroneous. When reading a codeword from memory, a decoder can be used to identify and correct the error using error correction coding (ECC). For example, the Bose-Chaudhuri-Hocquenghem (BCH) ECC scheme is used in applications where bit errors are often irrelevant. One of the error correction capabilities of an ECC scheme tends to increase as the length of the codeword increases. Therefore, ECC schemes implemented in data storage systems and communication devices often use longer codewords.

BCH decoding can be performed in multiple sequential stages to correct errors in the received data. For example, a BCH decoder can generate a symptom code component that can include a received codeword for one of the errors. The BCH decoder can generate a critical equation (e.g., an error location polynomial) that can be generated based on the calculated symptom code and the critical equation can indicate the number of errors detected in the received codeword. The location of the error detected within the received codeword can be determined based on the root of the key equation via an iterative handler such as a Chien search. Since the Chen search process is typically performed sequentially for each of the received codewords, the amount of time to process the codeword can be proportional to the length of the codeword. As the length of the codeword increases, the delay caused by Chen's search processing can limit the speed of ECC data correction.

The allocated ECC processing includes simultaneous processing of one data block and one or more sub-blocks of the data block. When a sub-block is determined to have no errors or has an error that can be corrected during sub-block processing, one or more portions of the data block processing may be skipped. For example, performing one of the Chen searches during the data block processing may skip the sub-blocks that have been corrected during the sub-block processing. Thus, the average time to process ECC codewords can be reduced as compared to performing one of the complete code searches for each received codeword.

The present invention discloses a system and method for using a linear error location search such as Chen's search during ECC decoding and having a reduced delay even when an error occurs at the end of a data block. An approximate location of one or more errors may be determined and an error location search may be initiated from the determined location. A substantially erroneous location can be determined by dividing the data block into a number of sub-blocks and performing an assigned ECC process on the individual sub-blocks. An error in the sub-block can be found using a smaller ECC than the ECC used for the main block. Sub-blocks with few errors can be corrected during sub-block processing, thereby reducing the number of loops used to perform the main block error location search and thus reducing latency.

Referring to Figure 1, a particular embodiment of one of the systems for performing error correction coding (ECC) processing of allocation is illustrated and generally designated 100. System 100 includes a data storage device 102 having one of ECC engines 114 configured to perform ECC processing. System 100 also includes a host device 104 operatively coupled to one of data storage devices 102.

In a particular embodiment, host device 104 is configured to communicate with data storage device 102 and to send a request for data stored at data storage device 102. The host device 104 is further configured to receive the data provided by the data storage device 102 in response to the requests. For example, the host device 104 can include a mobile phone, a music or video player, a game console, an e-book reader, a PDA, a computer (such as a laptop or a notebook). Computer), any other electronic device, or any combination thereof.

The data storage device 102 includes a controller 110 and a memory 112. The controller 110 is configured to manage the memory 112 and communicate with the host device 104 when the data storage device 102 is operatively coupled to the host device 104. The controller 110 includes an ECC engine 114 and can be configured to receive data read from the memory 112 and provide the received data to the ECC engine 114. The controller 110 can be configured to retrieve data output by the ECC engine 114 (such as decoded data that has been corrected for one or more errors that occurred during storage or transmission) and the decoded corrected data Provided to the host device 104.

The memory 112 is configured to store information such as data (e.g., user data) and ECC data (e.g., redundant data or "co-located") associated with the data. For example, the data may include data of a multimedia file to be stored at the memory 112, and the parity may include redundant information to enable the ECC engine 114 to detect and correct errors in the data. The data and the corresponding ECC data can be stored together as a data word. The memory 112 can be a non-volatile memory. For example, memory 112 can be a flash memory, such as a NAND flash memory. To illustrate, the data storage device 102 can be a memory card, such as a Secure Digital SD. Card, a microSD Card, a miniSD.TM card (trademark of SD-3C LLC of Wilmington, Delaware), a MultiMediaCard.TM (MMC.TM) card (Arlington, VA) Virginia) is a trademark of the JEDEC Solid State Technology Association or a CompactFlash (CF) card (a trademark of SanDisk Corporation of Milpitas, Calif.). As another example, data storage device 102 can be configured to be coupled to host device 104 as an embedded memory, such as eMMC. (trademark of JEDEC Solid State Technology Association, Arlington, VA) and eSD, as illustrative examples.

A representative ECC page 120 is stored in memory 112. The ECC page 120 includes a data block 130. The data block 130 includes a first sub-block (SB1) 121, a second sub-block (SB2) 122, a third sub-block (SB3) 123, and a first Four sub-blocks (SB4) 124. The data block 130 further includes ECC data associated with each of the sub-blocks 121-124, such as the first sub-ECC data 125, the second sub-ECC data 126, the third sub-ECC data 127, and the fourth sub-ECC. Information 128. In addition to the data block 130 having the combined sub-blocks 121-124 and the combined sub-ECC blocks 125-128, the ECC page 120 also includes a co-located block 129 that stores one of the ECC data corresponding to the data block 130.

The ECC engine 114 is configured to perform an ECC decoding operation on the received data via the assigned ECC processing. For example, ECC engine 114 may perform decoding in accordance with a BCH scheme, a Reed-Solomon scheme, or any other scheme that continuously searches for an error location, such as by using a Chen search. The ECC engine 114 can receive data read from memory (such as ECC page 120) and process the read data 116 along a parallel processing path. A first processing path includes a data block ECC decoder 142 to perform decoding of one of the entire ECC codewords, such as the entire ECC page 120 containing the data block 130 and the ECC data 129. A second parallel processing path includes a sub-block ECC encoder 140 to use ECC data corresponding to one or more sub-blocks (eg, sub-blocks 121-124) of the data (eg, sub-ECC data 125-128) ) to perform ECC processing of the sub-blocks. The ECC engine 114 may initiate one of the data block ECC operations at the data block ECC decoder 142 and one of the sub-block ECC operations at the sub-block ECC encoder 140 substantially simultaneously.

During operation, in response to errors detected in one or more of sub-blocks 121-124 that may be modified at sub-block ECC decoder 140 using sub-ECC data 125-128, may be reduced for use in One of the ECC processing of the data block 130 at the data block ECC decoder 142. For example, three of the four sub-blocks (eg, sub-blocks 121-123) may be determined to be revampable via sub-block ECC processing at sub-block ECC decoder 140. Accordingly, one of the error location searches at the data block ECC decoder 142 can be selectively initiated to bypass the correctable sub-blocks 121-123 and can limit the error location search to being determined not to be processed by the sub-block ECC. The positioning error in the modified sub-block 124 is incorrect. Examples of sub-block and data block processing are explained in more detail with respect to Figures 3 through 4.

Each of the sub-blocks 121-124 can be processed faster than the ECC page 120, but since one of the ECC bits of the sub-ECC data 125-128 is a smaller number, each of the sub-blocks 121-124 can have a reduced Error correction rate (and possibly a large error correction probability). By using the allocated ECC processing, the ECC engine 114 provides ECC decoding (which has an intensity associated with the total co-location of one of the ECC pages) while achieving one or more sub-blocks that can be modified in parallel with modifying the ECC page. Faster operation.

Referring to Figure 2, a particular embodiment of one of the systems for performing ECC processing of the allocation is illustrated and generally designated 200. System 200 includes a primary ECC processing circuit 202 and a sub-ECC processing circuit 204. For example, primary ECC processing circuit 202 may correspond to data block ECC decoder 142 of FIG. 1 and sub-ECC processing circuit 204 may correspond to sub-block ECC decoder 140 of FIG. One of the outputs of the sub-ECC processing circuit 204 can be provided to the control circuit 206. Control circuit 206 has an output coupled to one of main ECC processing circuits 202. System 200 is configured to receive a data word illustrated as one of ECC pages 120.

The ECC page 120 is provided via a parallel processing path for processing at the primary ECC processing circuit 202 and at the sub-ECC processing circuit 204. The main ECC processing circuit 202 can perform ECC processing on the entire ECC page 120. For example, the primary ECC processing circuit 202 can generate a symptom code that is determined to have a key equation indicating one of the orders of the number of errors in the ECC page 120, and a positioning error (such as by performing a Chen search). The resulting information after the correction of the error is provided as corrected information 240.

Sub-ECC processing circuit 204 can be configured to perform ECC processing of first sub-block 121 using first sub-ECC material 125. The sub-ECC processing circuit 204 can determine the symptom code, generate a key equation, and perform a Chen search of the first sub-block 121 using the first sub-ECC material 125. The sub-ECC processing circuit 204 can be configured to process the second sub-block 122 using the second sub-ECC data 126, the third sub-block 123 using the third sub-ECC data 127, and the fourth sub-ECC data 128. Four sub-blocks 124. For example, sub-ECC processing circuit 204 can be configured to process one or more stages of ECC processing in a pipelined manner as illustrated with respect to FIG. As another example, sub-ECC processing circuit 204 can include multiple parallel ECC processing circuits to process two or more of sub-blocks 121-124 in parallel with one another.

The result 250 of the sub-ECC processing is provided to control circuit 206. These results may include the number 254 of errors detected during sub-ECC processing of each of sub-blocks 121-124, indicating whether any of sub-blocks 121-124 are uncorrectable (ie, One or more indications 252, other information, or any combination thereof, with more errors than errors that may be corrected using sub-ECC data 125-128. Control circuit 206 can be configured to determine one or more parameters (such as a Chen search start position 260 and a Chen search end position 262) to continue the main ECC processing more efficiently based on the results returned from sub-ECC processing circuit 204. Processing of circuit 202.

For example, the various components of ECC processing may require different amounts of time. To illustrate, symptom code calculations can be performed in a fixed time interval, and the generation of a critical equation can be proportional to the number of errors in the ECC page, and the execution of the Chen search can also be required with errors. The number is proportional to the amount of time and the location of the error in the ECC page. The result of the sub-ECC processing circuit 204 indicating whether the error has been corrected or whether the error in each of the sub-blocks 121-124 is uncorrectable may enable the main ECC processing circuit 202 to bypass one or more of the execution main ECC processing. A situation. To illustrate, when sub-ECC processing circuit 204 is capable of correcting all detected errors in the first three sub-blocks 121-123 but not correcting errors occurring in fourth sub-block 124, control circuit 206 may The configuration is instructed to cause the primary ECC processing circuit 202 to initiate the Chen search process selectively at the beginning of the fourth sub-block 124 (i.e., at the first bit after the third ECC profile 127). In this manner, due to the parallel ECC processing of the first three sub-blocks 121-123, the total number of one of the Chen search processing cycles at the primary ECC processing circuit 202 can be substantially reduced.

Referring to Figure 3, there is illustrated a data flow diagram illustrating one of an example of ECC processing in an assigned ECC system (such as ECC engine 114 of Figure 1 or system 200 of Figure 2) and generally indicating the assigned ECC system Is 300. The data flow is depicted in accordance with one of the representative timings of the ECC processing of ECC page 120 of FIG. 1 and includes a data flow in a sub-ECC operation 302 and a data flow in a primary ECC operation 304. Sub-ECC operation 302 may correspond to processing in sub-block ECC decoder 140 of FIG. 1 or sub-ECC processing circuit 204 of FIG. The main ECC operation 304 may correspond to the processing in the data block ECC decoder 142 of FIG. 1 or the main ECC processing circuit 202 of FIG.

As illustrated, the sub-ECC operation 302 can span, for example, a first loop 310, a second loop 311, a third loop 312, a fourth loop 313, a fifth loop 314, and a sixth loop 315. A pipeline is streamlined. Each of the loops 310-315 is illustrated as generally corresponding to one of the individual portions of the ECC page 120 and also corresponding to one of the pipeline stages associated with the sub-ECC processing.

The sub-ECC operation 302 can include: a first pipeline stage for calculating a symptom code of a received sub-block; and a second pipeline stage for generating each sub-area based on the calculated symptom code One of the key equations of the block; and a third pipeline stage for performing a Chen search to locate and correct errors in the sub-block. The pipeline stages can be configured such that each subsequent sub-block sequentially enters the first pipeline stage and can process three or more sub-blocks simultaneously, with one sub-block at each pipeline stage And the processing of each of the sub-blocks at least partially overlaps with the processing of one or more other sub-blocks.

To illustrate, the first loop 310 includes a process of using the first sub-block 121 of the first ECC profile 125, illustrating the first execution of the symptom code calculation of the first sub-block 121 using the first sub-ECC profile 125 during the period. Symptom code processing 331. Additionally, the symptom code generation 321 of the primary ECC operation 304 begins during the first cycle 310.

The second loop 311 follows the first loop 310 and includes processing of the second sub-block 122 of the second ECC profile 126 entering the pipeline, which begins with a second symptom code process 341. Additionally, during the second loop 311, a first key equation generation 332 of the first sub-block 121 is performed. After the first key equation generation 332 of the first sub-block 121, the first sub-block 121 and the first Chen search processing 333 of the first sub-ECC data 125 begin during the second loop 311 and continue to the third loop. 312.

During the third cycle 312, processing using the third sub-block 123 of the third ECC profile 127 begins with the third symptom code process 351 of the third sub-block 123. In addition, the first sub-block 121 and the first sub-ECC processing 125 of the first sub-ECC data 125 are completed, and the second key equation generation 342 of the second sub-block 122 is performed. Also illustrated, during the third loop 312, at the end of the first sub-block 121 and the first Chen search processing 333 of the first sub-ECC data 125, the second sub-block 122 and the second sub-ECC data 126 The second Chen search process 343 begins. The elapsed time is illustrated between the completion of the second critical equation process 342 during the third cycle 312 and the beginning of the second Chen search process 343, which is the first Chen search process that occupies the Chen search pipeline stage. Caused by 333. The temporary interruption in the processing of the second sub-block 122 is illustrated for the purpose of generally illustrating pipeline processing and should not be considered as limiting or necessarily representative of one of the processes within system 300.

The process of using the fourth sub-block 124 of the fourth ECC profile 128 begins during a fourth loop 313 with the fourth symptom code process 361. Also during the fourth loop 313, the third key generation 352 of the third sub-block 123 begins with the start of the third sub-block search processing 353 of the third sub-block 123 and the third sub-ECC data 127. Also during the fourth loop 313, the second sub-block 122 and the second Chen search processing 343 of the second sub-ECC data 126 are completed.

During a fifth cycle 314, a fourth key equation generation 362 of the fourth sub-word 124 is performed. In addition, the third sub-block 123 and the third sub-ECC search processing 353 of the third sub-ECC data 127 are completed and the fourth sub-block 124 and the fourth sub-ECC search processing 363 of the fourth sub-ECC data 128 start. Additionally, during the fifth cycle 314, the symptom code processing 324 of the primary ECC operation 304 is completed and the key equation generation 322 of the primary ECC begins. As illustrated, when the primary ECC operation 304 begins the critical equation generation 322, the sub-ECC processing of the first and second sub-blocks 121 and 122 is complete and the sub-ECC processing of the third and fourth sub-blocks 123 and 124 is get on.

During the sixth loop 315, the sub-ECC processing of the fourth sub-block 124 terminates and the primary ECC key equation generation 322 continues. Therefore, at the time of initiating the main ECC Chen search process 323, one or more regions may be analyzed during processing of the individual sub-blocks 121-124 and/or during the Chen search process 323. For example, when the sub-ECC processing of the first sub-block 121 and the second sub-block 122 is completed without an uncorrectable error, there is no need for the first and second sub-blocks during the main ECC operation 304. The data bits in 121 and 122 and in the first and second ECC blocks 125 and 126 are applied to the Chen search process 322.

If the sub-ECC operation 302 of the third sub-block 123 indicates an uncorrectable error and the fourth sub-block 124 indicates that the sub-ECC operation 302 can be modified by the sub-ECC operation 302, the Chen search processing 323 can be controlled to process only the third sub-block 123 and Third ECC block 127. The total processing time of one of the Chen search processes 323 used to perform the main ECC operation 304 can be reduced to a quarter or less, which can be proportional to the length of one of the ECC pages 120 in the conventional system and can be constructed A substantial part of the decoding process. As another example, when the sub-ECC operation 302 indicates that none of the sub-words 121-124 has an uncorrectable error, the Chen search process 323 of the primary ECC operation 304 may be limited to only one of the ECC data 129 searches or Can be skipped together.

Referring to Figures 4A-4B, a particular embodiment of a method 400 is illustrated. The method 400 begins on Figure 4A and continues to Figure 4B. Method 400 illustrates that one of the processing procedures can be performed based on the results of the sub-ECC processing, such as by control circuit 206 of FIG. Method 400 is illustrated with reference to the data flow diagram of FIG. 4A illustrates performing a Chen search for a sub-block indicated by a sub-ECC operation as having an uncorrectable error and determining whether all errors in the ECC word have been corrected. 4B illustrates the processing when an error remains uncorrected (eg, one or more of the sub-blocks are miscorrected during sub-ECC processing) and includes execution of sub-blocks indicated as having no uncorrectable errors. A Chen search.

At 402, an indication is received that the primary key generation process has completed. For example, the indication can be received after the key generation process 322 of FIG. At 404, a determination is made whether the first sub-block 121 results in an uncorrectable error. In response to the first sub-block 121 at 404 causing an uncorrectable error, a Chen search may be initiated in the main ECC operation 304, starting with one of the first sub-blocks 121 and continuing to the first sub- One of the ECC materials 125 ends.

At 408, a determination is made as to whether the second sub-block 122 results in an uncorrectable error. When the second sub-block 122 is determined to have not caused an uncorrectable error, the process continues to 412. Alternatively, when the second sub-block 122 is determined to have caused an uncorrectable error, the second sub-ECC data corresponding to the second sub-block 122 and the second sub-block 122 is executed in the main ECC at 410. One of the 126 primary ECC Chen searches, and processing continues to 412.

At 412, a determination is made as to whether the third sub-block 123 results in an uncorrectable error. When the third sub-block 123 is determined to have not caused an uncorrectable error, the process proceeds to 416. Alternatively, when the third sub-block 123 is determined to have caused an uncorrectable error, the main ECC Chen search processing corresponding to the third sub-block 123 and the third sub-ECC data 127 is performed at 414, and Processing continues to 416.

At 416, a determination is made whether the fourth sub-block 124 results in an uncorrectable error or whether the processing of the fourth sub-block 124 has not completed. When the fourth sub-block 124 results in an uncorrectable error at 416 or the Chen search processing of the fourth sub-block 124 has not been completed, the main ECC Chen search process may be performed in the order of one of the fourth sub-blocks 124. The first bit begins and continues to the end of the ECC page 120 (i.e., contains ECC data 129). Alternatively, when the fourth sub-block 124 is not indicated as having an uncorrectable error and the fourth Chen search process 363 has been completed, processing continues to 420, which is made in 420 (in sub-ECC operation 302 and in Whether the sum of one of the errors detected in any of the Chen search of 406, 410, and 414 is equal to one of the orders of one of the main key equations generated by the critical equation process 322 of the autonomous ECC operation 304.

In response to determining that the sum of the found errors is not equal to the order of the primary key equation of the primary ECC operation 304, the Chen search process is performed at 424 from the beginning of the ECC data 129 of the ECC page 120. Otherwise, processing continues to 426 where a determination is made whether one of the corrected ECC errors is equal to one of the orders of the key equations generated by the master key processing 322 of the primary ECC operation 304. When the number of modified ECC errors (including sub-ECC and main ECC corrections) is equal to the order of the key equations generated by the critical equation process 322, all detected errors based on the main ECC operation 304 have been detected and are sub- The ECC operation 302 and/or the target Chen search process performed at one or more of 406, 410, 414, 418, or a combination thereof, is modified. Thus, at 428, all detected errors have been corrected and the ECC processing of ECC page 120 is complete. When the number of corrected errors at 426 is determined to be not equal to an order of the primary key equation, processing continues to 430, illustrated in Figure 4B.

At 430, a determination is made whether the first sub-block 121 is determined by the sub-ECC operation 302 to have one of the uncorrectable errors. When the first sub-block is determined by the sub-ECC operation 302 to have no uncorrectable error, the Chen search process of the first sub-block 121 and the primary ECC operation 304 of the first sub-ECC data 125 is performed at 432. Continuing to 434, a determination is made at 434 as to whether the number of corrected errors is equal to one of the orders of the primary key equation. When the number of corrected errors made at 434 is equal to one of the orders of the primary key equation, all detected errors have been corrected at 436 and processing is complete. Otherwise, a determination is made at 438 as to whether the second sub-block 122 is determined by the sub-ECC operation 302 to have caused an uncorrectable error. When the second sub-block 122 is determined by the sub-ECC operation 302 to have not caused an uncorrectable error, the second sub-block 122 and the second sub-ECC data 126 may be subjected to the Chen search processing of the main ECC operation 304 at 440. . After the second Chen search process is completed at 440, or when the second sub-block 122 is determined by the sub-ECC operation 302 to have an uncorrectable error, whether the number of corrected errors is equal to one of the primary key equations at 442 One of the orders is determined.

If the number of corrected errors at 442 is determined to be equal to one of the main key equations, then all detected errors have been corrected at 444 and processing is complete. Otherwise, a determination is made at 446 as to whether the third sub-block 123 is determined by the sub-ECC operation 302 to be uncorrectable. If the third sub-block 123 is determined by the sub-ECC operation 302 to have no uncorrectable error, then the third sub-block 123 and the third sub-ECC data 127 perform the Chen search process of the main ECC operation 304. After the completion of the Chen search process at 448, or after determining at 446 that the third sub-block 123 is determined to have an uncorrectable error by the sub-ECC operation 302, whether the number of corrected errors is equal to the primary key equation at 450 One of the orders is determined.

When the number of corrected errors at 450 is determined to be equal to the order of the main equation, all detected errors have been corrected at 452 and processing is complete. Otherwise, a determination is made at 454 as to whether the fourth sub-block 124 is determined by the sub-ECC operation 302 to have an uncorrectable error. If the fourth sub-block 124 is determined by the sub-ECC operation 302 to have no uncorrectable error at 454, then the fourth sub-block 124 and the fourth sub-ECC data 128 are subjected to Chen search processing at 456.

At 458, a determination is made whether the total corrected error is equal to one of the orders of the primary key equation. If so, all detected errors have been corrected at 460 and processing ends. If the number of corrected errors at 458 is not equal to the order of the primary key equation, then the number of errors that have occurred exceeds the capacity of the primary ECC operation 304, an error is generated at 462 and processing terminates.

Figure 5 is a flow diagram of one of the embodiments of one of the methods of ECC processing assigned. The method can be performed in a controller of a memory device, such as controller 110 of FIG. The method includes receiving, at 502, data comprising a data block and a primary error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and a first ECC data corresponding to the first sub-block. The memory device can include a non-volatile memory and can perform the receiving of the data by reading data from the non-volatile memory and transmitting the read data to an ECC engine of the controller. For example, ECC page 120 can be received at ECC engine 114 of FIG. 1 as read material 116.

At 504, a data block ECC operation is initiated to process the data block using the primary ECC data. The data block ECC operation may include a main symptom code generation processing program, a main key equation generation processing program, and a main error position processing program. For example, the data block ECC operation may be the primary ECC operation 304 of FIG. The initiation of the data area can be performed by providing data to one of the data block ECC decoders (such as the data block ECC decoder 142 of FIG. 1) and instructing the data block ECC decoder to begin processing the data. Block ECC operation.

At 506, a sub-block ECC operation is initiated to process the first sub-block using the first ECC profile. The data block ECC operation and the sub-block ECC operation can be initiated substantially simultaneously. The sub-block ECC operation may include a sub-block symptom code generation processing program, a sub-block key equation generation processing program, and a sub-block error position processing program for each sub-block in the data block. The data block can include a second sub-block and a second ECC data corresponding to the second sub-block. The sub-block ECC operation may further process the second sub-block using the second ECC data. Sub-block ECC operations may be pipelined and the processing of the second sub-block may at least partially overlap with the processing of the first sub-block. For example, sub-block ECC operations may be associated with sub-ECC operation 302 of FIG. The initiation of the sub-block may be performed by providing data to one of the sub-block ECC decoders (such as sub-block ECC decoder 140 of FIG. 1) and instructing the sub-block ECC decoder to begin processing the data. ECC operation.

At 508, one of the error locations of the data block ECC operation is selectively initiated based on the result of one of the sub-block ECC operations. For example, in response to a sub-block ECC operation indicating an uncorrectable error in the first sub-block, the error location search can be initiated to begin at one of the first sub-blocks. The error location search may include a Chen search, such as the Chen search process 323 of FIG.

To illustrate, sub-block ECC can be performed by receiving a start location data indicating that a bit position (such as the Chen search start position 260 of FIG. 2) cannot be corrected by one of the sub-blocks of the sub-block ECC operation. The result of the operation selectively initiates an error location search for the data block ECC operation. End position data indicating an end bit position (such as the Chen search end position 262 of FIG. 2) indicating one of the ECC data of the sub-block that cannot be corrected by the sub-block ECC operation may also be received. The error location search can be initiated to process the data sequentially from the start bit position to the end bit position.

The data block ECC operation can determine the first number of errors in the data. The first number of errors is determined by a data block ECC operation, such as based on an order corresponding to one of the key equations of the data block. For example, at decision 420 of FIG. 4A, the first number of errors can be compared to one of the second errors corrected by the sub-block ECC operation.

When the data block contains a plurality of sub-blocks, the error location search can be controlled to process each of the plurality of sub-blocks identified as having uncorrectable errors during the sub-block ECC operation. For example, a Chen search can be selectively performed in response to decisions 404, 408, 412, and 416 of FIG. 4A. After completing an error location search for one of the plurality of sub-blocks identified as having an uncorrectable error, the number of corrected errors can be compared to the first number of errors in the material. In response to the first number of errors exceeding the number of corrected errors, the error location search can be controlled to process the primary ECC data, as illustrated at 420-424 of Figure 4A.

The number of corrected errors can be updated when one or more errors are corrected in the primary ECC profile. When the first number of errors exceeds the number of corrected errors, the error location search may be controlled to process at least one of the plurality of sub-blocks that were not identified as having uncorrectable errors during sub-block ECC operation, Such as responding to decisions 430, 438, 446 and 454 of FIG.

Although the ECC system assigned in FIG. 1 is implemented in a data storage device, in other embodiments the distributed ECC system can be implemented in other systems, such as a communication system. For example, the ECC engine 114 of FIG. 1 can be implemented in a wireless receiver to correct errors that occur during transmission of an encoded signal.

Although ECC page 120 is illustrated as having four sub-blocks 121-124, in other embodiments ECC page 120 may have four sub-blocks or more than four sub-blocks. The sub-blocks may be the same size or may have different sizes within the ECC page 120. Additionally, although the sub-block operations 302 and FIG. 4 of FIG. 3 are illustrated as sequentially processing the sub-blocks 121-124, in other embodiments the sub-block processing may be performed in a non-sequential order or may be skipped. One or more sub-blocks. For example, the average ECC decoding delay can be reduced by simultaneously processing a single sub-block with the primary block and controlling one of the primary blocks based on processing one of the sub-blocks.

Although the various components illustrated herein are illustrated as block components and are generally set forth, such components can include one or more microprocessors, state machines, or configured to cause data storage device 102 of FIG. Other circuits capable of performing specific functions belonging to such components. For example, sub-block ECC decoder 140 and data block ECC decoder 142 of FIG. 1 may represent physical components, such as hardware controllers, state machines, logic circuits, or enable ECC engine 114 of FIG. 1 to use sub-blocks. One of the ECC decoders 140 results in performing the assigned ECC processing to adjust the other structure of the processing at the data block ECC decoder 142.

Sub-block ECC decoder 140 and data block ECC decoder 142 of FIG. 1 may be implemented as dedicated hardware (ie, circuitry) to achieve reduced latency. Alternatively, the sub-block ECC of FIG. 1 may be implemented using a microprocessor or microcontroller that is programmed to perform ECC decoding, such as symptom code generation, critical equation generation, or error location search, in one or more stages. One or both of decoder 140 and data block ECC decoder 142. In a particular embodiment, one or both of the sub-block ECC decoder 140 and the data block ECC decoder 142 include executable instructions executed by a processor and the instructions are stored in the memory 112. . Alternatively or additionally, executable instructions executed by one of the processors that may be included in controller 110 may be stored at a separate memory location of one of the portions of non-system memory 112, such as a read-only memory (ROM) ) (not shown).

In a particular embodiment, data storage device 102 can be configured to be selectively coupled to one of the one or more external devices. However, in other embodiments, the data storage device 102 can be attached or embedded within one or more host devices, such as within a housing of a portable communication device. For example, data storage device 102 can be within a packaged device, such as a wireless telephone, a PDA, a gaming device or console, a portable navigation device, or other device that uses internal non-volatile memory. In a particular embodiment, data storage device 102 includes a non-volatile memory such as a flash memory (eg, NAND, NOR, multi-level cell (MLC), split bit line NOR (DINOR), AND High capacitance coupling ratio (HiCR), asymmetric contactless transistor (ACT) or other flash memory), erasable programmable read only memory (EPROM), and an erasable programmable program Read-only memory (EEPROM), a read-only memory (ROM), a single-time programmable memory (OTP), or any other type of memory.

The description of the embodiments set forth herein is intended to provide a general understanding of the various embodiments. Other embodiments may be utilized and derived from the present invention so that structural and logical substitutions and changes can be made without departing from the scope of the invention. The invention is intended to cover any and all subsequent modifications or variations of the various embodiments. Accordingly, the invention is to be considered as illustrative and not limiting.

The above-identified subject matter is to be considered as illustrative and not restrictive, and the scope of the invention is intended to cover all such modifications, improvements and other embodiments falling within the scope of the invention. Therefore, to the extent permitted by law, the scope of the invention is determined by the broadest interpretation of the scope of the following claims and their equivalents, and should not be limited or limited by the foregoing embodiments.

100. . . system

102. . . Data storage device

104. . . Host device

110. . . Controller

112. . . Memory

114. . . Error correction coding engine

116. . . Reading data

120. . . Error correction code page

121. . . First subblock/subword

122. . . Second subblock/subword

123. . . Third subblock/subword

124. . . Fourth subblock/subword

125. . . First sub-error correction code data

126. . . Second sub-correction coding data

127. . . Third sub-correction coding data

128. . . Fourth sub-correction coding data

129. . . Co-located block/error correction coding data

130. . . Data block

140. . . Subblock error correction codec

142. . . Data block error correction codec

200. . . system

202. . . Main error correction coding processing circuit

204. . . Sub-error correction coding processing circuit

206. . . Control circuit

240. . . Corrected data

250. . . result

252. . . Indication

254. . . Number of errors

260. . . Chen's search start position

262. . . Chen's search end position

300. . . Assigned error correction coding system

302. . . Sub-error correction encoding operation

304. . . Master error correction encoding operation

310. . . First cycle

311. . . Second cycle

312. . . Third cycle

313. . . Fourth cycle

314. . . Fifth cycle

315. . . Sixth cycle

321. . . Symptom code generation

322. . . Key equation generation

323. . . Chen search processing

331. . . First symptom code processing

332. . . First key equation generation

333. . . First Chen search processing

341. . . Second symptom code processing

342. . . Second key equation generation

343. . . Second Chen search processing

351. . . Third symptom code processing

352. . . Third key generation

353. . . Third Chen search processing

361. . . Fourth symptom code processing

362. . . Fourth key equation generation

363. . . Fourth Chen search processing

1 is a block diagram of a particular illustrative embodiment of a system including a data storage device having one of an ECC engine having assigned error correction coding (ECC) processing;

2 is a block diagram of one particular illustrative embodiment of one of the systems for performing an assigned ECC process;

3 is a data flow diagram of one of the specific illustrative embodiments of one of the pipelined ECC processes;

4A-4B are flow diagrams of a particular illustrative embodiment of a method for controlling a Chen search during data block processing based on the results of sub-block processing in an allocated ECC processing system; And

Figure 5 is a flow diagram of one of the specific illustrative embodiments of one of the methods of ECC processing assigned.

100. . . system

102. . . Data storage device

104. . . Host device

110. . . Controller

112. . . Memory

114. . . Error correction coding engine

116. . . Reading data

120. . . Error correction code page

121. . . First subblock/subword

122. . . Second subblock/subword

123. . . Third subblock/subword

124. . . Fourth subblock/subword

125. . . First sub-error correction code data

126. . . Second sub-correction coding data

127. . . Third sub-correction coding data

128. . . Fourth sub-correction coding data

129. . . Co-located block/error correction coding data

130. . . Data block

140. . . Subblock error correction codec

142. . . Data block error correction codec

Claims (24)

A method comprising: receiving, in a controller of a memory device, data comprising a data block and a main error correction coding (ECC) data of the data block, the data block comprising one of the first data a sub-block and a first ECC data corresponding to the first sub-block; starting a data block ECC operation to process the data block using the main ECC data; starting a sub-block ECC operation to use the First ECC data to process the first sub-block; and selectively initiating an error location search for the data block ECC operation based on one of the sub-block ECC operations. The method of claim 1, wherein in response to the sub-block ECC operation indicating an uncorrectable error in the first sub-block, the error location search is initiated to begin at one of the beginning of the first sub-block. The method of claim 1, wherein the error location search comprises a Chen search. The method of claim 1, wherein the data block includes a second sub-block and a second ECC data corresponding to the second sub-block, and wherein the sub-block ECC operation further uses the second ECC data Processing the second sub-block. The method of claim 4, wherein the sub-block ECC operation is pipelined and wherein processing of the second sub-block at least partially overlaps processing of the first sub-block. The method of claim 1, wherein the data block ECC operation determines a first number of errors in the data, and further comprising: correcting the first number of errors with an error corrected by the sub-block ECC operation A second number is compared. The method of claim 1, wherein the data block comprises a plurality of sub-blocks, and further comprising: controlling the error location search to process the plurality of sub-regions identified as having uncorrectable errors during the sub-block ECC operation Each of the blocks. The method of claim 7, further comprising, after completing the search for the error location of each of the plurality of sub-blocks identified as having an uncorrectable error: a number of the corrected errors and an error in the material Comparing a first number, wherein the first number of errors is determined by the data block ECC operation; and controlling the error location search to process the primary in response to the first number of errors exceeding the number of corrected errors ECC information. The method of claim 8, wherein the first number of errors is based on an order corresponding to one of the key equations of the data block. The method of claim 8, further comprising: updating the number of corrected errors when one or more errors are corrected in the primary ECC profile; and when the first number of errors exceeds the number of corrected errors, The error location search is controlled to process at least one of the plurality of sub-blocks that were not identified as having an uncorrectable error during the sub-block ECC operation. The method of claim 1, wherein the memory device further comprises a non-volatile memory, and wherein receiving the data is performed by: reading the data from the non-volatile memory; and reading the data The data is sent to one of the ECC engines of the controller. The method of claim 1, wherein: the initiating the data block ECC operation is performed by: providing the data to an input of a data block ECC decoder; and indicating the data block ECC decoder Initiating processing of the data; and performing the initiating the sub-block ECC operation by: providing the data to an input of a sub-block ECC decoder; and instructing the sub-block ECC decoder to begin processing data. The method of claim 12, wherein the data block ECC operation and the sub-block ECC operation are initiated substantially simultaneously. The method of claim 1, wherein the error location search for selectively starting the data block ECC operation based on the result of the sub-block ECC operation is performed by: receiving an indication that the sub-block is not available The ECC operation corrects the start position data of the start bit position of one of the sub-blocks; and receives the end position data of the end bit position corresponding to one of the ECC data of the sub-block that cannot be corrected by the sub-block ECC operation. And starting the error location search to sequentially process the data from the start bit position to the end bit position. The method of claim 1, wherein the data block ECC operation comprises a main symptom code generation processing program, a main key equation generation processing program, and a main error position processing program, and wherein the sub-block ECC operation includes a sub-region The block symptom code generation processing program, a sub-block key equation generation processing program, and one sub-block error position processing program of each sub-block in the data block. A data storage device comprising: a memory; and a controller coupled to the memory, wherein the controller includes an error correction coding (ECC) engine, the error correction coding (ECC) engine comprising: a data a block ECC decoder configured to process data retrieved from the memory, the data comprising a data block and a primary error correction coding (ECC) data of the data block; and a sub-block ECC decoding And configured to process sub-blocks of the data block and ECC data corresponding to the sub-blocks, wherein the ECC engine is configured to initiate the data block ECC decoder substantially simultaneously and Processing of the data at the sub-block ECC decoder. The data storage device of claim 16, wherein the ECC engine is configured to selectively initiate an error location search at the data block ECC decoder based on a result of one of the sub-block ECC decoders. The data storage device of claim 17, wherein the ECC engine further comprises a control circuit responsive to the sub-block ECC decoder and configured to select the error location search at the data block ECC decoder A start position is to search for errors in the sub-blocks identified by the sub-block ECC decoder as uncorrectable. The data storage device of claim 16, wherein the memory system is a flash memory. The data storage device of claim 19, wherein the data storage device is one of: a flash memory card; a universal serial bus (USB) flash drive; and a solid state disk drive (SSD); and an embedded flash memory. A data storage device comprising: a flash memory; and a controller coupled to the flash memory, wherein the controller includes an error correction coding (ECC) engine, the error correction coding (ECC) engine The method includes: a data block ECC decoder configured to process data retrieved from the flash memory, the data comprising a data block and a main error correction coding (ECC) data of the data block; a sub-block ECC decoder configured to process sub-blocks of the data block and ECC data corresponding to the sub-blocks; and control circuitry responsive to the sub-block ECC decoder and configured The error location is searched for by one of the error locations at the ECC decoder of the data block to search for an error in the sub-block identified by the sub-block ECC decoder as uncorrectable. The data storage device of claim 21, wherein the ECC engine is configured to initiate processing of the data at the data block ECC decoder and the sub-block ECC decoder substantially simultaneously. The data storage device of claim 21, wherein the data storage device is configured to be replaceably coupled to a host device. The data storage device of claim 21, wherein the data storage device is configured to be coupled to a host device as an embedded memory.