KR101367351B1 - System and method of distributive ecc processing - Google Patents

Abstract

Systems and methods for performing distributed ECC operations are disclosed. The method according to the invention comprises receiving, at a controller of a memory device, data comprising a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and first ECC data corresponding to the first sub-block. The method includes initiating a data block ECC operation to process the data block using the main ECC data and initiating a sub-block ECC operation to process the first sub-block using the first ECC data. Steps. The method also includes selectively initiating an error location search of the data block ECC operation based on a result of the sub-block ECC operation.

Description

Distributed ECC Processing System and Method {SYSTEM AND METHOD OF DISTRIBUTIVE ECC PROCESSING}

In general, the present invention relates to error correction coding (ECC) processing.

During the process of writing data to memory, the data is often encoded into extra bits (parity bits) to form a codeword. Some of the bits representing the codeword may change due to the presence of noise, and errors may corrupt the original codeword. When a codeword is read from memory, a decoder can be used to identify and correct errors using error correction coding (ECC). For example, in applications where bit errors tend to be uncorrelated, Bose-Chaudhuri-Hocquenghem (BCH) ECC schemes are used. The error correction capability of the ECC scheme tends to increase as the length of the codeword increases. As a result, ECC schemes implemented in data storage systems and communication devices tend to use longer codewords.

BCH decoding may be performed in multiple successive stages to correct errors in the received data. For example, the BCH decoder may generate syndrome components for the received codeword that may include errors. The BCH decoder can generate a key equation, such as, for example, an error location polynomial, which can be generated based on the calculated syndromes and can detect a number of detected in the received codeword. It may indicate errors. The locations of the detected errors within the received codeword can be determined based on the roots of the key equation, for example through an iterative process such as a chien search or the like. In general, since the Chien search process is performed sequentially for each value of the received codeword, the amount of time it takes to process the codeword may be proportional to the length of the codeword. As the length of the codeword increases, the delays caused by the Chien search process may limit the rate of ECC data correction.

Distributed ECC processing includes simultaneous processing of a data block and one or more sub-blocks of the data block. If it is determined that the sub-block has no errors or it is determined that there are errors that can be corrected during sub-block processing, one or more portions of the data block processing may be skipped. For example, a Chien search performed during data block processing may skip sub-blocks that were corrected during sub-block processing. As a result, compared to performing a full Chien search for all received codewords, the average time for processing ECC codewords can be reduced.

1 is a block diagram of one exemplary embodiment of a system including a data storage device having an error correction coding (ECC) engine with distributed ECC processing.
2 is a block diagram of one exemplary embodiment of a system that performs distributed ECC processing.
3 is a data flow diagram for one exemplary embodiment of pipelined distributed ECC processing.
4A-4B are flowcharts of one exemplary embodiment of a method of controlling Chien search during data block processing based on the results of sub-block processing in a distributed ECC processing system.
5 is a flowchart of one exemplary embodiment of a distributed ECC processing method.

Systems and methods are disclosed that use linear error location searches such as Chien searches and the like during ECC decoding and reduce the delay even when errors occur at the end of the data block. The approximate location of one or more errors can be determined and an error location search can be started from the determined location. The approximate error location can be determined by dividing the data block into sub-blocks and performing distributed ECC processing for each sub-block. Errors in sub-blocks may be found using an ECC smaller than the ECC used for the main block. Sub-blocks with fewer errors can be corrected during sub-block processing, which can reduce the number of cycles for performing main block error location search and thus reduce delay.

Referring to FIG. 1, a particular embodiment of a system 100 for performing distributed error correction coding (ECC) processing is shown. System 100 includes a data storage device 102 having an ECC engine 114, which is configured to perform distributed ECC processing. The system 100 also includes a host device 104 operatively connected to the data storage device 102.

In one embodiment, host device 104 is configured to communicate with data storage device 102 and is configured to send requests for data stored at data storage device 102. In addition, the host device 104 is configured to receive data provided by the data storage device 102 in response to the requests. For example, the host device 104 may be a mobile phone, music or video player, game console, e-book reader, personal digital assistant (PDA), laptop computer or notebook computer, or any other. Other electronic devices or any combination thereof.

The data storage device 102 includes a controller 110 and a memory 112. The controller 110 is configured to manage the memory 112 and enables communication with the host device 104 when the data storage device 102 is operably connected to the host device 104. The controller 110 includes an ECC engine 114 and can be configured to receive data read from the memory 112 and provide the received data to the ECC engine 114. The controller 110 may be configured to retrieve data output by the ECC engine 114, such as decoded data, for example, where corrections to one or more errors that occurred during storage or transmission have been performed, and And may provide the decoded correction data to the host device 104.

The memory 112 stores information such as data (eg, user data) and ECC data (eg, redundant data or "parity") associated with the data. For example, the data may include data of a multimedia file stored in memory 112, and the parity may include redundant information that enables the ECC engine 114 to detect and correct errors in the data. Can be. The data and corresponding ECC data may be stored together as data words. The memory 112 may be a nonvolatile memory. For example, the memory 112 may be a flash memory such as a NAND flash memory. As an example, the data storage device 102 may be a Secure Digital SD® card, a microSD® card, a MiniSD ™ card (Delaware, Wellington, SD-3C LLC). Trademark), Multimedia Card ™ card (MMC ™ card) (trademark of JEDEC Solid State Technology Association, Arlington, VA), or CompactFlash® card (Sandisk, Milpitas, Calif.) Memory card). As another example, the data storage device 102 is configured to be coupled to the host device 104 as an illustrative example, such as eMMC® (trademark of the JEDEC Solid State Technology Association of Arlington, Virginia) and eSD, or the like. May be

Representative ECC pages 120 are stored in memory 112. The ECC page 120 includes a first sub-block (SB1) 121, a second sub-block (SB2) 122, a third sub-block (SB3) 123, and a fourth sub-block (SB4). It includes a data block 130 that includes 124. Data block 130 may also include, for example, first sub-ECC data 125, second sub-ECC data 126, third sub-ECC data 127, and fourth sub-ECC data 128. ECC data associated with each sub-blocks 121-124, such as; In addition to the data block 130 with the combined sub-blocks 121-124 and the combined sub-ECC data 125-128, the ECC page 120 also includes ECC data corresponding to the data block 130. The parity block 129 further stores.

The ECC engine 114 is configured to perform an ECC decoding operation on data received through distributed ECC processing. For example, the ECC engine 114 may perform decoding according to the BCH scheme, the Reed-Solomon scheme, or any other scheme for serially searching for error locations by using, for example, Chien search. have. The ECC engine 114 receives the data read from the memory (eg, ECC page 120) and processes the read data 116 according to parallel processing paths. The first processing path includes a data block ECC decoder 142 that performs decoding on the entire ECC codeword, such as the entire ECC page 120 including the data block 130 and the ECC data 129, for example. do. The second processing path in parallel is one or more sub-blocks of data (eg, sub-blocks 121-124) using ECC data (eg, sub-ECC data 125-128) corresponding to the sub-blocks. A sub-block ECC decoder 140 that performs ECC processing for. The ECC engine 114 may start the data block ECC operation at the data block ECC decoder 142 and the sub-block ECC operation at the sub-block ECC decoder 140 at substantially the same time.

During operation, in response to errors detected in one or more sub-blocks 121-124, which may be corrected in sub-block ECC decoder 140 using sub-ECC data 125-128, the data The amount of ECC processing for data block 130 in block ECC decoder 142 may be reduced. For example, it may be determined that three of the four sub-blocks (eg, sub-blocks 121-123) may be corrected through sub-block ECC processing at the sub-block ECC decoder 140. have. As a result, error location retrieval at data block ECC decoder 142 may optionally be initiated to bypass correctable sub-blocks 121-123 and corrected by sub-block ECC processing. It may be limited to locating errors in sub-block 124 that have been determined to be uncorrectable. Examples of sub-block and data block processing are described in more detail below with reference to FIGS.

Each sub-blocks 121-124 may be processed faster than the ECC page 120, but due to fewer ECC bits in the sub-ECC data 125-128, a reduced error correction rate ( And perhaps more mis-correction). By using distributed ECC processing, the ECC engine 114 provides ECC decoding with strengths related to the overall parity for the ECC page, and also corrects one or more sub-blocks in parallel with correcting the ECC page. If possible, it can enable faster operation.

2, a particular embodiment of a system for performing distributed ECC processing is shown and denoted with 200. System 200 includes a main ECC processing circuit 202 and a sub-ECC processing circuit 204. For example, the main ECC processing circuit 202 may correspond to the data block ECC decoder 142 of FIG. 1 and the sub-ECC processing circuit 204 may correspond to the sub-block ECC decoder 140 of FIG. 1. have. The output of the sub-ECC processing circuit 204 is provided to the control circuit 206. The control circuit 206 has an output connected to the main ECC processing circuit 202. System 200 is configured to receive a data word illustrated by ECC page 120.

An ECC page 120 is provided through parallel processing paths for processing in the main ECC processing circuit 202 and the sub-ECC processing circuit 204. The main ECC processing circuit 202 may perform ECC processing for the entire ECC page 120. For example, the main ECC processing circuit 202 may generate syndromes, determine a key equation with an order representing a number of errors in the ECC page 120, and perform a Chien search, for example, by performing a Chien search. Find the location of errors. The resulting data with errors corrected is provided as corrected data 240.

The sub-ECC processing circuit 204 can be configured to perform ECC processing for the first sub-block 121 using the first sub-ECC data 125. The sub-ECC processing circuit 204 can determine syndromes, generate a key equation, and perform Chien search for the first sub-block 121 using the first sub-ECC data 125. . In addition, the sub-ECC processing circuit 204 processes the second sub-block 122 using the second sub-ECC data 126, and uses the third sub-ECC data 127 to generate the third sub-ECC data 127. Process the block 123, and process the fourth sub-block 124 using the fourth sub-ECC data 128. For example, the sub-ECC processing circuit 204 can be configured to process one or more stages of ECC processing in a pipelined manner as described with respect to FIG. 3. As another example, the sub-ECC processing circuit 204 can include a plurality of parallel ECC processing circuits to process the two or more sub-blocks 121-124 in parallel with each other.

The results 250 of the sub-ECC processing are provided to the control circuit 206. These results indicate which of the multiple errors 254, sub-blocks 121-124, detected during sub-ECC processing of each of the sub-blocks 121-124 were uncorrectable (ie, sub-ECC). One or more indications 252, other information, or any combination thereof, indicating that there are more errors than can be corrected using data 125-128. The control circuit 206 may, for example, maintain the Chien search start position 260 in order to more efficiently continue the processing of the main ECC processing circuit 202 based on the results returned from the sub-ECC processing circuit 204. May be configured to determine one or more parameters, such as Chien search end location 262, and the like.

For example, various components of ECC processing may require different amounts of time. By way of example, syndrome calculation may be performed at a fixed time interval, while generation of key equations may require an amount of time proportional to the number of errors in the ECC page and perform a Chien search. Doing so may require an amount of time proportional to the number of errors and the location of the errors in the ECC page. The results of the sub-ECC processing circuit 204 indicating whether errors were corrected or whether errors in each of the sub-blocks 121-124 were uncorrectable indicate that the main ECC processing circuit 202 is one or more aspects of main ECC processing. It may be possible to bypass the performance of aspects. By way of example, the sub-ECC processing circuit 204 may correct all errors detected in the first three sub-blocks 121-123, but the errors occurring in the fourth sub-block 124 are uncorrectable. (uncorrectable), the control circuit 206 may optionally initiate Chien search processing at the beginning of the fourth sub-block 124 (ie, at the first bit following the third ECC data 127). It may be configured to direct the main ECC processing circuit 202. In this way, the total number of Chien search processing cycles in the main ECC processing circuit 202 can be substantially reduced because of parallel ECC processing for the first three sub-blocks 121-123.

Referring to FIG. 3, there is shown a data flow diagram illustrating an example of ECC processing in a distributed ECC system such as, for example, the ECC engine 114 of FIG. 1 or the system 200 of FIG. It is named 300. The data flow is shown according to representative timing of ECC processing for the ECC page 120 of FIG. 1 and includes the data flow in the sub-ECC operation 302 and the data flow in the main-ECC operation 304. do. Sub-ECC operation 302 may correspond to processing at sub-block ECC decoder 140 of FIG. 1 or processing at sub-ECC processing circuit 204 of FIG. 2. Main-ECC operation 304 may correspond to processing in data block ECC decoder 142 of FIG. 1 or processing in main-ECC processing circuit 202 of FIG. 2.

As illustrated, the sub-ECC operation 302 may comprise a first cycle 310, a second cycle 311, a third cycle 312, a fourth cycle 313, a fifth cycle 314, and a first cycle. It can be pipelined for multiple pipeline cycles, such as six cycles 315. Each of the cycles 310-315 is illustrated as generally corresponding to each portion of the ECC page 120 and also corresponds to the processing time of each pipeline stage related to the sub-ECC processing.

The sub-ECC operation 302 includes a first pipeline stage for calculating syndromes for the received sub-block, a second pipeline stage for generating a key equation for each sub-block based on the calculated syndromes, And a third pipeline stage for performing Chien search for locating and correcting errors in the sub-block. The next sub-block enters the first pipeline stage sequentially in each cycle and three or more sub-blocks can be processed simultaneously with one sub-block in each pipeline stage, and each sub-block's The pipeline stages can be configured such that the processing at least partially overlaps with the processing of one or more other sub-blocks.

By way of example, the first cycle 310 includes processing for the first sub-block 121 using the first ECC data 125, as illustrated by the first syndrome processing 331, wherein The syndrome calculation for the first sub-block 121 is performed using the first sub-ECC data 125 during one syndrome processing 331. In addition, syndrome calculation 321 for the main ECC operation 304 is initiated during the first cycle.

The second cycle 311 includes processing for the second sub-block 122 following the first cycle 310 and using the second ECC data 126 entering the pipeline, and the second syndrome processing Beginning with 341. In addition, during the second cycle 311, a first key equation generation 332 for the first sub-block 121 is performed. Subsequent to first key equation generation 332 for the first sub-block 121, first Chien search processing 333 for the first sub-block 121 and the first sub-ECC data 125. This is initiated during the second cycle 311 and continues to the third cycle 312.

During the third cycle 312, processing of the third sub-block 123 using the third ECC data 127 begins with a third syndrome processing 351 for the third sub-block 123. In addition, the first Chien search processing 333 for the first sub-block 121 and the first sub-ECC data 125 is completed, and a second key equation for the second sub-block 122 is generated. 342 is performed. Further, as illustrated, if the first Chien search processing 333 for the first sub-block 121 and the first sub-ECC data 125 ends during the third cycle 312, the second sub Second Chien search processing 343 for block 122 and second sub-ECC data 126 begins. During the third cycle 312, the elapsed time is illustrated between the end of the second key equation generation process 342 and the start of the second Chien search processing 343, which occupies the Chien search pipeline stage and From the first Chien search processing 333. A temporary interruption to the processing of the second sub-block 122 is shown to generally illustrate pipelined processing, and such interruption should not be considered limiting or necessarily representative of processing within the system 300. .

During the fourth cycle 313, processing of the fourth sub-block 124 using the fourth ECC data 128 begins with a fourth syndrome processing 361. In addition, during the fourth cycle 313, third key equation generation 352 for the third sub-block 123 is initiated, followed by the third sub-block 123 and the third sub-ECC data. Third Chien search processing 353 for 127 begins. In addition, during the fourth cycle 313, the second Chien search processing 343 is completed for the second sub-block 122 and the second sub-ECC data 126.

During the fifth cycle 314, fourth key equation generation 362 for the fourth sub-word 124 is performed. In addition, the third Chien search processing 353 for the third sub-block 123 and the third sub-ECC data 127 is completed, and the fourth sub-block 124 and the fourth sub-ECC data ( The fourth Chien search processing 363 for 128 begins. In addition, during the fifth cycle 314, syndrome processing 321 of the main ECC operation 304 is completed and key equation generation 322 of the main ECC operation 304 begins. As illustrated, when the main ECC operation 304 initiates key equation generation 322, the sub-ECC processing for the first and second sub-blocks 121, 122 has been completed and the third and Sub-ECC processing for the fourth sub-blocks 123, 124 is in progress.

During the sixth cycle 315, the sub-ECC processing for the fourth sub-block 124 ends while the main ECC key generation 322 continues. As a result, once main Chien search processing 323 is initiated, one or more areas to be analyzed during search start location and / or Chien search processing 323, as a result of the processing of the individual sub-blocks 121-124, Can be known. For example, when the sub-ECC processing for the first sub-block 121 and the second sub-block 122 is completed without uncorrectable errors occurring, the first and second For the data bits within the sub-blocks 121 and 122 and the first and second ECC-blocks 125 and 126, the Chien search processing 322 need not be applied during the main ECC operation 304.

If the sub-ECC operation 302 of the third sub-block 123 represents uncorrectable errors while the fourth sub-block 124 is marked as correctable by the sub-ECC operation 302, Chien search processing 322 may be controlled to process only the third sub-block 123 and the third ECC block 127.

Total processing time for performing Chien search processing 322 for the main ECC operation 304 (in conventional systems may be proportional to the length of the ECC page 120 and constitutes a substantial proportion of the decoding process). May be reduced by more than four times. As another example, if the sub-ECC operation 302 indicates that none of the sub-words 121-124 have uncorrectable errors, the Chien search processing 323 of the main ECC operation 304 The search may be limited to the search of the ECC data 129 or may be skipped altogether.

4A-4B, a particular embodiment of a method 400 is shown, which begins with FIG. 4A and proceeds to FIG. 4B. The method 400 illustrates a process that may be performed by, for example, the control circuit 206 of FIG. 2 based on the result of the sub-ECC processing. The method 400 is described with reference to the data flow diagram in FIG. 4A shows performing a Chien search on sub-blocks indicated by sub-ECC operation as having uncorrectable errors and determining whether all errors in the ECC word have been corrected. 4B shows the processing of where errors remain uncorrected (ie, one or more sub-blocks were miscorrected during sub-ECC processing) and sub-blocks indicated as having no uncorrectable errors. Involves performing a Chien search for.

An indication is received at step 402 that the main key generation processing is complete. For example, this indication may be received subsequent to key generation processing 322 of FIG. 3. In step 404, it is determined whether the first sub-block 121 causes an uncorrectable error. In response to the first sub-block 121 causing an uncorrectable error in step 404, beginning at the beginning of the first sub-block 121 and continuing to the end of the first sub-ECC data 125. Chien search may be initiated in the main ECC operation.

In step 408, it is determined whether the second sub-block 122 causes an uncorrectable error. If it is determined that the second sub-block 122 does not cause an uncorrectable error, processing proceeds to step 412. Otherwise, if it is determined that the second sub-block 122 causes an uncorrectable error, then the second ECC data 126 for the second sub-block 122 and the second sub-block 122 are added to the second sub-block 122. The corresponding main ECC Chien search is performed in the main ECC (step 410) and processing proceeds to step 412.

In step 412, it is determined whether the third sub-block 123 causes an uncorrectable error. If it is determined that the third sub-block 123 does not cause an uncorrectable error, processing proceeds to step 416. Otherwise, if it is determined that the third sub-block 123 causes an uncorrectable error, the third ECC data 127 for the third sub-block 123 and the third sub-block 123 is not included. The corresponding main ECC Chien search is performed (step 414) and processing proceeds to step 416.

It is determined at step 416 whether the fourth sub-block 124 causes uncorrectable errors or whether processing for the fourth sub-block 124 has not been completed. If in step 416 the fourth sub-block 124 causes uncorrectable errors or the Chien search processing for the fourth sub-block 124 has not been completed, then the main ECC Chien search processing may be performed. ECC Chien search processing begins consecutively with the first bit of the fourth sub-block 124 and continues to the end of the ECC page 120 (ie, includes ECC data 129). Alternatively, if the fourth sub-block 124 is not marked as having uncorrectable errors or the fourth Chien search processing is completed, processing proceeds to step 420, where the errors (sub-ECC operation 302 and And determining whether the sum of the Chien searches 406, 410, 414 is equal to the order of the main key equation derived from the key equation processing 322 of the main ECC operation 304. do.

In response to determining that the sum of the errors found is not equal to the order of the main key equation of the main ECC operation 304, the Chien search processing is performed from the beginning of the ECC data 129 of the ECC page 120. (Step 424). Otherwise, processing proceeds to step 426 where it is determined whether the number of corrected ECC errors is equal to the order of the key equation generated by the main key processing 322 of the main ECC operation 304. . If the number of corrected ECC errors (including sub-ECC and main ECC corrections) is equal to the order of the key equation derived from key equation processing 322, then all detected errors are based on main ECC operation 304. And corrected by the targeted Chien search processing performed by sub-ECC operation 302 and / or in one or more of steps 406, 410, 414, 418, or a combination thereof. As a result, all detected errors have been corrected, and ECC processing for the ECC page 120 is completed at step 428. If it is determined in step 426 that the number of corrected errors is not equal to the order of the main key equation, processing proceeds to step 430, where step 430 is shown in FIG. 4B.

It is determined whether the sub-ECC operation 302 has determined that the first sub-block 121 has uncorrectable errors. If the sub-ECC operation 302 determines that the first sub-block 121 has no uncorrectable errors, the Chien search processing of the main ECC operation 304 is performed by the first sub-block 121 and the first sub. Is performed on the ECC data 125 (step 432). Subsequently at step 434, it is determined whether the number of corrected errors is equal to the order of the main key equation. If it is determined in step 434 that the number of corrected errors is equal to the order of the main key equation, all detected errors have been corrected and processing is completed in step 436. If not, it is determined whether sub-ECC operation 302 has determined that second sub-block 122 causes uncorrectable errors (step 438). If the sub-ECC operation 302 determines that the second sub-block 122 has no uncorrectable errors, the Chien search processing of the main ECC operation 304 is performed by the second sub-block 122 and the second. 2 is performed on the sub-ECC data 126 (step 440). After the second Chien search processing is completed in step 440, or if the sub-ECC operation 302 determines that the second sub-block 122 has uncorrectable errors, the number of corrected errors is the main key equation. It is determined in step 442 whether it is equivalent to the order of.

If at step 442 it is determined that the number of corrected errors is equal to the order of the main key equation, all detected errors have been corrected and processing is completed at step 444. If not, it is determined whether the third sub-block 123 has been determined by sub-ECC operation 302 as not correctable (step 446). If the sub-ECC operation 302 determines that the third sub-block 123 has no uncorrectable errors, the Chien search processing of the main ECC operation 304 is performed by the third sub-block 123 and the third. 3 sub-ECC data 127 is performed (step 448). After the Chien search processing is completed in step 448 or after step 446 determines that the third sub-block 123 has been determined by sub-ECC operation 302 that it has uncorrectable errors, the number of corrected errors Is determined in step 450 whether is equal to the order of the main key equation.

If at step 450 it is determined that the number of corrected errors is equal to the order of the main key equation, all detected errors have been corrected and processing is completed at step 452. If not, it is determined whether the fourth sub-block 124 has been determined by sub-ECC operation 302 that it has uncorrectable errors (step 454). If the sub-ECC operation 302 determines that the fourth sub-block 124 has no uncorrectable errors, the Chien search processing of the main ECC operation 304 is performed by the fourth sub-block 124 and the second. 4 sub-ECC data 128 is performed (step 456).

It is determined at step 458 whether the total number of corrected errors is equal to the order of the main key equation. If so, all detected errors have been corrected and processing ends at step 460. If at step 458 the number of corrected errors is not equal to the order of the main key equation, then the number of errors generated is beyond the capacity of the main ECC operation 304, at step 462 an error is generated and processing is terminated. .

5 is a flowchart of one embodiment of a distributed ECC processing method. The method may be performed, for example, in a controller of a memory device, such as controller 110 of FIG. The method includes receiving 502 data including a data block and main error correction coding (ECC) data for the data block. The data block includes a first sub-block of data and first ECC data corresponding to the first sub-block. The memory device may include a nonvolatile memory and the step of receiving data may be performed by reading data from the nonvolatile memory and transferring the read data to the controller's ECC engine. For example, the ECC page 120 may be received at the ECC engine 114 of FIG. 1 as read data 116.

A data block ECC operation is initiated to process the data block using the main ECC data (step 504). The data block ECC operation may include a main syndrome generation process, a main key equation generation process, and a main error location process. For example, the data block ECC operation may be the main ECC operation 304 of FIG. Initiating a data block ECC operation may be performed by providing data to an input of a data block ECC decoder, such as data block ECC decoder 142 of FIG. 1, and instructing the data block ECC decoder to begin data processing. .

The sub-block ECC operation may begin to process the first sub-block using the first ECC data (step 506). The data block ECC operation and the sub-block ECC operation can be started substantially simultaneously. Sub-block ECC operations may include a sub-block syndrome generation process, a sub-block key equation generation process, and a sub-block error location process, for each sub-block in the data block. The data block may include a second sub-block and second ECC data corresponding to the second sub-block. The sub-block ECC operation may also process the second sub-block using the second ECC data. The sub-block ECC operation may be pipelined and the processing for the second sub-block may at least partially overlap with the processing for the first sub-block. For example, the sub-block ECC operation may be the sub-ECC operation 302 of FIG. Initiating sub-block ECC operation is provided by providing data to an input of a sub-block ECC decoder such as sub-block ECC decoder 140 of FIG. 1 and instructing the sub-block ECC decoder to start data processing. Can be performed.

Error location retrieval of the data block ECC operation is optionally initiated based on the result of the sub-block ECC operation (step 508). For example, in response to a sub-block ECC operation indicating uncorrectable errors in the first sub-block, the error location search may be initiated to begin at the beginning of the first sub-block. The error location search may include a Chien search, such as Chien search processing 323 of FIG.

For example, selectively initiating an error location search of the data block ECC operation based on the result of the sub-block ECC operation may include: starting bit position of the sub-block that cannot be corrected by the sub-block ECC operation (eg, Chien of FIG. 2). By receiving start position data indicating search start position 260. End position data indicating an end bit position (eg, Chien search end position 262 of FIG. 2) of the ECC data corresponding to an uncorrectable sub-block by the sub-block ECC operation may also be received. An error location search can be initiated to sequentially process data from the start bit position to the end bit position.

The data block ECC operation can determine a first number of errors in the data. The first number of errors is determined by the data block ECC operation, for example, based on the order of key equations corresponding to the data block. The first number of errors may be compared with the second number of errors corrected by the sub-block ECC operation, such as for example, decision step 420 of FIG. 4A.

If the data block includes a plurality of sub-blocks, the error location search may be controlled to process each of the plurality of sub-blocks identified as having uncorrectable errors during the sub-block ECC operation. For example, a Chien search may optionally be performed in response to the determinations 404, 408, 412, 416 of FIG. 4A. After the error location search of each of the plurality of sub-blocks identified as having uncorrectable errors is completed, the number of corrected errors may be compared with the first number of errors in the data. In response to the first number of errors exceeding the number of corrected errors, the error location search may be controlled to process main ECC data as illustrated in 420-424 of FIG. 4A.

The number of corrected errors can be updated when one or more errors in the main ECC data are corrected. When the first number of errors exceeds the number of corrected errors, during sub-block ECC operation as having uncorrectable errors, such as, for example, in response to the decisions 430, 438, 446, 454 of FIG. 4. The error location search can be controlled to process at least one of the plurality of sub-blocks that are not identified.

Although implemented in the distributed ECC system data storage device of FIG. 1, in other embodiments the distributed ECC system may be implemented in other systems, such as a communication system. For example, the ECC engine 114 of FIG. 1 may be implemented in a wireless receiver that corrects errors that occur during transmission of an encoded signal.

Although the ECC page 120 is illustrated as having four sub-blocks 121-124, in other embodiments the ECC page 120 may have more than four or fewer than four sub-blocks. May have The sub-blocks may have the same size or different sizes within the ECC page 120. Also, although the sub-block operation 302 of FIG. 3 and the processing of FIG. 4 are illustrated as processing the sub-blocks 121-124 sequentially, the sub-block processing in other embodiments is non-sequential. May be performed in order or one or more sub-blocks may be skipped. For example, by processing one sub-block concurrently with the main block and controlling the Chien search in the main block based on the results of the sub-block processing, the average ECC decode latency may be reduced. .

Although the various components described herein are illustrated in block terms and described in general terms, these components may be associated with one or more microprocessors, state machines, or the data storage device 102 of FIG. 1. Other circuits may be included to enable certain functions to be performed. For example, the sub-block ECC decoder 140 and data block ECC decoder 142 of FIG. 1 may be, for example, hardware controllers, state machines, logic circuits, or the ECC engine 114 of FIG. The results of sub-block ECC decoder 140 may be used to represent physical components, such as other structures, that may perform distributed ECC processing to coordinate processing at ECC decoder 142.

The sub-block ECC decoder 140 and data block ECC decoder 142 of FIG. 1 may be implemented in dedicated hardware (eg, circuits) for reduced delay. Alternatively, either or both of the sub-block ECC decoder 140 and data block ECC decoder 142 of FIG. 1 may be implemented using a microprocessor or may include, for example, syndrome generation, key equation generation, Or may be implemented using a microcontroller programmed to perform one or more stages of ECC decoding, such as error location search. In a particular embodiment, either or both of sub-block ECC decoder 140 and data block ECC decoder 142 includes executable instructions executed by a processor and the instructions are stored in memory 112. do. Alternatively or additionally, executable instructions executed by a processor that may be included in controller 110 are, for example, separate portions of memory 112 such as read-only memory (RAM) (not shown). It may be stored in a memory location. In certain embodiments, data storage device 102 may be a portable device configured to be selectively coupled to one or more external devices. However, in other embodiments, data storage device 102 may be attached or may be embedded within one or more host devices (eg, in a housing of a portable communication device). For example, the data storage device 102 may be in a packaged device such as a wireless telephone, personal digital assistant (PDA), gaming device or console, portable navigation device, or other device using internal non-volatile memory. have. In one embodiment, the data storage device 102 is, for example, NAND, NOR, multilevel cell (MLC), divided bit-line NOR (DINOR), AND, high-capacity coupling ratio (high). flash memory, such as capacitive coupling ratio (HiCR), asymmetrical contactless transistor (ACT) or other flash memories, erasable programmable read-only memory (EPROM), electrically erased and Nonvolatile, such as electrically-erasable programmable read-only memory (EEPROM), read-only memory (RAM), one-time programmable memory (OTP), or other types of memories It may include a memory.

The examples of the embodiments described herein are intended to provide a general understanding of the various embodiments. Other embodiments may be utilized and derived from the present disclosure, and thus structural and logical substitutions and changes may be made without departing from the scope of the present invention. This disclosure is intended to cover any or all subsequent modifications or variations of the various embodiments. Accordingly, the disclosure and the drawings are to be regarded in an illustrative rather than a restrictive sense.

The foregoing invention is to be considered as illustrative and not restrictive. And the appended claims are intended to cover all such variations, refinements, and other embodiments that fall within the scope of the invention. Thus, to the extent permitted by law, the scope of the invention is to be determined by the broadest possible interpretation of the following claims and their equivalents, and is not limited or limited by the foregoing description of the invention. .

Claims (24)

As a distributed ECC processing method,
In the controller of the memory device,
Receiving data comprising a data block and main error correction coding (ECC) data for the data block, the data block comprising a first sub-block of data and a first ECC corresponding to the first sub-block; Includes data;
Initiating a data block ECC operation to process the data block using the main ECC data;
Initiating a sub-block ECC operation to process the first sub-block using the first ECC data; And
Selectively initiating an error location search of the data block ECC operation based on a result of the sub-block ECC operation
Distributed ECC processing method comprising a. The method of claim 1,
In response to the sub-block ECC operation indicating uncorrectable errors in a first sub-block, the error location search is initiated to begin at the beginning of the first sub-block. Processing method. The method of claim 1,
The error location search comprises a Chien search. The method of claim 1,
The data block includes a second sub-block and second ECC data corresponding to the second sub-block, and the sub-block ECC operation also uses the second ECC data for the second sub-block. Distributed ECC processing method, characterized in that for processing. 5. The method of claim 4,
The sub-block ECC operation is pipelined and processing the second sub-block at least partially overlaps with processing the first sub-block. The method of claim 1,
The data block ECC operation determines a first number of errors in the data, and
Comparing the first number of errors with a second number of errors corrected by the sub-block ECC operation
Distributed ECC processing method further comprising. The method of claim 1,
The data block comprises a plurality of sub-blocks, and
Controlling the error location search to process each of the plurality of sub-blocks identified during the sub-block ECC operation as having uncorrectable errors
Distributed ECC processing method further comprising. The method of claim 7, wherein
After the error location search for each of the plurality of sub-blocks identified as having uncorrectable errors is complete,
Comparing the number of corrected errors with a first number of errors in the data, wherein the first number of errors is determined by the data block ECC operation; And
In response to the first number of errors exceeding the number of corrected errors, controlling the error location search to process the main ECC data.
Distributed ECC processing method further comprising. 9. The method of claim 8,
And wherein said first number of errors is based on an order of a key euqation corresponding to a data block. 9. The method of claim 8,
When one or more errors in the main ECC data are corrected, updating the number of corrected errors; And
When the first number of errors exceeds the number of corrected errors, the error location search to process at least one of a plurality of sub-blocks not identified during the sub-block ECC operation that have uncorrectable errors. Steps to control
Distributed ECC processing method further comprising. The method of claim 1,
The memory device further comprises a nonvolatile memory, and
Receiving the data,
Read data from the nonvolatile memory; And
Distributed ECC processing, characterized in that performed by transmitting the read data to the controller's ECC engine. The method of claim 1,
Initiating the data block ECC operation,
Provide data to an input of a data block ECC decoder; And
Performed by instructing the data block ECC decoder to begin processing for the data, and
Initiating the sub-block ECC operation,
Provide data to an input of a sub-block ECC decoder; And
Distributed ECC processing, characterized by instructing the sub-block ECC decoder to begin processing for the data. The method of claim 12,
The data block ECC operation and the sub-block ECC operation are initiated simultaneously. The method of claim 1,
Selectively initiating an error location search of the data block ECC operation based on a result of the sub-block ECC operation,
Receive start position data indicating a start bit position of a sub-block that is uncorrectable by the sub-block ECC operation;
Receive end position data indicating an end bit position of ECC data corresponding to the sub-block that cannot be corrected by the sub-block ECC operation; And
And performing the error position search to sequentially process the data from the start bit position to the end bit position. The method of claim 1,
The data block ECC operation includes a main syndrome generation process, a main key equation generation process, and a main error location process,
The sub-block ECC operation includes a sub-block syndrome generation process, a sub-block key equation generation process, and a sub-block error locating process for each sub-block in the data block. ECC processing method. 1. A data storage device,
A memory; And
A controller connected to the memory,
The controller includes an error correction coding (ECC) engine, the error correction coding engine,
A data block ECC decoder adapted to process data retrieved from the memory, the data comprising a data block and main error correction coding (ECC) data for the data block; And
Sub-block ECC decoder configured to process sub-blocks of the data block and ECC data corresponding to the sub-blocks
Including;
The ECC engine is configured to initiate processing of the data at the data block ECC decoder and the sub-block ECC decoder simultaneously. 17. The method of claim 16,
And the ECC engine is configured to selectively initiate an error position search at the data block ECC decoder based on a result of the sub-block ECC decoder. 18. The method of claim 17,
The ECC engine further includes a control circuit,
The control circuitry sets a starting position of an error location search in the data block ECC decoder to search for errors in sub-blocks responsive to the sub-block ECC decoder and identified as uncorrectable by the sub-block ECC decoder. And a data storage device for selecting. 17. The method of claim 16,
Processing at the data block ECC decoder is at least partially overlapping with processing at the sub-block ECC decoder. 1. A data storage device,
Flash memory; And
A controller connected to the flash memory,
The controller includes an error correction coding (ECC) engine, the error correction coding engine,
A data block ECC decoder adapted to process data retrieved from the flash memory, the data comprising a data block and main error correction coding (ECC) data for the data block;
A sub-block ECC decoder configured to process sub-blocks of the data block and ECC data corresponding to the sub-blocks; And
Control circuitry configured to select a starting position of an error location search in the data block ECC decoder in response to the sub-block ECC decoder and to search for errors in sub-blocks identified as uncorrectable by the sub-block ECC decoder.
Data storage device comprising a. 21. The method of claim 20,
The ECC engine is configured to initiate processing of the data at the data block ECC decoder and the sub-block ECC decoder simultaneously. 21. The method of claim 20,
And the data storage device is removably coupled to a host device. 21. The method of claim 20,
And the data storage device is coupled to a host device as an embedded memory. delete

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