TW201310540A - Manufacturing method for semiconductor device having metal gate - Google Patents

Abstract

A manufacturing method for a semiconductor device having metal gate includes providing a substrate having at least a first semiconductor device formed thereon, forming a first gate trench in the first semiconductor device, forming a first work function metal layer in the first gate trench, and performing a decoupled plasma oxidation to the first work function metal layer.

Description

Semiconductor component having metal gates

The present invention relates to a semiconductor device having a metal gate and a method of fabricating the same, and more particularly to a semiconductor device having a metal gate in a gate last process and a method of fabricating the same.

As the size of semiconductor components continues to shrink, the conventional method of reducing the thickness of the gate dielectric layer, such as reducing the thickness of the yttria layer, for optimization purposes, is due to the tunneling effect of electrons. A physical limitation that causes excessive leakage current. In order to effectively extend the evolution of logic components, high dielectric constant (hereinafter referred to as high-k) materials have an effective reduction in physical limit thickness and the same equivalent oxide thickness (EOT). In order to effectively reduce the leakage current and achieve the equivalent capacitance to control the channel switch, it is used to replace the conventional ruthenium dioxide layer or the ruthenium oxynitride layer as the gate dielectric layer.

However, the conventional gate material polysilicon is faced with boron penetration effect, which leads to problems such as lower component efficiency; and the polysilicon gate encounters an inevitable depletion effect, making the equivalent gate dielectric layer The increase in thickness and the decrease in the gate capacitance value lead to difficulties such as the deterioration of the component driving capability. In response to this problem, the semiconductor industry has proposed to replace the traditional polysilicon gate with a new gate material, such as a metal gate with a work function metal layer, as a matching high-k gate dielectric layer. Control electrode.

However, even if a high-k gate dielectric layer is used in place of a conventional germanium dioxide or tantalum oxynitride dielectric layer, and a metal gate with a matching work function is substituted for a conventional polysilicon gate, how to continuously increase the performance of the semiconductor device, for example, It can ensure that the metal gate of an n-type metal-oxide-semiconductor (nMOS) transistor has a work function of about 4.1 electron volts (eV) and a p-type metal-oxide (p-type metal- Oxide-semiconductor, pMOS) The metal gate of the transistor has a work function of around 5.1 eV, which has been a problem for semiconductor manufacturers.

Accordingly, it is an object of the present invention to provide a method of fabricating a metal gate that ensures that the metal gate of an nMOS transistor or pMOS transistor has a desired work function.

According to the scope of the invention provided by the present invention, a method of fabricating a semiconductor device having a metal gate is provided, which first provides a substrate on which at least one first semiconductor component is formed. A first gate trench is formed in the first semiconductor device, and then a first work function metal layer is formed in the first gate trench. After the first work function metal layer is formed in the first gate trench, the first work function metal layer is subjected to a decoupled plasma oxidation (hereinafter referred to as DPO) treatment.

The method for fabricating a semiconductor device having a metal gate according to the present invention is to perform a DPO process after forming the first work function metal layer in a semiconductor device, particularly a gate trench of a P-type semiconductor device. Adjusting the work function of the first work function metal layer to a target work function. In addition, since the first work function metal layer after the DPO process already has the target work function, the method for fabricating the semiconductor device having the metal gate provided by the present invention can even replace the conventional post-metal anneal. And to avoid the impact of post-metal heat treatment. In other words, the method for fabricating a semiconductor device having a metal gate provided by the present invention not only ensures that the metal gate of the semiconductor device has a satisfactory work function, but further ensures the electrical performance of the semiconductor device having the metal gate. .

Please refer to FIG. 1 to FIG. 5 . FIG. 1 to FIG. 5 are schematic diagrams showing a first preferred embodiment of a method for fabricating a semiconductor device having a metal gate according to the present invention. As shown in FIG. 1, the preferred embodiment first provides a substrate 100, such as a germanium substrate, a germanium-containing substrate, or a silicon-on-insulator (SOI) substrate. A first semiconductor component 110 and a second semiconductor component 112 are formed on the substrate 100, and a shallow trench isolation (shallow trench) for providing electrical isolation is formed in the substrate 100 between the first semiconductor component 110 and the second semiconductor component 112. Isolation, STI) 102. The first semiconductor component 110 has a first conductivity type, and the second semiconductor component 112 has a second conductivity pattern, and the first conductivity pattern is complementary to the second conductivity pattern. In the preferred embodiment, the first semiconductor component 110 is a p-type semiconductor component; and the second semiconductor component 112 is an n-type semiconductor component.

Please refer to Figure 1. The first semiconductor device 110 and the second semiconductor device 112 each include a gate dielectric layer 104, a bottom barrier layer 106 and a dummy gate (not shown) such as a polysilicon layer. The gate dielectric layer 104 can be a conventional germanium dioxide layer or a high dielectric constant gate dielectric layer or a combination thereof; and the bottom barrier layer 106 comprises titanium nitride (TiN), but is not limited thereto. this. In addition, the first semiconductor component 110 and the second semiconductor component 112 respectively include a first light doped drain (LDD) 120 and a second LDD 122, a sidewall 124, and a first source/汲The pole 130 and a second source/drain 132. In addition, the surface of the first source/drain 130 and the second source/drain 132 respectively comprise a metal halide 134. On the first semiconductor element 110 and the second semiconductor element 112, a contact etch stop layer (CESL) 140 and an inter-layer dielectric (ILD) layer 142 are sequentially formed. . The fabrication steps and material selection of the above-mentioned components, and even the selective epitaxial growth (SEG) method for forming the source/drain electrodes 130, 132, etc. in the semiconductor industry to provide stress and improve electrical performance are Those skilled in the art are well known and will not be described here.

Please continue to see Figure 1. After forming the CESL 140 and the ILD layer 142, a portion of the CESL 140 and the ILD layer 142 are removed by a planarization process until the dummy gates of the first semiconductor component 110 and the second semiconductor component 112 are exposed, and then utilized. A suitable etching process removes the dummy gates of the first semiconductor component 110 and the second semiconductor component 112, and simultaneously forms a first gate trench 150 and a first semiconductor component 110 and the second semiconductor component 112. The second gate trench 152. It should be noted that the preferred embodiment can be integrated with a high-k first process, in which case the gate dielectric layer 104 contains a high dielectric constant (high-k constant). A gate dielectric layer, which may be a metal oxide layer, such as a rare earth metal oxide layer. The high-k gate dielectric layer 104 can be selected from the group consisting of hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), and hafnium silicon oxynitride (HfSiON). , aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), oxidation Zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), yttrium Oxide (strontium bismuth tantalate, SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT) and barium strontium titanate (Ba _x Sr) _a group consisting of _1-x TiO ₃ , BST). In addition, between the high-k gate dielectric layer 104 and the substrate 100, an interfacial layer (not shown) may be disposed. After forming the first gate trench 150 and the second gate trench 152, an etch stop layer may be formed on the bottom barrier layer 106 in the first gate trench 150 and the second gate trench 152 (etch stop) The etch stop layer 108 may include tantalum nitride (TaN), but is not limited thereto.

It is also worth noting that the preferred embodiment can be integrated with a high-k last process, in which case the gate dielectric layer can be a conventional germanium dioxide layer. After the polysilicon layer is removed to form the first gate trench 150 and the second gate trench 152, the gate dielectric layer exposed to the bottom of the first gate trench 150 and the second gate trench 152 can serve as an interface layer ( The figure is not shown). A high-k gate dielectric layer 104 is then formed over the substrate 100, which may comprise the materials described above. After the high-k gate dielectric layer 104 is formed, the foregoing etch stop layer 108 may be formed thereon.

Please refer to Figure 1 again. After forming the etch stop layer 108, a chemical vapor deposition (CVD) process or a physical vapor deposition (PVD) process is performed on the first gate trench 150 and the second gate. A first work function metal layer 160 is formed in the trench 152. The first work function metal layer 160 may be a p-type work function metal layer having a p-type conductivity type, for example, titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (tantalum nitride) , TaN), tantalum carbide (TaC), tungsten carbide (WC), or aluminum titanium nitride (TiAlN), but is not limited thereto. In addition, the first work function metal layer 160 may be a single layer structure or a composite layer structure.

Please still refer to Figure 1. After forming the first work function metal layer 160, a DPO process 162 is performed to adjust the work function of the first work function metal layer 160. The DPO process 162 has a process temperature and the process temperature is less than 400 ° C, preferably between room temperature and 200 ° C. In addition, the DPO treatment 162 may further comprise the step of introducing nitrogen or argon. According to the DPO process 162 provided by the preferred embodiment, the work function of the first work function metal layer 160 is adjusted to be between 4.9 electron volts (eV) and 5.2 eV, and preferably 5.1 eV.

It should be noted that, in the preferred embodiment, it is not limited to performing a post metal anneal after forming the first work function metal layer 160, using a high temperature adjustment of more than 400 ° C or even 550 ° C. The work function of the metal layer 160 of a work function. Such high temperatures are not conducive to the low thermal budget requirements of the first work function metal layer 160, and thus have a negative impact on the metal layer. However, since the DPO process 162 provided by the preferred embodiment can ensure that the first work function metal layer 160 obtains the target work function, the foregoing metal post-heat treatment can be omitted, and the metal post-heat treatment can be avoided to the first work function metal. The negative effects caused by layer 160.

Please refer to Figure 2. Next, a patterned mask, such as a patterned photoresist layer (not shown), is formed on the substrate 100, but is not limited thereto. The patterned mask is used to cover the first semiconductor component 110 and expose the first work function metal layer 160 at the second semiconductor component 112. The first work function metal layer 160, which is not protected by the patterned mask, is then removed using a suitable etchant such that the etch stop layer 108 is re-exposed within the second gate trench 152. Upon removal of the first work function metal layer 160, the etch stop layer 108 protects the underlying barrier layer 106 and the high-k gate dielectric layer 104. It is also worth noting that, in order to improve the filling result of the subsequent metal film layer, when the first work function metal layer 160 in the second gate trench 152 is completely removed, the patterned mask can be formed in the first gate. The surface of the pole trench 150 has a lower surface than the opening of the first gate trench 150. Therefore, when the first work function metal layer 160 is removed, the first work function metal layer 160 remains only in the first gate trench 150, especially the bottom and sidewalls of the first gate trench 150, so that the first gate The height of the first work function metal layer 150 on the sidewall of the trench 150 is smaller than the depth of the first gate trench 150, thereby increasing the filling ability of the subsequent metal film layer.

Please continue to see Figure 2. After the first work function metal layer 160 in the second gate trench 152 is removed, a CVD process or a PVD process is performed to form a second work function metal layer 170 on the substrate 100. The second work function metal layer 170 may be an n-type work function metal layer having an n-type conductivity type, such as a titanium aluminide (TiAl) layer, a zirconium aluminide (ZrAl) layer, and a tungsten aluminide ( A tungsten aluminide, WAl) layer, a tantalum aluminide (TaAl) layer or a hafnium aluminide (HfAl) layer, but is not limited thereto. In addition, the second work function metal layer 170 may be a single layer structure or a composite layer structure.

Please refer to Figure 2. After forming the second work function metal layer 170, a decoupled plasma nitridation (hereinafter referred to as DPN) process 172 is performed to adjust the work function of the second work function metal layer 170. The DPN process 172 has a process temperature and the process temperature is less than 400 ° C, preferably between room temperature and 200 ° C. In addition, the DPN process 172 may further comprise the step of introducing nitrogen or argon. According to the DPN process 172 provided by the preferred embodiment, the work function of the second work function metal layer 170 is adjusted to be between 3.9 eV and 4.2 eV, and preferably 4.1 eV. It is also worth noting that a mask (not shown) may be selectively formed at the first semiconductor device 110 before the DPN process 172 is performed to prevent the DPN process 172 from affecting the first semiconductor device 110. The work function of the two work function metal layer 170 and the first work function metal layer 160.

Please refer to Figure 3. After the DPN process 172 is performed to adjust the work function of the second work function metal layer 170, a heat treatment 174 is performed to more stabilize the bonding of the nitrogen atoms with the metal material in the second work function metal layer 170 to increase the second work function metal. The stability of layer 170. It should be noted that the temperature of one of the heat treatments 174 provided by the preferred embodiment is less than 400 ° C, and therefore more in line with the low thermal budget requirements of the metal materials. In other words, the low temperature heat treatment provided by the preferred embodiment can avoid affecting the first work function metal layer 160 and the second work function metal layer 170 while increasing the stability of the second work function metal layer 170.

Please refer to Figure 4. Next, a fill metal layer 180 is formed on the second work function metal layer 170 in the first gate trench 150 and the second gate trench 152. In addition, a top barrier layer (not shown) may be disposed between the second work function metal layer 170 and the filling metal layer 180, and the top barrier layer may include TiN, but is not limited thereto. The filling metal layer 180 is used to fill the first gate trench 150 and the second gate trench 152, and may select a metal or metal oxide having excellent filling ability and a lower resistance, such as aluminum (Al). Titanium aluminide (TiAl) or titanium aluminum oxide (TiAlO), but is not limited thereto.

Please refer to Figure 5. Finally, a planarization process, such as a CMP process, is performed to remove the excess fill metal layer 180, the second work function metal layer 170, the first work function metal layer 160, and the etch stop layer 108, and complete a A metal gate 190 and a second metal gate 192 are fabricated. In addition, the present embodiment can also selectively remove the ILD layer 142 and the CESL 140 and the like, and then reform the CESL and the dielectric layer to effectively improve the electrical performance of the semiconductor device. Since the above CMP process and the like are known to those of ordinary skill in the art, they are not described herein.

The method for fabricating a semiconductor device having a metal gate according to the present invention is to form a first work function metal layer 160 and a second work function metal layer 170, respectively, for the first work function metal layer 160 and the second work The function metal layer 170 performs DPO processing 162 and DPN processing 172 to adjust the work function of the first work function metal layer 160 and the second work function metal layer 170 to a target work function. In addition, since the first work function metal layer 160 and the second work function metal layer 170 after the DPO process 162 and the DPN process 172 already have a target work function, the method for fabricating the semiconductor device having the metal gate provided by the present invention may be Substituting the metal for post-heat treatment, or substantially reducing the process temperature required for post-metal post-heat treatment. In other words, the method for fabricating a semiconductor device having a metal gate provided by the present invention can avoid the influence of the post-metal heat treatment and ensure the electrical performance of the semiconductor device having the metal gate.

Please refer to FIG. 6 to FIG. 10 . FIG. 6 to FIG. 10 are schematic diagrams showing a second preferred embodiment of a method for fabricating a semiconductor device having a metal gate according to the present invention. It is to be noted that, in the second preferred embodiment, the material selection of the same elements as the first preferred embodiment will not be described herein. As shown in FIG. 6, the preferred embodiment first provides a substrate 200 having a first semiconductor component 210 and a second semiconductor component 212 formed thereon, and between the first semiconductor component 210 and the second semiconductor component 212. The substrate 200 is formed with an STI 202 that provides electrical isolation. In the preferred embodiment, the first semiconductor component 210 is a p-type semiconductor component; the second semiconductor component 212 is an n-type semiconductor component.

Please refer to Figure 6. The first semiconductor device 210 and the second semiconductor device 212 each include a gate dielectric layer 204, a bottom barrier layer 206 and a dummy gate (not shown). In addition, the first semiconductor device 210 and the second semiconductor device 212 respectively include a first LDD 220 and a second LDD 222, a sidewall 224, a first source/drain 230, and a second source/drain 232. In addition, the surface of the first source/drain 230 and the second source/drain 232 respectively comprise a metal halide 234. On the first semiconductor element 210 and the second semiconductor element 212, a CESL 240 and an ILD layer 242 are sequentially formed.

Please continue to see Figure 6. Then, a portion of the CESL 240 and the ILD layer 242 are removed by a planarization process, and the dummy gates of the first semiconductor device 210 and the second semiconductor device 212 are removed by a suitable etching process while simultaneously being used in the first semiconductor. A first gate trench 250 and a second gate trench 252 are formed in the component 210 and the second semiconductor component 212, respectively. It should be noted that the preferred embodiment can be integrated with a high-k first process, in which case the gate dielectric layer 204 includes a high-k gate dielectric layer. In addition, between the high-k gate dielectric layer 204 and the substrate 200, an interface layer (not shown) may be disposed. The preferred embodiment can also be integrated with the post gate dielectric layer process. The gate dielectric layer can be a conventional germanium dioxide layer and serve as an interface layer (not shown), followed by the substrate 200. A high-k gate dielectric layer 204 is formed thereon. After forming the first gate trench 250 and the second gate trench 252, or forming the high-k gate dielectric layer 204 in the first gate trench 250 and the second gate trench 252, the first An etch stop layer 208 is formed on the bottom barrier layer 250 in the gate trench 250 and the second gate trench 252.

Please still refer to Figure 6. After the etch stop layer 208 is formed, a second work function metal layer 270 is formed in the first gate trench 250 and the second gate trench 252. The second work function metal layer 270 can be an n-type work function metal layer having an n-type conductivity. In addition, the second work function metal layer 270 can be a single layer structure or a composite layer structure.

As shown in FIG. 6, after the second work function metal layer 270 is formed, a DPN process 272 is performed to adjust the work function of the second work function metal layer 270. Other parameters or steps of the process temperature of the DPN process 272 can be found in the first preferred embodiment. According to the DPN process 272 provided by the preferred embodiment, the work function of the second work function metal layer 270 is adjusted to be between 3.9 eV and 4.2 eV, and preferably 4.1 eV.

Please refer to Figure 7. After the DPN process 272 is performed to adjust the work function of the second work function metal layer 270, a heat treatment 274 is performed to more stably bond the nitrogen atoms to the metal material in the second work function metal layer 270 to increase the second work function metal. The stability of layer 170. It should be noted that the process temperature of one of the heat treatments 274 provided by the preferred embodiment is less than 400 ° C, and thus is more in line with the low thermal budget requirements of the metal materials.

Please refer to Figure 8. Next, a patterned mask, such as a patterned photoresist layer (not shown), is formed on the substrate 200, but is not limited thereto. The patterned mask is used to cover the second semiconductor component 212 and expose the second work function metal layer 270 at the first semiconductor component 210. A second work function metal layer 270 that is not protected by the patterned mask is then removed using a suitable etchant. It is also worth noting that in order to improve the filling result of the subsequent metal film layer, when the second work function metal layer 270 in the first gate trench 250 is completely removed, the patterned mask can be formed in the second gate. The surface of the pole trench 252 is lower than the opening of the second gate trench 252. Therefore, when the second work function metal layer 270 is subsequently removed, the second work function metal layer 270 remains only in the second gate trench 252. The bottom of the second gate trench 252 has a lower height than the second gate trench 252, thereby increasing the thickness of the subsequent metal film layer. Fill in the ability.

Please continue to see Figure 8. After the second work function metal layer 270 in the first trench trench 250 is removed, a first work function metal layer 260 is formed on the substrate 200. The first work function metal layer 260 can be a p-type work function metal layer having a p-type conductivity. In addition, the first work function metal layer 260 can be a single layer structure or a composite layer structure.

As shown in FIG. 8, after forming the first work function metal layer 260, a DPO process 262 is performed to adjust the work function of the first work function metal layer 260. Other parameters or steps of the process temperature of the DPO process can be found in the first preferred embodiment. According to the DPO process 262 provided by the preferred embodiment, the work function of the first work function metal layer 260 is adjusted to be between 4.9 eV and 5.2 eV, and preferably 5.1 eV. It is also worth noting that a mask (not shown) may be selectively formed at the second semiconductor component 212 prior to performing the DPO process 262 to prevent the DPO process 262 from affecting the second semiconductor component 212. The work function of the work function metal layer 260 and the second work function metal layer 270.

It should be noted that, in the preferred embodiment, although a metal post-heat treatment is not performed after forming the first work function metal layer 260, the first work function metal layer is adjusted by using a temperature higher than 400 ° C or even 550 ° C. 160 work function. Such high temperatures are not conducive to the low thermal budget requirements of the first work function metal layer 160, and thus have a negative impact on the metal layer. However, due to the DPO process 262 provided by the preferred embodiment to ensure that the first work function metal layer 260 obtains the target work function, the foregoing metal post-heat treatment can be omitted, and the metal post-heat treatment is applied to the first work function metal. The negative impact of layer 260.

Please refer to Figure 9. Next, a fill metal layer 280 is formed on the first work function metal layer 260 in the first gate trench 250 and the second gate trench 252. In addition, a top barrier layer (not shown) may be disposed between the first work function metal layer 260 and the fill metal layer 280. The fill metal layer 280 is used to fill the first gate trench 250 and the second gate trench 252, and may select a metal or metal oxide having excellent filling ability and lower resistance.

Please refer to Figure 10. Finally, a planarization process, such as a CMP process, is performed to remove the excess fill metal layer 280, the first work function metal layer 260, the second work function metal layer 270, and the etch stop layer 208 to complete a A metal gate 290 and a second metal gate 292 are fabricated. In addition, the present embodiment can also selectively remove the ILD layer 242 and the CESL 240 and the like, and then reform the CESL and the dielectric layer to effectively improve the electrical performance of the semiconductor device. Since the above CMP process and the like are known to those of ordinary skill in the art, they are not described herein.

The method for fabricating a semiconductor device having a metal gate according to the present invention is to form a second work function metal layer 270 and a first work function metal layer 260, respectively, to a second work function metal layer 270 and a first work. The function metal layer 260 performs a DPN process 272 and a DPO process 262 to adjust the work function of the second work function metal layer 270 and the first work function metal layer 260 to a target work function. In addition, since the first work function metal layer 260 after the DPO process 262 already has the target work function, the method for fabricating the semiconductor device having the metal gate provided by the present invention can replace the post-metal heat treatment, thereby avoiding the post-metal heat treatment. The presence of the second work function metal layer 270 affects the electrical performance of the semiconductor component having the metal gate.

In summary, the method for fabricating a semiconductor device having a metal gate according to the present invention is a method for forming an n-type work function metal layer after forming a work function metal layer required for an n-type or p-type semiconductor device. The p-type work function metal layer performs a DPN process and a DPO process to adjust the work function of the work function metal layer to a target work function. In addition, since the target work function is obtained by both the DPN process and the DPO-treated n-type and p-type work function metal layers, the method for fabricating the semiconductor device having the metal gate provided by the present invention can even replace the conventional metal. Heat treatment and avoid the effects of post-metal heat treatment. In other words, the method for fabricating a semiconductor device having a metal gate provided by the present invention not only ensures that the metal gate of the semiconductor device has a satisfactory work function, but further ensures the electrical performance of the semiconductor device having the metal gate. .

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100, 200. . . Base

102, 202. . . Shallow trench insulation

104, 204. . . High dielectric constant gate dielectric layer

106, 206. . . Bottom barrier layer

108, 208. . . Etch stop layer

110, 210. . . First semiconductor component

112, 212. . . Second semiconductor component

120, 220. . . First lightly doped bungee

122, 222. . . Second lightly doped bungee

124, 224. . . Side wall

130, 230. . . First source/dip

132, 232. . . Second source/dip

134, 234. . . Metal telluride

140, 240. . . Contact hole etch stop layer

142, 242. . . Inner dielectric layer

150, 250. . . First gate ditches

152, 252. . . Second gate ditches

160, 260. . . First work function metal layer

162, 262. . . Sub-coupled plasma oxidation treatment

170, 270. . . Second work function metal layer

172, 272. . . Sub-coupled plasma nitriding treatment

174, 274. . . Heat treatment

180, 280. . . Filled metal layer

190, 290. . . First metal gate

192, 292. . . Second metal gate

1 to 5 are schematic views showing a first preferred embodiment of a method for fabricating a semiconductor device having a metal gate according to the present invention.

6 to 10 are schematic views showing a second preferred embodiment of a method for fabricating a semiconductor device having a metal gate according to the present invention.

100. . . Base

102. . . Shallow trench isolation

104. . . High dielectric constant gate dielectric layer

106. . . Bottom barrier layer

108. . . Etch stop layer

110. . . First semiconductor component

112. . . Second semiconductor component

120. . . First lightly doped bungee

122. . . Second lightly doped bungee

124. . . Side wall

130. . . First source/dip

132. . . Second source/dip

134. . . Metal telluride

140. . . Contact hole etch stop layer

142. . . Inner dielectric layer

150. . . First gate ditches

152. . . Second gate ditches

160. . . First work function metal layer

162. . . Sub-coupled plasma oxidation treatment

Claims (16)

A method of fabricating a semiconductor device having a metal gate, comprising: providing a substrate on which at least one first semiconductor component is formed; forming a first gate trench in the first semiconductor component; Forming a first work function metal layer in the gate trench; and performing a decoupled plasma oxidation (DPO) process on the first work function metal layer. The manufacturing method of claim 1, wherein the split-coupled plasma oxidation treatment has a process temperature, and the process temperature is less than 400 °C. The manufacturing method of claim 2, wherein the process temperature is between room temperature and 200 °C. The manufacturing method of claim 1, wherein the sub-coupled plasma oxidation treatment further comprises the step of introducing nitrogen or argon. The manufacturing method of claim 1, wherein the first semiconductor component is a P-type semiconductor component. The manufacturing method according to claim 5, further comprising a second semiconductor component, wherein the second semiconductor component is an N-type semiconductor component. The manufacturing method of claim 6, further comprising: forming a second gate trench in the second semiconductor component; forming a second work function metal layer in the second gate trench; The second work function metal layer is subjected to a decoupled plasma nitridation (DPN) process. The manufacturing method of claim 7, wherein the split-coupled plasma nitriding treatment has a process temperature, and the process temperature is less than 400 °C. The manufacturing method of claim 8, wherein the process temperature is between room temperature and 200 °C. The manufacturing method of claim 7, wherein the partial-coupled plasma oxidation treatment further comprises the step of introducing nitrogen or argon. The manufacturing method described in claim 7 further includes a heat treatment performed after the split-type plasma nitriding treatment. The manufacturing method according to claim 11, wherein one of the heat treatment processes is lower than 400 °C. The manufacturing method of claim 7, wherein the first work function metal layer is formed after performing the split-coupled plasma nitriding treatment. The manufacturing method of claim 7, wherein the second work function metal layer is formed after performing the split-coupled plasma oxidation treatment. The manufacturing method of claim 7, wherein the first gate trench is formed simultaneously with the second gate trench system. The manufacturing method of claim 1, further comprising the step of forming a filling metal layer, wherein the filling metal layer fills at least the first gate trench.