TW201308599A - Trench-gate metal oxide semiconductor device and fabricating method thereof - Google Patents

Abstract

A trench-gate metal oxide semiconductor device includes a substrate, a first gate dielectric layer, a first gate electrode and a first source/drain structure. The substrate has a first doping region, a second doping region and at least one trench. A P/N junction is formed between the first doping region and the second doping region. The trench extends from a surface of the substrate to the first doping region through the second doping region and the P/N junction. The first gate dielectric layer is formed on a sidewall of the second trench. The first gate electrode is disposed within the trench. A height difference between the top surface of the first gate electrode and the surface of the substrate is substantially smaller than 1500 Å . The first source/drain structure is formed in the substrate and adjacent to the first gate dielectric layer.

Description

Trench type metal-oxide-semiconductor element and method of manufacturing the same

The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a trench type metal-oxide-semiconductor device and a method of fabricating the same.

A trench-gate metal oxide semiconductor (TMOS) field effect transistor is characterized by an etched trench in which a gate structure is embedded in a semiconductor epitaxial layer. Since the drift path of the field effect transistor is formed along the sidewall of the trench, the channel length of the field effect transistor can be greatly increased, thereby greatly reducing the resistance of the characteristic channel ( About 30% lower). Therefore, under the same operating current, it not only helps to reduce static power loss, improve component current density, but also improves the disadvantages of conventional planar channel field effect transistors that cannot simultaneously increase component density and low on-resistance requirements. . It is important to improve the feature size and the shrinking of the wiring space.

However, with the increasing complexity of integrated circuits, the development of trench gate metal oxide semiconductor field effect transistors still has its limits. Therefore, there is a need to further integrate the structure and system with transistors with planar channels to cope with The accumulating degree of integrated circuits is increasing, as well as the development needs of diversified functions, and reducing manufacturing costs.

In view of the above, one of the objects of the present invention is to provide a trench-gate metal oxide semiconductor (TMOS) device including: a substrate, a first gate dielectric layer, and a first gate electrode And the first source/drain. The substrate has a first doped region, a second doped region, and at least one trench; and the first doped region and the second doped region form a P/N junction; the trench extends from the surface of the substrate through the first The two doped regions and the P/N junction enter the first doped region. The first gate dielectric layer is on the sidewall of the trench. The first gate electrode is located in the gate trench, and the height difference between the upper surface of the first gate electrode and the surface of the substrate is substantially less than 1500 . The first source/drain potential substrate is adjacent to the first gate dielectric layer.

In an embodiment of the invention, the trench metal oxide semiconductor device further includes a dielectric capping layer covering the upper surface of the first gate electrode.

In an embodiment of the invention, the first doped region is an N-type well region extending from the surface of the substrate into the substrate, and the second doped region is a P-type well region; and the P-type well region is formed by the surface of the substrate Extends into the N-well region. In an embodiment of the invention, the substrate comprises an N-type buried layer and a P-type epitaxial layer on the buried layer, wherein the P-type epitaxial layer allows the N-type well region to extend from the surface of the substrate into the substrate .

In one embodiment of the invention, the first source/drain is an N-type doped structure extending from the surface of the substrate into the P-type well region along the sidewall of the trench.

In an embodiment of the invention, the trench metal oxide semiconductor device further includes a third doped region, a second gate dielectric layer, a second gate dielectric layer, and a second source/drain structure. Wherein, the third doping region is located in the substrate and is separated from the first doping region and has the same electrical property as the first doping region. The second gate dielectric layer is on the surface of the substrate of the third doped region. The second gate electrode is located on the second gate dielectric layer. The second source/drain structure is located in the third doped region adjacent to the second gate dielectric layer and has the same electrical conductivity as the second doped region.

Another object of the present invention is to provide a method of fabricating a trench metal oxide semiconductor device comprising the steps of first defining a first region and a second region on a substrate. Thereafter, at least one first trench is formed in the second region; a dielectric layer is formed on the first region and the second region, and the first trench is filled. Forming at least one second trench in the first region using the dielectric layer as an etch mask layer; then forming a first gate dielectric layer on the sidewall of the second trench; and filling the second trench with the conductor material To form a first gate electrode layer.

In an embodiment of the invention, the first source/drain structure is formed before or after forming the second trench, further included in the first region.

In one embodiment of the invention, the dielectric layer is a chemical vapor deposited layer; the conductor material is polycrystalline germanium.

In an embodiment of the invention, after filling the conductor material, the method further comprises the step of forming a flat layer over the conductor material. Thereafter, chemical mechanical polishing is performed to remove the planarization layer, and a portion of the conductor material; and a blanket etching process is performed to remove the conductor material and the dielectric layer on both surfaces of the first region and the second region.

In an embodiment of the invention, after removing the conductor material and the dielectric layer, the method further comprises the steps of: forming a second gate dielectric layer over the second region; forming a second layer on the second gate dielectric layer a gate electrode; and a second source/drain structure in the second region.

In an embodiment of the invention, before forming the second source/drain structure, the first gate electrode is further covered with a dielectric cap layer.

It is still another object of the present invention to provide a method of fabricating a trench metal oxide semiconductor device comprising the steps of first defining a first region and a second region on a substrate. A patterned hard mask layer is formed on the first region and the second region. The patterned hard mask layer is then etched as a mask to form at least one trench in the first region. Then, a first gate dielectric layer is formed on the sidewall of the trench; and the trench is filled with a conductor material to form a first gate electrode layer.

In an embodiment of the invention, before the step of forming the patterned hard mask layer, the method further comprises: forming at least one isolation structure in the second region. In one embodiment of the invention, the isolation structure is a shallow trench isolator and the conductor material is polysilicon.

In one embodiment of the invention, the patterned hard mask layer comprises a hafnium oxide film layer and a tantalum nitride film layer, or a hafnium oxide thick film layer and a tantalum nitride film layer.

In an embodiment of the invention, after filling the conductor material, the method further comprises the step of forming a flat layer covering the conductor material. Chemical mechanical polishing is then performed to remove the flat layer, as well as a portion of the conductor material. A full etch process is then performed to remove the conductor material and the patterned hard mask layer on both the first and second regions.

In an embodiment of the present invention, after removing the conductor material and patterning the hard mask layer, the method further includes: forming a second gate dielectric layer over the second region; forming a first layer on the second gate dielectric layer a second gate electrode; and in the second region, a second source/drain structure is formed.

In an embodiment of the invention, the dielectric cap layer is further covered on the gate electrode before the second source/drain structure is formed.

According to the above embodiment, the present invention integrates a trench metal oxide semiconductor device with two processes for fabricating a metal oxide semiconductor device having planar vias, thereby fabricating a trench metal oxide semiconductor structure. And a (complementary) metal oxide semiconductor device of a planar channel metal oxide semiconductor structure.

In some embodiments of the invention, the shallow trench isolation process in a planar channel metal oxide semiconductor process can be integrated with the trench etch step of a trench metal oxide semiconductor process. The dielectric layer used to form the shallow trench isolation structure is used as an etching mask layer for forming trenches, which has the advantages of reducing the manufacturing cost, achieving the semiconductor process and structural integration, and reducing the process cost.

SUMMARY OF THE INVENTION An object of the present invention is to provide an advanced trench metal oxide semiconductor device and a method of fabricating the same, which can successfully integrate two metal oxide semiconductor structures having planar vias and vertical vias, and manufacturing processes thereof, and reduce manufacturing cost. The above and other objects, features, and advantages of the present invention will become more apparent and understood. The details are as follows.

Referring to FIG. 1A to FIG. 1I, FIG. 1A to FIG. 1I are schematic cross-sectional views showing a process of a complementary metal-oxide-semiconductor device 100 according to a preferred embodiment of the present invention. Wherein, a method of manufacturing the complementary metal oxide semiconductor device 100 includes the following steps:

First, a first region 101a and a second region 101b are defined on the substrate 101. In some embodiments of the present invention, the first region 101a and the second region 101b are defined by a series of ion implantation processes, according to the functional requirements of the transistor component. Two ion doped regions separated from each other are formed in the material 101. The first region 101a includes a first doping region 102. The second region 101b then includes a third doped region 104 (as shown in FIG. 1A) separated from the first doped region 102.

The electrical conductivity of the third doped region 104 is determined by the conductivity type of the component to be formed. If the elements to be formed in the two doped regions have the same conductivity type, the electrical properties of the two doped regions are the same, and vice versa. In an embodiment of the invention, the electrical conductivity of the third doped region 104 may be the same as or different from the first doped region 102. In the present embodiment, the third doping region 104 is electrically identical to the first doping region 102.

The so-called electrical properties of the present invention can be classified into two types, P type and N type, which are implanted dopants such as boron ions (B+) and phosphorus ions (P+), and arsenic ions ( The semiconductor regions of As+) and strontium ions (Sb+) are determined by positive charge (transfer carrier is a hole) or negative (transfer carrier is an electron). It should be noted, however, that the electrical properties employed by the various components in the following embodiments are merely illustrative and not specific.

For example, in the present embodiment, the substrate 101 includes an N-type buried layer 106 and a P-type epitaxial layer 107 on the buried layer 106. The first doped region 102 is an N-type well region extending from the substrate surface 101c into the P-type epitaxial layer 107. The third doped region 104 extends from the substrate surface 101c into another N-type well region of the P-type epitaxial layer 107. The third doped region 104 and the first doped region 102 are separated from each other by the P-type epitaxial layer 107 of the substrate 101.

Thereafter, at least one first trench 108 is formed in the second region 101b. In an embodiment of the present invention, the first trench 108 is formed by first growing a pad of germanium oxide layer and a layer of tantalum nitride (not shown) on the surface 101c of the substrate; The trench etching sequentially forms at least one shallow trench in the pad yttria layer, the tantalum nitride layer, and the substrate 101. A dielectric layer 109 is formed overlying the first region 101a and the second region 101b of the substrate 101 and filling the first trench 108 (as shown in FIG. 1B). In one embodiment of the invention, dielectric layer 109 is a deposited oxide layer formed by a chemical vapor deposition process.

Next, etching is performed using the dielectric layer 109 as a hard mask to form at least one second trench 110 substantially perpendicular to the substrate surface 101c in the first region 101a. Then, a first gate dielectric layer 111 is formed on the sidewall 110a of the second trench 110 (as shown in FIG. 1C). In some embodiments of the present invention, before forming the first gate dielectric layer 111, an oxidized sacrificial layer (not shown) is preferably formed on the sidewall 110a of the second trench 110, and the repair etching is caused by the sidewall 110a. Damage. After removing the oxidized sacrificial layer, the first thyristor layer 111 is formed on the sidewall 110a and the bottom surface of the second trench 110 by chemical vapor deposition, thermal oxidation, or other suitable method. The material of the first gate dielectric layer 111 is preferably hafnium oxide.

Subsequently, the second trench 110 is filled with a conductor material 112 (as shown in FIG. 1D). In some embodiments of the present invention, the conductive material 112 is a polysilicon material which is overlaid on the first gate dielectric layer 111 by a deposition process and fills the second trench 110.

After filling the conductor material 112, the conductor material 112 is preferably planarized. First, a planarization layer 113, such as a ruthenium dioxide layer, is selectively formed over the conductor material 112 over the conductor material 112 (as depicted in FIG. 1E). Thereafter, a chemical mechanical polishing process is performed to remove the planarization layer 113, and a portion of the dielectric layer 109 and the conductor material 112, and expose the substrate surface 101c (as depicted in FIG. 1F).

Then, an etching process is selectively performed to remove a small portion of the conductive material 112 located in the second trench 110, and a portion of the conductive material 112 and a portion of the second trench 110 are located. The first gate dielectric layer 111 remains as a vertical gate oxide layer 111a and a vertical gate electrode 112a (shown in FIG. 1G) of the subsequently formed trench MOSFET.

It should be noted that the function of the flat layer 113 is only used to planarize the surface depression formed by the trench material process of the conductive material 112 as a polishing buffer layer for the subsequent chemical mechanical polishing process. Therefore, in some embodiments of the present invention, after filling the conductor material 112, the flat layer 113 is not formed, but the chemical mechanical polishing process is directly performed. Alternatively, after the planarization layer 113 is formed, selective etching is directly performed to remove the dielectric layer 109 and the conductor material 112 described above.

However, since the removal of the conductor material 112 by the etching process can be precisely controlled, the height difference S between the vertical gate electrode 112a and the substrate surface 101c can be more accurately controlled to be substantially less than 1500. In the range.

After the conductor material 112 and the first gate dielectric layer 111 are removed, a series of ion implantation processes are performed to form a second doping region 103 in the substrate 101 of the first region 101a. In some preferred embodiments of the invention, the second doped region 103 is a P-type well region extending from the substrate surface 101c into the first doped region 102 (N-type well region).

Next, a second gate dielectric layer 117 is formed over the substrate surface 101c of the second region 101b, and a second gate electrode 118 is formed on the second gate dielectric layer 117 (as shown in FIG. 1H). A plurality of (at least one) fourth doped regions 105 are formed in the second doped region 103 by another ion implantation process. The fourth doping region 105 is a substrate surface 101c of the first active region 101a, extending along the trench sidewall 110a into the first doping region 102, and having a higher concentration of N-type dopants. Miscellaneous structure. The fourth doping region 105 is adjacent to the vertical gate oxide layer 111a and is surrounded by the second doping region 103 (P-type well region).

Then, using the second gate dielectric layer 117 and the second gate electrode 118 as a mask, another series of ion implantation processes are performed, and a planar channel metal oxide semiconductor field effect transistor element is defined in the second region 101b. The second source/drain structure 116 of 12 is adjacent to the second gate dielectric layer 117 and the second gate electrode 118. The preparation of the planar channel metal oxide semiconductor field effect transistor element 12 is completed (as shown in FIG. 1I). In the present embodiment, the second source/drain structure 116 is separated by two P-type dopings which are separated from each other and extend from the substrate surface 101c into the third doping region 104 (N-type well region), respectively. Miscellaneous structure.

Since the second doping region 103 and the first doping region 102 form a P/N junction 115; and the fourth doping region 105 has the same electrical property as the first doping region 102, and is second The doped region 103 forms another P/N junction 114. Therefore, the fourth doping region 105 and the first doping region 102 can be respectively used as the source or drain of the trench MOSFET field element 10 (hereinafter referred to as the first source/drain); The second doped region 103 between the fourth doped region 105 and the first doped region 102 constitutes a channel of the trench MOSFET field element 10. Therefore, the doping depth of the second doping region 103 can determine the channel length of the trench MOSFET field element 10.

It is to be noted, however, that in the present embodiment, the ion doping process for forming the second doping region 103 and the fourth doping region 105 is performed after the second trench is formed. However, in other embodiments of the present invention, the ion doping process for forming the second doping region 103 and the fourth doping region 105 may also be performed immediately after the process step of forming the first gate dielectric layer 111; After the first source/drain is formed, the trench etching process is performed in the first region 101a to form the second trench 110. Because of the above two embodiments, similar process steps are adopted, the difference is only that the order of implementation is different, so the detailed process is not described here.

In addition, in the preferred embodiment of the present invention, prior to forming the second source/drain structure 116 of the planar channel MOSFET, it is further included in the planar channel metal oxide semiconductor field effect transistor. Above the vertical gate electrode 112a of the crystal element 12 and the trench metal-oxide-semiconductor field effect transistor element 10, a dielectric cap layer 119 (shown in FIG. 1I) is selectively covered, and the material of the dielectric cap layer 119 is covered. Preferably, it may comprise tantalum nitride, hafnium oxide or the like. This ensures that the conductor material 112 (polysilicon) filled in the second trench 110 is not damaged by the subsequent process of fabricating the planar channel metal oxide semiconductor field effect transistor element 12. Therefore, the channel length of the first gate electrode 111 can be controlled more accurately.

Subsequently, the planar via metal oxide semiconductor field effect transistor element 12 and the trench metal oxide semiconductor field effect transistor element 10 are integrated into a complementary metal oxide semiconductor by a semiconductor back-end process (not shown). Element 100.

Referring to FIG. 2A to FIG. 2H, FIG. 2A to FIG. 2H are schematic cross-sectional views showing a process of the complementary metal-oxide-semiconductor device 200 according to another preferred embodiment of the present invention. Wherein, a method of manufacturing the complementary metal oxide semiconductor device 200 includes the following steps:

First, a first region 201a and a second region 201b are defined on the substrate 201. In some embodiments of the present invention, the first region 201a and the second region 201b are preferably defined by a series of ion implantation processes according to the functional requirements of the transistor component. Two ion doped regions separated from each other are formed in the material 201. The first region 201a includes a first doping region 202. The second region 201b includes a third doping region 204 (as shown in FIG. 2A), and the third doping region 204 is electrically identical to the first doping region 202.

In the present embodiment, the substrate 201 includes an N-type buried layer 206 and a P-type epitaxial layer 207 on the buried layer 206. The first doped region 202 is an N-type well region extending from the substrate surface 201c into the P-type epitaxial layer 207. The third doped region 204 extends from the substrate surface 201c into another N-type well region of the P-type epitaxial layer 207. And the first doping region 202 and the third doping region 204 are separated from each other by the P-type epitaxial layer 207 of the substrate 201.

Thereafter, at least one isolation structure 208 is formed in the second region 201b. In one embodiment of the invention, the isolation structure 208 is a shallow trench isolation layer. As for the preparation method, a pad yttrium oxide layer and a tantalum nitride layer (not shown) are first grown on the surface 201c of the substrate; then a micro-etching process is performed to perform shallow trench etching, sequentially in the pad yttrium oxide. At least one shallow groove (not shown) is formed in the layer, the tantalum nitride layer and the substrate 201. The shallow trench is filled with a dielectric material, and a planarization process is performed on the dielectric material to form an isolation structure 208 as illustrated in FIG. 2B.

Next, an ion implantation process is performed to form a second doping region 203 among the substrates 201 of the first active region 201a. In some preferred embodiments of the present invention, the second doped region 203 is a P-type well region extending from the substrate surface 201c into the first doped region 202 (N-type well region) (as shown in FIG. 2C). Painted).

Thereafter, a patterned hard mask layer 220 is formed on the substrate 201 to cover the first region 201a and the second region 201b, and a portion of the substrate surface 201c of the first region 201a is exposed. In an embodiment of the invention, the patterned hard mask layer 220 comprises a hafnium oxide film layer and a tantalum nitride film layer. In yet another embodiment, the hard mask layer 220 comprises a thick yttrium oxide film layer and a tantalum nitride film layer. In the present embodiment, the hard mask layer 220 is prepared by first forming a tantalum nitride film layer 220a on the substrate 201 by using a deposition process; and depositing with tetraethoxy decane as a precursor. On the tantalum nitride film layer 220a, a thick ruthenium oxide film layer 220b is formed; and then patterned to expose a portion of the substrate surface 201c located in the first region 201a (as shown in FIG. 2D).

Next, the mask is etched using the patterned hard mask layer 220 to form at least one trench 210 in the first active region 201a. Then, on the sidewall 210a of the trench 210, a first gate dielectric layer 211 is formed (as shown in FIG. 2E). In some embodiments of the present invention, before forming the first gate dielectric layer 211, an oxidized sacrificial layer (not shown) is preferably formed on the sidewall 210a of the trench 210 to repair the damage caused by the etching to the sidewall 210a. . After removing the oxidized sacrificial layer, a first thyristor layer 211 is formed on the trench sidewalls 210a and the bottom by chemical vapor deposition, thermal oxidation, or other suitable methods. The material of the first gate dielectric layer 211 is preferably hafnium oxide.

Subsequently, the trench 210 is filled with a conductor material 212. In some embodiments of the present invention, the conductive material 212 is a polysilicon material that is overlaid on the first gate dielectric layer 211 by a deposition process and fills the trenches 210.

After filling the conductor material 212, the conductor material 212 is preferably planarized. First, a planarization layer 213, such as a ruthenium dioxide layer, is selectively formed over the conductor material 212 overlying the conductor material 212 (as depicted in Figure 2F). Thereafter, a chemical mechanical polishing process is performed to remove the flat layer 213, the hard mask layer 220, and a portion of the conductor material 212, and expose the substrate surface 201c.

Then, a full etching process is performed to remove a small portion of the conductor material 212 located in the second trench 210, and a portion of the conductive material 212 located in the second trench 210 and a portion of the first portion The gate dielectric layer 211 remains to form a trench metal oxide semiconductor field effect transistor element 20 (as depicted in Figure 2G).

It is worth noting that the function of the flat layer 213 is only used to planarize the surface depression formed by the filling process of the conductor material 212, and is used as a grinding buffer layer for the subsequent chemical mechanical polishing process. Therefore, in some embodiments of the present invention, after filling the conductor material 212, the planarization layer 213 is not formed, but the chemical mechanical polishing process is directly performed. Alternatively, after the planarization layer 213 is formed, selective etching is directly performed to remove the dielectric layer 209 and the conductor material 212 described above.

Wherein, a portion of the conductor material 212 remaining in the trench 210 is a vertical gate electrode 212a of the trench MOSFET field element 20; and a first gate dielectric layer at the trench sidewall 210a. 211 is a vertical gate oxide layer 211a of the trench MOSFET field effect element 20.

In addition, since the second doping region 203 and the first doping region 202 form a P/N junction 215; and the fourth doping region 205 has the same electrical property as the first doping region 202, and The two doped regions 203 form another P/N junction 214. Therefore, the fourth doping region 205 and the first doping region 202 may be respectively used as the source or drain of the trench MOSFET field element 20 (hereinafter referred to as the first source/drain); The second doped region 203 between the fourth doped region 205 and the first doped region 202 constitutes a channel of the trench MOSFET field element 20. Therefore, the doping depth of the second doping region 203 can determine the channel length of the trench MOSFET field element 20.

Next, a dielectric cap layer 219 is overlaid on the first region 201a, the second region 201b, and the vertical gate electrode 212a of the trench MOSFET. A second gate dielectric layer 217 is formed over the substrate surface 201c of the second region 201b, and a second gate electrode 218 is formed on the second gate dielectric layer 217. Then, through another ion implantation process, a plurality of (at least one) fourth doped regions 205 are formed adjacent to the first gate dielectric layer 211 and the vertical gate oxide layer 211a; and a second gate dielectric layer is formed. 217 and the second gate electrode 218 are masks, synchronized in the third doped region 204, defining a second source/drain structure 216 of the planar channel MOSFET field element 22 adjacent to the second gate Electrical layer 217 and second gate electrode 218 complete the fabrication of planar channel MOSFET field effect transistor 22 (as depicted in Figure 2H). As shown in FIG. 2H, the fourth doped region 205 is an N-type layer extending from the substrate surface 201c of the first active region 201a into the first doped region 202 and having a higher concentration of N-type dopants. Doped structure. The fourth doping region 205 is surrounded by the second doping region 203 (P-type well region).

Subsequently, the planar via metal oxide semiconductor field effect transistor element 22 and the trench metal oxide semiconductor field effect transistor element 20 are integrated into a complementary metal oxide semiconductor by a semiconductor back end process (not shown). Element 200.

According to the above embodiments, the present invention integrates a trench metal oxide semiconductor device and a process for fabricating a planar via metal oxide semiconductor device, thereby fabricating a trench metal oxide semiconductor structure and planar channel metal oxide. (Complementary) metal oxide semiconductor device of a semiconductor structure.

In some embodiments of the invention, the shallow trench isolation process in a planar channel metal oxide semiconductor process can be integrated with the trench etch step of a trench metal oxide semiconductor process. The use of a dielectric layer for forming a shallow trench isolation structure into an etch mask layer for forming trenches has the advantage of reducing manufacturing costs, achieving the above-described object of integrating semiconductor processes and structures and reducing process cost.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

10. . . Trenched metal oxide semiconductor field effect transistor

12. . . Planar channel metal oxide semiconductor field effect transistor

100. . . Complementary metal oxide semiconductor device

101. . . Substrate

101a. . . First district

101b. . . Second district

101c. . . Substrate surface

102. . . First doped region

103. . . Second doped region

104. . . Third doped region

105. . . Fourth doped region

106. . . Buried layer

107. . . P-type epitaxial layer

108. . . First groove

109. . . Dielectric layer

110. . . Second groove

110a. . . Side wall of the second groove

111. . . First gate dielectric layer

111a. . . Vertical gate oxide

112. . . Conductor material

112a. . . Vertical gate electrode

113. . . Flat layer

114. . . P/N junction

115. . . P/N junction

116. . . Second source/drain structure

117. . . Second gate dielectric layer

118. . . Second gate electrode

119. . . Dielectric overlay

S. . . Height difference

20. . . Trenched metal oxide semiconductor field effect transistor

twenty two. . . Planar channel metal oxide semiconductor field effect transistor

200. . . Complementary metal oxide semiconductor device

201. . . Substrate

201a. . . First district

201b. . . Second district

201c. . . Substrate surface

202. . . First doped region

203. . . Second doped region

204. . . Third doped region

205. . . Fourth doped region

206. . . Buried layer

207. . . P-type epitaxial layer

208. . . Isolation structure

210. . . Trench

210a. . . Side wall of the second groove

211. . . First gate dielectric layer

211a. . . Vertical gate oxide

212. . . Conductor material

212a. . . Vertical gate electrode

213. . . Flat layer

214. . . P/N junction

215. . . P/N junction

216. . . Second source/drain structure

217. . . Second gate dielectric layer

218. . . Second gate electrode

219. . . Dielectric overlay

220. . . Hard mask layer

220a. . . Tantalum nitride film layer

220b. . . Thick ruthenium oxide layer

1A through 1I are schematic cross-sectional views showing a process of a complementary metal-oxide-semiconductor device according to a preferred embodiment of the present invention.

2A through 2H are schematic cross-sectional views showing a process of a complementary metal oxide semiconductor device according to another preferred embodiment of the present invention.

10. . . Trenched metal oxide semiconductor field effect transistor

12. . . Planar channel metal oxide semiconductor field effect transistor

100. . . Complementary metal oxide semiconductor device

101. . . Substrate

101a. . . First active zone

101b. . . Second active area

102. . . First doped region

103. . . Second doped region

104. . . Third doped region

105. . . Fourth doped region

106. . . Buried layer

107. . . P-type epitaxial layer

109. . . Dielectric layer

111a. . . Vertical gate oxide

112a. . . Vertical gate electrode

114. . . P/N junction

115. . . P/N junction

116. . . Second source/drain structure

117. . . Second gate dielectric layer

118. . . Second gate electrode

119. . . Dielectric overlay

Claims (19)

A trench-gate metal oxide semiconductor (TMOS) device includes: a substrate having a first doped region, a second doped region, and at least one trench, wherein the first a doped region and the second doped region form a P/N junction, the trench extends from a substrate surface through the second doped region and the P/N junction, and enters the first doping a first gate dielectric layer on the sidewall of the trench; a first gate electrode located in the trench, and an upper surface of the first gate electrode and the surface of the substrate Between substantially less than 1500 a height difference; and a first source/drainage located in the substrate adjacent to the first gate dielectric layer. The trench MOS device of claim 1, further comprising a dielectric capping layer covering the upper surface of the first gate electrode. The trench MOS device of claim 1, wherein the first doped region is an N-type well region extending from the surface of the substrate into the substrate; the second doped region It is a P-type well region and extends from the surface of the substrate into the N-type well region. The trench MOS device of claim 3, wherein the substrate comprises: an N-type buried layer; a P-type epitaxial layer on the buried layer, and The N-well region is extended into the surface of the substrate. The trench MOS device of claim 3, wherein the first source/drain is an N-type doped structure; the surface of the substrate is along the trench The sidewall extends into the P-well region. The trench MOS device of claim 1, further comprising: a third doped region located in the substrate and separated from the first doped region, and having the same a doped region of the same electrical property; a second gate dielectric layer on the surface of the substrate of the third doped region; a second gate electrode on the second gate dielectric layer; and a A second source/drain structure is located in the third doped region adjacent to the second gate dielectric layer and has the same electrical property as the second doped region. A method of fabricating a trench MOS device includes: defining a first region and a second region on a substrate; forming at least one first trench in the second region; forming a dielectric a layer on the first region and the second region, and filling the first trench; using the dielectric layer as an etch mask layer, forming at least one second trench in the first region; forming a The first gate dielectric layer is on the sidewall of the second trench; and the second trench is filled with a conductive material to form a first gate electrode. The method for fabricating a trench MOS device according to claim 7, wherein before or after forming the second trench, further comprising the first region, forming a first source/汲Pole structure. The method of fabricating a trench metal oxide semiconductor device according to claim 7, wherein the dielectric layer is a chemical vapor deposited layer; and the conductive material is polycrystalline germanium. The method for fabricating a trench MOS device according to claim 7, wherein after filling the conductor material, further comprising: forming a flat layer overlying the conductor material; performing a chemical mechanical polishing Removing the planar layer, and a portion of the conductive material; and performing a blanket etching process to remove the conductive material and the dielectric layer on both surfaces of the first region and the second region. The method for manufacturing a trench metal oxide semiconductor device according to claim 10, after removing the conductive material and the dielectric layer, further comprising: forming a second gate over the second region a dielectric layer; a second gate electrode formed on the second gate dielectric layer; and a second source/drain structure formed in the second region. The method for manufacturing a trench MOS device according to claim 11, further comprising: covering the first gate electrode with a dielectric cover before forming the second source/drain structure Floor. A method of fabricating a trench metal oxide semiconductor device, comprising: defining a first region and a second region on a substrate; forming a patterned hard mask layer in the first region and the second region Forming the hard mask layer as a mask, performing an etching process to form at least one trench in the first region; forming a first gate dielectric layer on the sidewall of the trench; The trench is filled with a conductor material to form a first gate electrode. The method of fabricating a trench metal oxide semiconductor device according to claim 13, wherein before the step of forming the patterned hard mask layer, the method further comprises: forming at least one isolation structure in the second region in. The method of fabricating a trench metal oxide semiconductor device according to claim 14, wherein the isolation structure is a shallow trench isolator; the conductor material is polysilicon. The method for fabricating a trench metal oxide semiconductor device according to claim 13, wherein the patterned hard mask layer comprises a hafnium oxide thin film layer and a tantalum nitride thick film layer, or a tantalum oxide layer a film layer and a tantalum nitride film layer. The method of manufacturing a trench MOS device according to claim 13, wherein after filling the conductor material, further comprising: forming a flat layer covering the conductor material; performing a chemical mechanical polishing removal The planarization layer, and a portion of the conductor material; and performing a full etch process to remove the conductor material and the patterned hard mask layer on both surfaces of the first region and the second region. The method for manufacturing a trench MOS device according to claim 17, after removing the conductive material and the patterned hard mask layer, further comprising: forming a layer over the second region a second gate dielectric layer; and a second gate electrode formed on the second gate dielectric layer; and a second source/drain structure in the second region. The method for fabricating a trench MOS device according to claim 18, further comprising: covering the first gate electrode with a dielectric cover before forming the second source/drain structure Floor.