TW201308544A - Chip package structure and manufacturing method thereof - Google Patents
Chip package structure and manufacturing method thereof Download PDFInfo
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- TW201308544A TW201308544A TW100127432A TW100127432A TW201308544A TW 201308544 A TW201308544 A TW 201308544A TW 100127432 A TW100127432 A TW 100127432A TW 100127432 A TW100127432 A TW 100127432A TW 201308544 A TW201308544 A TW 201308544A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Abstract
Description
本發明是有關於一種半導體封裝技術，且特別是有關於一種晶片封裝結構及其製作方法。The present invention relates to a semiconductor package technology, and more particularly to a chip package structure and a method of fabricating the same.
一般而言，積體電路(integrated circuit，IC)製造完成後需經過封裝製程來保護晶片免於外力破壞，並且將晶片上的電極透過載板擴大電極間距而引接至外部裝置(例如：印刷電路板、顯示面板等)。球格陣列封裝(Ball Grid Array，BGA)、薄膜覆晶(chip-on-film，COF)封裝皆為常見的封裝技術。Generally, an integrated circuit (IC) is subjected to a packaging process to protect the wafer from external force damage, and the electrodes on the wafer are connected to an external device through the carrier plate to enlarge the electrode spacing (for example, a printed circuit). Board, display panel, etc.). Ball Grid Array (BGA) and chip-on-film (COF) packages are common packaging technologies.
電子產品的功能不斷地擴充而體積及重量則不斷地縮小，促使晶片功能需求持續增加，相對應地I/O端點數目增加，而晶片尺寸則持續在縮小，晶片與載板之間的間距亦隨之縮小。然而，晶片功能增加伴隨而來的還有運作過程中產生的熱亦增加，而熱對於元件效能的影響也趨於明顯。The functions of electronic products continue to expand and the volume and weight continue to shrink, which has led to an increase in the demand for wafer functions. The number of corresponding I/O terminals has increased, while the size of the wafers has continued to shrink, and the gap between the wafer and the carrier. It also shrinks. However, the increase in wafer function is accompanied by an increase in heat generated during operation, and the effect of heat on component performance tends to be significant.
為了解決散熱問題，在目前的技術中，一般皆是在晶片的背面(與主動面相對的表面)上貼附散熱片，以藉由散熱片將晶片在運作過程中所產生的熱排出。隨著晶片尺寸縮小，散熱片的尺寸也必須縮小。然而，散熱片尺寸的縮小有其限制及困難度，且將小尺寸散熱片貼設於晶片，在製程上也越趨困難。In order to solve the heat dissipation problem, in the current technology, a heat sink is generally attached on the back surface of the wafer (the surface opposite to the active surface) to discharge the heat generated by the wafer during operation by the heat sink. As the size of the wafer shrinks, the size of the heat sink must also shrink. However, there are limitations and difficulties in reducing the size of the heat sink, and it is more difficult to process the small-sized heat sink on the wafer.
本發明提供一種晶片封裝結構，其具有較大的散熱面積及較佳散熱效果。The invention provides a chip package structure, which has a large heat dissipation area and a better heat dissipation effect.
本發明另提供一種晶片封裝結構的製作方法，其可形成具有較大散熱面積及較佳散熱效果的晶片封裝結構。The invention further provides a method for fabricating a chip package structure, which can form a chip package structure having a large heat dissipation area and a better heat dissipation effect.
本發明提出一種晶片封裝結構，其包括載板、晶片、封裝膠體、金屬層以及多個第一金屬球。晶片具有主動表面以及與主動表面相對的背面。主動表面上設置有多個凸塊。晶片藉由這些凸塊與載板電性連接。封裝膠體至少填充於晶片與載板之間，以包覆凸塊。金屬層形成於晶片的背面上。第一金屬球配置於金屬層上。The present invention provides a wafer package structure including a carrier, a wafer, an encapsulant, a metal layer, and a plurality of first metal balls. The wafer has an active surface and a back surface opposite the active surface. A plurality of bumps are disposed on the active surface. The bumps are electrically connected to the carrier by the bumps. The encapsulant is at least filled between the wafer and the carrier to cover the bumps. A metal layer is formed on the back side of the wafer. The first metal ball is disposed on the metal layer.
依照本發明實施例所述之晶片封裝結構，更包括堆疊設置於第一金屬球上的多個第二金屬球。The chip package structure according to the embodiment of the invention further includes a plurality of second metal balls stacked on the first metal ball.
依照本發明實施例所述之晶片封裝結構，上述之第一金屬球及第二金屬球的種類例如為結線凸塊或錫球。According to the chip package structure of the embodiment of the invention, the type of the first metal ball and the second metal ball are, for example, a line bump or a solder ball.
依照本發明實施例所述之晶片封裝結構，上述之第一金屬球及第二金屬球的材料例如為金、銀、鋁、銅或錫。According to the chip package structure of the embodiment of the invention, the material of the first metal ball and the second metal ball is, for example, gold, silver, aluminum, copper or tin.
依照本發明實施例所述之晶片封裝結構，上述之第一金屬球的高度例如大於或等於20 μm。According to the chip package structure of the embodiment of the invention, the height of the first metal ball is, for example, greater than or equal to 20 μm.
本發明另提出一種晶片封裝結構的製作方法，此方法包括以下步驟：於晶片的背面上形成金屬層；於金屬層上形成多個第一金屬球；將晶片的主動表面面向載板，並藉由多個凸塊使晶片與載板電性連接；形成封裝膠體，至少填充於晶片與載板之間，以包覆凸塊。The invention further provides a method for fabricating a chip package structure, the method comprising the steps of: forming a metal layer on the back surface of the wafer; forming a plurality of first metal balls on the metal layer; facing the active surface of the wafer toward the carrier plate, and borrowing The wafer is electrically connected to the carrier by a plurality of bumps; and the encapsulant is formed to be filled at least between the wafer and the carrier to cover the bumps.
依照本發明實施例所述之晶片封裝結構的製作方法，上述之在形成第一金屬球之後，還可以於第一金屬球上堆疊設置多個第二金屬球。According to the method of fabricating a chip package structure according to the embodiment of the invention, after forming the first metal ball, a plurality of second metal balls may be stacked on the first metal ball.
依照本發明實施例所述之晶片封裝結構的製作方法，上述之第一金屬球及第二金屬球的種類例如為結線凸塊或錫球。According to the method of fabricating a chip package structure according to the embodiment of the invention, the first metal ball and the second metal ball are, for example, a wire bump or a solder ball.
依照本發明實施例所述之晶片封裝結構的製作方法，上述之第一金屬球及第二金屬球的材料例如為金、銀、鋁、銅或錫。According to the method of fabricating a chip package structure according to the embodiment of the invention, the material of the first metal ball and the second metal ball is, for example, gold, silver, aluminum, copper or tin.
依照本發明實施例所述之晶片封裝結構的製作方法，上述之第一金屬球的高度例如大於或等於20 μm。According to the method of fabricating a chip package structure according to an embodiment of the invention, the height of the first metal ball is, for example, greater than or equal to 20 μm.
依照本發明實施例所述之晶片封裝結構的製作方法，上述之於晶片的背面上形成金屬層的方法例如是先於晶圓的背面上形成金屬層。之後，切割晶圓，以形成多個晶片。According to the method for fabricating a chip package structure according to the embodiment of the invention, the method for forming a metal layer on the back surface of the wafer is, for example, forming a metal layer on the back surface of the wafer. Thereafter, the wafer is diced to form a plurality of wafers.
依照本發明實施例所述之晶片封裝結構的製作方法，上述之第一金屬球例如於晶片與載板電性連接之後形成。According to the method of fabricating a chip package structure according to the embodiment of the invention, the first metal ball is formed, for example, after the wafer is electrically connected to the carrier.
依照本發明實施例所述之晶片封裝結構的製作方法，上述之第一金屬球例如於封裝膠體形成之後形成。According to the method of fabricating a chip package structure according to an embodiment of the invention, the first metal ball is formed, for example, after the encapsulant is formed.
基於上述，本發明於晶片的背面上形成金屬層，且於金屬層上形成有金屬球，不僅可以有效地增加晶片封裝結構的散熱面積，以利晶片封裝結構的散熱，並且亦大幅提升於小尺寸晶片上形成散熱結構的可行性及便利性。Based on the above, the present invention forms a metal layer on the back surface of the wafer, and forms a metal ball on the metal layer, which not only can effectively increase the heat dissipation area of the chip package structure, but also facilitates heat dissipation of the chip package structure, and is also greatly improved. Feasibility and convenience of forming a heat dissipation structure on a wafer.
為讓本發明之上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。The above described features and advantages of the present invention will be more apparent from the following description.
圖1A至圖1C為依照本發明一實施例所繪示的晶片封裝結構的製作方法的剖面示意圖。首先，請參照圖1A，於晶片100的背面100a上形成金屬層102。在一實施例中，於晶片100的背面100a上形成金屬層102的方法例如是先於晶圓的背面上形成金屬層102，然後對晶圓進行切割，以形成多個晶片100。或者，在另一實施例中，也可以是先對晶圓進行切割而形成多個晶片100，然後再於每一個晶片100的背面100a上形成金屬層102。金屬層102的材料例如為金、鋁、銅、鉻、鈦或鈦鎢。金屬層102例如是藉由物理氣相沈積法形成於晶圓或晶片100上。舉例來說，金屬層102可以濺鍍的方式形成於晶圓或晶片100之背面100a上。1A-1C are schematic cross-sectional views showing a method of fabricating a chip package structure according to an embodiment of the invention. First, referring to FIG. 1A, a metal layer 102 is formed on the back surface 100a of the wafer 100. In one embodiment, the method of forming the metal layer 102 on the back surface 100a of the wafer 100 is, for example, forming a metal layer 102 on the back side of the wafer, and then cutting the wafer to form a plurality of wafers 100. Alternatively, in another embodiment, the wafer may be first diced to form a plurality of wafers 100, and then the metal layer 102 may be formed on the back surface 100a of each of the wafers 100. The material of the metal layer 102 is, for example, gold, aluminum, copper, chromium, titanium or titanium tungsten. The metal layer 102 is formed on the wafer or wafer 100 by, for example, physical vapor deposition. For example, the metal layer 102 can be formed on the back side 100a of the wafer or wafer 100 by sputtering.
然後，請參照圖1B，以晶片100的主動表面100b(與背面100a相對的表面)面向載板104的覆晶方式，將晶片100裝設於載板104上，並藉由凸塊106使晶片100與載板104之電性端點電性連接。載板104例如為可撓性載板或硬式載板。可撓性載板的材料可選自聚醯亞胺(polyimide，PI)、聚酯類化合物(polyethylene terephthalate，PET)或其他合適的可撓性材料。硬式載板的材料可選自FR4、FR5、雙順丁烯二酸醯亞胺-三氮雜苯(bismaleimide triazine，BT)或其他合適的材料。凸塊106之種類包含電鍍凸塊、無電鍍凸塊、結線凸塊、導電聚合物凸塊或金屬複合凸塊。本實施例以可撓性載板為例，可撓性載板104包含基材層104a以及設置於基材層104a上的多個引腳104b。晶片100是以凸塊106對應連接引腳104b而與可撓性載板104電性連接。在將晶片100與可撓性載板104電性連接之後，接著形成封裝膠體108。於本實施例中，封裝膠體108至少填充於晶片100與可撓性載板104之間，以包覆凸塊106，藉以防止濕氣及汙染物進入，進而保護凸塊106與可撓性載板104之引腳104b的電性連接點。Then, referring to FIG. 1B, the wafer 100 is mounted on the carrier 104 by the flip chip of the active surface 100b of the wafer 100 (the surface opposite to the back surface 100a) facing the carrier 104, and the wafer is made by the bumps 106. 100 is electrically connected to the electrical terminals of the carrier board 104. The carrier 104 is, for example, a flexible carrier or a rigid carrier. The material of the flexible carrier may be selected from the group consisting of polyimide (PI), polyethylene terephthalate (PET) or other suitable flexible materials. The material of the rigid carrier may be selected from the group consisting of FR4, FR5, bismaleimide triazine (BT) or other suitable materials. The types of bumps 106 include plated bumps, electroless bumps, wire bumps, conductive polymer bumps, or metal composite bumps. In this embodiment, a flexible carrier is exemplified. The flexible carrier 104 includes a substrate layer 104a and a plurality of pins 104b disposed on the substrate layer 104a. The wafer 100 is electrically connected to the flexible carrier 104 by the bumps 106 corresponding to the connection pins 104b. After the wafer 100 is electrically connected to the flexible carrier 104, the encapsulant 108 is then formed. In the present embodiment, the encapsulant 108 is at least filled between the wafer 100 and the flexible carrier 104 to cover the bumps 106, thereby preventing moisture and contaminants from entering, thereby protecting the bumps 106 and the flexible carrier. The electrical connection point of the pin 104b of the board 104.
之後，請參照圖1C，於金屬層102上形成多個第一金屬球110，以形成晶片封裝結構10。晶片封裝結構10可藉由第一金屬球110來達成散熱的目的。第一金屬球110例如為結線凸塊或錫球。當第一金屬球110為結線凸塊時，其是利用打線機以打線(wire bond)的方式形成於金屬層102上。當第一金屬球110為錫球時，其是可利用網板印刷、電鍍或植球的方式先將銲錫形成於金屬層102上，再經過回銲(reflow)步驟形成金屬球並使其黏固於金屬層102上。第一金屬球110的材料也可以為金、銀、鋁或銅。第一金屬球110的高度可大於或等於20 μm。Thereafter, referring to FIG. 1C, a plurality of first metal balls 110 are formed on the metal layer 102 to form the chip package structure 10. The chip package structure 10 can achieve the purpose of heat dissipation by the first metal ball 110. The first metal ball 110 is, for example, a knot bump or a solder ball. When the first metal ball 110 is a junction bump, it is formed on the metal layer 102 by wire bonding using a wire bonding machine. When the first metal ball 110 is a solder ball, the solder can be formed on the metal layer 102 by screen printing, electroplating or ball planting, and then the metal ball is formed and adhered by a reflow process. It is fixed on the metal layer 102. The material of the first metal ball 110 may also be gold, silver, aluminum or copper. The height of the first metal ball 110 may be greater than or equal to 20 μm.
在本實施例中，由於晶片100的背面100a上形成有金屬層102，且金屬層102上形成有第一金屬球110，因此晶片於運作中產生的熱可以直接經由晶片100背面100a上的第一金屬球110傳導消散，並且透過多個第一金屬球110可以有效地增加晶片封裝結構10的散熱面積，以利於晶片封裝結構10的散熱。再者，以打線製程或植球步驟形成第一金屬球110，較不受晶片尺寸縮小之限制，可適用於小尺寸晶片，且在製程上亦較為容易及便利。In this embodiment, since the metal layer 102 is formed on the back surface 100a of the wafer 100, and the first metal ball 110 is formed on the metal layer 102, the heat generated in the operation of the wafer can directly pass through the first surface 100a of the wafer 100. A metal ball 110 is conductively dissipated, and the heat dissipation area of the chip package structure 10 can be effectively increased by the plurality of first metal balls 110 to facilitate heat dissipation of the chip package structure 10. Furthermore, the first metal ball 110 is formed by a wire bonding process or a ball implantation step, which is less than the size limitation of the wafer, and is applicable to a small-sized wafer, and is also relatively easy and convenient in the process.
在上述實施例中，第一金屬球110於封裝膠體108形成之後形成。在其他實施例中，也可以在晶片100與載板104電性連接之後先形成第一金屬球110，然後再形成封裝膠體108。In the above embodiment, the first metal ball 110 is formed after the encapsulant 108 is formed. In other embodiments, the first metal ball 110 may be formed after the wafer 100 is electrically connected to the carrier 104, and then the encapsulant 108 is formed.
此外，在上述實施例中，第一金屬球110形成於晶片100與載板104電性連接之後。在其他實施例中，也可以在晶片100與載板104電性連接之前先將第一金屬球110形成於金屬層102上，然後再將晶片100與載板104電性連接。Further, in the above embodiment, the first metal ball 110 is formed after the wafer 100 is electrically connected to the carrier 104. In other embodiments, the first metal ball 110 may be formed on the metal layer 102 before the wafer 100 is electrically connected to the carrier 104, and then the wafer 100 is electrically connected to the carrier 104.
為了進一步增加晶片封裝結構10的散熱面積，在形成第一金屬球110之後，還可以於第一金屬球110上形成第二金屬球。In order to further increase the heat dissipation area of the chip package structure 10, after the first metal ball 110 is formed, a second metal ball may be formed on the first metal ball 110.
圖2為依照本發明另一實施例所繪示的晶片封裝結構的剖面示意圖。請參照圖2，在晶片封裝結構20中，第二金屬球112形成於第一金屬球110上，且每一個第二金屬球112分別堆疊於一個第一金屬球110上。如此一來，晶片封裝結構20與晶片封裝結構10相比可以具有更大的散熱面積，更有利於晶片封裝結構的散熱。第二金屬球112的材料例如為金、銀、鋁、銅或錫。第二金屬球112的高度可大於或等於20 μm。當然，視實際需求，還可以於第二金屬球112上以相同的方式形成金屬球，以增加晶片封裝結構的散熱面積。2 is a cross-sectional view of a chip package structure in accordance with another embodiment of the present invention. Referring to FIG. 2, in the chip package structure 20, the second metal balls 112 are formed on the first metal balls 110, and each of the second metal balls 112 is stacked on a first metal ball 110. As a result, the chip package structure 20 can have a larger heat dissipation area than the chip package structure 10, which is more advantageous for heat dissipation of the chip package structure. The material of the second metal ball 112 is, for example, gold, silver, aluminum, copper or tin. The height of the second metal ball 112 may be greater than or equal to 20 μm. Of course, metal balls can be formed on the second metal ball 112 in the same manner according to actual needs to increase the heat dissipation area of the chip package structure.
圖3為依照本發明另一實施例所繪示的晶片封裝結構的剖面示意圖。請參照圖3，晶片封裝結構30與晶片封裝結構20的差異在於：第二金屬球112是錯開排列於第一金屬球110上，每一個第二金屬球112分別堆疊於兩相鄰的第一金屬球110上。當然，視實際需求，還可以於第二金屬球112上以相同的方式形成金屬球，以增加晶片封裝結構的散熱面積。3 is a cross-sectional view of a chip package structure in accordance with another embodiment of the present invention. Referring to FIG. 3, the difference between the chip package structure 30 and the chip package structure 20 is that the second metal balls 112 are staggered on the first metal ball 110, and each of the second metal balls 112 is stacked on the two adjacent first. On the metal ball 110. Of course, metal balls can be formed on the second metal ball 112 in the same manner according to actual needs to increase the heat dissipation area of the chip package structure.
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作些許之更動與潤飾，故本發明之保護範圍當視後附之申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
10、20、30．．．晶片封裝結構10, 20, 30. . . Chip package structure
100．．．晶片100. . . Wafer
100a．．．背面100a. . . back
100b．．．主動表面100b. . . Active surface
102．．．金屬層102. . . Metal layer
104．．．載板104. . . Carrier board
104a．．．基材層104a. . . Substrate layer
104b．．．引腳104b. . . Pin
106．．．凸塊106. . . Bump
108．．．封裝膠體108. . . Encapsulant
110．．．第一金屬球110. . . First metal ball
112．．．第二金屬球112. . . Second metal ball
圖1A至圖1C為依照本發明一實施例所繪示的晶片封裝結構的製作方法的剖面示意圖。1A-1C are schematic cross-sectional views showing a method of fabricating a chip package structure according to an embodiment of the invention.
圖2為依照本發明另一實施例所繪示的晶片封裝結構的剖面示意圖。2 is a cross-sectional view of a chip package structure in accordance with another embodiment of the present invention.
圖3為依照本發明另一實施例所繪示的晶片封裝結構的剖面示意圖。3 is a cross-sectional view of a chip package structure in accordance with another embodiment of the present invention.
10．．．晶片封裝結構10. . . Chip package structure
100．．．晶片100. . . Wafer
102．．．金屬層102. . . Metal layer
104．．．載板104. . . Carrier board
104a．．．基材層104a. . . Substrate layer
104b．．．引腳104b. . . Pin
106．．．凸塊106. . . Bump
108．．．封裝膠體108. . . Encapsulant
110．．．第一金屬球110. . . First metal ball
Claims (13)
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| TW100127432A TW201308544A (en) | 2011-08-02 | 2011-08-02 | Chip package structure and manufacturing method thereof |
| CN2011103079740A CN102915979A (en) | 2011-08-02 | 2011-09-29 | Chip packaging structure and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| TW100127432A TW201308544A (en) | 2011-08-02 | 2011-08-02 | Chip package structure and manufacturing method thereof |
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| TW201308544A true TW201308544A (en) | 2013-02-16 |
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| TW529112B (en) * | 2002-01-07 | 2003-04-21 | Advanced Semiconductor Eng | Flip-chip packaging having heat sink member and the manufacturing process thereof |
| US20050258536A1 (en) * | 2004-05-21 | 2005-11-24 | Taiwan Semiconductor Manufacturing Co., Ltd. | Chip heat sink device and method |
| TW200830488A (en) * | 2007-01-10 | 2008-07-16 | Siliconware Precision Industries Co Ltd | Heat-dissipating semiconductor package |
| TWI395312B (en) * | 2010-01-20 | 2013-05-01 | 矽品精密工業股份有限公司 | Package structure having mems element and method of making the same |
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