TW201308515A - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

A semiconductor structure is provided in the present invention. The semiconductor structure includes a substrate, a first material layer and a second material layer. A trench region is defined on the substrate. The trench region includes two separated first regions and a second region, wherein the second region is adjacent to and between the two first regions. The first material layer is disposed on the substrate outside the trench region. The second material layer is disposed in the second region and is level with the first material layer.

Description

Semiconductor structure and its manufacturing method

The present invention relates to a semiconductor structure and a method of fabricating the same, and more particularly to a semiconductor structure having two dielectric layers on a substrate in the same layer structure and a method of fabricating the same.

In the semiconductor process, in order to smoothly transfer the pattern of integrated circuits to the semiconductor wafer, the circuit pattern must first be designed on a mask layout, and then the mask pattern output according to the mask layout. (photomask pattern) to make a reticle, and transfer the pattern on the reticle to the semiconductor wafer in a certain proportion, which is commonly known as lithography.

With the rapid increase of the integrated level of semiconductor circuits, the linewidth required by lithography has also evolved from the original 65 nanometers (nm) to 45 meters, or even 32 micrometers, which makes semiconductor components The distance is getting shorter. However, due to the influence of the optical proximity effect (OPE), the distance of the above components has reached its limit in the exposure process. For example, in order to obtain a small-sized component, the pitch of the light-transmitting region of the photomask will be reduced in accordance with the size of the device, but if the interval between the light-transmitting regions is reduced to a specific range (the exposure wavelength is 1/2) Or when the light passing through the reticle is diffracted, which affects the resolution of the transferred pattern, causing deviations in the pattern on the photoresist, such as right-angled comer rounded ), line end shortened, and line width increase/decrease are all defects of the photoresist pattern caused by the common optical proximity effect.

A dual exposure technique has been developed to reduce the effects of optical proximity effects by using two exposure processes to form the desired pattern. However, there are still many problems with the existing double exposure technology that need to be overcome.

The present invention thus proposes a semiconductor structure and a method of fabricating the same that avoids the effects of optical proximity effects and forms the pattern to be formed.

According to an embodiment, the present invention provides a semiconductor structure including a substrate, a first material layer, and a second material layer. A trench region is defined on the substrate, the trench region has two first regions that are not adjacent, and a second region is located between the two first regions and adjacent to the first regions. The first material layer is disposed in a region other than the trench region of the substrate. The second material layer is disposed in the second region, and the second material layer is aligned with the first material layer.

According to another embodiment, the present invention provides a method of forming a semiconductor structure. First, a substrate is defined. A trench region is defined on the substrate. The trench region has two first regions that are not adjacent to each other, and a second region is located between the two first regions and adjacent to the first regions. Forming a first material layer on the substrate, and then removing the first material layer in the trench region to form a first patterned material layer. A second patterned material layer is then formed in the first region on the substrate, wherein the first patterned material layer and the second patterned material layer are uniform.

The present invention forms a special semiconductor structure by means of double exposure, and the formed semiconductor structure has a trench or strip structure which can have a pattern similar to a rectangle, avoiding the optical proximity effect in the prior art. The resulting rounded corners are rounded.

The present invention will be further understood by those skilled in the art to which the present invention pertains. The effect.

Please refer to FIG. 1A, FIG. 1B, FIG. 2A, FIG. 2B, FIG. 3A and FIG. 3B, which are schematic diagrams showing the steps of forming a semiconductor structure in the first embodiment of the present invention, wherein FIG. 1A and FIG. 2A and 3A are cross-sectional views of 1B, 2B, and 3B, respectively, and are drawn along the line AA' in the 1B. As shown in FIG. 1A and FIG. 1B, a substrate 300 is first provided. The substrate 300 may include a substrate having a semiconductor material, such as a silicon substrate, an epitaxial silicon substrate, a silicon germanium substrate, a silicon carbide substrate, or a germanium coating. a silicon-on-insulator (SOI) substrate, which may also comprise a substrate having a non-semiconductor material, such as a glass substrate, to form a thin-film-transistor display device thereon, or It is a fused quartz to form a photomask thereon. In another embodiment, the substrate 300 may include different doping regions, one or more layers of dielectric layers or a plurality of metal interconnection systems, and have one or A plurality of microelectronic components are disposed therein, such as a complementary metal oxide semiconductor (CMOS) or a photo-diode. Next, a first patterned material layer 306 is formed on the substrate 300, such as a poly-silicon layer. The first patterned material layer 306 has a plurality of first strip structures 306a that are substantially parallel to each other in a first direction 301. The first patterned material layer 306 is formed by, for example, forming a first material layer (not shown) on the substrate 300, and then forming a patterned photoresist layer (not shown) on the first material layer, and The etching process is performed by patterning the photoresist layer as a mask to form a first patterned material layer 306.

As shown in FIGS. 2A and 2B, a patterned photoresist layer 308 is formed on the first patterned material layer 306. The patterned photoresist layer 308 has a trench 308a to expose a portion of the first patterned material layer 306. In a preferred embodiment of the invention, the trench 308a extends in a second direction 303 that is substantially perpendicular to the first direction 301.

As shown in FIGS. 3A and 3B, an etching process is performed by patterning the photoresist layer 308 as a mask, and the first patterned material layer 306 exposed by the trench 308a is removed to form a second patterned material layer 312. . After the etching process, the strip structures 306a in the first patterned material layer 306 are cut off to form a second strip structure 312a and a third strip structure 312b. The second strip structure 312a and the third strip structure 312b have a pattern approximate to a rectangle. Through the foregoing manner, the rounding of the right angle corner due to the optical proximity effect in the prior art can be avoided. Finally, the patterned photoresist layer 308 is removed.

Please refer to FIG. 4A, FIG. 4B, FIG. 5A, FIG. 5B, FIG. 6A, FIG. 6B, FIG. 7A and FIG. 7B, and illustrate the steps of forming a semiconductor structure in the second embodiment of the present invention. Schematic diagram, wherein FIG. 4A, FIG. 5A, FIG. 6A, and FIG. 7A are cross-sectional views of FIG. 4B, FIG. 5B, FIG. 6B, and FIG. 7B, respectively, and along the BB' tangent line in FIG. 4B. Drawn. As shown in FIGS. 4A and 4B, a substrate 400 is first provided. The embodiment of the substrate 400 is as described in the first embodiment, and details are not described herein. A first patterned material layer 406 is then formed on the substrate 400. The first patterned material layer 406 has a plurality of first trenches 406a substantially parallel to a first direction 401. The material of the first patterned material layer 406 may comprise a material suitable as a hard mask, such as silicon nitride (SiN), metal or an advanced pattern film (APF) provided by Applied Materials. It may also comprise a material suitable as an inter-dielectric layer (ILD) or an inter-metal dielectric layer (IMD), such as silicon dioxide (SiO ₂ ).

As shown in FIGS. 5A and 5B, a second substance layer 412 is entirely formed on the substrate 400. The second material layer 412 fills at least the first trench 406a in the first patterned material layer 406. In a preferred embodiment of the present invention, the material of the second material layer 412 may be a material suitable as a hard mask, such as tantalum nitride, metal or an advanced patterned film, or may be suitable as a general inner dielectric. The material of the layer or the dielectric layer between the metal layers, such as cerium oxide. It should be noted that the material of the second material layer 412 has an etching selectivity ratio with the material of the first patterned material layer 406. For example, the first patterned material layer 406 may be a chemical vapor deposited (CVD) germanium dioxide, and the second material layer 412 may be a spin-on dielectric layer (SOD), or The first patterned material layer 406 and the second material layer 412 may be formed by chemical vapor deposition by adjusting a difference in carbon content and a pore density to form a dielectric layer having a different etching rate.

As shown in FIGS. 6A and 6B, a patterned photoresist layer 408 is formed on the second material layer 412. The patterned photoresist layer 408 has at least one strip structure 408a that extends a second direction 403 that is substantially perpendicular to the first direction 401. The strip structure 408a will cover a portion of the first trench 406a. The strip structure 408 has a width W2 that is substantially equal to the critical dimension (CD) that the exposure station can form on the substrate 400.

As shown in FIG. 7A and FIG. 7B, an etching process is performed by patterning the photoresist layer 408 as a mask, and the second material layer 412 not covered by the patterned photoresist layer 408 is removed to form a second. Patterned material layer 414. Since there is an etch selectivity ratio between the second material layer 412 and the first patterned material layer 406, the pattern of the strip structure 408a of the patterned photoresist layer 408 is only transferred into the second material layer 412, so that the second The substance layer 412 forms a second patterned material layer 414. As shown in FIGS. 7A and 7B, the second patterned material layer 414 has a separation structure 414a, the first trench 406a of the first patterned material layer 406 is disposed, and the first trench 406a is disposed. Separate into a second trench 406b and a third trench 406c. The second trench 406b and the third trench 406c have a pattern that approximates a rectangle. The partition structure 414a also has a pattern similar to a rectangle, and the rectangle has a width W2. Through the foregoing manner, it is possible to avoid the rounding of the right-angled corner caused by the optical proximity effect in the prior art. Finally, the patterned photoresist layer 408 is removed.

Please refer to FIG. 8 , which is a schematic diagram showing the steps of forming a semiconductor structure in an embodiment of the present invention. As shown in FIG. 8, when the material of the first patterned material layer 406 and the second patterned material layer 414 is a hard mask material, after the steps of FIGS. 7A and 7B are completed, the processing can be continued. An etching step. For example, the first patterned material layer 406 and the second patterned material layer 414 are masked to etch the substrate 400, and a fourth trench 400b and a fifth trench 400c are formed in the substrate 400. Similarly, the fourth trench 400b and the fifth trench 400c have a pattern similar to a rectangle.

Please refer to FIG. 9, which is a schematic diagram showing the steps of forming a semiconductor structure in an embodiment of the present invention. As shown in FIG. 9, when the material of the first patterned material layer 406 and the second patterned material layer 414 is a dielectric material, after the steps of FIGS. 7A and 7B are completed, the second A third material layer 416 is formed in the trench 406b and the third trench 406c. For example, after a third material layer is completely formed on the substrate 400, a planarization process is performed to make the first patterned material layer 406, the second patterned material layer 414, and the third material layer 416 high. In a preferred embodiment of the present invention, the third material layer 416 comprises a conductive material such as a metal, and is electrically connected to an internal metal wiring system (not shown) or a microelectronic component (not shown) in the substrate 400.

Please refer to FIG. 10A, FIG. 10B, FIG. 11A, FIG. 11B, FIG. 12A, FIG. 12B, FIG. 13A and FIG. 13B, and illustrate the steps of forming a semiconductor structure in the third embodiment of the present invention. Schematic diagram, wherein FIG. 10A, FIG. 11A, FIG. 12A, and FIG. 13A are cross-sectional views of FIG. 10B, FIG. 11B, FIG. 12B, and FIG. 13B, respectively, and along the CC' tangent line in FIG. 10B. Drawn. A substrate 500 is first provided. The embodiment of the substrate 500 is as described in the first embodiment, and details are not described herein. Next, a first patterned material layer 506 is formed on the substrate 500. The first patterned material layer 506 will have a spacer structure 506a extending in a second direction 503 and having a width W3. The width W3 is substantially equal to the critical dimension that the exposure station can form on the substrate 500. The material of the first patterned material layer 506 may comprise a material suitable as a hard mask, such as tantalum nitride, metal or an advanced patterned film, or may be suitable as an inner dielectric layer or a metal interlayer dielectric layer. Material such as cerium oxide.

As shown in FIGS. 11A and 11B, a second substance layer 512 is formed on the substrate 500, and the second substance layer 512 is aligned with the first patterned substance layer 506. For example, a second material layer 512 may be deposited on the substrate 500 and then subjected to a planarization process, such as a chemical mechanical polish (CMP) process or an etching back process. The second material layer 512 is at the same level as the first patterned material layer 506. In the preferred embodiment of the present invention, the material of the second material layer 512 may be a material suitable as a hard mask, such as tantalum nitride or metal or an advanced patterned film, or may be suitable as a general inner dielectric. The material of the layer or the dielectric layer between the metal layers, such as cerium oxide. It should be noted that the material of the second material layer 512 has an etching selectivity ratio with the material of the first patterned material layer 506.

As shown in FIGS. 12A and 12B, a patterned photoresist layer 508 is formed on the first patterned material layer 506 and the second material layer 512. The patterned photoresist layer 508 has a plurality of trenches 508a. The trenches 508a are substantially parallel to each other in a first direction 501. In a preferred embodiment of the invention, the first direction 501 will be substantially perpendicular to the second direction 503.

As shown in FIG. 13A and FIG. 13B, an etching process is performed by patterning the photoresist layer 508 as a mask, and the second material layer 512 not covered by the patterned photoresist layer 508 is removed to form a second. The material layer 514 is patterned. Since there is an etch selectivity ratio between the second material layer 512 and the first patterned material layer 506, the pattern of the trench 508a of the patterned photoresist layer 508 is only transferred into the second material layer 512, so that the second material layer 512 forms a second patterned material layer 514. As shown in FIG. 13A and FIG. 13B, the second patterned material layer 514 may include a plurality of second trenches 514b and a plurality of third trenches 514c, each of the second trenches 514b corresponding to a third trench 514c, and each The second trench 514b and the third trench 514c are separated by a partition structure 506a of the first patterned material layer 506. It should be noted that the partition structure 506a of the first patterned material layer 506 of the present embodiment connects two or more sets of the second trench 514b and the third trench 514c. The second trench 514b and the third trench 514c have a pattern that approximates a rectangle. Through the foregoing manner, it is possible to avoid the rounding of the right-angled corner caused by the optical proximity effect in the prior art. Finally, the patterned photoresist layer 508 is removed.

Similarly, in another embodiment, if the material of the first patterned material layer 506 and the second patterned material layer 514 is a hard mask material, an etching step may be further performed, and the first patterned material is used. The layer 506 and the second patterned material layer 514 are masks to etch the substrate 500 to form a structure similar to that of FIG. Alternatively, if the material of the first patterned material layer 506 and the second patterned material layer 514 is a dielectric material, a third material layer may be further formed in the second trench 514b and the third trench 514c to obtain a similar The structure of Figure 9.

Please refer to FIG. 14A, FIG. 14B, FIG. 15A, FIG. 15B, FIG. 16A, FIG. 16B, FIG. 17A, FIG. 17B, FIG. 18A and FIG. 18B, which are illustrated as the fourth aspect of the present invention. A schematic diagram of a step of forming a semiconductor structure in the embodiment, wherein FIG. 14A, FIG. 15A, FIG. 16A, FIG. 17A, and FIG. 18A are FIG. 14B, FIG. 15B, FIG. 16B, FIG. 17B, and FIG. 18B, respectively. A cross-sectional view of the figure, taken along the DD' tangent line in Figure 14B. As shown in FIG. 14A and FIG. 14B, a substrate 600 is first provided. The embodiment of the substrate 600 is as in the first embodiment and will not be described herein. Next, a first patterned material layer 606 is formed on the substrate 600. The first patterned material layer 606 has a plurality of first trenches 606a substantially parallel to a first direction 601. The material of the first material layer 602 may comprise a material suitable as a hard mask, such as tantalum nitride, metal or an advanced patterned film, or may be suitable as an inner dielectric layer or a dielectric interlayer dielectric layer. For example, cerium oxide.

As shown in FIGS. 15A and 15B, a second substance layer 612 is entirely formed on the substrate 600. The second material layer 612 fills at least the first trench 606a in the first patterned material layer 606. Preferably, the second material layer 612 covers the first patterned material layer 606 to make the first patterned material layer. 606 was not exposed. In a preferred embodiment of the present invention, the material of the second material layer 612 may be a material suitable as a hard mask, such as tantalum nitride, metal or an advanced patterned film, or may be suitable as a general inner dielectric. The material of the layer or the dielectric layer between the metal layers, such as cerium oxide. In this embodiment, the first patterned material layer 606 and the second material layer 612 may not have an etching selectivity ratio, that is, the same material may be included.

As shown in FIGS. 16A and 16B, a patterned photoresist layer 608 is formed on the second material layer 612. The patterned photoresist layer 608 has a trench 608a extending in a second direction 603 that is substantially perpendicular to the first direction 601.

As shown in FIGS. 17A and 17B, an etching process is performed by patterning the photoresist layer 608 as a mask, and the second material layer 612 not covered by the patterned photoresist layer 608 is removed to form a second. Patterned material layer 614. As shown in FIGS. 17A and 17B, the second patterned material layer 614 may include a plurality of second trenches 614a corresponding to the first trenches 606a disposed in the first patterned material layer 606.

Next, as shown in FIGS. 18A and 18B, a third substance layer 616 is formed on the substrate 600 to be filled in at least the second trench 614a. The manner in which the third substance layer 616 is formed is, for example, a chemical vapor deposition or an epitaxial process. The material of the third material layer 616 may be a material suitable as a general inner dielectric layer or a metal interlayer dielectric layer, such as cerium oxide, or a germanium grown by an epitaxial process. Finally, a planarization process, such as a chemical mechanical polishing process or an etch back process, is performed such that the first patterned material layer 606, the second patterned material layer 614, and the third material layer 616 are aligned. As shown in FIGS. 18A and 18B, the first patterned material layer 606 has a first trench 606a filled with a second patterned material layer 614 and a third material layer 616, wherein the third material layer 616 The first trench 606a is divided into two parts. The second patterned material layer 614 and the third material layer 616 in the first trench 606a of the present embodiment have a pattern similar to a rectangle. Through the foregoing manner, the rounding of the right angle corner due to the optical proximity effect in the prior art can be avoided.

As shown in FIGS. 18A and 18B, the present invention provides a semiconductor structure including a substrate 600, a first patterned material layer 606, a second patterned material layer 614, and a third material layer 616. A trench region 618 is defined on the substrate 600. The trench region 618 includes two first regions 620 and a second region 622. The second region 622 is located between the two first regions 620 and adjacent to the first region 620. The first patterned material layer 606 is disposed on the substrate 600 other than the trench region 618. The second patterned material layer 614 is disposed in the two first regions 620. The third substance layer 616 is disposed in the second region 622. As shown in FIG. 18B, in an embodiment, the third substance layer 616 is disposed only in the second region 622; and as the process method is different, as shown in FIG. 13B, in another embodiment, The three material layer 616 (position analogous to the first patterned material layer 506 in the 13B) may also be disposed in a region other than the trench region 618, for example, the third material layer 616 may join two or more trench regions. The first patterned material layer 606, the second patterned material layer 614, and the third material layer 616 are high. In one embodiment of the invention, the first patterned material layer 606 and the second patterned material layer 614 comprise different dielectric materials, and the third material layer 616 comprises an epitaxial germanium. In another embodiment of the present invention, the first patterned material layer 606 and the third patterned material layer 616 comprise different dielectric materials, and the second patterned material layer 614 comprises a conductive material (please refer to FIG. 9 together) Example).

In addition, it should be noted that in the foregoing embodiment, the trench region 618 is a rectangular region, but in another embodiment, the trench region 618 may also have a turn at the second region 622. Please refer to FIG. 19, which is a schematic diagram of a semiconductor structure in accordance with an embodiment of the present invention. As shown in FIG. 19, the two first regions 620 of the trench region 618 are trapezoidal, and the second region 622 is a polygon containing at least one set of parallel sides. The set of parallel sides has a width W therebetween, and in a preferred embodiment of the invention, the width W is substantially equal to the critical dimension that the exposure station can form on the substrate 600. Such a structure can also be formed by the manufacturing methods of the first to fourth embodiments described above.

In summary, the present invention forms a special semiconductor structure by using a double exposure method, and the formed semiconductor structure has a trench or strip structure which can have a pattern similar to a rectangle, and avoids optical interference in the prior art. The rounding angle of the right angle caused by the proximity effect.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

300,400,500,600. . . Substrate

400b. . . Fourth ditches

400c. . . Fifth ditches

301,401,501,601. . . First direction

312. . . Second patterned material layer

312a. . . Second strip structure

312b. . . Third strip structure

412,512,612. . . Second substance layer

303,403,503,603. . . Second direction

306,406,506,606. . . First patterned material layer

306a. . . First strip structure

406a, 606a. . . First ditches

406b. . . Second ditches

406c. . . Third ditches

506a. . . Separation structure

308,408,508,608. . . Second patterned photoresist layer

308a, 508a, 608a. . . ditch

408a. . . Strip structure

414,514,614. . . Second patterned material layer

414a. . . Separation structure

514b. . . Second ditches

514c. . . Third ditches

614a. . . Second ditches

416,616. . . Third substance layer

618. . . Ditch area

620. . . First area

622. . . Second area

1A, 1B, 2A, 2B, 3A, and 3B are schematic views showing steps of forming a semiconductor structure in the first embodiment of the present invention.

4A, 4B, 5A, 5B, 6A, 6B, 7A, and 7B are schematic views showing steps of forming a semiconductor structure in the second embodiment of the present invention.

8 and 9 are schematic views showing the steps of forming a semiconductor structure in two embodiments of the present invention.

10A, 10B, 11A, 11B, 12A, 12B, 13A, and 13B are schematic views showing steps of forming a semiconductor structure in a third embodiment of the present invention.

14A, 14B, 15A, 15B, 16A, 16B, 17A, 17B, 18A, and 18B are diagrams showing a fourth embodiment of the present invention.

Figure 19 is a schematic view showing a semiconductor structure in an embodiment of the present invention.

601. . . First direction

603. . . Second direction

606. . . First patterned material layer

606a. . . First ditches

614. . . Second patterned material layer

614a. . . Second ditches

616. . . Third substance layer

618. . . Ditch area

620. . . First area

622. . . Second area

Claims (21)

A semiconductor structure comprising: a substrate having at least one trench region defined thereon, the trench region having two non-adjacent first regions, and a second region between the two first regions and the first The region is adjacent to each other; a first material layer is disposed outside the trench region of the substrate; and a second material layer is disposed in the second region, the second material layer is aligned with the first material layer. The semiconductor structure of claim 1, wherein the first material layer and the second material layer comprise different dielectric materials. The semiconductor structure of claim 1, wherein the second region comprises a plurality of opposite sides that are substantially parallel to each other. The semiconductor structure of claim 1, wherein the second substance layer is disposed only in the second region. The semiconductor structure of claim 1, wherein the second material layer is further disposed in an area outside the trench region and extends to a second region of another trench region. The semiconductor structure of claim 1, wherein the two first regions are substantially trapezoidal. The semiconductor structure of claim 1, wherein the trench region is a rectangle. The semiconductor structure of claim 1, further comprising a third material layer disposed in the two first regions, and the third material layer is aligned with the first material layer and the second material layer. The semiconductor structure of claim 8, wherein the first material layer and the third material layer comprise different dielectric materials, and the second material layer comprises an epitaxial germanium. The semiconductor structure of claim 8, wherein the first material layer and the second material layer comprise different dielectric materials, and the third material layer comprises a conductive material. A method of forming a semiconductor structure, comprising: providing a substrate, wherein the substrate defines a trench region having two non-adjacent first regions, and a second region between the two first regions and Adjacent to the two first regions; forming a first material layer on the substrate, and then removing the first material layer in the trench region to form a first patterned material layer; and the first on the substrate A second patterned material layer is formed in the two regions, wherein the first patterned material layer and the second patterned material layer are uniform. The method of forming a semiconductor structure of claim 11, wherein the second region comprises a plurality of opposite sides that are substantially parallel to each other. The method of forming a semiconductor structure according to claim 11, wherein the first patterned material layer and the second patterned material layer have an etching selectivity ratio. The method of forming a semiconductor structure according to claim 11, wherein the first patterned material layer is formed first, and the second patterned material layer is formed. The method of forming a semiconductor structure according to claim 11, wherein the second patterned material layer is formed first, and the first patterned material layer is formed. The method for forming a semiconductor structure according to claim 11, after the forming the first patterned material layer and the second patterned material layer, further comprising performing an etching process to form the first patterned material layer And the second patterned material layer is a mask to etch the substrate. The method of forming a semiconductor structure according to claim 11, after forming the first patterned material layer and the second patterned material layer, further comprising forming a third material layer in the two first regions Wherein the third substance layer is at the same level as the first substance layer and the second substance layer. The method of forming a semiconductor structure according to claim 17, wherein the first material layer and the second material layer comprise different dielectric materials, and the third material layer comprises a conductive layer. The method for forming a semiconductor structure according to claim 11, wherein after forming the first patterned material layer and before forming the second patterned material layer, forming a third material layer in the two In a region, wherein the third material layer is at the same level as the first material layer. The method of forming a semiconductor structure according to claim 19, wherein the first material layer and the third material layer comprise different dielectric materials, and the second material layer comprises an epitaxial germanium. The method of forming a semiconductor structure according to claim 11, wherein the forming the first patterned material layer comprises using a first mask pattern, and forming the second patterned material layer comprises using a first a second mask pattern, the first mask pattern being substantially perpendicular to the second mask pattern.