TW201308439A - Fabrication method of trenched power MOSFET - Google Patents

Abstract

A fabrication method of a trenched power mosfet is provided. Firstly, a pattern layer is formed on a base. Then, an etching step is carried out to form a gate trench in the base being shielded by the pattern layer. Thereafter, a first oxide layer is formed in the gate trench for increasing the wideness of the gate trench. After removing the first oxide layer, a gate oxide layer is formed to line the inner surfaces of the gate trench. Then, an open penetrating the gate oxide layer at the bottom of the gate trench is formed by using the pattern layer as an etching mask. Thereafter, a thick oxide layer is formed in the open, and two first heavily doped regions are formed at the opposite sides of the thick oxide layer to prevent the body region covering the bottom of the trench gate.

Description

Trench type power MOS half field effect transistor manufacturing method

The invention relates to a method for fabricating a trench type power MOS field effect transistor, in particular to a method for fabricating a trench type power MOS field effect transistor capable of reducing switching loss of a gold oxide half field effect transistor.

Power MOS field effect transistors are widely used in switching elements of power devices, such as power supplies, rectifiers or low voltage motor controllers, and the like. Today's power MOS field effect transistors are designed with vertical structures to increase component density. The back side of the wafer is used as a drain, and the source and gate of a plurality of transistor elements are formed on the front side of the wafer. Since the drains of the individual transistor elements are connected in parallel, their withstand current can be increased.

The operating loss of power MOS field effect transistors can be divided into two categories: switching loss and conducting loss. Among them, the switching loss caused by the input capacitance Ciss increases as the operating frequency increases. Basically, the input capacitance Ciss includes a gate-to-source capacitance Cgs and a gate-to-drain capacitance Cgd. Therefore, reducing the gate-to-drain capacitance Cgd helps to reduce the switching loss in addition to increasing the avalanche energy in the case of inductive load switching (UIS).

Therefore, how to fabricate a power MOS field effect transistor with a low gate-to-drain capacitance Cgd has become one of the topics that the industry has paid attention to.

The main object of the present invention is to provide a method for manufacturing a power MOS field effect transistor, which can increase the thickness of the insulating layer between the gate and the drain to reduce the capacitance of the gate to the drain and improve the switching loss.

Another object of the present invention is to provide a method for fabricating a power MOS field effect transistor that can adjust the profile of the body region to enhance avalanche energy.

In order to achieve the above object, the present invention provides a method of manufacturing a trench type power MOS field effect transistor. First, a patterned layer is formed on a substrate. The patterned layer has a first opening to define a gate trench within the substrate. Subsequently, the substrate is etched through the patterned layer to form a gate trench in the substrate. Next, a first oxide layer is formed in the gate trench by oxidation. The first oxide layer covers at least the sidewalls of the gate trench. Subsequently, the first oxide layer is removed to enlarge the width of the gate trench and the bottom width of the gate trench is greater than the width of the first opening. Then, a gate oxide layer is formed on the inner side surface of the gate trench. Next, the bottom of the gate trench is etched by an anisotropic etching technique through the pattern layer to form a second open bare substrate. A thick oxide layer is then formed in the second opening. Subsequently, two first heavily doped regions are formed on both sides of the thick oxide layer by ion implantation to prevent the body region surrounding the gate trench from diffusing to the bottom of the gate trench.

According to an embodiment of the invention, after the step of forming the pattern layer, the present invention forms a first spacer layer in the first opening of the pattern layer. The gate trench is formed in the substrate by using the pattern layer and the first spacer layer structure as an etch mask.

According to an embodiment of the present invention, after the step of forming the second opening, the method further includes: expanding the width of the first opening of the pattern layer to expose the entire opening of the gate trench.

According to an embodiment of the invention, the thick oxide layer is formed in the second opening by wet oxidation.

In accordance with an embodiment of the invention, the thick oxide layer is formed in the second opening by a deposition and etch back process.

According to an embodiment of the invention, in the step of forming the second opening, a narrow trench is formed under the second opening. The width of the opening of the narrow groove corresponds to the width of the second opening.

According to an embodiment of the invention, a heavily doped region is pre-formed in the substrate below the gate trench prior to the step of forming the second opening. A narrow trench formed by the subsequent steps is formed through the heavily doped region to form a first heavily doped region on either side of the narrow trench.

According to an embodiment of the invention, a heavily doped region is pre-formed in the substrate below the gate trench prior to the step of forming the second opening. The subsequent step is to directly form a thick oxide layer formed by wet oxidation through the heavily doped region to form a first heavily doped region on both sides of the thick oxide layer.

According to an embodiment of the invention, the step of forming the first heavily doped region is followed by the step of forming a thick oxide layer, and the first heavily doped region is formed under the bottom of the gate trench by ion implantation.

The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.

1A to 1K are diagrams showing a first preferred embodiment of a method of manufacturing a trench type power MOS field effect transistor of the present invention. As shown in FIG. 1A, first, a pattern layer 115 is formed on a substrate. The substrate may be a substrate or a germanium substrate 100 having a surface covered with an epitaxial layer 110. The figure is exemplified by a germanium substrate 100 having a surface covered with an epitaxial layer 110. The germanium substrate 100 has a high concentration of the first conductivity type dopant, and the epitaxial layer 110 has the same conductivity type as the germanium substrate 100, but has a lower doping concentration. The pattern layer 115 covers the epitaxial layer 110 and has a first opening 117 to define a gate trench in the epitaxial layer 110.

Subsequently, as shown in FIG. 1B, a first spacer structure 120a is formed in the first opening 117 of the pattern layer 115 to define a third opening 119 having a narrow width in the first opening 117. The first spacer layer structure 120a can be fabricated in a generally spaced layer structure process. For example, a spacer layer material layer may be deposited along the surface of the pattern layer 115; then, the upper surface of the pattern layer 115 and the bottom surface of the first opening 117 are removed by an anisotropic etching. A portion of the first spacer structure 120a on the sidewall of the first opening 117 is left. Accordingly, the material selected for the spacer material layer must be different from the pattern layer 115 for the purpose of selective etching. For example, in this embodiment, the pattern layer 115 is formed by using a yttria material, and the first spacer layer structure 120a is formed by using a tantalum nitride material. Next, the patterned layer 115 and the first spacer layer structure 120a are etched, and the epitaxial layer 110 is etched to form the gate trench 130 in the epitaxial layer 110. The opening width of the gate trench 130 substantially corresponds to the width of the third opening 119 and is smaller than the width of the first opening 117. The difference in width between the third opening 119 and the first opening 117 is mainly determined by the thickness of the spacer layer material layer.

Subsequently, as shown in FIG. 1C, a first oxide layer 132 is formed on the exposed surface of the epitaxial layer 110 by oxidation. Since the upper surface of the epitaxial layer 110 is still covered by the pattern layer 115, the first oxide layer 132 is formed in the gate trench 130 to cover the sidewall and the bottom surface of the gate trench 130. It should be noted that the formation of the first oxide layer 132 consumes part of the epitaxial layer material at the same time, and the sidewall of the gate trench 130 is outwardly displaced. Subsequently, the first oxide layer 132 is removed to enlarge the width of the gate trench 130 such that the bottom width of the gate trench 130 is greater than the width of the third opening 119. In a preferred embodiment, the first oxide layer 132 can be a sacrificial oxide layer. Then, as shown in FIG. 1D, a gate oxide layer 134 is formed on the inner side surface of the gate trench 130. Next, as shown in FIG. 1E, a heavily doped region 140 is formed by ion implantation into the epitaxial layer 110 under the gate trench 130. It should be noted that although the width of the third opening 119 is smaller than the bottom width of the gate trench 130, due to the characteristics of the ion implantation step, the heavily doped region 140 formed under the gate trench 130 can still be laterally expanded to cover the entire The bottom surface of the gate trench 130. Moreover, in order to ensure that the heavily doped region 140 completely covers the bottom surface of the gate trench 130, the embodiment may also use an oblique ion implantation step or a thermal diffusion step after the ion implantation step.

Then, as shown in FIG. 1F, the gate oxide layer 134 at the bottom of the gate trench 130 is etched by the anisotropic etching technique through the pattern layer 115 and the third opening 119 defined by the first spacer layer structure 120a. A second opening 136 is formed to expose the heavily doped region 140. This second opening 136 is substantially aligned with the third opening 119. The width of the second opening 136 is less than the width of the bottom of the gate trench 130.

Then, as shown in FIG. 1G, a thick oxide layer 138 is directly formed in the second opening 136 by oxidation. The thick oxide layer 138 extends through the heavily doped region 140 to form two first heavily doped regions 140a on either side of the thick oxide layer 138. In a preferred embodiment, to ensure that the thick oxide layer 138 has sufficient thickness to extend below the heavily doped region 140, a wet oxidation process may be employed to increase the growth rate of the oxide layer. After the step of using the thick oxide layer 138 to distinguish the heavily doped regions 140 from the two first heavily doped regions 140a, a thermal diffusion step may be additionally applied to adjust the extent of the first heavily doped regions 140a ( As shown in the figure, the first heavily doped region 140a is expanded from the range defined by the broken line portion to the range defined by the solid line portion).

Next, the first spacer structure 120a is removed such that the entire opening of the gate trench 130 is exposed. Then, as shown in FIG. 1H, a gate polysilicon structure 150, a first dielectric structure 152 and a second dielectric structure 154 are sequentially formed in the first opening 117 of the gate trench 130 and the pattern layer 115. . The gate polysilicon structure 150 is located within the gate trench 130. The first dielectric structure 152 and the second dielectric structure 154 cover the gate polysilicon structure 150 and are located substantially in the first opening 117 of the pattern layer 115. In this step, the material selected for the second dielectric structure 154 is different from the constituent material of the pattern layer 115 for the purpose of selective etching. The constituent material of the first dielectric structure 152 is not limited thereto.

Then, as shown in FIG. 1I, the pattern layer 115 is removed by selective etching, and the first dielectric structure 152 and the second dielectric structure 154 overlying the gate polysilicon structure 150 are retained. Then, a body region 160 is formed around the gate trench 130 by ion implantation. Since the conductivity type of the body region 160 is different from the first heavily doped region 140a, the first heavily doped region 140a formed under the gate trench 130 can prevent the body region 160 from diffusing to cover the bottom of the gate trench 130. This causes the transistor component to fail. In addition, the presence of the first heavily doped region 140a also helps to change the profile of the lower surface of the body region 160 to increase the avalanche voltage of the transistor element. Next, a doping region 170 is formed on the surface layer of the body region 160 in another ion implantation step.

Subsequently, as shown in FIG. 1J, a second spacer layer structure 156 is formed on the side of the first dielectric structure 152 and the second dielectric structure 154 to define a source doping region 170a and a source contact window 165. The scope. Then, the second spacer layer structure 156 is used as a mask, and the epitaxial layer 110 is etched to form the source contact window 165 through the doping region 170 while the source doping region 170a is formed on the side of the source contact window 165. . Finally, as shown in FIG. 1K, the heavily doped region 180 is formed at the bottom of the source contact window 165 by ion implantation to reduce the contact resistance between the metal layer and the body region 160. A source metal layer 190 is then deposited on the epitaxial layer 110 to electrically connect the source doped region 170a with the heavily doped region 180.

2A to 2F are diagrams showing a second preferred embodiment of the method for producing a trench type power MOS field effect transistor of the present invention. As shown in FIG. 2A, unlike the first embodiment of the present invention, the first spacer layer structure 120a is formed in the first opening 117 of the pattern layer 115 to define the opening width of the gate trench 130. The embodiment eliminates the fabrication of the first spacer layer structure 120a, and directly defines the opening width of the gate trench 230 by using the opening of the pattern layer 215. As shown in FIGS. 2B to 2D, the present embodiment is used to fabricate a first oxide layer 232, a gate oxide layer 234, a heavily doped region 240, a second opening 236, a thick oxide layer 238, and a first heavily doped region 240a. The steps are substantially the same as the first embodiment of the present invention, and are not described herein.

However, since the first spacer layer structure 120a is not formed in the embodiment, the opening width of the pattern layer 215 of the embodiment may be smaller than the opening width of the gate trench 230. In order to ensure that the entire opening of the gate trench 230 is exposed, in order to facilitate the fabrication of the subsequent gate polysilicon structure 250, as shown in FIG. 2E, this embodiment is after the step of forming the second opening 236. An etching step is applied to the pattern layer 215 to enlarge the opening width of the pattern layer 215 (the solid line portion in the figure shows the etched pattern layer 215'). It should be noted that in order to avoid this etching step while removing the gate oxide layer 234 located in the gate trench 230, the constituent material of the pattern layer 215 is different from the gate oxide layer 234. For example, in this embodiment, the pattern layer 215 is formed by using tantalum nitride.

Then, as shown in Fig. 2F, the gate polysilicon structure 250 and the dielectric structure 252 are sequentially formed in the openings of the gate trench 230 and the pattern layer 215'. The gate polysilicon structure 250 is completely within the gate trench 230. The dielectric structure 252 covers the gate polysilicon structure 250 and extends upwardly from the gate trench 230 into the opening of the pattern layer 215'. Compared with the first embodiment of the present invention, the first dielectric structure 152 and the second dielectric structure 154 of FIG. 1H are replaced by a dielectric structure 252. However, the material selected for the dielectric structure 252 needs to be different from the constituent material of the pattern layer 215 for the purpose of selective etching. For example, in this embodiment, the pattern layer 215 may be formed by using tantalum nitride, and the dielectric structure 252 may be formed by using tantalum oxide for the purpose of selective etching.

3A to 3C are diagrams showing a third preferred embodiment of the manufacturing method of the trench type power metal oxide field effect transistor of the present invention. Fig. 3A corresponds to the fabrication steps of the 1Fth drawing of the first embodiment. As shown in the figure, in the step of etching the gate oxide layer 134 at the bottom of the gate trench 330 through the pattern layer 115 and the first spacer layer structure 120a, in addition to forming the second opening 336, A narrow trench 337 is formed under the opening 336 to penetrate the heavily doped region to form two first heavily doped regions 340a on opposite sides of the narrow trench 337. The opening width of the narrow groove 337 corresponds to the width of the second opening 336. Subsequently, as shown in FIG. 3B, a thick oxide layer 338 is formed to fill at least the narrow trenches 337 by a deposition and etch back process. Although the step of FIG. 3B is to form a thick oxide layer 338 in the narrow trench 337 by a deposition and etch back process. However, as shown in Fig. 3C, this embodiment can also take the form of oxidation to form a thick oxide layer 338' in the narrow trenches 337.

4A to 4C are views showing a fourth preferred embodiment of the method for producing a trench type power MOS field effect transistor of the present invention. 4A is substantially corresponding to the fabrication step of FIG. 3B. However, as shown in FIG. 4A, in the step of fabricating the thick oxide layer 438 in this embodiment, no heavily doped regions are formed in the gate trench 430. Below. In other words, in the present embodiment, after the fabrication of the thick oxide layer 438 is completed, the first heavily doped region is formed under the gate trench 430.

As shown in FIG. 4B, after the fabrication of the thick oxide layer 438 is completed, the first spacer structure 120a is removed, leaving the entire opening of the gate trench 430 exposed. Then, two first heavily doped regions 440a are formed on both sides of the thick oxide layer 438 by ion implantation.

The ion implantation step of FIG. 4B adopts a forward ion implantation mode. Therefore, before the ion implantation step, the first spacer layer structure 120a must be removed to ensure that the dopant can be smoothly implanted into the thick oxide layer 438. Inside the epitaxial layer 110 on both sides. However, the embodiment is not limited to this. As shown in Fig. 4C, this embodiment can also form the first heavily doped region 440a' by oblique ion implantation. At this time, the first spacer layer structure 120a is removed before the ion implantation step, and the first spacer layer structure 120a can be used as a mask to prevent dopant implantation on the side of the gate trench 430. Inside the epitaxial layer 110.

Fig. 5 is a fifth preferred embodiment of the manufacturing method of the trench type power MOS field effect transistor of the present invention. Figure 5 corresponds to the fabrication steps of Figure 1H. As shown in FIG. 5, this embodiment replaces the first dielectric structure 152 and the second dielectric structure 154 of FIG. 1H with a dielectric structure 552. However, the material selected for the dielectric structure 552 needs to be different from the constituent material of the pattern layer 115 for the purpose of selective etching. The subsequent steps of this embodiment are substantially the same as the first embodiment of the present invention, and are not described herein.

6A to 6C are diagrams showing a sixth preferred embodiment of the manufacturing method of the trench type power metal oxide field effect transistor of the present invention. Figure 6A corresponds to the fabrication steps of Figure 1H. As shown in FIG. 6A, the present embodiment is formed in the opening of the gate trench and the pattern layer 115, and sequentially forms a gate polysilicon structure 650 and a dielectric structure 652. The upper surface of the gate polysilicon structure 650 is spaced apart from the opening of the gate trench by a predetermined distance, and the dielectric structure 652 extends upward from the gate trench into the opening of the pattern layer 115.

Subsequently, as shown in FIG. 6B, the pattern layer 115 on the epitaxial layer 110 and the portion of the dielectric structure 652 protruding from the gate trench are removed by a planarization process, leaving a portion of the dielectric structure 652a to cover the gate. Very polycrystalline structure 650. For example, this step can be performed using a typical CMP process. Next, the remaining dielectric structure 652a is directly used as a mask, and the epitaxial layer 110 is selectively etched to expose the dielectric layer 652a to the epitaxial layer 110. Then, the body region 660 and the doping region 670 are sequentially formed in the epitaxial layer 110 by ion implantation. Then, as shown in FIG. 6C, a second spacer layer structure 656 is formed on the side of the dielectric structure 652a to define a range of the source doping region 670a and the source contact window 665. Next, the doped region 670 is etched with the second spacer layer structure 656 as a mask to form the source contact window 665 through the doped region 670. Then, a heavily doped region 680 is formed at the bottom of the source contact window 665 by ion implantation. The subsequent steps of this embodiment are substantially the same as the first embodiment of the present invention, and are not described herein.

As described above, the present invention expands the width of the gate trench through the fabrication of the first oxide layer, and forms a second opening in the gate oxide layer at the bottom of the gate trench by using the opening of the pattern layer to form a thick oxide layer. At the center of the bottom surface of the gate trench. In addition, the present invention utilizes the pattern layer to form a dielectric structure protruding above the epitaxial layer over the gate polysilicon structure, and a spacer layer structure is formed on both sides of the dielectric structure to define a source doped region and a source contact window. position. Therefore, the fabrication method of the present invention only needs to use a mask to simultaneously define the gate trench, the thick oxide layer at the center of the bottom surface of the gate trench, and the position of the source doped region. This saves costs while avoiding alignment errors that are easily caused by the use of multiple reticle.

Secondly, the manufacturing method of the present invention is to form a thick oxide layer at the center of the bottom surface of the gate trench, thereby reducing the capacitance of the gate to the drain and improving the switching loss. In addition, the manufacturing method of the present invention simultaneously forms a first heavily doped region on both sides of the thick oxide layer, and the conductivity type is different from the body region, thereby helping to adjust the contour of the body region to enhance the avalanche energy.

The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent. In addition, any of the objects or advantages or features of the present invention are not required to be achieved by any embodiment or application of the invention. In addition, the abstract sections and headings are only used to assist in the search of patent documents and are not intended to limit the scope of the invention.

100. . .矽 substrate

110. . . Epitaxial layer

115. . . Pattern layer

117. . . First opening

120a. . . First spacer structure

119. . . Third opening

130. . . Gate trench

132. . . First oxide layer

134. . . Gate oxide layer

140. . . Heavily doped region

136. . . Second opening

138. . . Thick oxide layer

140a. . . First heavily doped region

150. . . Gate polysilicon structure

152. . . First dielectric structure

154. . . Second dielectric structure

160. . . Body area

170. . . Doped region

156. . . Second spacer structure

170a. . . Source doping region

165. . . Source contact window

180. . . Heavily doped region

190. . . Source metal layer

215,215’. . . Pattern layer

230. . . Gate trench

232. . . First oxide layer

234. . . Gate oxide layer

240. . . Heavily doped region

236. . . Second opening

238. . . Thick oxide layer

240a. . . First heavily doped region

250. . . Gate polysilicon structure

252. . . Dielectric structure

330. . . Gate trench

336. . . Second opening

337. . . Narrow groove

338,338’. . . Thick oxide layer

438. . . Thick oxide layer

430. . . Gate trench

440a, 440a’. . . First heavily doped region

552. . . Dielectric structure

650. . . Gate polysilicon structure

652. . . Dielectric structure

652a. . . Dielectric structure

660. . . Body area

670. . . Doped region

656. . . Second spacer structure

670a. . . Source doping region

665. . . Source contact window

680. . . Heavily doped region

1A to 1K are diagrams showing a first preferred embodiment of a method of manufacturing a trench type power MOS field effect transistor of the present invention.

2A to 2F are diagrams showing a second preferred embodiment of the method for producing a trench type power MOS field effect transistor of the present invention.

3A to 3C are diagrams showing a third preferred embodiment of the manufacturing method of the trench type power metal oxide field effect transistor of the present invention.

4A to 4C are views showing a fourth preferred embodiment of the method for producing a trench type power MOS field effect transistor of the present invention.

Fig. 5 is a fifth preferred embodiment of the manufacturing method of the trench type power MOS field effect transistor of the present invention.

6A to 6C are diagrams showing a sixth preferred embodiment of the manufacturing method of the trench type power metal oxide field effect transistor of the present invention.

100. . .矽 substrate

110. . . Epitaxial layer

115. . . Pattern layer

130. . . Gate trench

120a. . . First spacer structure

119. . . Third opening

134. . . Gate oxide layer

138. . . Thick oxide layer

140a. . . First heavily doped region

Claims (12)

A method for manufacturing a trench type power MOS field effect transistor, comprising at least the steps of: forming a pattern layer on a substrate, the pattern layer having a first opening to define a gate trench in the substrate Etching the substrate through the pattern layer to form the gate trench; oxidizingly forming a first oxide layer (sacrificial oxide layer) in the gate trench, the first oxide layer covering at least the gate a sidewall of the trench; removing the first oxide layer to expand a width of the gate trench; forming a gate oxide layer on an inner surface of the gate trench; and transmitting the pattern layer by an anisotropic etching technique Etching the bottom of the gate trench to form a second opening to expose the substrate; forming a thick oxide layer in the second opening; and ion implanting to form two first heavily doped regions The two sides of the thick oxide layer prevent diffusion of a body region surrounding the gate trench to the bottom of the gate trench. The method for manufacturing a trench type power MOS field effect transistor according to the first aspect of the invention, after the step of forming the pattern layer, further comprising forming a first spacer layer on the pattern layer In an opening, the gate trench is formed in the substrate by using the pattern layer and the first spacer layer structure as an etch mask. The method for manufacturing a trench type power MOS field effect transistor according to claim 2, wherein the width of the second opening corresponds to one of the first spacer structures defined in the first opening. The width of the third opening. The method for manufacturing a trench type power MOS field effect transistor according to claim 1 is further included in the second opening after the step of forming the second opening and before the step of forming the thick oxide layer A narrow trench is formed, the opening width of the narrow trench corresponding to the width of the second opening. The method for manufacturing a trench type power MOS field effect transistor according to claim 4, wherein the step of forming the first heavily doped region is performed before the step of forming the second opening to form a heavily doped region. In the substrate below the gate trench, and the narrow trench is penetrated through the heavily doped region to form the first heavily doped region on both sides of the narrow trench. The method for manufacturing a trench type power MOS field effect transistor according to claim 1, wherein the step of forming the first heavily doped region comprises forming a heavily doped region before the step of forming the second opening. In the substrate below the gate trench, and the thick oxide layer is formed in the second opening by wet oxidation to penetrate the heavily doped region to form the first heavily doped region On both sides of the thick oxide layer. The method for manufacturing a trench type power MOS field effect transistor according to claim 1, wherein the thickness of the first oxide layer is greater than the thickness of the gate oxide layer. The method for manufacturing a trench type power MOS field effect transistor according to claim 2, wherein the first heavily doped region is formed by oblique ion implantation after the step of forming the thick oxide layer. Formed below the bottom of the gate trench. The method for manufacturing a trench-type power MOS field-effect transistor according to the first aspect of the invention, after the step of forming the second opening, further comprising: expanding the width of the first opening of the pattern layer by etching, The entire opening of the gate trench is exposed, wherein a constituent material of the pattern layer is different from the gate oxide layer. The method for manufacturing a trench power MOS field effect transistor according to claim 2, after the step of forming the second opening, further comprising removing the first spacer structure to expose the gate trench The entire opening. The method for manufacturing a trench type power MOS field effect transistor according to claim 1, wherein after the step of forming the first heavily doped regions, the method further comprises: forming a gate polysilicon structure in the gate trench a dielectric structure is formed over the gate polysilicon structure, the dielectric structure is located in the first opening; and a second spacer layer is formed on a side of the dielectric structure to define two sources The pole doped regions are on both sides of the gate trench. The method for manufacturing a trench type power MOS field effect transistor according to claim 1, wherein after the step of forming the first heavily doped regions, the method further comprises: forming a gate polysilicon structure in the gate trench Forming a dielectric structure over the gate polysilicon structure; masking the dielectric structure to etch the substrate to protrude from an upper surface of the substrate; and forming two A third spacer layer is formed on both sides of the dielectric structure to define two source doped regions on opposite sides of the gate trench.