TW201306211A - Package-to-package stacking by using interposer with traces, and or standoffs and solder balls - Google Patents

Abstract

The present invention discloses the structure and process for fabrication of an electronic package to contain and protect Package-to-Package (P2P) stacked module of integrated circuit (IC) chips. The process includes a step of providing an interposer that includes conductive traces interconnected between pre-designated contract pads disposed on a top and/ or bottom surfaces for mounting at least a top or bottom packages of the IC chips with electric terminals contacting the contact pads disposed on the top and/ or bottom surface of the interposer. Standoffs and passive components can also be added onto interposer in order to improve solder joints reliability, electrical performance and main board density at the same time. The inclusion of passive components on the interposer could enhance the electrical performance and the testability of the finished package stack.

Description

Package-on-package stack using an interposer containing wires and/or brackets and solder balls

The present invention relates to an electronic package, and more particularly to a package structure and process for fabricating an improved electronic package using an interposer including a holder and a solder ball to electrically connect the package to the package (P2P) And stacking.

Conventional electronic component packaging techniques using direct package-on-package (P2P) stack structures are still limited by specific alignment requirements, more specifically, in the form of leadframe packages or solder ball grid arrays (BGA). The package form, the direct P2P stack package requires a one-to-one alignment relationship between the corresponding connections on the two packages. U.S. Patent Nos. 6,049,123, 6, 168, 970, 6, 572, 387, 5, 455, 740, each of each of each of each of each of each of each of each of each of each of each of each of each of of This structure. Since one-to-one alignment is required, the pin or solder ball array arrangement in the upper and lower packages must be perfectly matched.

Subject to the above-mentioned one-to-one alignment requirements, the availability of direct P2P stacked packages is very limited. Today, electronic packages implemented using direct P2P stack structures are still limited to stacked memory products, such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM). In these P2P packages, the same leadframe package is stacked along the periphery of the molded body. At the same time, in the BGA package, in order to use the solder balls for the stack electrical connection, the layout of the P2P direct stack structure is also limited by the fact that the solder balls can only be arranged outside the molded body, and the tin of the upper and lower parts is The ball position must match exactly. Due to these limitations, the upper and lower packages have to be specially ordered. Therefore, subject to the one-to-one requirement, traditional direct P2P stacked packages can only stack the same kind of electronic packages in nature. Due to the alignment and wiring requirements, stacking different types of packages is unrealistic.

Another packaging technique uses a stacked electronic component structure that utilizes a wafer-to-wafer (D2D) stacking method to fabricate a single package containing multiple integrated circuit (IC) wafers. however, The electrical connections for wire bonding in a D2D package must be placed around or at the edge of the wafer, i.e., the location used to separate the wafers, so the D2D package cannot be applied to wafers containing a central contact pad structure. Moreover, the D2D method has cumulative yield problems since each individual wafer cannot be aged and fully electrically tested before being assembled into a single sealed body.

The application of D2D packaging technology is further limited by actual commercial considerations. In general, semiconductor companies are more inclined to sell packaged wafers in the form of assembled components in order to increase revenue, rather than selling just-processed wafers or bare wafers, if directly processed wafers or bare wafers are directly When sold in the market, semiconductor companies that produce integrated circuit chips will lose some of the profits that are generated in the downstream process. And the yield information obtained from process control and testing is also clearly disclosed during the wafer sales process.

In addition, it is difficult to distinguish between the purchase and sale of processed wafers or bare wafers. Since unpackaged bare wafers are not protected by any seals or packages, they are susceptible to damage. Since many parties, including semiconductor wafer suppliers and assembly companies, are involved in the manufacture of packaged components, it is difficult to determine who is responsible for component damage or reliability whenever a package containing multiple wafers presents reliability or other problems. Responsible party for loss of sexual problems. For these reasons, D2D packaging technology has many potential benefits, and practically it cannot replace or even supplement the package using P2P stack structure.

P2P Stack Package In addition to the above difficulties and limitations, the cost impact of assembling an existing P2P package is another major problem, especially when the P2P package needs to be assembled into a customized package. As mentioned earlier, existing P2P requires customized components to match other packages in the stack, and customized components will extend the production cycle and increase the complexity of inventory control.

For these reasons, it is highly desirable to develop improved package structures and methods for assembling P2P electronic packages to overcome the difficulties and limitations encountered by those skilled in the art.

In view of this, it is known that there is a great need for a package-and-package stack structure using an interposer containing wires and/or brackets and solder balls to improve the above-described lack.

The main object of the present invention is to provide a use of a wire and/or a support and a solder ball. The interposer is packaged and packaged, and the package structure and process are further improved to further improve the package-to-package (P2P) stack assembly process. The present invention uses a customized interposer to stack standard packages and solve the above discussion. Difficulties and limitations.

It is still another object of the present invention to provide a packaged package stack using an interposer comprising wires and/or holders and solder balls, using a printed circuit board (PCB) having wires on its upper and/or lower surface. Or an interposer of a polymeric film to stack an electronic package containing vias molded into a leadframe or ball grid array (BGA) substrate such that the P2P stacked solder joints can be placed directly over the wafer in the underlying package to This minimizes the size of the P2P stack.

It is yet another object of the present invention to provide a packaged package stack using an interposer comprising wires and/or brackets and solder balls, using a PCB interposer containing wires at the top and bottom thereof, the top wire and the standard surface The placement (SMT) package is connected, and the bottom wire is connected to the via hole in the BGA package with via holes, which makes the implementation of the P2P stacked package more flexible and convenient.

Another object of the present invention is to provide a package-in-package stack using an interposer containing wires and/or brackets and solder balls, using a spacer layer containing a holder and solder balls to stack standard package components, for example, A standard quad flat-lead package (QFP) or thin outline package (TSOP) on a BGA package with molded vias makes P2P stacked package implementations more flexible and convenient.

Another object of the present invention is to provide a packaged package stack using an interposer comprising wires and/or brackets and solder balls for stacking in a molding using a PCB interposer comprising a holder, solder balls and passive components. The standard SMT of the BGA package of the via hole makes the implementation of the P2P stacked package more flexible and convenient.

Another object of the present invention is to provide a package-in-package stack using an interposer comprising wires and/or brackets and solder balls, using a PCB interposer to assemble a stacked package containing optional polymer bumps, the polymerization The bumps are used in special packages such as flip-chips to reduce the temperature of the stacking process of the P2P package, and the polymer bumps can also offset part of the package warpage and absorb thermal stress.

To achieve the above objects, the present invention provides an electronic package including a packaged package containing and protecting a package of integrated circuit chips and using an interposer containing wires and/or brackets and solder balls. The electronic package includes an interposer having conductive paths or wires for connecting specific electrical contact pads disposed on the upper and lower surfaces of the interposer, such that the interposer can be mounted with at least one top package of the IC wafer containing the electrical terminals and The bottom, top and bottom package electrical terminals are used to connect the electrical contact pads on the upper and lower surfaces of the interposer. In a preferred embodiment, the interposer further includes a bracket disposed on an upper surface or a lower surface thereof. In another embodiment, the interposer further includes solder balls or conductive polymer bumps disposed on an upper surface or a lower surface thereof. In another embodiment, the interposer further includes a passive electronic component disposed on its upper or lower surface.

The purpose, technical contents, features and effects achieved by the present invention will be more readily understood by the detailed description of the embodiments and the accompanying drawings.

1A is a cross-sectional view of a customized printed circuit board (PCB) interposer 100 designed to provide top package 114 (Fig. 2) mounted on the interposer to 1B. Electrically electrically connected wiring of the bottom package 105 of the figure. Other package features and options are described further below. The interposer 100 of FIG. 1A has an upper surface including a top electrical contact pad 101, and the interposer 100 further has a lower surface including a bottom electrical contact pad 102. The bottom electrical contact pads 102 are arranged to match the layout of the hole contacts 111 and 117 on the upper side of the bottom package 105 in FIG. 1B. The interposer 100 is composed of a layered core layer 103 comprising wires 104 for connection, which are placed in the intermediate layer of the PCB and in contact with the bottom electrical contact pads 102.

The bottom package 105 of FIG. 1B includes a lead frame package, as described in US Pat. No. 7,667,338, which includes a molded lead frame 110 sealed to a sealing body 106 or a base BGA package. The disclosure in U.S. Patent No. 7,667,338 is incorporated herein by reference. The bottom package 105 contains an integrated circuit (IC) wafer 108 that is distributed over the leadframe 110 by bond wires 109. The electrical terminals on the connection are connected. The bottom package 105 further includes a plurality of hole joints, such as hole joints 111, 112, 116 and 117, which penetrate the sealing body 106 and are bonded to the bottom solder balls 113 or to the PCB interposer in FIG. The electrical contact pads 102 of the lower surface of 100 form an electrical connection.

2 illustrates that the interposer 100 in FIG. 1A provides a convenient electrical connection between the second top package 114 on the interposer and the first package 105 under the lower surface of the interposer 100 with the solder balls attached thereto. . The second top package 114 includes another IC wafer 110 that is wire bonded to the lead frame 115, and the lead frame 115 and the gull-wing pin 116 are electrically connected. This second top package 114 will then be surface mounted to the hole contacts 117 and 101 on the upper surface of the interposer. A wire formed inside the interposer and a hole joint penetrating the laminated interposer are used to connect the top and bottom pads. As a specific application, the distribution of the contact pads on the top and bottom surfaces of the interposer 100 is consistent with the standard pin distribution of the top and bottom packages stacked in a P2P structure. The standard pinouts for these packages can be standard TSOP (thin small outline package), QFP (quadruple-lead flat package in Reference 1), CSP (wafer size package), BGA (ball grid array package) Or, as described in "Microelectronics Packaging Handbook" by IBM's Tummala and Rymeszewski and published by Van Nostrand (New York Library of Congress, 88-14254), with different contact pad distributions. Hole type BGA.

Figure 3 shows an interposer 118 containing a stent 120 adhered to its lower surface. The interposer 118 further includes a solder ball 122 attached to its lower surface. It is worth noting that in order to make the stacking process easy and to provide spacing between the interposer and the stacked packages, the brackets can have different shapes and be placed in many locations. As shown in FIG. 3, the bracket 120 can be made of various materials and adhered to the interposer 118. As shown by element 139 in Figure 5, the stent may also be ball bonded to the interposer with a solder-coated high polymer. The interposer 118 shown provides more flexibility for the development of the stacked process. Once the size, shape and position of the bracket 120 are optimized, one can use the hard mold to make the steel mold and the molding compound to manufacture the bracket, so that the step of separately manufacturing the bracket can be omitted.

In FIG. 3, a standard leadframe QFP top package 114 is mounted over electrical contact pads 119 on the upper surface of interposer 118. A molded BGA package 125 covers an IC wafer 129 and is overlaid on the plastic cover 126 by bond wires 130. The plastic cover 126 is composed of a seal material 127 having via holes 128 that are distributed through the plastic cover 126 over the interposer. Lower side.

The molded BGA package 124 is arranged to be stacked under the interposer 118 to serve as a bottom package for the stacked P2P structure. Molded BGA package 125 has molded electrical contact pads 132 on the lower surface that can be thinned to mold contact lines 133 and solder balls 134. In order to accommodate the warpage that may be formed in the operation of the bottom package, the stent 120 as shown in Fig. 3 may also use a high polymer elastic fiber material or a spring loaded pin.

The high polymer bump material and process described in Figure 5 below can provide an additional benefit in forming a flexible electrical connection containing a support that is more reliable and less expensive to manufacture. Since the pitch requirement of the interposer is much looser than that of the flip chip, the solder bump mask is fabricated in the present invention in comparison to placing the solder balls and the holder in two different process steps. The cost and technology on the floor are greatly reduced.

As shown in FIG. 3, in order to attach the solder ball 122 to the interposer 118, a pad 121 is also deposited on the lower surface of the interposer 118. The solder balls 122 are then surface mounted and stacked vertically over the vias 128 filled with conductive material, thus forming an electrical connection to the molded BGA package 124 stacked under the interposer 118. The bracket 120 placed on the corner or center can also serve as a support for the spacer structure to prevent collapse of the soldered electrical connection.

Figure 4 shows the interposer 118 and a standard surface mount (SMT) top package 114 stacked from above, the interposer 118 comprising the support 120 and the solder balls 122 on the lower surface, and the solder paste 137 adhered to the interposer Passive element 136 on the upper surface. The solder balls 122 disposed on the lower surface of the interposer 118 further provide a surface mount onto the bottom package 124. The distribution of via connectors 128 on the bottom package 124 matches the solder balls 122 on the lower surface of the interposer 118. . As part of the P2P stacked package, the passive component 136 may include resistors or capacitors formed and mounted on the interposer 118 to increase motherboard density and component performance. Functional measurement by placing passive components on the interposer The test can be implemented on the stacked package module layer instead of the mother board layer to improve its flexibility and manufacturability.

Figure 5 shows the BGA substrate on which the flip chip 148 is mounted, which are connected by fine pitch solder bumps 149. The gap 151 between the flip chip surface and the fine pitch solder bumps 149 therebetween is filled by the underfill material 150 instead of the overmolded seal. Since the back of the flip chip integrated circuit is actually bare, in this case, the solder balls 138 and the high polymer carrier balls 139 on the lower surface of the interposer 118 are directly exposed to the exposed contact pads 146 on the BGA substrate 147, and the plurality of layers. The laminate of the routed metal coating 145 is connected to the electrical contact pads 144 at the bottom. In this case, a standard quad flat pin package 141 and passive component 153 can be surface mounted on top of the interposer. The polymer scaffolding ball 139 ensures a suitable spacing. Tin balls 143 attached to the lower surface of the BGA substrate will be used to mount the entire stacked module to the motherboard.

Here, the use of the polymer bump technology is to form a bracket or an electrical connection protrusion on the PCB interposer. The silver-filled high polymer bumps may be composed of a thermosetting plastic or a thermoplastic such as EPO-TEK E2101 (thermosetting) and EPO-TEK E5022 (thermoplastic) for screen printing.

These high polymer bumps can be bonded at relatively low temperatures and have good thermal conductivity and low modulus of elasticity, which can improve the manufacturability and reliability of the interposer stack structure, while other stacked tins The ball 138 can be welded in a regular manner. Components in the standard quad flat package and passive components 153, such as resistors or capacitors, can be mounted on the top surface of the interposer.

Figure 6 shows an alternative embodiment in which the top standard tetragonal inclusion of the interposer 118 is stacked by filling the underfill 152, such as a gel or grease having thermal conductivity, between the interposer 118 and the bottom package 142. The foot is packaged flat into the bottom package 142 in Figure 5 to form a P2P stacked package.

The underfill 152 is composed of a material that has a thermally conductive but non-electrically conductive material, such as a tantalum gel with tantalum nitride or other ceramic oxide particles, which can increase the heat dissipation of the entire stacked module 154 and Prevent impurities from entering the P2P structure, thereby improving component reliability Sex and life. Additionally, passive element 151 can be bonded to the top surface of the interposer.

Figure 7 is a cross-sectional view of the lower half of Figure 6, the only difference being that the mounting of the interposer 118 to the bottom package 142 uses a bracket. The interposer 118 is composed of a compound having good thermal conductivity to increase the heat dissipation power of the stacked structure. There are several wires 701 and contact pads 702 on the upper surface of the interposer 118. These wires and contact pads are designed and fabricated in a special distribution to accommodate pre-specified surface mountable packages or components that are to be placed onto the interposer, such that the bottom package 142 can be easily integrated with various product stickers. It is loaded onto the interposer 118.

Figure 7 is a lower portion of Figure 6, in which the interposer is mounted on a bottom package containing a support and a thermally dissipative thermal composite that improves the stack structure. It is worth noting that the top wire 701 and contact pad 702 can be designed to accommodate any desired SMT size to enable integration with various products. Here are some examples of applications:

1. A standard micro processing unit (MCU) located above a custom graphics processing unit (GPU).

2. Integrate standard digital products on custom analog products.

3. Install different kinds of memory products, such as DRAM, SRAM, ROM or flash memory onto the processor package.

4. Integrate different types of memory that require different wafer processes, such as integrated DRAM and static RAM or flash memory.

5. Stack the sensor or MEMS component onto the processor.

Given the breadth of applications, one can choose to only offer and sell the base module, or further install the top package and make a complete P2P structure, as described in the Process Flow Diagram section.

Figure 8 shows that various forms of surface mount BGA 801 and surface mount 802 are placed over the interposer of the bottom package base module by using different land pitches. It is noted that some solder joints for stacking can be placed directly over the bottom wafer region 810.

Figure 9 shows that with a two-layer stent structure, stacked solder joints 902 and 903 can be placed directly over wafer area 910 of the bottom flip chip component. This is the energy provided by the intermediary layer. The unique ability to make the smallest P2P size. The smallest sized central lead connects the memory package 904 to the large size processor die 905. This arrangement is the only way to achieve a P2P structure with a near CSP structure.

In accordance with the above figures and description, the application of the present invention discloses a packaged electronic package using a package containing wires and/or brackets and solder balls to house and protect the stacked electronic packages therein. The electronic package further includes an interposer having wires for electrically connecting the contact pads distributed on the upper and lower surfaces of the interposer for mounting at least one of the stacked electronic packages described above to the interposer The upper and lower surfaces of the layer. In another embodiment, the interposer is a printed circuit board (PCB) interposer.

In another embodiment, the interposer is a laminated printed circuit board (PCB) interposer comprising a plurality of laminate layers, the plurality of laminate layers being electrically connected by wires disposed thereon. In another embodiment, at least one stacked electronic package contains an integrated circuit (IC) wafer.

In another embodiment, the interposer further includes a plurality of brackets disposed on the top surface, or a bottom surface of the interposer.

In another embodiment, the interposer is a printed circuit board (PCB) interposer comprising conductive via connectors for electrical connections between the contact pads disposed on the top and bottom surfaces of the PCB interposer. In another embodiment, the interposer is a printed circuit board (PCB) interposer comprising a multilayer laminate having electrically conductive via joints for distribution between the wires on the multilayer laminate layer and over Electrical connection between the contact pads on the upper and lower surfaces of the laminated PCB interposer. In another embodiment, the interposer further comprises a scaffold disposed on the upper surface of the interposer or on the lower surface of the interposer. In another embodiment, the interposer further comprises solder balls or conductive high polymer bumps distributed on the upper surface of the interposer or on the lower surface of the interposer. In another embodiment, the interposer further comprises passive electrical components distributed on the upper surface of the interposer or on the lower surface of the interposer, and distributed under the interposer for filling and protecting the bottom under the interposer and the interposer The space between the packages and the underfill of the thermal conductivity of the stacked modules. In another embodiment, at least one heap The stacked electronic package includes an integrated circuit (IC) chip formed on a semiconductor wafer for mounting from a lower surface of the interposer; and the contact pads formed in the form of solder joints are distributed over a semiconductor wafer directly above The surface area is used to optimize the size of the electronic package. In another embodiment, the contact pads distributed on the upper and lower surfaces are pre-specified and designed to match the pins of the electronic package mounted to the upper and lower surfaces of the interposer. The process flow of the PCB interposer stack of the present invention is as follows:

Step 1: Design the wires and contact pads for the size of the stacked components.

Second step: Align the upper side of the molding holes 111 and 117 in Fig. 1B with the contact pads on the lower side of the interposer 102 in Fig. 1A. A properly designed bracket can be used to make the stack alignment process easier.

The third step: attaching the solder balls 122 (Fig. 2) to the back of the electrical contact pads 102 on the interposer. It is also verified whether the pin 116 of the top element and the electrical contact pads 101 and 107 on the upper side of the interposer are aligned.

Step 4: Adhere the bracket 120 in Figure 3 to the back of the interposer. Different types of stents are available as described in the preferred embodiment. Note that the height of the bracket will determine the shape of the solder ball joint after being squeezed, which will significantly affect the reliability of the fatigue life.

Step 5: Reflow and connect the solder joint 122 in Fig. 4 to the upper side of the molding hole 128. It is noted that the mechanical support can be placed on top of the molded body 126 to provide a positive spacing. Even if there are multiple reflows next, the solder joints will not collapse due to melting again or due to the weight of the stacked structure. One can also choose to use the elastomeric polymer sphere 118 and the polymer stent sphere 139 in Figure 5 as a scaffold to provide more flexible support and more flexibility. If the bottom package is electrically connected to the flip chip as in the flip chip 148 of Figure 5, the placement of the stacked pads will be limited. Stacked solder joints will have to be placed outside of the flip chip area due to the inability to connect from the back of the flip chip. However, with the interposer and dual-stack stack as shown in Figure 9, this limitation will no longer exist.

Step 6: Adhere and reflow all the upper components, passive or active SMT package onto the upper surface of the interposer. At this point, the P2P package is complete and ready for functional electrical testing.

An optional business model allows the process flow to end in step 5. The component in which the interposer is mounted as in Fig. 7 is tested and sold as a component. This basic unit with customized pins and dimensions on the upper surface of the interposer can be shipped to the customer. Let the customer choose the components they want most to complete the P2P structure as shown in Figures 8 and 9.

The foregoing embodiments of the present invention are disclosed above, but are not intended to limit the invention. Modifications and modifications made without departing from the spirit and scope of the invention are claimed in the scope of the invention.

100‧‧‧Intermediary

101‧‧‧Electric contact pads

102‧‧‧Electric contact pads

103‧‧‧Layered core layer

104‧‧‧Wire

105‧‧‧ bottom package

106‧‧‧ Sealing body

107‧‧‧Contact pads

108‧‧‧Integrated Circuit (IC) Wafer

109‧‧‧bonding leads

110‧‧‧ lead frame

111‧‧‧Molded holes

112‧‧‧ hole joint

113‧‧‧ solder balls

114‧‧‧Top package

115‧‧‧ lead frame

116‧‧‧ hole joint

117‧‧‧ hole contact

118‧‧‧Intermediary

119‧‧‧Electric contact pads

120‧‧‧ bracket

121‧‧‧ solder pads

122‧‧‧ solder balls

124‧‧‧Molded BGA package

125‧‧‧Molded BGA package

126‧‧‧ molded body

127‧‧‧ Sealing material

128‧‧‧through holes

129‧‧‧ IC chip

130‧‧‧bonding leads

132‧‧‧Molded electrical contact pads

133‧‧‧Thin molded contact line

134‧‧‧ solder balls

136‧‧‧ Passive components

137‧‧‧ solder paste

138‧‧‧ solder balls

139‧‧‧High polymer support ball

141‧‧‧Standard square-lead flat package

142‧‧‧ bottom package

143‧‧‧ solder balls

144‧‧‧Electric contact pads

145‧‧‧Road metal coating

146‧‧‧Contact pads

147‧‧‧BGA substrate

148‧‧‧Flip Chip

149‧‧‧ solder bumps

150‧‧‧ underfill material

151‧‧‧ gap

152‧‧‧Bottom filling

153‧‧‧ Passive components

154‧‧‧Module

701‧‧‧ wire

702‧‧‧Contact pads

801‧‧‧Surface package BGA

802‧‧‧Surface package ViaPak

810‧‧‧Bottom wafer area

901‧‧‧ wafer area

902‧‧‧Stack solder joints

903‧‧‧Stack solder joints

904‧‧‧Storage package

905‧‧‧ processor chip

1A is a cross-sectional view of a PCB interposer having an upper surface and an electrical contact pad on the upper surface of the present invention.

1B is a cross-sectional view of the package implemented by the PCB interposer of FIG. 1A of the present invention, and the solder filled holes in the upper and lower halves of the molded body are used for stacking and connecting the lead frame BGA package. Molded holes.

Figure 2 is a cross-sectional view of a package implemented by a PCB interposer containing a top wire for connection to a standard surface mount gull wing lead frame package.

Figure 3 is a cross-sectional view of the package of the present invention comprising a carrier and a solder ball PCB interposer for stacking standard QFPs into a BGA package of a mold cavity.

Figure 4 is a cross-sectional view of a package implemented by a PCB interposer comprising a stent, a solder ball, and a passive component for stacking a standard surface mount (SMT) package to a BGA package of a mold cavity.

Figure 5 is a cross-sectional view of a package implemented in the present invention using polymer bumps to assemble a PCB interposer of a stacked package.

Figure 6 is a cross-sectional view of the interposer of the present invention comprising a PCB holder and a solder ball containing a high polymer ball at the bottom, the interposer being stackable to a flip chip having an underfill on its surface and in a BGA package Wafer.

Figure 7 is a bottom view of Figure 6, which shows a laminated PCB interposer containing a basic component of a P2P structure - a mechanical support. To accommodate various SMT packages, the upper surface of the interposer can be Constructed with SMT of various sizes.

Figure 8 is a cross-sectional view of a P2P structure in which the various forms and different pitch packages of the present invention are stacked on an interposer.

Figure 9 is a cross-sectional view showing the P2P structure in which the solder balls are directly stacked on the wafer area of the flip chip in the bottom package in order to make the package size as small as possible, and the figure shows that the present invention can be obtained using the interposer. A unique feature.

100‧‧‧Intermediary

101‧‧‧Electric contact pads

105‧‧‧ bottom package

110‧‧‧ lead frame

114‧‧‧Top package

115‧‧‧ lead frame

116‧‧‧ hole joint

117‧‧‧ hole contact

Claims (17)

An electronic package for accommodating and protecting a stacked electronic package therein, comprising at least: an interposer having a wire; at least one contact pad on a lower surface of the interposer, wherein the wire is electrically connected to the contact pad The wire is distributed over the lower surface of the interposer; and at least one of the stacked electronic packages is mounted on the upper or lower surface of the interposer and in electrical contact with the contact pads. The electronic package of claim 1, wherein the interposer is an interposer of a printed circuit board. The electronic package of claim 1, wherein the interposer is an interposer of a laminate printed circuit board having a plurality of laminate layers, the wires on which the laminate layers are connected to each other. The electronic package of claim 1, wherein at least one of the stacked electronic packages comprises an integrated circuit (IC) chip. The electronic package of claim 1, wherein the interposer is a printed circuit board interposer comprising a hole joint, the electrical contact pads distributed on the upper and lower surfaces of a PCT interposer, and interconnected by the hole joint. The electronic package of claim 1 wherein the interposer is a laminated printed circuit board interposer comprising a multi-layer laminate having at least one hole joint for connection distribution to the multilayer laminate The wire on the layer and the contact pads distributed on the upper and lower surfaces of the interposer of the laminated printed circuit board. The electronic package of claim 1, wherein the interposer further comprises a bracket disposed on an upper surface of the interposer. The electronic package of claim 1, wherein the interposer further comprises a bracket disposed on a lower surface of the interposer. The electronic package of claim 1, wherein the interposer further comprises a plurality of solder balls distributed on an upper surface of the interposer. The electronic package of claim 1, wherein the interposer further comprises a plurality of conductive high-concentrating protrusions distributed on an upper surface of the interposer. The electronic package of claim 1, wherein the interposer further comprises a plurality of solder balls distributed on a lower surface of the interposer. The electronic package of claim 1, wherein the interposer further comprises a plurality of conductive high-concentration protrusions distributed on a lower surface of the interposer. The electronic package of claim 1, wherein the interposer further comprises at least one passive electrical component, the passive electrical component being distributed on an upper surface of the interposer. The electronic package of claim 1, wherein the interposer further comprises at least one passive electrical component, the passive electrical component being distributed on a lower surface of the interposer. The electronic package of claim 1 further comprising at least one underfill material distributed under the interposer for filling and protecting a bottom package space between the interposer and the interposer, and To improve the thermal conductivity of the stacked modules. The electronic package of claim 1, further comprising an integrated circuit chip and at least one solder joint, the integrated circuit wafer being formed on a semiconductor wafer, and the integrated circuit wafer is mounted on a lower surface of the interposer; The solder joint distribution is located on an upper surface area of the semiconductor wafer. The electronic package of claim 1, wherein the contact pad is pre-specified and designed to match pins of an electronic package mounted on upper and lower surfaces of the interposer.