TW201306197A - MPS-C2 semiconductor package - Google Patents
MPS-C2 semiconductor package Download PDFInfo
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- TW201306197A TW201306197A TW100125903A TW100125903A TW201306197A TW 201306197 A TW201306197 A TW 201306197A TW 100125903 A TW100125903 A TW 100125903A TW 100125903 A TW100125903 A TW 100125903A TW 201306197 A TW201306197 A TW 201306197A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/8114—Guiding structures outside the body
Abstract
Description
本發明係有關於半導體裝置，特別係有關於一種以金屬柱銲接為晶片連接之半導體封裝構造。The present invention relates to a semiconductor device, and more particularly to a semiconductor package structure in which a metal pillar is soldered to a wafer.
「以金屬柱銲接為晶片連接」(MPS-C2,Metal Post Solder-Chip Connection)是一種先進的覆晶接合技術，習知覆晶接合是在晶片主動面上設置複數個銲球，作為與基板結合之凸塊，藉由晶片翻轉使主動面朝向基板以及迴焊(reflowing)溶接的方式，使銲球電性與機械性接合至在基板的對應接墊上。然而，銲球為圓弧側壁，當凸塊間距設計越來越小，相鄰銲球容易焊接一起，故使用銲球的覆晶接合不符合微間距凸塊(間距小於100微米)接合之要求。"MPS-C2 (Metal Post Solder-Chip Connection)" is an advanced flip chip bonding technology. Conventional flip chip bonding is to place a plurality of solder balls on the active surface of the wafer as a substrate. The bonded bumps electrically and mechanically bond the solder balls to the corresponding pads on the substrate by flipping the active surface toward the substrate and reflowing by wafer inversion. However, the solder ball is a circular arc side wall. When the bump pitch design is smaller and smaller, the adjacent solder balls are easy to be soldered together, so the flip chip bonding using the solder balls does not meet the requirements of the micro pitch bumps (the pitch is less than 100 micrometers). .
美國專利US 6,229,220 B1號「Bump structure,bump forming method and package connecting body」，IBM(International Business Machines Corporation)公司採用金屬柱取代以往的銲球，作為覆晶接合之凸塊，以銲料連接金屬柱與基板上接墊。迴焊之溫度只能熔化銲料而未到達金屬柱的熔點，使金屬柱保持柱狀形狀。金屬柱(即作為晶片凸塊的間距)得以縮小，也不會發生傳統銲球橋接短路的問題。因此，凸塊可更高密度配置，亦能維持至少大於金屬柱高度的覆晶間隙。然而，在迴焊之前或同時，需要使用覆晶接合機使晶片往基板壓合，在實際MPS-C2半導體封裝產品中會有一定的製程不良品。U.S. Patent No. 6,229,220 B1, "Bump structure, bump forming method and package connecting body", IBM (International Business Machines Corporation) uses a metal column to replace a conventional solder ball as a bump-bonded bump, and a metal pillar is connected by solder. The pads on the substrate. The temperature of the reflow can only melt the solder without reaching the melting point of the metal column, so that the metal column maintains the columnar shape. The metal pillars (i.e., the pitch as the wafer bumps) are reduced, and the problem of the conventional solder ball bridging short circuit does not occur. Therefore, the bumps can be arranged at a higher density and can maintain a flip-chip gap at least greater than the height of the metal post. However, before or at the same time, the flip chip bonding machine is required to press the wafer to the substrate, and there are certain process defects in the actual MPS-C2 semiconductor package product.
如第1圖所示，一種習知典型的「以金屬柱銲接為晶片連接」(MPS-C2)之半導體封裝構造100主要包含一晶片110、一基板120及銲料140。該晶片110之主動片設有複數個金屬柱112，藉由銲料140接合該些金屬柱112至位在該基板120上表面之複數個接墊122。另以一底部填充膠之封膠體150填入在該晶片110與該基板120之間的覆晶間隙。該些金屬柱112之高度為覆晶間隙之二分之一以上，使銲料140不足以被迴焊成球狀。由製程不良品分析發現，該晶片110會相對於該基板120產生傾斜或斷裂，部份之金屬柱112下方之銲料140會過度溢出，甚至於導致銲料橋接之電性短路，而且因該晶片110之傾斜使得覆晶間隙不一致，該封膠體150在覆晶間隙變小的空間容易產生氣泡151，使得MPS-C2半導體封裝產品的可靠度不佳。據此研判，此缺陷之形成係為在迴焊之前或過程中覆晶接合力量過大所造成，其目的是為了使尚未迴焊前之銲料能有效接觸所有金屬柱至對應之接墊。如覆晶接合力量過小，因基板本身會有一定水平度偏差，以印刷電路板為例將更為明顯，如壓合力量過小，迴焊前之銲料則無法接觸所有金屬柱至對應接墊，導致空焊或假焊問題。因此，習知MPS-C2半導體封裝產品在覆晶接合步驟的製程窗(即可供作業的允許範圍)甚小，機台參數之設定或是基板特性之掌握稍有不慎，便產生不良品。As shown in FIG. 1, a conventional semiconductor package structure 100 of "metal pillar soldering as a wafer connection" (MPS-C2) mainly includes a wafer 110, a substrate 120, and a solder 140. The active sheet of the wafer 110 is provided with a plurality of metal pillars 112. The metal pillars 112 are joined by solder 140 to a plurality of pads 122 on the upper surface of the substrate 120. A flip-chip gap 150 between the wafer 110 and the substrate 120 is filled with an underfill adhesive 150. The height of the metal pillars 112 is more than one-half of the flip-chip gap, so that the solder 140 is insufficient to be reflowed into a spherical shape. It is found that the wafer 110 is inclined or broken relative to the substrate 120, and the solder 140 under the metal pillars 112 may overflow excessively, even causing an electrical short circuit of the solder bridge, and the wafer 110 is damaged. The tilt of the flip-chip gap is inconsistent, and the sealant 150 is likely to generate bubbles 151 in a space where the flip-chip gap becomes small, so that the reliability of the MPS-C2 semiconductor package product is not good. According to this study, the defect is formed by excessive bonding force before or during reflow, and the purpose is to enable the solder before the reflow to effectively contact all the metal posts to the corresponding pads. If the flip-chip bonding force is too small, the substrate itself will have a certain degree of deviation. The printed circuit board will be more obvious. For example, if the pressing force is too small, the solder before the reflow cannot contact all the metal posts to the corresponding pads. Causes empty or false soldering problems. Therefore, the conventional MPS-C2 semiconductor package product has a very small process window (that is, the allowable range of work available) in the flip chip bonding step, and the setting of the machine parameters or the mastery of the substrate characteristics is slightly inadvertent, resulting in defective products. .
有鑒於此，本發明之主要目的係在於提供一種以金屬柱銲接為晶片連接之半導體封裝構造，用以改善習知「以金屬柱銲接為晶片連接」(MPS-C2)類型半導體封裝構造因晶片與基板非平行壓合產生在金屬柱側邊之封裝氣泡以及金屬柱下銲料橋接短路之問題。In view of the above, the main object of the present invention is to provide a semiconductor package structure in which a metal pillar is soldered as a wafer to improve the conventional "metal pillar soldering as a wafer connection" (MPS-C2) type semiconductor package structure. Non-parallel pressing with the substrate creates problems with packaged bubbles on the sides of the metal posts and solder bridge shorts under the metal posts.
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明主要揭示一種以金屬柱銲接為晶片連接之半導體封裝構造，係主要包含一晶片、一基板及銲料。該晶片係具有複數個設於一主動表面之金屬柱。該基板係具有一上表面，該基板在該上表面設置有複數個接墊以及複數個在該些接墊兩側之間隔條。該銲料係焊接該些金屬柱之複數個突出端面至該些接墊。其中，該些間隔條之高度係略大於該些金屬柱之突出高度，當該晶片之該主動表面接觸至該些間隔條，令該基板平行於該晶片並且該些突出端面至該些接墊之間形成一使該些金屬柱不致直接碰觸到該些接墊之固定焊接間隙。The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention mainly discloses a semiconductor package structure in which a metal pillar is soldered to a wafer, and mainly includes a wafer, a substrate, and solder. The wafer has a plurality of metal posts disposed on an active surface. The substrate has an upper surface, and the substrate is provided with a plurality of pads on the upper surface and a plurality of spacer strips on opposite sides of the pads. The solder is soldered to the plurality of protruding end faces of the metal posts to the pads. The height of the spacer strips is slightly larger than the protruding height of the metal pillars. When the active surface of the wafer contacts the spacer strips, the substrate is parallel to the wafer and the protruding end faces are to the pads. A fixed weld gap is formed between the metal posts so as not to directly touch the pads.
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.
在前述的半導體封裝構造中，該晶片之該主動表面係可包含一供接觸該些間隔條之保護層。In the foregoing semiconductor package construction, the active surface of the wafer may include a protective layer for contacting the spacers.
在前述的半導體封裝構造中，該基板係可為一印刷電路板。In the aforementioned semiconductor package construction, the substrate may be a printed circuit board.
在前述的半導體封裝構造中，可另包含一封膠體，係至少填入於在該晶片與該基板之間的間隙，以密封該些金屬柱、該銲料與該些間隔條。In the foregoing semiconductor package structure, a glue may be further included in at least a gap between the wafer and the substrate to seal the metal pillars, the solder and the spacers.
在前述的半導體封裝構造中，該封膠體係可為一底部填充膠。In the aforementioned semiconductor package construction, the encapsulation system can be an underfill.
在前述的半導體封裝構造中，該封膠體係可為一模封化合物，並密封該晶片。In the aforementioned semiconductor package construction, the encapsulation system can be a mold compound and seal the wafer.
在前述的半導體封裝構造中，該基板之該上表面係可形成有一焊罩層，該些間隔條係形成於該焊罩層上並且為一厚度大於該焊罩層之增厚防焊圖案。In the foregoing semiconductor package structure, the upper surface of the substrate may be formed with a solder mask layer, and the spacer strips are formed on the solder mask layer and are thickened solder resist patterns having a thickness greater than the solder mask layer.
在前述的半導體封裝構造中，該些間隔條係可具有一平行於該晶片之鄰近側邊之連續條狀。In the foregoing semiconductor package construction, the spacer strips may have a continuous strip shape parallel to adjacent sides of the wafer.
在前述的半導體封裝構造中，該些間隔條係可具有一平行於該晶片之鄰近側邊之非連續條狀。In the foregoing semiconductor package construction, the spacer strips may have a discontinuous strip shape parallel to adjacent sides of the wafer.
在前述的半導體封裝構造中，在該晶片與該基板之間的間隙係可超過該晶片之厚度。In the aforementioned semiconductor package construction, the gap between the wafer and the substrate may exceed the thickness of the wafer.
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.
依據本發明之第一具體實施例，一種以金屬柱銲接為晶片連接之半導體封裝構造200舉例說明於第2圖之截面示意圖以及第3圖在晶片接合時之截面示意圖。該半導體封裝構造200係主要包含一晶片210、一基板220及銲料240。According to a first embodiment of the present invention, a semiconductor package structure 200 soldered to a wafer is illustrated in a cross-sectional view of FIG. 2 and a cross-sectional view of FIG. 3 at the time of wafer bonding. The semiconductor package structure 200 mainly includes a wafer 210, a substrate 220, and a solder 240.
該晶片210係具有複數個設於一主動表面211之金屬柱212，例如銅柱、金柱、銀柱、高溫錫鉛柱或複數金屬層組成之金屬柱。該主動表面211係為各式所需積體電路之形成表面，該主動表面211可更設置有複數個銲墊213，作為積體電路之對外接點，而該些金屬柱212可利用電鍍或是接植方式設置於該些銲墊213上，該些金屬柱212可直接接合於該些銲墊213，或者在該些銲墊213與該些金屬柱212之間可設置有一凸塊下金屬層(圖中未繪出)。該基板220係具有一上表面221，該基板220在該上表面221設置有複數個接墊222以及複數個在該些接墊222兩側之間隔條230，可為絕緣材質。該些間隔物230不僅僅只有維持覆晶間隙之作用，同時作為一緩衝體，用以避免在晶片壓合時發生該晶片210之斷裂或該些金屬柱212之損傷。較佳地，該晶片210之該主動表面211係可包含一供接觸該些間隔條230且電性絕緣之保護層214，以避免該晶片210之電性短路以及避免因該些間隔條230之壓迫所造成內部積體電路之損傷。The wafer 210 has a plurality of metal pillars 212 disposed on an active surface 211, such as copper pillars, gold pillars, silver pillars, high temperature tin-lead pillars or metal pillars composed of a plurality of metal layers. The active surface 211 is a forming surface of various integrated circuits. The active surface 211 can be further provided with a plurality of pads 213 as external contacts of the integrated circuit, and the metal posts 212 can be plated or The metal pillars 212 can be directly bonded to the solder pads 213, or a bump metal can be disposed between the solder pads 213 and the metal pillars 212. Layer (not shown). The substrate 220 has an upper surface 221. The substrate 220 is provided with a plurality of pads 222 and a plurality of spacer strips 230 on opposite sides of the pads 222. The substrate 220 can be made of an insulating material. The spacers 230 serve not only as a function of maintaining the flip-chip gap, but also as a buffer to prevent breakage of the wafer 210 or damage of the metal pillars 212 during wafer bonding. Preferably, the active surface 211 of the wafer 210 can include a protective layer 214 for contacting the spacers 230 and electrically insulating to avoid electrical shorting of the wafer 210 and avoiding the spacers 230. The damage caused by the internal integrated circuit caused by the compression.
在一具體結構中，該基板220之該上表面221係可形成有一焊罩層223，該些間隔條230係形成於該焊罩層223上並且為一厚度大於該焊罩層223之增厚防焊圖案，使得該些間隔條230可在基板220製程中同時被製作，以降低該些間隔條230之設置成本，並且該些間隔條230與該焊罩層223的結合良好，不會有位移的問題。此外，由增厚防焊圖案構成之該些間隔條230也相對於該晶片210與該些金屬柱212更為柔軟，以發揮晶片壓合時在該晶片210與該基板220之間的緩衝體作用，該晶片210即使有傾斜現象也會回復到與該基板220平行之狀態。In a specific structure, the upper surface 221 of the substrate 220 can be formed with a solder mask layer 223. The spacer strips 230 are formed on the solder mask layer 223 and have a thickness greater than that of the solder mask layer 223. The solder resist pattern is such that the spacer strips 230 can be simultaneously fabricated in the process of the substrate 220 to reduce the installation cost of the spacer strips 230, and the spacer strips 230 are well bonded to the solder mask layer 223, and there is no The problem of displacement. In addition, the spacer strips 230 formed by the thickened solder resist pattern are also softer relative to the wafer 210 and the metal pillars 212 to serve as a buffer between the wafer 210 and the substrate 220 during wafer bonding. As a function, the wafer 210 returns to a state parallel to the substrate 220 even if it is tilted.
該銲料240係焊接該些金屬柱212之複數個突出端面215至該些接墊222。並且，該些間隔條230之高度Hs係略大於該些金屬柱212之突出高度Hp，其中該些間隔條230之高度Hs係為由該上表面221至該些間隔條230用以接觸該主動表面211之一表面之垂直高度，該些金屬柱212之突出高度Hp係為由該主動表面211至該些突出端面215之垂直高度。在本實施例中，該些間隔條230之高度Hs亦應大於該些金屬柱212之間距。如第3圖所示，在晶片接合過程中可沿用既有的覆晶接合設備，該晶片210以一取放頭吸附並往該基板220壓合，該基板220係預先承載在一覆晶接合載台20上，並且在該些接墊222上可先塗覆一助焊劑30，可與對應位置之銲料240沾黏接觸，迴焊時有助於該銲料240對該些接墊222的焊接，而迴焊該銲料240的步驟可在晶片壓合之後放進一迴焊爐內進行，或者可以在晶片壓合之過程中同時加熱達成。當該晶片210之該主動表面211接觸至該些間隔條230，能令該基板220平行於該晶片210並且該些突出端面215至該些接墊222之間形成一供銲料240填充之固定焊接間隙，使該些金屬柱212不致直接碰觸到該些接墊222。更具體地，該基板220係可為一印刷電路板，利用該些間隔條230與該晶片210之壓迫接觸，有效解決習知印刷電路板的翹曲誤差造成的金屬柱212空焊以及焊料擴散的橋接問題。較佳地，在該晶片210接合之後，在該晶片210與該基板220之間的間隙係可超過該晶片210之厚度，以符合超薄型半導體封裝產品。The solder 240 solders a plurality of protruding end faces 215 of the metal posts 212 to the pads 222. Moreover, the height Hs of the spacer strips 230 is slightly larger than the protruding height Hp of the metal pillars 212. The height Hs of the spacer strips 230 is used by the upper surface 221 to the spacer strips 230 for contacting the active strips. The vertical height of one surface of the surface 211, the protruding height Hp of the metal posts 212 is the vertical height from the active surface 211 to the protruding end faces 215. In this embodiment, the height Hs of the spacer strips 230 should also be greater than the distance between the metal pillars 212. As shown in FIG. 3, an existing flip chip bonding apparatus can be used in the wafer bonding process. The wafer 210 is adsorbed by a pick-and-place head and is pressed against the substrate 220. The substrate 220 is pre-loaded on a flip chip bond. On the stage 20, a flux 30 may be applied to the pads 222 to be in contact with the solder 240 of the corresponding position, and the solder 240 may be soldered to the pads 222 during reflow. The step of reflowing the solder 240 may be carried out in a reflow oven after wafer bonding, or may be achieved by simultaneous heating during wafer bonding. When the active surface 211 of the wafer 210 contacts the spacers 230, the substrate 220 can be parallel to the wafer 210 and the protruding ends 215 to the pads 222 form a solder for filling the solder 240. The gaps prevent the metal posts 212 from directly touching the pads 222. More specifically, the substrate 220 can be a printed circuit board, and the spacers 230 are pressed into contact with the wafer 210 to effectively solve the problem of soldering of the metal pillars 212 and solder diffusion caused by the warpage error of the conventional printed circuit board. The bridging problem. Preferably, after the wafer 210 is bonded, the gap between the wafer 210 and the substrate 220 may exceed the thickness of the wafer 210 to conform to the ultra-thin semiconductor package product.
前述的半導體封裝構造可另包含一封膠體250，係至少填入於在該晶片210與該基板220之間的間隙，以密封該些金屬柱212、該銲料240與該些間隔條230。在本實施例中，該封膠體250係可為一底部填充膠。較佳地，如第4圖所示，該些間隔條230係可具有一平行於該晶片210之鄰近側邊之連續條狀，使得該些間隔條230更具有導引封膠體250流動之增益效果。在一變化實施例中，如第5圖所示，該些間隔條230’係可具有一平行於該晶片210之鄰近側邊之非連續條狀，非連續條狀的缺口有利於該些間隔條230’被該封膠體250包覆。The foregoing semiconductor package structure may further comprise a glue body 250 filled at least between the wafer 210 and the substrate 220 to seal the metal pillars 212, the solder 240 and the spacer strips 230. In this embodiment, the encapsulant 250 can be an underfill. Preferably, as shown in FIG. 4, the spacer strips 230 may have a continuous strip parallel to the adjacent sides of the wafer 210, such that the spacer strips 230 further have a gain for guiding the flow of the encapsulant 250. effect. In a variant embodiment, as shown in FIG. 5, the spacer strips 230' may have a discontinuous strip parallel to the adjacent sides of the wafer 210, and the discontinuous strip-shaped notches facilitate the intervals. Strip 230' is covered by the encapsulant 250.
因此，本發明之以金屬柱銲接為晶片連接之半導體封裝構造200係用以改善習知「以金屬柱銲接為晶片連接」(MPS-C2)類型半導體封裝構造因晶片與基板非平行壓合產生在金屬柱側邊之封裝氣泡以及金屬柱下銲料橋接短路之問題。Therefore, the semiconductor package structure 200 of the present invention in which the metal pillars are soldered to the wafer is used to improve the conventional "slice bonding by metal pillars" (MPS-C2) type semiconductor package structure due to non-parallel pressing of the wafer and the substrate. The problem of encapsulating bubbles on the sides of the metal posts and solder bridging shorts under the metal posts.
依照本發明之第二實施例，另揭示一種以金屬柱銲接為晶片連接之半導體封裝構造。如第6圖所示，該半導體封裝構造300係主要包含一晶片210、一基板220及銲料240，其主要元件之作用與連接關係大致與第一實施例相同，故沿用相同圖號並不再贅述。其特徵在於，該些間隔條230之高度係略大於該些金屬柱212之突出高度，當該晶片210之該主動表面211接觸至該些間隔條230，令該基板220平行於該晶片210並且該些金屬柱212不致直接碰觸到該些接墊222。並在本實施例中，該封膠體250係可為一模封化合物，並密封該晶片210。此外，較佳地，該半導體封裝構造300係可另包含一熱固性黏膠331，係黏接該些間隔條230至該晶片210之主動表面211，以避免銲料240在迴焊之前的晶片位移。而該些間隔條230可具有一半錐形截面，以避免該熱固性黏膠331流動擴散到該基板220之該上表面221。According to a second embodiment of the present invention, a semiconductor package structure in which a metal pillar is soldered to a wafer is disclosed. As shown in FIG. 6, the semiconductor package structure 300 mainly includes a wafer 210, a substrate 220, and a solder 240. The functions and connection relationships of the main components are substantially the same as those of the first embodiment, so that the same figure number is not used. Narration. The height of the spacer strips 230 is slightly larger than the protruding height of the metal pillars 212. When the active surface 211 of the wafer 210 contacts the spacer strips 230, the substrate 220 is parallel to the wafer 210 and The metal posts 212 do not directly touch the pads 222. In the present embodiment, the encapsulant 250 can be a mold compound and seal the wafer 210. In addition, the semiconductor package structure 300 can further include a thermosetting adhesive 331 for bonding the spacers 230 to the active surface 211 of the wafer 210 to avoid wafer displacement of the solder 240 before reflow. The spacer strips 230 may have a semi-conical cross section to prevent the thermosetting adhesive 331 from flowing and diffusing to the upper surface 221 of the substrate 220.
以上所述，僅是本發明的較佳實施例而已，並非對本發明作任何形式上的限制，雖然本發明已以較佳實施例揭露如上，然而並非用以限定本發明，任何熟悉本項技術者，在不脫離本發明之技術範圍內，所作的任何簡單修改、等效性變化與修飾，均仍屬於本發明的技術範圍內。The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.
20．．．覆晶接合載台20. . . Flip chip bonding stage
30．．．助焊劑30. . . Flux
100．．．以金屬柱銲接為晶片連接之半導體封裝構造100. . . Semiconductor package structure with metal pillar soldering as wafer connection
110．．．晶片110. . . Wafer
112．．．金屬柱112. . . Metal column
120．．．基板120. . . Substrate
122．．．接墊122. . . Pad
140．．．銲料140. . . solder
150．．．封膠體150. . . Sealant
151．．．氣泡151. . . bubble
200．．．以金屬柱銲接為晶片連接之半導體封裝構造200. . . Semiconductor package structure with metal pillar soldering as wafer connection
210．．．晶片210. . . Wafer
211．．．主動表面211. . . Active surface
212．．．金屬柱212. . . Metal column
213．．．銲墊213. . . Solder pad
214．．．保護層214. . . The protective layer
215．．．突出端面215. . . Protruding end face
220．．．基板220. . . Substrate
221．．．上表面221. . . Upper surface
222．．．接墊222. . . Pad
223．．．焊罩層223. . . Welding mask
230．．．間隔條230. . . Spacer
230’．．．間隔條230’. . . Spacer
240．．．銲料240. . . solder
250．．．封膠體250. . . Sealant
300．．．以金屬柱銲接為晶片連接之半導體封裝構造300. . . Semiconductor package structure with metal pillar soldering as wafer connection
331．．．熱固性黏膠331. . . Thermosetting adhesive
Hs．．．間隔條之高度Hs. . . Height of the spacer
Hp．．．金屬柱之突出高度Hp. . . Metal column protrusion height
第1圖：習知以金屬柱銲接為晶片連接之半導體封裝構造之截面示意圖。Fig. 1 is a schematic cross-sectional view showing a semiconductor package structure in which a metal pillar is soldered to a wafer.
第2圖：依據本發明之第一實施例，一種以金屬柱銲接為晶片連接之半導體封裝構造之截面示意圖。2 is a cross-sectional view showing a semiconductor package structure in which a metal pillar is soldered to a wafer in accordance with a first embodiment of the present invention.
第3圖：依據本發明之第一實施例，該半導體封裝構造在晶片接合時之截面示意圖。Fig. 3 is a cross-sectional view showing the semiconductor package structure at the time of wafer bonding in accordance with a first embodiment of the present invention.
第4圖：依據本發明之第一實施例，該半導體封裝構造所使用之一基板之立體示意圖。Figure 4 is a perspective view of a substrate used in the semiconductor package structure in accordance with a first embodiment of the present invention.
第5圖：依據本發明之第一實施例之變化例，該半導體封裝構造所使用之另一基板之立體示意圖。Figure 5 is a perspective view of another substrate used in the semiconductor package structure in accordance with a variation of the first embodiment of the present invention.
第6圖：依據本發明之第二實施例，一種以金屬柱銲接為晶片連接之半導體封裝構造之截面示意圖。Figure 6 is a cross-sectional view showing a semiconductor package structure in which a metal pillar is soldered to a wafer in accordance with a second embodiment of the present invention.
200．．．以金屬柱銲接為晶片連接之半導體封裝構造200. . . Semiconductor package structure with metal pillar soldering as wafer connection
210．．．晶片210. . . Wafer
211．．．主動表面211. . . Active surface
212．．．金屬柱212. . . Metal column
213．．．銲墊213. . . Solder pad
214．．．保護層214. . . The protective layer
215．．．突出端面215. . . Protruding end face
220．．．基板220. . . Substrate
221．．．上表面221. . . Upper surface
222．．．接墊222. . . Pad
223．．．焊罩層223. . . Welding mask
230．．．間隔條230. . . Spacer
240．．．銲料240. . . solder
250．．．封膠體250. . . Sealant
Hs．．．間隔條之高度Hs. . . Height of the spacer
Hp．．．金屬柱之突出高度Hp. . . Metal column protrusion height
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100125903A TW201306197A (en) | 2011-07-22 | 2011-07-22 | MPS-C2 semiconductor package |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100125903A TW201306197A (en) | 2011-07-22 | 2011-07-22 | MPS-C2 semiconductor package |
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| Publication Number | Publication Date |
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| TW201306197A true TW201306197A (en) | 2013-02-01 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI721884B (en) * | 2019-12-26 | 2021-03-11 | 台灣積體電路製造股份有限公司 | Package and method of forming the same |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI721884B (en) * | 2019-12-26 | 2021-03-11 | 台灣積體電路製造股份有限公司 | Package and method of forming the same |
| US11664300B2 (en) | 2019-12-26 | 2023-05-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Fan-out packages and methods of forming the same |
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