TW201301820A - Communicating with a self-clocking amplitude modulated signal - Google Patents
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Abstract
Description
本發明大體上係關於信號傳輸,並且特定而言係關於與數位資料信號組合的時脈信號的傳輸。 The present invention relates generally to signal transmission, and in particular to the transmission of clock signals in combination with digital data signals.
本申請案係2010年5月7日申請的標題為「CAPACITIVE DIVIDER TRANSMISSION SCHEME FOR IMPROVED COMMUNICATIONS ISOLATION」的美國專利申請案第12/775,517號(下文為「`517申請案」)的部分接續,其主張2009年5月8日申請的標題為「A ROBUST 2-WIRE DAISY CHAIN COMMUNICATION SYSTEM」的美國臨時專利申請案第61/176,800號(下文為「`800申請案」)的權利。本申請案亦係關於2011年6月20日申請的標題為「AMPLITUDE ADJUSTED PULSE FOR DC BALANCED SIGNAL WITH TRANSFORMER COUPLING」的美國臨時專利申請案第61/498,984號(下文為「984申請案」)。本申請案據此主張`517申請案、`800申請案以及`984申請案的優先權權利。該`517申請案、`800申請案以及`984申請案據此以引用的方式併入本文中。 This application is a sequel to the continuation of U.S. Patent Application Serial No. 12/775,517, entitled "CAPACITIVE DIVIDER TRANSMISSION SCHEME FOR IMPROVED COMMUNICATIONS ISOLATION", which is filed on May 7, 2010, which is hereby incorporated herein by reference. The right of U.S. Provisional Patent Application No. 61/176,800 (hereinafter referred to as "the '800 Application"), entitled "A ROBUST 2-WIRE DAISY CHAIN COMMUNICATION SYSTEM", filed on May 8, 2009. The present application is also related to U.S. Provisional Patent Application Serial No. 61/498,984, entitled "AMPLITUDE ADJUSTED PULSE FOR DC BALANCED SIGNAL WITH TRANSFORMER COUPLING", filed on June 20, 2011 (hereinafter referred to as "984 Application"). This application claims the priority rights of the '517 application, the '800 application, and the `984 application. The '517 application, the '800 application, and the '984 application are hereby incorporated herein by reference.
已經開發用於傳輸組合時脈信號及數位資料信號的傳輸器。但是組合信號已經在載波上被調變。此雖然在特定 情況下係有益的,但是對電路增加額外的複雜度。 Transmitters have been developed for transmitting combined clock signals and digital data signals. However, the combined signal has been modulated on the carrier. Although this is specific The situation is beneficial, but adds extra complexity to the circuit.
在一實例中,提供一種用於傳輸信號的方法。該方法包括產生曼徹斯特編碼資料串流及將該曼徹斯特編碼資料串流與放大時脈信號組合以產生振幅調變信號,該振幅調變信號在該放大時脈信號的每一邊緣上具有零交叉。接著該振幅調變信號經由通信媒體發送。 In an example, a method for transmitting a signal is provided. The method includes generating a Manchester encoded data stream and combining the Manchester encoded data stream with an amplified clock signal to produce an amplitude modulated signal having a zero crossing on each edge of the amplified clock signal. The amplitude modulation signal is then transmitted via the communication medium.
在下文詳細描述中,參考形成本發明的一部分的附圖,並且附圖藉由圖解的方式顯示實行本發明的特定實施方案。充分詳細地描述此等實施例以使熟習此項技術者能夠實行本發明,並且應瞭解可利用其他實施例並且在不背離本發明的範圍的情況下可作出邏輯、機械及電改變。因此,下文詳細描述不具限制之意。 In the following detailed description, reference to the accompanying drawings The embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is understood that other embodiments may be utilized, and logical, mechanical, and electrical changes can be made without departing from the scope of the invention. Therefore, the following detailed description is not intended to be limiting.
高電壓系統通常需要在存在電磁干擾(EMI)及功率瞬變的情況下提供電壓隔離及穩健性能的通信方案。此等方案透過限制EMI傳輸得到進一步改良。本文描述的實施例提供因低EMI發射而具有高瞬變及抗EMI能力的傳輸系統及方案。 High voltage systems typically require communication solutions that provide voltage isolation and robust performance in the presence of electromagnetic interference (EMI) and power transients. These solutions are further improved by limiting EMI transmission. Embodiments described herein provide transmission systems and solutions that have high transient and EMI immunity due to low EMI emissions.
圖1A係具有電容耦合的通信系統100的一實施例的示意圖。通信系統100包括經由通信媒體106耦合至第二收發器104的第一收發器102。通信媒體106用作第一收發器 102與第二收發器104之間的傳輸線。通信媒體106的實施例包括有線鏈結例如電纜(例如,易曲扁平電纜)、電路板跡線、雙絞線或其他通信媒體。第一收發器102與第二收發器104之間的通信在共用的通信媒體106上係雙向的。通信媒體106至第一及第二收發器102及104的連接可用現在已知的或以後開發的任何合適連接實現。 FIG. 1A is a schematic diagram of an embodiment of a communication system 100 having capacitive coupling. Communication system 100 includes a first transceiver 102 coupled to a second transceiver 104 via communication medium 106. Communication medium 106 is used as the first transceiver A transmission line between 102 and the second transceiver 104. Embodiments of communication medium 106 include wired links such as cables (e.g., flexible flat cables), circuit board traces, twisted pairs, or other communication media. Communication between the first transceiver 102 and the second transceiver 104 is bidirectional on the shared communication medium 106. The connection of communication medium 106 to first and second transceivers 102 and 104 can be accomplished with any suitable connection now known or later developed.
第一收發器102具有接收功能,該接收功能包括通信引腳輸入箝位107、耦合至差動驅動器132的輸入的觸發驅動器133,其中兩個回饋電阻器131-1及131-2耦合至差動驅動器132的輸出。第一收發器102亦包括傳輸驅動器134。對稱地,該第二收發器104具有:接收功能性,其包括耦合至差動驅動器135的輸入的觸發驅動器136,其中兩個回饋電阻器137-1及137-2耦合至差動驅動器135的輸出;及傳輸功能性,其包括傳輸驅動器138。本文描述的電阻器可為任何合適電阻元件。 The first transceiver 102 has a receive function including a communication pin input clamp 107, a trigger driver 133 coupled to the input of the differential driver 132, wherein the two feedback resistors 131-1 and 131-2 are coupled to the difference The output of the drive 132. The first transceiver 102 also includes a transmission driver 134. Symmetrically, the second transceiver 104 has a receive functionality that includes a trigger driver 136 coupled to an input of the differential driver 135, wherein the two feedback resistors 137-1 and 137-2 are coupled to the differential driver 135 Output; and transport functionality, including transport driver 138. The resistors described herein can be any suitable resistive element.
本文進一步關於方塊A、B及C論述通信系統100。每一方塊包括組態為執行一個或多個功能的電路。如將描述,方塊A及C為方塊B提供終端負載,方塊B作出反應提供電壓分壓及電壓隔離。方塊A及C可以提供低阻抗負載條件,該低阻抗負載條件允許傳輸信號同時減小EMI效果。在一實例中,第一收發器102包括第一埠120-1及第二埠120-2以與具有第三埠120-3及第四埠120-4的第二收發器104通信。該第一及第二收發器102及104可經由稱為高路徑139-1及低路徑139-2的兩條路徑耦合在一起。高路 徑139-1可包括從第一收發器102的埠120-1通過方塊A、通信媒體106的一根或多根第一導線、方塊B及C至第二收發器104的埠120-3的信號路徑。低路徑139-2可包括從第一收發器102的埠120-2通過方塊A、通信媒體106的一根或多根第一導線、方塊B及C至第二收發器104的埠120-4的信號路徑。在一實例中,收發器102、104可經由高路徑139-1及低路徑139-2傳輸差動信號。 Communication system 100 is discussed further herein with respect to blocks A, B, and C. Each block includes circuitry configured to perform one or more functions. As will be described, blocks A and C provide terminal load for block B, and block B reacts to provide voltage division and voltage isolation. Blocks A and C can provide low impedance load conditions that allow signals to be transmitted while reducing EMI effects. In one example, the first transceiver 102 includes a first port 120-1 and a second port 120-2 to communicate with a second transceiver 104 having a third port 120-3 and a fourth port 120-4. The first and second transceivers 102 and 104 can be coupled together via two paths called high path 139-1 and low path 139-2. High road The path 139-1 may include from the 埠 120-1 of the first transceiver 102 through the block A, the one or more first wires of the communication medium 106, the blocks B and C to the 埠 120-3 of the second transceiver 104. Signal path. The low path 139-2 may include 埠 120-4 from the 埠 120-2 of the first transceiver 102 through block A, one or more first wires of the communication medium 106, blocks B and C to the second transceiver 104. Signal path. In an example, the transceivers 102, 104 can transmit differential signals via the high path 139-1 and the low path 139-2.
用方塊A整體顯示,第一收發器102可經由分別針對路徑139-1及139-2的電阻器113-1及113-2以及電容器114-1及114-2耦合至通信媒體106。電容器114-1及114-2各自連接至接地。差動電容器112可跨路徑139-1及139-2放置在電阻器113-1及113-2與通信媒體106之間。在一實施例中,收發器102及方塊A共同位於單晶片上。在一實施例中,收發器102及104之一或兩者係正交振幅調變(QAM)收發器。 As shown generally by block A, the first transceiver 102 can be coupled to the communication medium 106 via resistors 113-1 and 113-2 and capacitors 114-1 and 114-2 for paths 139-1 and 139-2, respectively. Capacitors 114-1 and 114-2 are each connected to ground. Differential capacitor 112 can be placed between resistors 113-1 and 113-2 and communication medium 106 across paths 139-1 and 139-2. In one embodiment, transceiver 102 and block A are co-located on a single wafer. In one embodiment, one or both of transceivers 102 and 104 are quadrature amplitude modulation (QAM) transceivers.
差動電容器112可耦合在路徑139-1及139-2之間以提供差動電容式終端並且可以減小電容器114-1及114-2的公差效果。電容器114-1及114-2係差動終端電容器,其可藉由形成至接地的放電路徑而提供防止瞬變的保護。當通信系統100暴露於頻率高於資料通信速率的EMI時,歸因於存在差動電容器112的路徑139-1及139-2上的低阻抗可減小接收器側上的EMI效果。此外,接收器上的低阻抗及高頻率可一起起作用來消除EMI。差動電容器112可減小接地連接的電容器114-1及114-2的公差效果。 A differential capacitor 112 can be coupled between paths 139-1 and 139-2 to provide a differential capacitive termination and can reduce the tolerance effects of capacitors 114-1 and 114-2. Capacitors 114-1 and 114-2 are differential termination capacitors that provide protection against transients by forming a discharge path to ground. When the communication system 100 is exposed to EMI having a frequency higher than the data communication rate, the EMI effect on the receiver side can be reduced due to the low impedance on the paths 139-1 and 139-2 where the differential capacitor 112 is present. In addition, the low impedance and high frequency on the receiver can work together to eliminate EMI. The differential capacitor 112 can reduce the tolerance effect of the grounded connected capacitors 114-1 and 114-2.
用方塊C整體顯示(與方塊A對稱),第二收發器104可經由分別針對路徑139-1及139-2的電阻器123-1及123-2以及電容器124-1及124-2耦合至通信媒體106。電容器124-1及124-2可連接至接地。差動電容器122可耦合在路徑139-1與139-2之間並且定位在電阻器123-1與123-2以及電阻器119-1與119-2之間。方塊C中的電容器以類似於方塊A中的電容器的方式操作。 As shown generally by block C (symmetric with block A), the second transceiver 104 can be coupled to via resistors 123-1 and 123-2 and capacitors 124-1 and 124-2 for paths 139-1 and 139-2, respectively. Communication medium 106. Capacitors 124-1 and 124-2 can be connected to ground. Differential capacitor 122 can be coupled between paths 139-1 and 139-2 and positioned between resistors 123-1 and 123-2 and resistors 119-1 and 119-2. The capacitor in block C operates in a manner similar to the capacitor in block A.
用隔離方塊B整體顯示,第二收發器104可透過變壓器118耦合至通信媒體106。變壓器118可為第二收發器104提供電壓隔離。在一些實例中,電阻器電路可用於將電流源轉化成電壓信號並且作為電壓分壓器提供信號衰減。例如,電阻器分壓器電路可用於定義第二收發器104上的信號並使信號衰減。此種電壓分壓可用於定標接收器上的電壓以允許與接收器特性的相容性。方塊A及C中的電阻器亦藉由透過通信媒體106限制信號的電流而提高防止瞬變事件的水準。 The second transceiver 104 can be coupled to the communication medium 106 via the transformer 118 as shown generally by the isolation block B. Transformer 118 can provide voltage isolation for second transceiver 104. In some examples, a resistor circuit can be used to convert a current source into a voltage signal and provide signal attenuation as a voltage divider. For example, a resistor divider circuit can be used to define the signal on the second transceiver 104 and attenuate the signal. This voltage division can be used to scale the voltage across the receiver to allow compatibility with receiver characteristics. The resistors in blocks A and C also increase the level of protection against transient events by limiting the current of the signal through communication medium 106.
在一實例中,電阻器分壓器電路可在針對每條通信路徑139-1、139-2的變壓器118的每一側上包括串聯電阻器。因此,在圖1A所示的實例中,第一電阻器119-1可串聯耦合在高路徑139-1與變壓器118之間。第二電阻器119-2可串聯耦合在路徑139-2與變壓器118之間。第三電阻器119-3可串聯耦合在第二收發器104的第三埠120-3與變壓器118之間。第四電阻器119-4可串聯耦合在第二收發器104的第四埠120-4與變壓器118之間。 In an example, the resistor divider circuit can include a series resistor on each side of the transformer 118 for each of the communication paths 139-1, 139-2. Thus, in the example shown in FIG. 1A, first resistor 119-1 can be coupled in series between high path 139-1 and transformer 118. The second resistor 119-2 can be coupled in series between the path 139-2 and the transformer 118. The third resistor 119-3 can be coupled in series between the third turn 120-3 of the second transceiver 104 and the transformer 118. The fourth resistor 119-4 can be coupled in series between the fourth turn 120-4 of the second transceiver 104 and the transformer 118.
電阻器分壓器電路亦可包括位於變壓器118兩側上耦合在通信路徑139-1、139-2之間的電阻器。因此,在圖1A所示的實例中,第五電阻器119-5耦合在高路徑139-1與低路徑139-2之間。此第五電阻器119-5在電路中耦合於通信媒體106與變壓器118之間。第六電阻器119-6亦可耦合在高路徑139-1與低路徑139-2之間。然而,此第六電阻器可在電路中耦合於變壓器118與第二收發器104的第三與第四埠120-3、120-4之間。電阻器119-1、119-2、119-3、119-4、119-5及119-6可用於提供如上所述之電壓分壓以進行信號衰減。在一實施例中,收發器104以及方塊B及C一起位於單晶片上。 The resistor divider circuit can also include a resistor coupled between communication paths 139-1, 139-2 on either side of transformer 118. Thus, in the example shown in FIG. 1A, a fifth resistor 119-5 is coupled between the high path 139-1 and the low path 139-2. This fifth resistor 119-5 is coupled in circuit between the communication medium 106 and the transformer 118. A sixth resistor 119-6 can also be coupled between the high path 139-1 and the low path 139-2. However, this sixth resistor can be coupled in circuit between the transformer 118 and the third and fourth turns 120-3, 120-4 of the second transceiver 104. Resistors 119-1, 119-2, 119-3, 119-4, 119-5, and 119-6 can be used to provide voltage division as described above for signal attenuation. In one embodiment, transceiver 104 and blocks B and C are located together on a single wafer.
圖1B係具有變壓器耦合的通信系統170的另一實施例的示意圖。通信系統170可包括類似於關於圖1A所述之通信系統100的許多組件。類似組件已用相同符號標注。通信系統170可包括與通信媒體106通信地耦合在一起的第一收發器102及第二收發器104。通信系統170亦可包括耦合在收發器102、104之間的複數個方塊D、E、F、G。每一方塊D、E、F及G包括組態為執行一個或多個功能的電路。 FIG. 1B is a schematic diagram of another embodiment of a communication system 170 having transformer coupling. Communication system 170 can include many components similar to communication system 100 described with respect to FIG. 1A. Similar components have been marked with the same symbol. Communication system 170 can include a first transceiver 102 and a second transceiver 104 communicatively coupled to communication medium 106. Communication system 170 can also include a plurality of blocks D, E, F, G coupled between transceivers 102, 104. Each block D, E, F, and G includes circuitry configured to perform one or more functions.
方塊D及E可提供允許信號傳輸同時減小EMI效果的低阻抗負載條件。系統170中的方塊D及E可類似於關於圖1A所述之方塊A及C,除方塊D及E不包括圖1A的可選串聯電阻器113-1、113-2及123-1、123-2以外。然而,電容器112、114-1、114-2、122、124-1及124-2以類似於 關於圖1A中的方塊A及C描述的方式發揮作用。 Blocks D and E provide low impedance load conditions that allow signal transmission while reducing EMI effects. Blocks D and E in system 170 may be similar to blocks A and C described with respect to FIG. 1A, except that blocks D and E do not include optional series resistors 113-1, 113-2, and 123-1, 123 of FIG. 1A. Outside of -2. However, capacitors 112, 114-1, 114-2, 122, 124-1, and 124-2 are similar The manner described with respect to blocks A and C in Fig. 1A functions.
通信系統170可包括一個或多個隔離方塊F及G以為收發器102、104提供隔離。隔離方塊F可位於終端方塊D與通信媒體106之間。隔離方塊F可包括耦合在第一及第二埠120-1、120-2與通信媒體106之間的變壓器121以為第一收發器102提供電壓隔離(例如,隔離邊界)。電阻器119-1、119-2及119-5可位於第一收發器102的第一及第二埠120-1、120-2與隔離方塊F的變壓器121之間。以此定位,電阻器119-1、119-2及119-5可以關於方塊C在電路100中所述之相同方式耦合在通信路徑139-1、139-2中。因此,第一電阻器119-1可串聯耦合在收發器102的第一埠120-1與隔離方塊F的變壓器121之間。第二電阻器119-2可串聯耦合在收發器102的第二埠120-2與隔離方塊F的變壓器121之間。第五電阻器119-5可耦合在高路徑139-1與低路徑139-2之間。在此實例中,第五電阻器119-5可在電路中耦合在收發器102的第一及第二埠120-1、120-2與隔離方塊F的變壓器121之間。因此,隔離方塊F可提供類似於圖1A的隔離方塊B的功能。 Communication system 170 may include one or more isolation blocks F and G to provide isolation for transceivers 102, 104. The isolation block F can be located between the terminal block D and the communication medium 106. The isolation block F can include a transformer 121 coupled between the first and second ports 120-1, 120-2 and the communication medium 106 to provide voltage isolation (e.g., isolation boundaries) for the first transceiver 102. Resistors 119-1, 119-2, and 119-5 may be located between first and second turns 120-1, 120-2 of first transceiver 102 and transformer 121 of isolation block F. With this positioning, resistors 119-1, 119-2, and 119-5 can be coupled in communication paths 139-1, 139-2 in the same manner as described in block C in circuit 100. Thus, the first resistor 119-1 can be coupled in series between the first 埠 120-1 of the transceiver 102 and the transformer 121 of the isolation block F. The second resistor 119-2 can be coupled in series between the second turn 120-2 of the transceiver 102 and the transformer 121 of the isolation block F. A fifth resistor 119-5 can be coupled between the high path 139-1 and the low path 139-2. In this example, a fifth resistor 119-5 can be coupled in the electrical circuit between the first and second turns 120-1, 120-2 of the transceiver 102 and the transformer 121 of the isolation block F. Thus, the isolation block F can provide functionality similar to the isolation block B of Figure 1A.
在一些實例中,隔離方塊可包括在通信媒體106的每一端部上以便在通信媒體106與收發器102、104之一者斷開連接時為可能與通信媒體106發生接觸的使用者提供保護。例如,此可能在通信系統100的安裝或維護期間發生。圖1B圖解說明包括兩個隔離方塊F及G的此類電路,每一收發器102、104上有一個隔離方塊。如所示,隔離方塊G 可為隔離方塊F的鏡像。因此,隔離方塊G可包括耦合在第三及第四埠120-3、120-4與通信媒體106之間的變壓器118以為第二收發器104提供電壓隔離(例如,隔離邊界)。隔離方塊G可包括電阻器119-3、119-4及119-6,該電阻器可位於第二收發器104的第三及第四埠120-3、120-4與隔離方塊G的變壓器118之間。電阻器119-3、119-4及119-6可與關於方塊C在電路100中所述相同的方式耦合在通信路徑139-1、139-2中。因此,電阻器119-3可串聯耦合在收發器104的第三埠120-3及隔離方塊G的變壓器118之間。電阻器119-4可串聯耦合在收發器104的第四埠120-4與隔離方塊G的變壓器118之間。電阻器119-6可耦合在高路徑139-1與低路徑139-2之間。在此實例中,電阻器119-6可在電路中耦合於收發器104的第三及第四埠120-3、120-4與隔離方塊G的變壓器118之間,因此,隔離方塊G可提供類似於隔離方塊F的功能。 In some examples, an isolation block can be included on each end of the communication medium 106 to provide protection to a user who may be in contact with the communication medium 106 when the communication medium 106 is disconnected from one of the transceivers 102, 104. For example, this may occur during installation or maintenance of communication system 100. FIG. 1B illustrates such circuitry including two isolation blocks F and G, with one isolation block on each transceiver 102, 104. As shown, the isolation block G Can be a mirror image of the isolation block F. Accordingly, the isolation block G can include a transformer 118 coupled between the third and fourth ports 120-3, 120-4 and the communication medium 106 to provide voltage isolation (eg, an isolation boundary) for the second transceiver 104. The isolation block G can include resistors 119-3, 119-4, and 119-6, which can be located at the third and fourth ports 120-3, 120-4 of the second transceiver 104 and the transformer 118 of the isolation block G. between. Resistors 119-3, 119-4, and 119-6 can be coupled in communication paths 139-1, 139-2 in the same manner as described with respect to block C in circuit 100. Thus, resistor 119-3 can be coupled in series between third turn 120-3 of transceiver 104 and transformer 118 of isolation block G. Resistor 119-4 can be coupled in series between fourth turn 120-4 of transceiver 104 and transformer 118 of isolation block G. Resistor 119-6 can be coupled between high path 139-1 and low path 139-2. In this example, resistor 119-6 can be coupled in circuit between third and fourth turns 120-3, 120-4 of transceiver 104 and transformer 118 of isolation block G, thus, isolation block G can provide Similar to the function of the isolation block F.
下文就單向通信態樣描述通信系統100、170的功能性,但是應瞭解系統100及170可以提供雙向通信。第一收發器102(充當傳輸器)可將信號傳輸至第二收發器104(充當接收器)。雖然第一收發器102正在傳輸,但是分別在方塊A及D中的電容器及電阻器可控制信號的邊緣速率(即,信號的上升時間)。在一實施例中,所傳輸信號可由收發器102中的圖4中下文描述的開關式電流源修改使得電容器112、114-1及114-2接收斜坡信號。來自此個信號的EMI發射頻率由斜坡的上升時間確定,其中提高傳輸信 號的頻率增大EMI的功率。因此,通信系統100及170中的功率可由邊緣頻率確定。隨著收發器102所傳輸的信號上升時間減短,經由通信媒體106傳輸的信號頻率亦減小。由於通信系統100、170的分離差動結構以及收發器102至通信媒體106的耦合可減小潛在EMI。方塊C及E可分別以類似於方塊A及D如何影響從第一傳輸器102傳輸的信號的方式影響從第二收發器104傳輸的信號。 The functionality of the communication systems 100, 170 is described below with respect to one-way communication aspects, but it should be appreciated that the systems 100 and 170 can provide two-way communication. The first transceiver 102 (acting as a transmitter) can transmit signals to the second transceiver 104 (acting as a receiver). Although the first transceiver 102 is transmitting, the capacitors and resistors in blocks A and D, respectively, can control the edge rate of the signal (ie, the rise time of the signal). In an embodiment, the transmitted signal may be modified by the switched current source described below in FIG. 4 in transceiver 102 such that capacitors 112, 114-1, and 114-2 receive the ramp signal. The EMI transmission frequency from this signal is determined by the rise time of the ramp, where the transmission signal is increased The frequency of the number increases the power of the EMI. Thus, the power in communication systems 100 and 170 can be determined by the edge frequency. As the signal rise time transmitted by transceiver 102 is reduced, the frequency of the signal transmitted via communication medium 106 is also reduced. The potential EMI can be reduced due to the separate differential structure of the communication systems 100, 170 and the coupling of the transceiver 102 to the communication medium 106. Blocks C and E can affect the signals transmitted from the second transceiver 104 in a manner similar to how blocks A and D affect the signals transmitted from the first transmitter 102, respectively.
圖1A中所示的可選電阻器113-1及113-2可改良極高頻率(VHF)EMI的消除以及收發器102及104的引腳輸入電容。包括電流源導出的傳輸方案的通信系統100的一些實施例可能不包括電阻器113-1及113-2。 The optional resistors 113-1 and 113-2 shown in FIG. 1A can improve the elimination of very high frequency (VHF) EMI and the pin input capacitance of the transceivers 102 and 104. Some embodiments of communication system 100 including a current source derived transmission scheme may not include resistors 113-1 and 113-2.
本文描述方塊A、B、C、D、E及F中的組件的值的實例來圖解說明與特定電流源值關係相稱的信號位準。應注意此實例僅為闡釋性,並且電容、電阻及電感可為任何合適值。 Examples of values of components in blocks A, B, C, D, E, and F are described herein to illustrate signal levels commensurate with a particular current source value relationship. It should be noted that this example is merely illustrative and that the capacitance, resistance, and inductance can be any suitable value.
圖1C係利用圖1A的通信系統100、圖1B的通信系統170或兩者的菊鏈系統140的一實施例的方塊圖。系統140包括使用複數個通信系統100、170以菊鏈方式通信地耦合在一起的N個裝置142-1至142-N。裝置142-1通信地耦合至第一收發器150-1,第一收發器150-1耦合至通信媒體106-1,通信媒體106-1耦合至第二收發器150-2,第二收發器150-2繼而耦合至裝置142-2。第一收發器150-1、通信媒體106-1及第二收發器150-2組成通信系統100或通信系統170並且因此如圖1A或圖1B所示耦合在一起。接著第二裝置142-2可提供時脈信號及資料信號給第三收發器150-3以沿著菊鏈向下傳輸至一個或多個裝置142-N。第三收發器150-3耦合至通信媒體106-2。其他裝置142-N可經由耦合至通信媒體106-(N-1)的收發器150-M從裝置沿著菊鏈向上接收信號。如此,收發器150-M利用通信媒體106-N將裝置142-N鏈結至菊鏈系統140。每一收發器150-1至150-N可具有至少兩個傳輸/接收埠(例如,120-1、120-2)。此外,對應於圖1A及圖1B的方塊A-G的電路可包括在各自的收發器150-1至150-N之間。 1C is a block diagram of an embodiment of a daisy chain system 140 utilizing the communication system 100 of FIG. 1A, the communication system 170 of FIG. 1B, or both. System 140 includes N devices 142-1 through 142-N communicatively coupled together in a daisy chain using a plurality of communication systems 100, 170. Apparatus 142-1 is communicatively coupled to first transceiver 150-1, first transceiver 150-1 is coupled to communication medium 106-1, communication medium 106-1 is coupled to second transceiver 150-2, second transceiver 150-2 is then coupled to device 142-2. The first transceiver 150-1, the communication medium 106-1, and the second transceiver 150-2 form a communication system 100 or communication system 170 and are thus coupled together as shown in FIG. 1A or FIG. 1B. The second device 142-2 can then provide a clock signal and a data signal to the third transceiver 150-3 for transmission down the daisy chain to one or more devices 142-N. The third transceiver 150-3 is coupled to the communication medium 106-2. The other device 142-N can receive signals from the device along the daisy chain via the transceiver 150-M coupled to the communication medium 106-(N-1). As such, the transceiver 150-M utilizes the communication medium 106-N to link the device 142-N to the daisy chain system 140. Each transceiver 150-1 to 150-N may have at least two transmission/reception ports (e.g., 120-1, 120-2). Further, circuits corresponding to blocks A-G of FIGS. 1A and 1B may be included between respective transceivers 150-1 to 150-N.
在一實施例中,菊鏈系統140可如下發揮作用。菊鏈系統140的時序由系統時脈152控制。裝置142-1提供來自系統時脈152的時脈(CLK)信號及資料信號給收發器150-1。收發器150-1可以將資料信號及時脈信號組合以形 成混合式編碼資料信號(在本文中亦稱為菊鏈信號)。混合式編碼資料信號係振幅調變方波信號且例如可根據下文論述的曼徹斯特編碼方案形成。此混合式編碼資料信號可經由通信媒體106-1傳輸至收發器150-2。在接收模式下操作,收發器150-2可以接收混合式編碼資料信號、將該信號解碼以提取資料信號及時脈信號。接著收發器150-2可提供資料信號及時脈信號給裝置142-2。 In an embodiment, the daisy chain system 140 can function as follows. The timing of the daisy chain system 140 is controlled by the system clock 152. Device 142-1 provides a clock (CLK) signal and data signal from system clock 152 to transceiver 150-1. The transceiver 150-1 can combine the data signal and the pulse signal to form A mixed coded data signal (also referred to herein as a daisy chain signal). The hybrid coded data signal is an amplitude modulated square wave signal and can be formed, for example, according to the Manchester coding scheme discussed below. This hybrid encoded data signal can be transmitted to transceiver 150-2 via communication medium 106-1. Operating in the receive mode, the transceiver 150-2 can receive the hybrid encoded data signal, decode the signal to extract the data signal and the pulse signal. Transceiver 150-2 can then provide a data signal to the device 142-2.
可以貫穿菊鏈系統140類似地重複此個過程。例如,在資料信號及時脈信號提供給裝置142-2後,裝置142-2可提供時脈信號及其自身的資料信號給收發器150-3以沿著菊鏈向下傳達給裝置142-N。收發器150-3可耦合至通信媒體106-2並且收發器150-3可將來自裝置142-2的資料信號與來自收發器150-2的所提取的時脈信號組合以形成第二混合式編碼資料信號。此第二混合式編碼資料信號可沿著菊鏈向下傳輸至收發器150-M。收發器150-M可接收混合式編碼資料信號,並且將信號解碼以提取資料信號及時脈信號。接著收發器150-M可提供資料信號及時脈信號給裝置142-N。因此,菊鏈收發器150-2至150-N可將來自系統時脈152的所提取的時脈信號提供給裝置142-2至142-N。 This process can be repeated similarly throughout the daisy chain system 140. For example, after the data signal and the pulse signal are provided to the device 142-2, the device 142-2 can provide the clock signal and its own data signal to the transceiver 150-3 for transmission down the daisy chain to the device 142-N. . Transceiver 150-3 can be coupled to communication medium 106-2 and transceiver 150-3 can combine the data signal from device 142-2 with the extracted clock signal from transceiver 150-2 to form a second hybrid Encoded data signals. This second hybrid encoded data signal can be transmitted down the daisy chain to the transceiver 150-M. The transceiver 150-M can receive the mixed encoded data signal and decode the signal to extract the data signal and the pulse signal. The transceiver 150-M can then provide a data signal to the device 142-N. Thus, the daisy-chain transceivers 150-2 through 150-N can provide the extracted clock signals from the system clock 152 to the devices 142-2 through 142-N.
如此,如圖1C所示,一個或多個通信系統100、170可以菊鏈方式鏈結在一起。菊鏈信號可將資料舉例而言諸如暫存器內容、裝置命令及讀取或寫入暫存器內容從一個裝置142-1、142-2、142-3、142-N提供給另一個裝置。 As such, as shown in FIG. 1C, one or more of the communication systems 100, 170 can be chained together in a daisy chain. The daisy chain signal can provide information such as register contents, device commands, and read or write scratchpad contents from one device 142-1, 142-2, 142-3, 142-N to another device, for example. .
在一實施例中,收發器150-1可封裝至單晶片上,單晶 片可與對應於方塊A-G的適當電路一起安裝至板上。接著該板可連接至裝置例如裝置142-1。在一實施例中,菊鏈系統140可用於將複數個裝置142-1、142-2、142-N以菊鏈方式耦合至複數個電池單元。菊鏈系統142可為進入電池組的模組。在一實施例中,電池單元為鋰離子(Li離子)電池單元。在另一實施例中,12個Li離子電池單元藉由通信系統100、170連接以保護穩健模組使之免遭瞬變事件及EMI。 In an embodiment, the transceiver 150-1 can be packaged onto a single wafer, single crystal The sheets can be mounted to the board along with appropriate circuitry corresponding to blocks A-G. The board can then be connected to a device such as device 142-1. In an embodiment, the daisy chain system 140 can be used to daisy-chain a plurality of devices 142-1, 142-2, 142-N to a plurality of battery cells. The daisy chain system 142 can be a module that enters the battery pack. In an embodiment, the battery unit is a lithium ion (Li ion) battery unit. In another embodiment, 12 Li-ion battery cells are connected by communication systems 100, 170 to protect the robust module from transient events and EMI.
圖2A係包括傳輸器210及接收器230的收發器200的一實施例的方塊圖。傳輸器210包括DC平衡資料編碼器212、乘法器214及求和器216。傳輸器210例如經由通信媒體106從裝置接收資料信號及時脈信號、將資料編碼、將該編碼資料與放大時脈信號組合並傳輸該資料。接收器230例如經由通信媒體106接收混合式編碼資料信號、將該資料信號解碼並提取時脈信號。 2A is a block diagram of an embodiment of a transceiver 200 that includes a transmitter 210 and a receiver 230. The transmitter 210 includes a DC balanced data encoder 212, a multiplier 214, and a summer 216. The transmitter 210 receives the data signal and the pulse signal from the device, for example, via the communication medium 106, encodes the data, combines the encoded data with the amplified clock signal, and transmits the data. Receiver 230 receives the hybrid encoded data signal, for example, via communication medium 106, decodes the data signal, and extracts the clock signal.
DC平衡資料編碼器212的一實施例採用曼徹斯特編碼;但是,DC平衡資料編碼器212可利用DC平衡資料的任何其他編碼方案。曼徹斯特編碼係針對每一資料比特、針對50%效率水準提供兩個時脈週期的基本編碼方案。換句話說,曼徹斯特編碼資料串流的每兩個邊緣產生一比特的資料。 An embodiment of DC balanced data encoder 212 employs Manchester encoding; however, DC balanced data encoder 212 may utilize any other encoding scheme for DC balanced data. The Manchester coding system provides a basic coding scheme for two clock cycles for each data bit, for a 50% efficiency level. In other words, every two edges of the Manchester encoded data stream produce one bit of data.
在一實施例中,具有類似振幅的資料(DATA)信號及時脈(CLK)信號在DC平衡資料編碼器212中被編碼。CLK信號及DATA信號被組合成基於振幅調變曼徹斯特編碼方案 的時序編碼信號。因此,時脈信號可容易地從曼徹斯特編碼資料恢復而無需鎖相回路(PLL),此係因為CLK信號嵌入在時序編碼信號中。此外,因為PLL非必需,所以用於觸發PLL的訓練順序不必添加至DC平衡資料編碼器212的輸出。因此,由於時序編碼信號無需被鎖定至時脈,所以DATA信號的每一比特可恢復而無延遲。 In one embodiment, a data (DATA) signal with a similar amplitude (CLK) signal is encoded in the DC balanced data encoder 212. CLK signal and DATA signal are combined into an amplitude-modulated Manchester coding scheme Timing coded signal. Therefore, the clock signal can be easily recovered from the Manchester encoded data without the need for a phase locked loop (PLL) because the CLK signal is embedded in the timing encoded signal. Furthermore, since the PLL is not necessary, the training sequence for triggering the PLL does not have to be added to the output of the DC balanced data encoder 212. Therefore, since the timing coded signal does not need to be locked to the clock, each bit of the DATA signal can be recovered without delay.
使用乘法器214,時脈信號的振幅乘以一個因數,例如2。求和器216將時序編碼信號及所乘得的CLK信號加總(該等信號分別為DC平衡資料編碼器212及乘法器214的輸出)並且產生傳輸至接收器230的總計輸出。 Using multiplier 214, the amplitude of the clock signal is multiplied by a factor, such as two. Summer 216 sums the time-coded signal and the multiplied CLK signal (the signals are the outputs of DC balance data encoder 212 and multiplier 214, respectively) and produces a total output that is transmitted to receiver 230.
接收器230包括零交叉偵測器232及求和器236,兩者直接耦合至傳輸器210、乘法器234及資料解碼器238。零交叉偵測器232接收傳輸的編碼信號並在其輸出終端恢復CLK信號。零交叉偵測器232的輸出藉由乘法器234相乘並且供應至求和器236的第一輸入終端。求和器236在其第二輸入終端上接收所傳輸信號。資料解碼器238接收求和器236的輸出以及由零交叉偵測器232恢復的時脈信號以恢復資料。在點A處所示的信號具有類似振幅。 Receiver 230 includes a zero crossing detector 232 and a summer 236, both coupled directly to transmitter 210, multiplier 234, and data decoder 238. Zero crossing detector 232 receives the transmitted encoded signal and recovers the CLK signal at its output terminal. The output of zero crossing detector 232 is multiplied by multiplier 234 and supplied to the first input terminal of summer 236. Summer 236 receives the transmitted signal on its second input terminal. Data decoder 238 receives the output of summer 236 and the clock signal recovered by zero crossing detector 232 to recover the data. The signal shown at point A has a similar amplitude.
圖2B係包括傳輸器260及接收器270的收發器250的一實施例的方塊圖。傳輸器260類似於傳輸器210,除傳輸器260使用XOR閘262代替DC平衡及資料編碼器212以外。同樣地,接收器270類似於接收器220,除接收器270使用XOR閘278代替資料解碼器278以外。編碼信號藉由混合曼徹斯特編碼信號(由XOR閘262產生)及時脈信號 以提供混合式編碼信號而產生。混合式編碼信號係在每一時脈邊緣上具有零交叉的振幅調變信號。混合式編碼信號維持資料信號的全面完整性。使用簡單的邏輯及電壓求和節點或者使用如下文圖4及圖5中所示的開關式電流源產生信號。出於闡釋性目的,圖2A及圖2B中使用2:1關係,但是可實施任何比率。 2B is a block diagram of an embodiment of a transceiver 250 that includes a transmitter 260 and a receiver 270. Transmitter 260 is similar to transmitter 210 except that transmitter 260 uses XOR gate 262 in place of DC balance and data encoder 212. Similarly, receiver 270 is similar to receiver 220 except that receiver 270 uses XOR gate 278 instead of data decoder 278. The encoded signal is mixed with a Manchester encoded signal (generated by XOR gate 262). Produced by providing a mixed coded signal. The hybrid coded signal has an amplitude modulated signal with zero crossings on each clock edge. The hybrid coded signal maintains the full integrity of the data signal. The signal is generated using a simple logic and voltage summing node or using a switched current source as shown in Figures 4 and 5 below. For illustrative purposes, a 2:1 relationship is used in Figures 2A and 2B, but any ratio can be implemented.
圖3A係在其輸入處接收差動菊鏈信號並且可從該差動菊鏈信號恢復時脈信號及資料信號的接收器300的一實施例的方塊圖。接收器300包括差動接收器302。差動接收器302將差動菊鏈信號轉換成單端信號,單端信號被供給至比較器304、306及308的第一輸入中。臨限Vth1、Vth2及Vth3分別被輸入至比較器304、306及308的第二輸入,並且定義各種菊鏈狀態的信號位準。比較器304、306及308的輸出被輸入至將輸入信號解碼成CLK信號及DATA信號的解碼器及濾波器310。零交叉定義CLK信號,其中正負電壓擺動與菊鏈信號的‘0’及‘1’狀態相關。即,比較器306所偵測到的每一零交叉被轉化成時脈信號的邊緣。而且,比較器304及306將脈衝(例如,正負電壓擺動)轉化成資料信號的數位值。 3A is a block diagram of an embodiment of a receiver 300 that receives a differential daisy chain signal at its input and recovers a clock signal and a data signal from the differential daisy chain signal. Receiver 300 includes a differential receiver 302. The differential receiver 302 converts the differential daisy chain signal into a single ended signal that is supplied to the first inputs of the comparators 304, 306, and 308. The thresholds Vth1, Vth2, and Vth3 are input to the second inputs of the comparators 304, 306, and 308, respectively, and define signal levels for various daisy chain states. The outputs of comparators 304, 306, and 308 are input to a decoder and filter 310 that decodes the input signal into a CLK signal and a DATA signal. The zero crossing defines the CLK signal, where the positive and negative voltage swings are related to the '0' and '1' states of the daisy chain signal. That is, each zero crossing detected by comparator 306 is converted to the edge of the clock signal. Moreover, comparators 304 and 306 convert pulses (e.g., positive and negative voltage swings) into digital values of the data signal.
圖3B係對應於圖3A的接收器300的時序圖。菊鏈信號係輸入至差動接收器302的差動輸入信號。信號A、B及C分別對應於比較器304、306及308的輸出。在此實例中,比較器306比較差動菊鏈信號與臨限Vth2。臨限Vth2具有0電壓或標稱電壓。因此,比較器306偵測零交叉並且直接 恢復時脈信號B。臨限Vth1及Vth3被設定為偵測菊鏈信號的高位準轉化。臨限Vth1被設定為偵測高振幅脈衝並且忽略低振幅脈衝。比較器304使用臨限Vth1輸出信號A,信號A對於每一高振幅脈衝具有脈衝。類似地,臨限Vth3被設定為只偵測低振幅脈衝,其中比較器308輸出針對菊鏈信號上的每一低振幅脈衝具有脈衝的信號C。解碼器及濾波器310將信號A、B及C解析為CLK信號DATA信號。在一實施例中,解碼器及濾波器310包括時脈濾波器、資料濾波器及資料重定時功能,如圖7中下文更詳細描述。 FIG. 3B is a timing diagram corresponding to the receiver 300 of FIG. 3A. The daisy chain signal is a differential input signal that is input to the differential receiver 302. Signals A, B, and C correspond to the outputs of comparators 304, 306, and 308, respectively. In this example, comparator 306 compares the differential daisy chain signal to the threshold Vth2. The threshold Vth2 has a voltage of 0 or a nominal voltage. Therefore, the comparator 306 detects zero crossings and directly Restore clock signal B. The thresholds Vth1 and Vth3 are set to detect high level conversion of the daisy chain signal. The threshold Vth1 is set to detect high amplitude pulses and ignore low amplitude pulses. Comparator 304 uses a threshold Vth1 output signal A, which has a pulse for each high amplitude pulse. Similarly, threshold Vth3 is set to detect only low amplitude pulses, with comparator 308 outputting a signal C having a pulse for each low amplitude pulse on the daisy chain signal. The decoder and filter 310 resolves signals A, B, and C into CLK signal DATA signals. In one embodiment, the decoder and filter 310 includes a clock filter, a data filter, and a data retiming function, as described in more detail below in FIG.
圖3C係接收器330的一個替代實施例的方塊圖。如同接收器300,接收器330包括比較器304、306及308以及解碼器及濾波器310。然而,接收器330不像接收器300中那樣具有差動接收器302。而是,第一菊鏈信號直接提供給比較器304、306及308的第一輸入。第二菊鏈信號(第一菊鏈信號的反轉)提供給由臨限Vth1修改的比較器304的第二輸入、直接提供給比較器306的第二輸入以及提供給由臨限Vth3修改的比較器308的第二輸入。 FIG. 3C is a block diagram of an alternate embodiment of receiver 330. Like receiver 300, receiver 330 includes comparators 304, 306, and 308, as well as a decoder and filter 310. However, the receiver 330 does not have the differential receiver 302 as in the receiver 300. Rather, the first daisy chain signal is provided directly to the first inputs of comparators 304, 306, and 308. The second daisy chain signal (inversion of the first daisy chain signal) is provided to the second input of the comparator 304 modified by the threshold Vth1, the second input provided directly to the comparator 306, and to the modified by the threshold Vth3 The second input of comparator 308.
圖4係收發器400的一實施例的示意圖,其係使用電流源構造。基於電壓源的替代構造亦係可行的。收發器400包括整體用410顯示的傳輸器及整體用430顯示的接收器。收發器400在輸入A、B、C、D、E及F處接收控制信號以及其對應的反轉信號、及。線406-1及406-2係前進至引腳外(例如,在一些實施例中係在外部裝置上)連接至通信媒體(例如,通信媒體106)的差動線。線408-1 及408-2供應電力給收發器400。收發器400在下文描述的正常模式、接收模式、傳輸模式及睡眠模式此四種模式下操作。 4 is a schematic diagram of an embodiment of a transceiver 400 that is constructed using a current source. Alternative configurations based on voltage sources are also possible. Transceiver 400 includes a transmitter that is generally shown at 410 and a receiver that is shown generally at 430. Transceiver 400 receives control signals and their corresponding inverted signals at inputs A, B, C, D, E, and F , and . Lines 406-1 and 406-2 are advanced to the differential line that is external to the pin (e.g., on an external device in some embodiments) to a communication medium (e.g., communication medium 106). Lines 408-1 and 408-2 supply power to transceiver 400. The transceiver 400 operates in the four modes of the normal mode, the reception mode, the transmission mode, and the sleep mode described below.
收發器400進一步包括接收放大器402、零交叉偵測器404及睡眠模式接收器403。收發器進一步包括整體由420顯示的開關電路。圖4進一步圖解說明將時脈及曼徹斯特編碼資料組合成混合式編碼信號的多個開關式電流源。傳輸器410包括顯示為1x單位源及3x單位源的複數個傳輸電流源412,同時接收器430控制顯示為0.289x單位的複數個接收電流源432。此等比率在傳輸及接收期間產生特定波形並且適應特定外部電路值。但是,應瞭解在其他實施方案中使用其他值。 The transceiver 400 further includes a receive amplifier 402, a zero crossing detector 404, and a sleep mode receiver 403. The transceiver further includes a switching circuit that is shown generally by 420. Figure 4 further illustrates a plurality of switched current sources that combine clock and Manchester encoded data into a mixed encoded signal. Transmitter 410 includes a plurality of transmit current sources 412 shown as 1x unit sources and 3x unit sources, while receiver 430 controls a plurality of receive current sources 432 shown as 0.289x units. These ratios produce specific waveforms during transmission and reception and are adapted to specific external circuit values. However, it should be understood that other values are used in other embodiments.
在正常模式期間,在菊鏈上無活動並且菊鏈系統中的每一收發器400的兩個接收器埠準備接收信號。在正常模式中,收發器400等待偵測到達連接至該兩個接收器埠的線406-1及406-2的菊鏈信號。在正常模式中,接收放大器402及驅動電流源432的零交叉偵測器404起作用。當接收器430處於正常模式中時,接收放大器402起作用並且轉化輸入波形電壓位準及時序以供隨後解碼。零交叉偵測器404產生接收伺服信號B及。接收伺服信號B及控制電流源432並且在正常模式及接收模式期間起作用。 During the normal mode, there is no activity on the daisy chain and the two receivers of each transceiver 400 in the daisy chain system are ready to receive signals. In the normal mode, transceiver 400 waits to detect daisy-chain signals arriving at lines 406-1 and 406-2 connected to the two receivers. In the normal mode, the receive amplifier 402 and the zero crossing detector 404 of the drive current source 432 function. When receiver 430 is in the normal mode, receive amplifier 402 acts and converts the input waveform voltage level and timing for subsequent decoding. Zero crossing detector 404 generates receiving servo signal B and . Receiving servo signal B and Current source 432 is controlled and functions during normal mode and receive mode.
在接收模式期間,收發器400在接收埠上偵測到從菊鏈傳入的傳輸。收發器400中繼接收埠上傳入至傳輸埠上將沿著菊鏈傳輸至下一個收發器的資訊。在正常模式期間 起作用的每一組件在接收模式期間亦起作用。旁路開關421-1及421-2具有低開放電容從而不以B及以及電流源432產生的接收伺服信號負載輸入波形。接收伺服電流源432經過調整以對R3進行任何改變。當收發器400處於接收模式中時,信號B及維持匯流排空閒狀態並促進正確的DC值。在正常模式或接收模式中,電流源C、、D及關閉,因為其正處於傳輸功能狀態。開關A在接收模式中為開放,所以從輸入至接收伺服電流源432的路徑經過電阻器R4。 During the receive mode, transceiver 400 detects a transmission from the daisy chain on the receive port. The transceiver 400 relays the information transmitted on the transmission to the next transceiver along the daisy chain. Each component that functions during normal mode also functions during the receive mode. Bypass switches 421-1 and 421-2 have low open capacitance so as not to B and And receiving the servo signal load input waveform generated by the current source 432. Receive servo current source 432 is adjusted to make any changes to R3. When the transceiver 400 is in the receiving mode, the signal B and Maintain the bus idle state and promote the correct DC value. In normal mode or receive mode, current source C, , D and Closed because it is in the transfer function state. Switch A is open in the receive mode, so the path from input to receive servo current source 432 passes through resistor R4.
信號C及係1x單位電流源開關驅動信號,其控制1x單位傳輸電流源412,1x單位傳輸電流源412在接收模式期間停用。信號D及係3x單位電流源開關驅動信號,其控制3x單位傳輸電流源412,3x單位傳輸電流源412在接收模式期間亦係停用的。如下所述,圖5係驅動信號C、、D及的例示性編碼器。 Signal C and A 1x unit current source switch drive signal that controls a 1x unit transfer current source 412 that is deactivated during the receive mode. Signal D and A 3x unit current source switch drive signal that controls the 3x unit transfer current source 412, which is also disabled during the receive mode. As shown below, Figure 5 is the driving signal C, , D and An exemplary encoder.
在傳輸模式中,收發器400沿著菊鏈傳輸編碼信號。當收發器400處於傳輸模式中時信號B及停用並且控制信號C、、D及開啟。開關A閉合,所以電阻器R4被旁通,產生返回電阻器R3的低阻抗路徑。輸出位準由R3的值及經過R3的電流值設定,經過R3的電流由具有C、、D及的電流源412引起。接收器430在傳輸模式期間停用。 In the transmission mode, the transceiver 400 transmits the encoded signal along the daisy chain. Signal B and when transceiver 400 is in transmission mode Deactivate and control signal C, , D and Open. Switch A is closed, so resistor R4 is bypassed, creating a low impedance path to return resistor R3. The output level is set by the value of R3 and the current value through R3. The current through R3 has C. , D and Current source 412 is caused. Receiver 430 is deactivated during the transmission mode.
睡眠模式使收發器400進入低電流狀態,其中接收放大器402及零交叉偵測器404斷電,而睡眠模式接收器403通電。控制信號B、、C、、D及在睡眠模式中關閉。 在睡眠模式期間開關E開放。在一實施例中,電阻器R2與電阻器R1的電阻比較具有高值電阻。與正常模式相比,其中開關E閉合,電阻器R2被旁通,在睡眠模式中電流流過電阻器R2及R1。在一實施例中,在電阻器R1與R3的中心連接之間存在緩衝器。 The sleep mode causes transceiver 400 to enter a low current state in which receive amplifier 402 and zero crossing detector 404 are powered down and sleep mode receiver 403 is powered. Control signal B, , C, , D and Turns off in sleep mode. Switch E is open during sleep mode. In one embodiment, resistor R2 has a high value resistance compared to the resistance of resistor R1. Compared to the normal mode, in which the switch E is closed and the resistor R2 is bypassed, current flows through the resistors R2 and R1 in the sleep mode. In an embodiment, there is a buffer between the center connections of resistors R1 and R3.
睡眠模式接收器403在其在路徑139-1或139-2上偵測到零交叉時將收發器400從睡眠模式喚醒。在一實施例中,睡眠模式接收器403處理4 kHz輸入時脈信號並且在相對低功率下操作。一旦識別喚醒條件,睡眠模式接收器即視需要關閉並且傳輸模式接收器402啟動。在收發器400係菊鏈的一部分的實施例中,傳輸器410亦啟動並且用於將喚醒信號中繼至下一個鏈結裝置。 Sleep mode receiver 403 wakes transceiver 400 from sleep mode when it detects a zero crossing on path 139-1 or 139-2. In an embodiment, sleep mode receiver 403 processes the 4 kHz input clock signal and operates at relatively low power. Once the wake condition is identified, the sleep mode receiver is turned off as needed and the transmission mode receiver 402 is activated. In an embodiment where the transceiver 400 is part of a daisy chain, the transmitter 410 is also activated and used to relay the wake-up signal to the next link device.
傳輸模式接收器402亦供給在接收模式期間提供通信空閒狀態伺服信號的零交叉偵測器404。此種功能可用於維持與多種傳輸電路的相容性並且在一些實例中不用於圖1A及圖1B所示的實施例。通信空閒狀態由皆處於預定邏輯位準的時脈信號及資料信號引起。在一實施例中,所有傳輸始於空閒狀態中的匯流排並且匯流排總是在傳輸後回復至空閒狀態。接收器430在通信超時之後被迫進入匯流排空閒狀態(如果不是事先在此狀態下)作為錯誤恢復系統的一部分。在一些實施例中,取決於用於高頻率(HF)雜訊消除的過濾位置,用於伺服功能的零交叉偵測器404與用於時脈恢復的偵測器相同。在其他實施例中,零交叉偵測器404不執行時脈恢復。 The transmit mode receiver 402 also supplies a zero crossing detector 404 that provides a communication idle state servo signal during the receive mode. Such functionality can be used to maintain compatibility with a variety of transmission circuits and is not used in the examples shown in Figures 1A and 1B in some examples. The communication idle state is caused by clock signals and data signals that are both at predetermined logic levels. In an embodiment, all transmissions begin with a bus in the idle state and the bus always returns to an idle state after transmission. Receiver 430 is forced into the bus idle state (if not previously in this state) after the communication has timed out as part of the error recovery system. In some embodiments, the zero crossing detector 404 for the servo function is the same as the detector for clock recovery, depending on the filtering position for high frequency (HF) noise cancellation. In other embodiments, zero crossing detector 404 does not perform clock recovery.
收發器400進一步包括整體用420顯示的開關電路,該開關電路經由在傳輸模式與接收模式之間觸發收發器400的信號進行開關。開關電路420包括接收在A處提供的信號的旁路電阻器R4及旁路開關421-1及421-2。信號A驅動開關電路420,開關電路420在收發器400處於傳輸模式時使電阻器R4旁通。當收發器400正在接收時,電阻器R4將驅動阻抗與外部電路阻抗隔離。假定係理想開關,則電阻器R4的例示性值係10 kΩ;然而,可使用任何合適電阻值。當為源電阻器R3製定大小時,將旁路開關421-1及421-2的開啟電阻考慮在內。電阻器R3與傳輸器410及接收器430兩者的電流源相互作用並提供傳輸器源阻抗及傳輸信號位準的驅動位準設定。R3的例示性值包括200 Ω、150 Ω及100 Ω或任何其他合適電阻值。 The transceiver 400 further includes a switching circuit, shown generally at 420, that switches via a signal that triggers the transceiver 400 between a transmission mode and a reception mode. Switching circuit 420 includes a shunt resistor R4 and bypass switches 421-1 and 421-2 that receive the signal provided at A. Signal A drives switch circuit 420, which bypasses resistor R4 when transceiver 400 is in the transmit mode. When the transceiver 400 is receiving, the resistor R4 isolates the drive impedance from the external circuit impedance. Assuming an ideal switch, the exemplary value of resistor R4 is 10 kΩ; however, any suitable resistance value can be used. When the source resistor R3 is sized, the turn-on resistance of the bypass switches 421-1 and 421-2 is taken into consideration. Resistor R3 interacts with the current sources of both transmitter 410 and receiver 430 and provides a drive level setting for the transmitter source impedance and transmission signal level. Exemplary values for R3 include 200 Ω, 150 Ω, and 100 Ω or any other suitable resistance value.
信號E驅動開關422-1及422-2,開關422-1及422-2使睡眠模式偏壓電阻器R2旁通以在傳輸模式下具有更高偏壓電流。電阻器R2在睡眠模式期間提供偏壓產生。電阻器R1在傳輸模式期間產生偏壓電壓。在另一實施例中,額外開關用於在關閉模式下隔離偏壓網路。 Signal E drives switches 422-1 and 422-2, and switches 422-1 and 422-2 bypass sleep mode bias resistor R2 to have a higher bias current in the transmit mode. Resistor R2 provides bias generation during the sleep mode. Resistor R1 generates a bias voltage during the transfer mode. In another embodiment, an additional switch is used to isolate the bias network in the off mode.
例如,使用非揮發性記憶體或遮罩單位電流源值可程式化。在一實例中,2.5 mA及4 mA電流與上文論述的例示性電阻R1-R4值一起使用並且使用例如下文所述圖9的外部電路,外部電路組件值顯示於上文表格I中。例示性選定電流源值係2.5 mA、4 mA及6.5 mA,但是可為任何合適電流。在本實施例中,當收發器400正在傳輸時,所汲取的 理論平均電流接著接近單位電流值的兩倍。 For example, using non-volatile memory or mask unit current source values can be programmed. In one example, the 2.5 mA and 4 mA currents are used with the exemplary resistors R1-R4 values discussed above and using an external circuit such as that described below in Figure 9, the external circuit component values are shown in Table I above. The exemplary selected current source values are 2.5 mA, 4 mA, and 6.5 mA, but can be any suitable current. In this embodiment, when the transceiver 400 is transmitting, the captured The theoretical average current is then close to twice the unit current value.
在圖4的替代實施例中,電流源經重新組態使得傳輸器電流源412位於開關電路420的左側並且接收器電流源432位於開關電路420的右側。此改良電流消耗及信號位準精確度。 In an alternate embodiment of FIG. 4, the current source is reconfigured such that the transmitter current source 412 is located to the left of the switching circuit 420 and the receiver current source 432 is located to the right of the switching circuit 420. This improves current consumption and signal level accuracy.
圖5係編碼器500的一實施例的示意圖。在本實施例中,編碼器500係接收CLK、DATA並傳輸使能(Tx使能)信號並輸出中間信號C、、D及的傳輸器編碼電路。傳輸器編碼電路500包括兩個反相器510及四個AND閘520。D、、C、驅動信號用於將資料串流正確地編碼成編碼的混合式信號。 FIG. 5 is a schematic diagram of an embodiment of an encoder 500. In this embodiment, the encoder 500 receives CLK, DATA and transmits an enable (Tx enable) signal and outputs an intermediate signal C, , D and Transmitter encoding circuit. Transmitter encoding circuit 500 includes two inverters 510 and four AND gates 520. D, , C, The drive signal is used to correctly encode the data stream into an encoded mixed signal.
在一實施例中,傳輸編碼電路500在C、、D及處耦合至圖4的傳輸器410。在一實施例中,傳輸器編碼電路500提供減小單位轉化上升時間同時幫助維持時脈恢復時序的額外邊緣上升功能。系統在開始每一1x轉化時立刻開啟相關3x電流源,放大波形並針對1x至3x轉化及3x至1x轉化兩者產生類似零交叉時序。 In an embodiment, the transmission encoding circuit 500 is in C, , D and It is coupled to the transmitter 410 of FIG. In an embodiment, the transmitter encoding circuit 500 provides an additional edge rise function that reduces the unit conversion rise time while helping to maintain the clock recovery timing. The system immediately turns on the associated 3x current source at the beginning of each 1x conversion, amplifies the waveform and produces a similar zero crossing timing for both 1x to 3x conversion and 3x to 1x conversion.
圖6係圖4及圖5的電路中的信號的一實施例的時序圖。在一實施例中,圖6實現與圖2A中所實現相同的最終結果,但是顯示中間驅動器信號D、、C及,傳輸器400使用該信號來產生編碼的混合式信號輸出。編碼的混合式信號係圖4的收發器400的最終輸出例如曼徹斯特編碼資料,而不顯示中間步驟。 6 is a timing diagram of an embodiment of a signal in the circuits of FIGS. 4 and 5. In an embodiment, Figure 6 implements the same final result as implemented in Figure 2A, but shows the intermediate driver signal D, , C and Transmitter 400 uses this signal to produce an encoded mixed signal output. The encoded mixed signal is the final output of the transceiver 400 of Figure 4, such as Manchester encoded data, without the intermediate steps being shown.
CLK、DATA及Tx使能信號被輸入至傳輸編碼電路 500,傳輸編碼電路500輸出D、、C、至收發器400。傳輸使能信號(Tx使能)啟動傳輸器410並且當收發器400傳輸時具有邏輯高。當收發器400所耦合的裝置(例如,裝置142-1)想要發送訊息時或當接收器430接收一個菊鏈埠上的訊息以透過下一個菊鏈埠中繼時,傳輸器410可以傳輸。 The CLK, DATA, and Tx enable signals are input to the transmission encoding circuit 500, and the transmission encoding circuit 500 outputs D, , C, To the transceiver 400. The transmit enable signal (Tx enable) activates the transmitter 410 and has a logic high when the transceiver 400 transmits. Transmitter 410 can transmit when a device coupled to transceiver 400 (e.g., device 142-1) wants to transmit a message or when receiver 430 receives a message on a daisy chain to relay through the next daisy chain. .
如圖6所示,編碼信號係振幅調變(具有振幅-3、-1、1及3,稱為合適單位值)並且在每一時脈邊緣上具有零交叉。因為在每一時脈邊緣上存在零交叉,所以CLK可直接恢復。即,所接收的振幅調變信號的每一零交叉可被轉化成從其恢復的時脈信號的邊緣。 As shown in Figure 6, the encoded signal is amplitude modulated (having amplitudes -3, -1, 1 and 3, referred to as suitable unit values) and has a zero crossing on each clock edge. Because there is a zero crossing on each clock edge, CLK can be recovered directly. That is, each zero crossing of the received amplitude modulated signal can be converted to the edge of the clock signal recovered therefrom.
圖7係接收器700的一實施例的示意圖。接收器700執行時脈恢復、信號重建、在接收器端部(例如,通信系統100、150中的第二收發器104的接收部分)上過濾以及對資料重定時。解碼器700包括資料濾波器702、資料重定時方塊704、增益電路706、時脈濾波器708、振盪器710及零交叉偵測器712。 FIG. 7 is a schematic diagram of an embodiment of a receiver 700. Receiver 700 performs clock recovery, signal reconstruction, filtering on the receiver end (e.g., the receiving portion of second transceiver 104 in communication systems 100, 150) and retimed the data. The decoder 700 includes a data filter 702, a data retiming block 704, a gain circuit 706, a clock filter 708, an oscillator 710, and a zero crossing detector 712.
在一實施例中,接收器700執行相反功能以將傳輸器確實所編碼的資料解碼。振幅調變信號(例如,編碼信號)提供在零交叉偵測器712的輸入處,該輸入使時脈(CLK)信號(w)恢復。時脈信號可藉由將振幅調變信號的每一零交叉轉化成時脈信號的邊緣。 In an embodiment, the receiver 700 performs the inverse function to decode the data that the transmitter does encode. An amplitude modulated signal (e.g., an encoded signal) is provided at the input of zero crossing detector 712 that recovers the clock (CLK) signal (w). The clock signal can be converted to the edge of the clock signal by converting each zero crossing of the amplitude modulated signal.
資料信號可藉由將振幅調變信號的電壓位準轉化為資料信號的數位值而恢復。在一實例中,振幅調變信號(例 如,編碼信號)由增益706修改,接著從恢復的時脈信號w減去該增益以產生嘈雜的恢復資料信號(x)(振幅受限信號)。信號x係第一級解碼資料信號並且被提供給零交叉偵測器714的輸入。過濾應用於此功能以幫助減小高頻雜訊影響。零交叉偵測器714輸出信號x(y)的較低雜訊版本。資料濾波器702進一步使用基於計數器的濾波運算來恢復資料信號(z)而減小信號y的雜訊。 The data signal can be recovered by converting the voltage level of the amplitude modulation signal to the digital value of the data signal. In an example, an amplitude modulation signal (example) For example, the encoded signal is modified by gain 706, which is then subtracted from the recovered clock signal w to produce a noisy recovered data signal (x) (amplitude limited signal). Signal x is the first stage decoded data signal and is provided to the input of zero crossing detector 714. Filtering is applied to this feature to help reduce the effects of high frequency noise. Zero crossing detector 714 outputs a lower noise version of signal x(y). The data filter 702 further uses a counter based filtering operation to recover the data signal (z) and reduce the noise of the signal y.
資料重定時方塊704對資料信號z重定時以在隨後成為一個時脈週期。1個時脈週期的延遲被提供給菊鏈接收與中繼的信號輸出之間的資料信號z以適應資料濾波器702的過濾。接收器700的輸出使信號能夠在第二菊鏈時脈週期開始時被傳輸使得第一傳輸時脈週期含有第一資料比特。例如,收發器104包括接收器700,接收器700將所接收資料解碼並且將其準備用於供收發器104中的傳輸器傳輸。在一實施例中,接收器700係菊鏈網路的一部分。資料信號恢復的其他方法係可行的,包括使用單端信號的直接信號臨限偵測。 Data retiming block 704 retimes data signal z to become a clock cycle thereafter. A delay of one clock cycle is provided to the data signal z between the daisy chain reception and the relayed signal output to accommodate the filtering of the data filter 702. The output of receiver 700 enables the signal to be transmitted at the beginning of the second daisy chain clock cycle such that the first transmission clock cycle contains the first data bit. For example, the transceiver 104 includes a receiver 700 that decodes the received data and prepares it for transmission by a transmitter in the transceiver 104. In an embodiment, the receiver 700 is part of a daisy chain network. Other methods of data signal recovery are possible, including direct signal threshold detection using single-ended signals.
圖8係對應於圖7的接收器的例示性時序圖。圖8顯示傳入的編碼信號(以實線顯示)與恢復的時脈w(以虛線顯示)之間的振幅關係以及如上所述之資料信號x、y及z。資料信號z中所示的短脈衝由資料濾波器702移除。 FIG. 8 is an exemplary timing diagram corresponding to the receiver of FIG. Figure 8 shows the amplitude relationship between the incoming coded signal (shown in solid lines) and the recovered clock w (shown in dashed lines) and the data signals x, y and z as described above. The short pulses shown in data signal z are removed by data filter 702.
圖9係對應於圖7的接收器的另一例示性時序圖。在此實例中,輸入信號與輸出信號關係顯示用於作為例如圖1C中的菊鏈通信系統的一部分的接收器700。接收器700 的額外功能係確保最小脈衝寬度使得短於指定長度的脈衝寬度以最小允許寬度再現。此應用於正脈衝及負脈衝兩者並且需限制由外來雜訊源諸如EMI引起的時脈抖動的累積影響。最小脈衝寬度取決於菊鏈時脈頻率並且由振盪器710的多個週期產生。例如,具有500 kHz菊鏈時脈及4 MHz系統振盪器710(菊鏈時脈的速率=振盪器速率/8)產生確保振盪器公差高達15%的正確運算的3個振盪器週期的最小脈衝寬度。當收發器處於正常通信模式中時,振盪器710連續運行。第二解碼功能使資料信號恢復(例如,參見圖2A及圖2B的資料解碼器238及278)。在圖9中,脈衝902已從信號w中的對應脈衝被修改為最小脈衝,其為短脈衝。 9 is another exemplary timing diagram corresponding to the receiver of FIG. In this example, the input signal and output signal relationship are shown for use as receiver 700, for example, as part of the daisy chain communication system of Figure 1C. Receiver 700 The extra function is to ensure that the minimum pulse width is such that the pulse width shorter than the specified length is reproduced with the minimum allowable width. This applies to both positive and negative pulses and limits the cumulative effects of clock jitter caused by foreign noise sources such as EMI. The minimum pulse width is dependent on the daisy chain clock frequency and is generated by multiple cycles of the oscillator 710. For example, with a 500 kHz daisy-chain clock and a 4 MHz system oscillator 710 (daisy chain clock rate = oscillator rate / 8) produces a minimum pulse of 3 oscillator cycles that ensures correct operation of the oscillator tolerance of up to 15% width. When the transceiver is in the normal communication mode, the oscillator 710 operates continuously. The second decoding function restores the data signal (see, for example, data decoders 238 and 278 of Figures 2A and 2B). In Figure 9, pulse 902 has been modified from the corresponding pulse in signal w to a minimum pulse, which is a short pulse.
在一實施例中,傳入的差動信號被轉換為單端信號並與恢復的時脈混合以重新產生資料信號。傳入的信號為此過程進行正確定標。上文所述的圖7中增益706的值例如0.866為圖2B的具有2.5 mA單位電流的電路提供正確位準並且稱為1 V峰-峰恢復時脈信號,外部電路元件在上文表格I中給出。 In an embodiment, the incoming differential signal is converted to a single-ended signal and mixed with the recovered clock to regenerate the data signal. The incoming signal is positively calibrated for this process. The value of gain 706 in Figure 7 described above, for example, 0.866, provides the correct level for the circuit of Figure 2B with a 2.5 mA unit current and is referred to as a 1 V peak-to-peak recovery clock signal, external circuit components in Table I above Given in .
圖10係編碼器1000的一實施例的示意圖。編碼器1000包括邏輯及電壓求和節點,該邏輯及電壓求和節點混合CLK信號與曼徹斯特編碼資料信號以產生混合式編碼信號。XOR閘1002接收CLK信號及資料信號並且輸出曼徹斯特編碼資料信號。此信號被輸入至零交叉偵測器1012,零交叉偵測器1012將該曼徹斯特編碼資料信號轉換成電壓位準程式化信號。在本實施例中,零交叉偵測器1012針對 邏輯高輸入輸出0.333 V信號,並且針對邏輯低輸入輸出-0.333 V信號。 FIG. 10 is a schematic diagram of an embodiment of an encoder 1000. Encoder 1000 includes logic and voltage summing nodes that mix the CLK signal with the Manchester encoded data signal to produce a mixed encoded signal. The XOR gate 1002 receives the CLK signal and the data signal and outputs a Manchester encoded data signal. This signal is input to a zero crossing detector 1012 which converts the Manchester encoded data signal into a voltage level programmed signal. In this embodiment, the zero-crossing detector 1012 is directed to The logic high input and output 0.333 V signal, and the logic low input and output -0.333 V signal.
類似地,XOR閘1004基於邏輯低信號與CLK信號的組合輸出信號至零交叉偵測器1014。零交叉偵測器1014針對邏輯高輸入輸出0.667 V信號,並且針對邏輯低輸入輸出-0.667 V信號。放大器1020將來自零交叉偵測器1014及1012的信號加總在一起並輸出振幅調變混合式編碼資料信號。混合式編碼資料信號的性質係使得零交叉提供在每一時脈邊緣上同時維持全面的資料完整性。 Similarly, XOR gate 1004 outputs a signal to zero-crossing detector 1014 based on a combination of a logic low signal and a CLK signal. The zero-crossing detector 1014 outputs a 0.667 V signal for a logic high input and a -0.667 V signal for a logic low input. Amplifier 1020 sums the signals from zero-crossing detectors 1014 and 1012 and outputs an amplitude-modulated mixed-coded data signal. The nature of the hybrid coded data signal is such that zero crossings are provided at each clock edge while maintaining full data integrity.
在本例示性實施例中,編碼器1000具有零交叉偵測器1014的編碼資料標定值與零交叉偵測器1012的編碼資料標定值的2:1關係,其提供良好的雜訊消除。此等因數的絕對值可經過選擇以在每一輸出處提供標稱2 V峰-峰信號(4 V峰-峰差動)。當類似地標定接收器電壓擺動時,增加此輸出擺動進一步改良穩健性。接收器(例如,接收器230)上的電壓擺動小於傳輸器(例如,傳輸器210)上的電壓擺動並且由外部組件(例如,圖1中的電阻器)的比率值確定。 In the present exemplary embodiment, encoder 1000 has a 2:1 relationship between the encoded data calibration value of zero crossing detector 1014 and the encoded data calibration value of zero crossing detector 1012, which provides good noise cancellation. The absolute values of these factors can be selected to provide a nominal 2 V peak-to-peak signal (4 V peak-to-peak differential) at each output. Increasing this output swing further improves robustness when the receiver voltage swing is similarly calibrated. The voltage swing on the receiver (eg, receiver 230) is less than the voltage swing on the transmitter (eg, transmitter 210) and is determined by the ratio value of an external component (eg, the resistor in FIG. 1).
圖11顯示與圖10所示的編碼器相關的不同信號的實例。圖11圖解說明時脈信號1102、資料信號1104、XOR信號1106及輸出信號1108。在一實例中,XOR信號1106包括由XOR閘1002輸出的曼徹斯特編碼資料信號。 Figure 11 shows an example of different signals associated with the encoder shown in Figure 10. FIG. 11 illustrates a clock signal 1102, a data signal 1104, an XOR signal 1106, and an output signal 1108. In an example, XOR signal 1106 includes a Manchester encoded data signal output by XOR gate 1002.
信號1108係由放大器1020輸出的混合式編碼資料信號。信號1108係振幅調變方波信號,其中方波脈衝的不同電壓位準對應於不同資料值。作為振幅調變方波信號,信 號1108的振幅對應於資料值(例如,數位值)。在一實例中,與數位0及數位1相關的電壓位準可分別為+/- 1 V及+/- 3 V。 Signal 1108 is a mixed coded data signal output by amplifier 1020. Signal 1108 is an amplitude modulated square wave signal in which different voltage levels of square wave pulses correspond to different data values. As an amplitude modulated square wave signal, the letter The amplitude of the number 1108 corresponds to a data value (eg, a digital value). In one example, the voltage levels associated with digit 0 and digit 1 can be +/- 1 V and +/- 3 V, respectively.
信號1108可包括複數個脈衝1110、1112、1114。每一脈衝1110、1112、1114對應於時脈信號1102的週期。脈衝包括輸出信號1108中的正負電壓擺動。在所示實例中,初始脈衝1110對應於由高電壓位準表示的數位1(例如,正負3伏特擺動)。因此,初始脈衝1110上升高達+3 V並下降低至-3 V。因此,初始脈衝1110維持平衡信號,達到+3伏特及-3伏特。 Signal 1108 can include a plurality of pulses 1110, 1112, 1114. Each pulse 1110, 1112, 1114 corresponds to the period of the clock signal 1102. The pulses include positive and negative voltage swings in the output signal 1108. In the illustrated example, the initial pulse 1110 corresponds to a digit 1 (eg, plus or minus 3 volts wobble) represented by a high voltage level. Therefore, the initial pulse 1110 rises up to +3 V and down to -3 V. Thus, the initial pulse 1110 maintains a balanced signal of +3 volts and -3 volts.
隨後的脈衝1112及1114亦可以具有基本平衡的信號。完成此以產生DC平衡輸出信號1108。即,可以完成此來產生基本上居中在大約0 v的輸出信號1108。在實例中,信號1108的第二脈衝1112對應於由低電壓位準表示的數位0(例如,正負1伏特擺動)。因此,混合式編碼資料信號1108係振幅調變信號。 Subsequent pulses 1112 and 1114 can also have a substantially balanced signal. This is done to generate a DC balanced output signal 1108. That is, this can be done to produce an output signal 1108 that is substantially centered at approximately 0 volts. In an example, the second pulse 1112 of the signal 1108 corresponds to a digit 0 (eg, plus or minus 1 volt swing) represented by a low voltage level. Therefore, the mixed coded data signal 1108 is an amplitude modulated signal.
圖12係解碼器1200的一實施例的示意圖。解碼器1200包括差動輸入級1202,其後係具有差動輸出的限制級1204。解碼器1200在允許使用具有替代(例如,電容式)耦合電路配置的接收器的標稱匯流排空閒電壓下提供差動輸入信號的負載終端。匯流排空閒電壓終端電路通常不在圖1的系統中使用。在一實施例中,解碼器1200中的電阻器1206-1及1206-2具有標稱高值,例如,100 kΩ。限制值係接收器輸入處的匯流排空閒狀態值以及其餘數。使能 電路偵測第一傳輸邊緣的到達並使能限制級1204。限制級1204停用,使得資料傳輸之後輸出符合匯流排空閒狀態。在傳輸結束時,匯流排總是處於空閒狀態。使能電路主要對裝置啟動提供正確初始狀態並且進一步校正任何錯誤匯流排空閒狀態。 12 is a schematic diagram of an embodiment of a decoder 1200. The decoder 1200 includes a differential input stage 1202 followed by a limit stage 1204 having a differential output. The decoder 1200 provides a load terminal that provides a differential input signal at a nominal bus idle voltage that allows the use of a receiver with an alternate (eg, capacitive) coupling circuit configuration. The bus idle voltage termination circuit is typically not used in the system of Figure 1. In one embodiment, resistors 1206-1 and 1206-2 in decoder 1200 have a nominal high value, for example, 100 kΩ. The limit value is the bus idle state value at the receiver input and the rest. Enable The circuit detects the arrival of the first transmission edge and enables the leveling stage 1204. The restriction stage 1204 is deactivated so that the output after the data transmission conforms to the bus idle state. At the end of the transfer, the bus is always idle. The enable circuit primarily provides the correct initial state for device startup and further corrects for any error bus idle state.
圖13係圖12的解碼器的例示性時序圖。注意輸出資料信號從輸入信號開始延遲一個時脈週期。源時脈延長一個時脈週期以促進用延遲的資料輸出進行解碼。在本實施例中,所有通信順序係多個8比特。 13 is an exemplary timing diagram of the decoder of FIG. Note that the output data signal is delayed by one clock cycle from the input signal. The source clock is extended by one clock cycle to facilitate decoding with delayed data output. In this embodiment, all communication sequences are a plurality of 8 bits.
圖14係電子系統1400的一實施例的方塊圖。電子系統1400包括鋰(Li)離子電池組1410、電源控制器1412及馬達1414。Li離子電池組1410適於包括多個平衡積體電路(IC)1401-1、1401-2至1401-N,該等平衡積體電路經由穩健的2線菊鏈通信系統(100、150)連接。平衡IC 1401-1、1401-2至1401-N監控電池1410中的單元。平衡IC 1401-1、1401-2至1401-N各自包括一個或多個收發器並且以菊鏈方式與通信媒體106-1至106-N連接。因此,該複數個平衡IC 1401-1、1401-2至1401-N及通信媒體106-1至106-N可對應於圖1C的菊鏈系統140。即,平衡IC 1401-1可包括耦合至收發器150-1的裝置142-1,其中第一平衡IC 1401-1的第一收發器150-1可耦合至第二平衡IC 1401-2的第二收發器150-2。 14 is a block diagram of an embodiment of an electronic system 1400. The electronic system 1400 includes a lithium (Li) ion battery pack 1410, a power controller 1412, and a motor 1414. Li-ion battery pack 1410 is adapted to include a plurality of balanced integrated circuits (ICs) 1401-1, 1401-2 through 1401-N that are connected via a robust 2-wire daisy chain communication system (100, 150) . The balance ICs 1401-1, 1401-2 through 1401-N monitor the cells in the battery 1410. The balancing ICs 1401-1, 1401-2 through 1401-N each include one or more transceivers and are daisy-chained to the communication media 106-1 through 106-N. Accordingly, the plurality of balanced ICs 1401-1, 1401-2 through 1401-N and communication media 106-1 through 106-N may correspond to the daisy chain system 140 of FIG. 1C. That is, the balance IC 1401-1 can include a device 142-1 coupled to the transceiver 150-1, wherein the first transceiver 150-1 of the first balance IC 1401-1 can be coupled to the second balance IC 1401-2 Two transceivers 150-2.
電子系統1400的一實施例係混合式電動車輛。在本實施例中,電池組1410係高電壓電池系統,其處理高達400 V。對於透過上述菊鏈系統通信的每一12電池單元組而言存在平衡IC 1401-1、1401-2、1401-N。菊鏈頂部與底部之間的電壓差係400 V,每者的位準為40 V。由於鋰離子電池1410中鋰的反應本質,在電池1410過熱或過度充電的情況下存在爆炸風險。本文所述之隔離通信系統的實施例藉由使用監控平衡IC 1401-1、1401-2、1401-N以及其電荷耗盡功能促進防止此類爆炸。 One embodiment of electronic system 1400 is a hybrid electric vehicle. In this embodiment, the battery pack 1410 is a high voltage battery system that processes up to 400 V. There are balance ICs 1401-1, 1401-2, 1401-N for each of the 12 battery cell groups that communicate through the daisy chain system described above. The voltage difference between the top and bottom of the daisy chain is 400 V, and each has a level of 40 V. Due to the reactive nature of lithium in lithium ion battery 1410, there is a risk of explosion in the event of overheating or overcharging of battery 1410. Embodiments of the isolated communication system described herein facilitate the prevention of such explosions by using monitoring balance ICs 1401-1, 1401-2, 1401-N and their charge depletion functions.
在另一實施例中,電池管理系統1400安裝在氣電混合或電動車輛中。圖15提供12單元系統的圖14的平衡IC 1401-1與1401-2之間的連接的更多詳情。若電壓源突然斷開連接,則感應尖峰可傳播通過電池組1410。標稱40 V可升高至120 V,平衡IC 1401-1、1401-2、1401-N之間的任何連接引起尖峰的一部分。在一實例中,通信媒體106-1引起70 V的暫態尖峰。由於通信系統被完全電隔離並被防護而使之免於此電壓瞬變位準,所以通信系統可倖存於瞬變而不受損,並且不使電子裝置暴露於危險電壓或溫度。 In another embodiment, the battery management system 1400 is installed in a gas-electric hybrid or electric vehicle. Figure 15 provides more details of the connection between the balancing ICs 1401-1 and 1401-2 of Figure 14 of a 12-cell system. If the voltage source is suddenly disconnected, the inductive spike can propagate through the battery pack 1410. The nominal 40 V can be raised to 120 V, and any connection between the balancing ICs 1401-1, 1401-2, 1401-N causes a portion of the spike. In one example, communication medium 106-1 causes a transient spike of 70 V. Since the communication system is fully electrically isolated and protected from this voltage transient level, the communication system can survive transients without damage and expose the electronic device to dangerous voltages or temperatures.
圖16係經由隔離通信系統(例如,通信系統100、170)傳輸資料的方法1600的一實施例的流程圖。在第一收發器例如第一收發器102上接收資料信號(方塊1610)。第一收發器對資料信號進行編碼(方塊1620)並且將其與時脈信號組合以產生混合式編碼資料信號(方塊1630)。第一收發器傳輸混合式編碼資料信號(方塊1640)。混合式編碼資料信號例如透過差動及AC耦合網路而傳輸,差動及AC耦合網路透過通信媒體106將第一收發器102連接至第二收發 器104。第二收發器接收混合式編碼資料信號(方塊1650)。第二收發器提取時脈信號並且將資料信號解碼(方塊1660)。在一實施例中,藉由偵測混合式編碼資料信號的零交叉提取時脈信號。 16 is a flow diagram of an embodiment of a method 1600 of transmitting material via an isolated communication system (e.g., communication system 100, 170). A data signal is received on a first transceiver, such as first transceiver 102 (block 1610). The first transceiver encodes the data signal (block 1620) and combines it with the clock signal to produce a hybrid encoded data signal (block 1630). The first transceiver transmits the hybrid encoded data signal (block 1640). The hybrid encoded data signal is transmitted, for example, via a differential and AC coupled network, and the differential and AC coupled network connects the first transceiver 102 to the second transceiver via the communication medium 106. 104. The second transceiver receives the hybrid encoded data signal (block 1650). The second transceiver extracts the clock signal and decodes the data signal (block 1660). In one embodiment, the clock signal is extracted by detecting a zero crossing of the mixed encoded data signal.
本文所述之實施例提供改良的隔離通信、減少的EMI發射及靈敏度以及增強的瞬變電壓保護。一些實施例提供一種差動AC耦合網路,其消除接收器上的EMI並且隔離通信媒體端部之間的瞬變影響。本文所述之實施例不受積體電路類型的限制。實施例亦不限於任何特定類型的處理技術,例如可用於製造本揭示內容的CMOS、雙極或BICMOS。鑑於本揭示內容,其他添加、減除或修改係顯而易見的並且旨在落於隨附申請專利範圍的範圍內。 Embodiments described herein provide improved isolated communication, reduced EMI emissions and sensitivity, and enhanced transient voltage protection. Some embodiments provide a differential AC coupling network that eliminates EMI on the receiver and isolates transient effects between communication media ends. The embodiments described herein are not limited by the type of integrated circuit. Embodiments are also not limited to any particular type of processing technique, such as CMOS, bipolar, or BICMOS that can be used to fabricate the present disclosure. Other additions, subtractions, or modifications are obvious in light of the present disclosure and are intended to fall within the scope of the appended claims.
已經描述由下列申請專利範圍定義的本發明的多個實施例。但是應瞭解可在不背離本發明的精神及範圍的情況下對該等所述實施例作出各種修改。本文所述之特定實施例的特徵及態樣可與其他實施例的特徵及態樣組合或替換。因此,其他實施例在下列申請專利範圍的範圍內。 A number of embodiments of the invention are defined by the scope of the following claims. It will be appreciated, however, that various modifications may be made to the described embodiments without departing from the spirit and scope of the invention. The features and aspects of the specific embodiments described herein may be combined or substituted with the features and aspects of other embodiments. Accordingly, other embodiments are within the scope of the following claims.
100‧‧‧通信系統 100‧‧‧Communication system
102‧‧‧第一收發器 102‧‧‧First transceiver
104‧‧‧第二收發器 104‧‧‧Second transceiver
106-1‧‧‧通信媒體 106-1‧‧‧Communication media
106-2‧‧‧通信媒體 106-2‧‧‧Communication media
106-N‧‧‧通信媒體 106-N‧‧‧Communication media
107‧‧‧箝位 107‧‧‧Clamp
112‧‧‧差動電容器 112‧‧‧Differential capacitor
113-1‧‧‧電阻器 113-1‧‧‧Resistors
113-2‧‧‧電阻器 113-2‧‧‧Resistors
114-1‧‧‧電容器 114-1‧‧‧ capacitor
114-2‧‧‧電容器 114-2‧‧‧ capacitor
118‧‧‧變壓器 118‧‧‧Transformers
119-1‧‧‧第一電阻器 119-1‧‧‧First resistor
119-2‧‧‧第二電阻器 119-2‧‧‧second resistor
119-3‧‧‧第三電阻器 119-3‧‧‧ Third resistor
119-4‧‧‧第四電阻器 119-4‧‧‧fourth resistor
119-5‧‧‧第五電阻器 119-5‧‧‧ fifth resistor
119-6‧‧‧第六電阻器 119-6‧‧‧ sixth resistor
120-1‧‧‧第一埠 120-1‧‧‧ first
120-2‧‧‧第二埠 120-2‧‧‧Second
120-3‧‧‧第三埠 120-3‧‧‧third
120-4‧‧‧第四埠 120-4‧‧‧Fourth
121‧‧‧變壓器 121‧‧‧Transformers
122‧‧‧差動電容器 122‧‧‧Differential capacitor
123-1‧‧‧電阻器 123-1‧‧‧Resistors
123-2‧‧‧電阻器 123-2‧‧‧Resistors
124-1‧‧‧電容器 124-1‧‧‧ capacitor
124-2‧‧‧電容器 124-2‧‧‧ capacitor
131-1‧‧‧回饋電阻器 131-1‧‧‧Response resistor
131-2‧‧‧回饋電阻器 131-2‧‧‧Response resistor
132‧‧‧差動驅動器 132‧‧‧Differential drive
133‧‧‧觸發驅動器 133‧‧‧ trigger driver
134‧‧‧傳輸驅動器 134‧‧‧Transport driver
135‧‧‧差動驅動器 135‧‧‧Differential drive
136‧‧‧觸發驅動器 136‧‧‧ trigger driver
137-1‧‧‧回饋電阻器 137-1‧‧‧Response resistor
137-2‧‧‧回饋電阻器 137-2‧‧‧ feedback resistor
138‧‧‧傳輸驅動器 138‧‧‧Transport driver
139-1‧‧‧高路徑 139-1‧‧‧High path
139-2‧‧‧低路徑 139-2‧‧‧Low path
140‧‧‧系統 140‧‧‧System
142-1‧‧‧裝置 142-1‧‧‧ device
142-2‧‧‧第二裝置 142-2‧‧‧second device
142-3‧‧‧第三裝置 142-3‧‧‧ third device
142-N‧‧‧其他裝置 142-N‧‧‧Other devices
150-1‧‧‧第一收發器 150-1‧‧‧First Transceiver
150-2‧‧‧第二收發器 150-2‧‧‧Second transceiver
150-3‧‧‧第三收發器 150-3‧‧‧ Third Transceiver
150-M‧‧‧收發器 150-M‧‧‧ transceiver
152‧‧‧系統時脈 152‧‧‧System clock
170‧‧‧通信系統 170‧‧‧Communication system
200‧‧‧收發器 200‧‧‧ transceiver
210‧‧‧傳輸器 210‧‧‧Transporter
212‧‧‧編碼器 212‧‧‧Encoder
214‧‧‧乘法器 214‧‧‧Multiplier
216‧‧‧求和器 216‧‧‧sumer
220‧‧‧接收器 220‧‧‧ Receiver
230‧‧‧接收器 230‧‧‧ Receiver
232‧‧‧偵測器 232‧‧‧Detector
234‧‧‧乘法器 234‧‧‧Multiplier
236‧‧‧求和器 236‧‧‧sumer
238‧‧‧資料解碼器 238‧‧‧ Data Decoder
250‧‧‧收發器 250‧‧‧ transceiver
260‧‧‧傳輸器 260‧‧‧transmitter
262‧‧‧XOR閘 262‧‧‧XOR gate
270‧‧‧接收器 270‧‧‧ Receiver
278‧‧‧XOR閘 278‧‧‧XOR gate
278‧‧‧資料解碼器 278‧‧‧Data Decoder
300‧‧‧接收器 300‧‧‧ Receiver
302‧‧‧差動接收器 302‧‧‧Differential Receiver
304‧‧‧比較器 304‧‧‧ Comparator
306‧‧‧比較器 306‧‧‧ Comparator
308‧‧‧比較器 308‧‧‧ comparator
310‧‧‧濾波器 310‧‧‧ filter
330‧‧‧接收器 330‧‧‧ Receiver
400‧‧‧收發器 400‧‧‧ transceiver
402‧‧‧放大器 402‧‧‧Amplifier
403‧‧‧接收器 403‧‧‧ Receiver
404‧‧‧偵測器 404‧‧‧Detector
406-1‧‧‧線 406-1‧‧‧ line
406-2‧‧‧線 406-2‧‧‧ line
408-1‧‧‧線 408-1‧‧‧ line
408-2‧‧‧線 408-2‧‧‧ line
410‧‧‧傳輸器 410‧‧‧Transporter
412‧‧‧電流源 412‧‧‧current source
420‧‧‧開關電路 420‧‧‧Switch circuit
421-1‧‧‧旁路開關 421-1‧‧‧ Bypass switch
421-2‧‧‧旁路開關 421-2‧‧‧ Bypass switch
422-1‧‧‧驅動開關 422-1‧‧‧Drive Switch
422-2‧‧‧驅動開關 422-2‧‧‧Drive Switch
430‧‧‧接收器 430‧‧‧ Receiver
432‧‧‧電流源 432‧‧‧current source
500‧‧‧編碼器 500‧‧‧Encoder
510‧‧‧反相器 510‧‧‧Inverter
700‧‧‧接收器 700‧‧‧ Receiver
702‧‧‧資料濾波器 702‧‧‧Data Filter
704‧‧‧重定時方塊 704‧‧‧Retiming Square
706‧‧‧增益電路 706‧‧‧gain circuit
708‧‧‧時脈濾波器 708‧‧‧clock filter
710‧‧‧振盪器 710‧‧‧Oscillator
712‧‧‧偵測器 712‧‧‧Detector
714‧‧‧偵測器 714‧‧‧Detector
902‧‧‧脈衝 902‧‧‧pulse
1000‧‧‧編碼器 1000‧‧‧Encoder
1002‧‧‧XOR閘 1002‧‧‧XOR gate
1004‧‧‧XOR閘 1004‧‧‧XOR gate
1012‧‧‧偵測器 1012‧‧‧Detector
1014‧‧‧偵測器 1014‧‧‧Detector
1020‧‧‧放大器 1020‧‧Amplifier
1102‧‧‧時脈信號 1102‧‧‧ clock signal
1104‧‧‧資料信號 1104‧‧‧Information signal
1106‧‧‧XOR信號 1106‧‧‧XOR signal
1108‧‧‧輸出信號 1108‧‧‧ Output signal
1110‧‧‧脈衝 1110‧‧‧pulse
1112‧‧‧脈衝 1112‧‧‧pulse
1114‧‧‧脈衝 1114‧‧‧pulse
1200‧‧‧解碼器 1200‧‧‧Decoder
1202‧‧‧輸入級 1202‧‧‧ input level
1204‧‧‧限制級 1204‧‧‧Restricted
1206-1‧‧‧電阻器 1206-1‧‧‧Resistors
1206-2‧‧‧電阻器 1206-2‧‧‧Resistors
1400‧‧‧系統 1400‧‧‧ system
1401-1‧‧‧積體電路(IC) 1401-1‧‧‧Integrated Circuit (IC)
1401-N‧‧‧積體電路(IC) 1401-N‧‧‧Integrated Circuit (IC)
1401-2‧‧‧積體電路(IC) 1401-2‧‧‧Integrated Circuit (IC)
1410‧‧‧電池組 1410‧‧‧Battery Pack
1412‧‧‧電力控制器 1412‧‧‧Power Controller
1414‧‧‧馬達 1414‧‧‧Motor
1600‧‧‧方法 1600‧‧‧ method
1610‧‧‧方塊 1610‧‧‧Box
1620‧‧‧方塊 1620‧‧‧ square
1630‧‧‧方塊 1630‧‧‧Box
1640‧‧‧方塊 1640‧‧‧ square
1650‧‧‧方塊 1650‧‧‧ square
1660‧‧‧方塊 1660‧‧‧
在瞭解圖式僅描繪例示性實施例並且因此不被視為限制範圍的情況下,例示性實施例將透過使用附圖另外特定詳細地加以描述。 The exemplified embodiments are described in detail with particular reference to the accompanying drawings.
圖1A係通信系統的一實施例之示意圖。 1A is a schematic diagram of an embodiment of a communication system.
圖1B係通信系統的另一實施例之示意圖。 1B is a schematic diagram of another embodiment of a communication system.
圖1C係利用圖1A及/或圖1B的通信系統的系統的一實施例之方塊圖。 1C is a block diagram of an embodiment of a system utilizing the communication system of FIGS. 1A and/or 1B.
圖2A及圖2B係用於圖1A、圖1B或圖1C的系統的收發器的替代性實施例之方塊圖。 2A and 2B are block diagrams of alternative embodiments of a transceiver for the system of FIG. 1A, FIG. 1B, or FIG. 1C.
圖3A係用於圖1A、圖1B或圖1C的系統的接收器的一實施例之方塊圖。 3A is a block diagram of an embodiment of a receiver for the system of FIG. 1A, FIG. 1B, or FIG. 1C.
圖3B係對應於圖3A的接收器之例示性時序圖。 FIG. 3B is an exemplary timing diagram corresponding to the receiver of FIG. 3A.
圖3C係用於圖1A、圖1B或圖1C的系統的接收器的替代實施例之方塊圖。 3C is a block diagram of an alternate embodiment of a receiver for the system of FIG. 1A, FIG. 1B, or FIG. 1C.
圖4係用於圖1A、圖1B或圖1C的系統的收發器的一實施例之示意圖。 4 is a schematic diagram of an embodiment of a transceiver for the system of FIG. 1A, FIG. 1B, or FIG. 1C.
圖5係與圖4的收發器一起使用的編碼器的一實施例之示意圖。 5 is a schematic diagram of an embodiment of an encoder for use with the transceiver of FIG.
圖6係圖4及圖5的電路中的信號之例示性時序圖。 6 is an exemplary timing diagram of signals in the circuits of FIGS. 4 and 5.
圖7係用於圖1A、圖1B或圖1C的系統的接收器的一實施例之示意圖。 7 is a schematic diagram of an embodiment of a receiver for the system of FIG. 1A, FIG. 1B, or FIG. 1C.
圖8及圖9係對應於圖7的接收器之例示性時序圖。 8 and 9 are exemplary timing diagrams corresponding to the receiver of FIG.
圖10係用於與圖2A的收發器一起使用的編碼器的另一實施例之示意圖。 10 is a schematic diagram of another embodiment of an encoder for use with the transceiver of FIG. 2A.
圖11係圖10的編碼器之例示性時序圖。 11 is an exemplary timing diagram of the encoder of FIG.
圖12係用於與圖2A的收發器一起使用的解碼器的一實施例之示意圖。 12 is a schematic diagram of an embodiment of a decoder for use with the transceiver of FIG. 2A.
圖13係圖12的解碼器之例示性時序圖。 13 is an exemplary timing diagram of the decoder of FIG.
圖14係用於與圖1C的系統一起使用的電池的一實施 例之方塊圖。 Figure 14 is an illustration of a battery for use with the system of Figure 1C. Example block diagram.
圖15係圖14的電池的兩個單元的一實施例之方塊圖。 Figure 15 is a block diagram of an embodiment of two cells of the battery of Figure 14.
圖16係經由圖1A、圖1B或圖1C的隔離通信系統傳輸資料的方法的一實施例之流程圖。 16 is a flow diagram of an embodiment of a method of transmitting data via the isolated communication system of FIG. 1A, FIG. 1B, or FIG. 1C.
根據一般實踐,不同描述的特徵不依比例繪製但繪製用於強調與例示性實施例相關之特定特徵。 Features of different descriptions are not drawn to scale, but are drawn to emphasize particular features associated with the illustrative embodiments.
100‧‧‧通信系統 100‧‧‧Communication system
102‧‧‧第一收發器 102‧‧‧First transceiver
104‧‧‧第二收發器 104‧‧‧Second transceiver
106‧‧‧通信媒體 106‧‧‧Communication media
107‧‧‧箝位 107‧‧‧Clamp
112‧‧‧差動電容器 112‧‧‧Differential capacitor
113-1‧‧‧電阻器 113-1‧‧‧Resistors
113-2‧‧‧電阻器 113-2‧‧‧Resistors
114-1‧‧‧電容器 114-1‧‧‧ capacitor
114-2‧‧‧電容器 114-2‧‧‧ capacitor
118‧‧‧變壓器 118‧‧‧Transformers
119-1‧‧‧第一電阻器 119-1‧‧‧First resistor
119-2‧‧‧第二電阻器 119-2‧‧‧second resistor
119-3‧‧‧第三電阻器 119-3‧‧‧ Third resistor
119-4‧‧‧第四電阻器 119-4‧‧‧fourth resistor
119-5‧‧‧第五電阻器 119-5‧‧‧ fifth resistor
119-6‧‧‧第六電阻器 119-6‧‧‧ sixth resistor
120-1‧‧‧第一埠 120-1‧‧‧ first
120-2‧‧‧第二埠 120-2‧‧‧Second
120-3‧‧‧第三埠 120-3‧‧‧third
120-4‧‧‧第四埠 120-4‧‧‧Fourth
122‧‧‧差動電容器 122‧‧‧Differential capacitor
123-1‧‧‧電阻器 123-1‧‧‧Resistors
123-2‧‧‧電阻器 123-2‧‧‧Resistors
124-1‧‧‧電容器 124-1‧‧‧ capacitor
124-2‧‧‧電容器 124-2‧‧‧ capacitor
131-1‧‧‧回饋電阻器 131-1‧‧‧Response resistor
131-2‧‧‧回饋電阻器 131-2‧‧‧Response resistor
132‧‧‧差動驅動器 132‧‧‧Differential drive
133‧‧‧觸發驅動器 133‧‧‧ trigger driver
134‧‧‧傳輸驅動器 134‧‧‧Transport driver
135‧‧‧差動驅動器 135‧‧‧Differential drive
136‧‧‧觸發驅動器 136‧‧‧ trigger driver
137-1‧‧‧回饋電阻器 137-1‧‧‧Response resistor
137-2‧‧‧回饋電阻器 137-2‧‧‧ feedback resistor
138‧‧‧傳輸驅動器 138‧‧‧Transport driver
139-1‧‧‧高路徑 139-1‧‧‧High path
139-2‧‧‧低路徑 139-2‧‧‧Low path
Claims (25)
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US201161498984P | 2011-06-20 | 2011-06-20 | |
US13/365,578 US8798175B2 (en) | 2009-05-08 | 2012-02-03 | Communicating with a self-clocking amplitude modulated signal |
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TW201301820A true TW201301820A (en) | 2013-01-01 |
TWI514828B TWI514828B (en) | 2015-12-21 |
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TW101116826A TWI514828B (en) | 2011-06-20 | 2012-05-11 | Method for transmitting amplitude modulated signal, transmitter and daisy chain communication system and intergrated circuit |
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TW (1) | TWI514828B (en) |
Cited By (2)
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TWI616077B (en) * | 2015-07-17 | 2018-02-21 | 廣播科技機構有限公司 | Transmitter for transmitting a data transmission signal and receiver for receiving the data transmission signal |
TWI718661B (en) * | 2019-09-10 | 2021-02-11 | 立錡科技股份有限公司 | Battery system, battery module and battery control circuit thereof |
Families Citing this family (2)
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CN103284104A (en) * | 2013-05-20 | 2013-09-11 | 安徽新荣久农业科技有限公司 | Seasoning health care osmunda japonica thunb and processing method thereof |
US9794054B2 (en) * | 2015-06-30 | 2017-10-17 | Stmicroelectronics International N.V. | Data on clock lane of source synchronous links |
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FR2735928B1 (en) * | 1995-06-22 | 1997-07-18 | France Telecom | MANCHESTER ENCODER / DECODER |
US6771712B2 (en) * | 2001-07-27 | 2004-08-03 | The Pulsar Network, Inc. | System for extracting a clock signal and a digital data signal from a modulated carrier signal in a receiver |
US7693216B1 (en) * | 2009-02-24 | 2010-04-06 | Daniel A. Katz | Modulating transmission timing for data communications |
US8576928B2 (en) * | 2009-05-08 | 2013-11-05 | Intersil Americas Inc. | Capacitive divider transmission scheme for improved communications isolation |
JP2011015071A (en) * | 2009-06-30 | 2011-01-20 | Sony Corp | Signal processing apparatus, information processing apparatus, multilevel coding method, and data transmission method |
JP2011041142A (en) * | 2009-08-17 | 2011-02-24 | Sony Corp | Information processing apparatus, and signal transmission method |
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TWI616077B (en) * | 2015-07-17 | 2018-02-21 | 廣播科技機構有限公司 | Transmitter for transmitting a data transmission signal and receiver for receiving the data transmission signal |
TWI718661B (en) * | 2019-09-10 | 2021-02-11 | 立錡科技股份有限公司 | Battery system, battery module and battery control circuit thereof |
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TWI514828B (en) | 2015-12-21 |
CN102843320A (en) | 2012-12-26 |
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