TW201251054A - Solar cell and method to manufacture the same - Google Patents

Solar cell and method to manufacture the same Download PDF

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TW201251054A
TW201251054A TW100120685A TW100120685A TW201251054A TW 201251054 A TW201251054 A TW 201251054A TW 100120685 A TW100120685 A TW 100120685A TW 100120685 A TW100120685 A TW 100120685A TW 201251054 A TW201251054 A TW 201251054A
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Taiwan
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type semiconductor
electrode
layer
semiconductor
solar cell
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TW100120685A
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Chinese (zh)
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Kun-Chih Lin
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Auria Solar Co Ltd
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

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Abstract

A solar cell is provided, and includes a substrate, a plurality of first electrodes, at least one P-type semiconductor, at least one N-type semiconductor, at least one dielectric member, an intrinsic layer and a second electrode. The first electrodes are spaced apart from each other and deposited on the substrate. The P-type semiconductor and the N-type semiconductor are respectively deposited on at least one of the first electrodes. The dielectric member is deposited on the substrate, and spaced the P-type semiconductor and the N-type semiconductor apart from each other. The intrinsic layer is deposited on the P-type semiconductor, the N-type semiconductor and the dielectric member, and the second electrode is deposited on the intrinsic layer. A method to manufacture abovementioned solar cell is also provided to make the P-type semiconductor, the N-type semiconductor, the dielectric member and the intrinsic layer deposited according to abovementioned configuration.

Description

201251054 六、發明說明: 【發明所屬之技術領域】 本發明係關於一種太陽於φ,201251054 VI. Description of the Invention: [Technical Field to Be Invented by the Invention] The present invention relates to a sun at φ,

製造方法,日桩别《 ϋ 電池(solarcell)及其 特疋有關於一種將P型半導體與N 能電池及其製造方法。達到4型化要求之太陽 【先前技術】 ^頁目前大眾所處的生活環境,由於工業的發 二使得全球的能源正急遽地被消耗。藉由許多學者 2調^來的調查報告,人類逐漸開始意識到自己 目則正處於能源嚴重短缺關鍵年代,全 可回收,生能源。根據美國能^ f a自2〇03年起异’石油、天然氣與煤等的非 士性能源將分別在41年、67年與192年内耗竭。 在這樣的情況下,太陽能、風力、地熱、生物能等再 生成源技術的開發勢必會越來越受到重視。 、在眾多的再生能源技術當中,由於太陽能具有發 ,過程無/亏染且無需維持費用的特性,所以目前普遍 欠世界各國的青睞,因而驅使太陽能電池市場在近幾 年快速蓬勃發展。在此前提下,有關太陽能開發議題 曰漸受到重視,因而驅使許多國家紛紛開始著手推行The manufacturing method, the Japanese battery (solarcell) and its features are related to a P-type semiconductor and N-energy battery and its manufacturing method. The sun that meets the requirements of type 4 [Prior Art] ^The current living environment of the public, due to the development of the industry, the global energy is being consumed eagerly. With the investigation reports of many scholars, people are gradually beginning to realize that they are in the critical era of severe energy shortages, and they are fully recoverable and produce energy. According to the United States, non-scientific energy sources such as oil, natural gas and coal will be depleted in 41, 67 and 192 years respectively. Under such circumstances, the development of regenerative source technologies such as solar energy, wind power, geothermal energy, and bioenergy is bound to receive more and more attention. Among the many renewable energy technologies, solar energy has been favored by countries all over the world due to its ability to emit light, process without/loss, and no need to maintain cost. This has driven the solar cell market to flourish in recent years. Under this premise, the issue of solar energy development has gradually received attention, which has driven many countries to start implementing

新能源政策,並實施補助獎勵辦法,以求積極發展與 推廣太陽能電池。 X 依據專豕的統s-f·結果顯示,太陽每年輕射至地球 的旎置約^5.4x10焦耳,而全世界每年所需的能量 約為UxlO焦耳;因此,只要人類可充分地利用從太 201251054 陽輻射至地球之能量的五萬分之一,則人類目前所面 臨的許多能源問題馬上便可被迎刃而解。有鑑於此, 實有必要積極發展太陽能電池以求纾解能源問題。 進一步討論,目前的太陽能電池的種類大致可分 為··(1)單/多晶石夕太陽能電池(Mono/Polycrystalline Solar Cell) ; (2)非晶矽/微晶矽薄膜太陽能電池 (Amorphous/Thin Film Solar Cell) ; (3)無機半導體 (Inorganic Solar Cell) ; (4)有機高分子太陽能電池 (Organic Solar Cell);以及(5)染料敏化太陽能電池 (Dye-Sensitized Solar Cell; DSSC)。其中,自從瑞士 科學家Gratzel於1991年提出其DSSC結構元件以及 工作原理以來’許多專家相繼提出多種二氧化鈦 (Ti02)薄膜、顆粒、以及奈米管(NT,nanotubes)的太 陽能製作技術。其中,上述第(1)(2)者通常可歸類為 石夕基太陽能電池’也是本發明所討論之主要課題;因 此,在本文中以下所述之太陽能電池係專指矽基太陽 能電池。New energy policies and implementation of subsidy incentives to actively develop and promote solar cells. X According to the results of the sf., the results show that the sun is about 5.4x10 joules per young shot, and the annual energy required by the world is about UxlO joules; therefore, as long as humans can make full use of it from 201205154 Sun radiates to one-five thousandth of the earth's energy, and many of the energy problems that humanity is currently facing can be solved immediately. In view of this, it is necessary to actively develop solar cells in order to solve the energy problem. Further discussion, the current types of solar cells can be roughly divided into: (1) Mono/Polycrystalline Solar Cell; (2) Amorphous/Microcrystalline Thin Film Solar Cells (Amorphous/ Thin Film Solar Cell; (3) Inorganic Solar Cell; (4) Organic Solar Cell; and (5) Dye-Sensitized Solar Cell (DSC). Among them, since the Swiss scientist Gratzel proposed its DSSC structural components and working principle in 1991, many experts have successively proposed a variety of titanium dioxide (Ti02) films, particles, and nanotubes. Among them, the above-mentioned (1) (2) can be generally classified as a Shih-ki solar cell, which is also a main subject of the present invention; therefore, the solar cell described below in this document exclusively refers to a ruthenium-based solar cell.

I 就目前現有之太陽能電池而言,多半需要竿設於 一固定物。在實務上,固定物可為建築物之頂部或側 壁’亦可或是太陽能供電糸統之基座或支架。為了節 省裝運時所佔用之材積,並且更便於梦兮於卜沭之闳 定物上’通常會希望太陽能電池要能^更輕薄,也就 是希望太陽能電池能夠薄型化。 在以上所述之認知基礎下’在目前現有之太陽能 電池中’通常都具有P型半導體層、本質層(Intrinsic Layer)與N型半導體層’且P型半導體層、本質層 與N型半導體層係依序垂直堆疊成一 ρθΙΝ堆疊^ 構’藉以組成一光電轉換層。然而,由於在pIN堆疊 結構中’P型半導體層、本質層與N型半導體層係依 201251054 ΐ垂’將會導致光1轉換層的厚度偏 t 無法達到薄型化的要求。由此可 運時的之太陽能電池將會造成倉儲與裝 運㈣工間成本以及組裝時的組農成本大幅增加。 【發明内容】 本發明所欲解決之技術問題與目的: 層與由序=ρ·型半導趙層、本質 情故,致使太陽能電池 溥孓化的要求緣此,本發明之主 型半:體陽严電池及其製造方法,其係將p 能電池=度導體橫向分隔配置’藉以減少太陽 本發明解決問題之技術手段: 段传i ί明ί fί習知技術之問題所採用之技術手 d陽能電池’其係包含-基板、複數個 H二至少,半導體、至少-N型半導體、 個二本質層與一第二電極。上述複數 體與n型:於該基板上。p型半導 之至少分別堆疊於上述複數個第一電極 型半導體與N ,並且將p 與本質層之間橫向分隔配置N f半導體係在弟一電極 6 201251054 在本發明較佳實施例中,八 包括氧化石夕、氮化石夕與氮氧乂^電70件之材料可 電極盥第-雷朽夕中之至少一者。第一 之太陽明導電氧化物。上述 第二電極上。此外’且賴層係堆疊於 括玻璃或透明樹脂。基板與保護層之材料可包 段更以之問題所採用之技術手 一 了社W電池之製造方法, 極r接反著並在在第基成、複數個彼此相間之第一電 ^ ^ . 電極上为別形成至少一 p型丰導舻 =二型半導人體,並在p型半導體與⑵ 元件,藉以分隔p型半導= =導體。取後’在P型半導體、N型入 電S牛ίϊ ί 一本質層;並且在本質層上形成-7」 電極。較佳者,可繼續在第二電極上提供—保護 段還i ί ϊ ί料f ^術之問題所採用之技術手 =共了另一種太陽能電池 = 並在基板上形成-第-電極。接著在 、电極上形成一本質層,並在本質層上开彡赤5小 P型半導體與至少一 ;^型半導體,且 丄 '一 N型半導體相門13J ^ 1半導體係與 上八C後’在p型半導體與μ半導體 成一苐二電極,藉以形成複數個第二體 S在:型t導體與_半導體之間形成:介 二體:_半導體。較佳者 、弟一電極與介電疋件上提供一保護層。 由以上敘述可知,在依據本發明所提供处 Y /的製造方法中,係使太陽能電 = 間橫向分隔配置。 以弟一電極)與本質層之 7 201251054 本發明對照先前技術之功效: 相較於習知太陽能電池的PIN堆疊結構,由於在 本發明所提供之太陽能電池及其製造方法中,係使太 陽能電池中之P型半導體與N型半導體在第一電極 (或第二電極)與本質層之間橫向分隔配置;因此, 可使本發明所製作出之太陽能電池較習知太陽能電 池更為輕薄,藉以達到薄型化的要求。顯而易見地, 藉由本發明所提供之技術手段,可使所製作出之太陽 能電池更易於裝運與組裝,藉以大幅節省倉儲與裝運 時的空間成本,並且節省組裝時所需花費的組裝成 本0 本發明所採用的具體實施例,將藉由以下之實施 例及圖式作進一步之說明。 【實施方式】 由於本發明所提供之太陽能電池的製造方法,可 廣泛運用於製作多種太陽能電池,其組合實施方式更 是不勝枚舉,故在此不再——贅述,僅列舉其中兩個 較佳實施例來加以具體說明。 請參閱第一 A圖至第一 F圖,其係顯示本發明第 一實施例所提供之一種太陽能電池的一系列製造方 法示意圖。第一 A圖係顯示在本發明第一實施例中, 係先提供一基板,並依序在基板上堆疊一第一電極層 與一矽基半導體層;第一 B圖係顯示將第一電極層與 矽基半導體層加以圖案化,藉以形成複數個第一電極 與複數個矽基半導體;第一 C圖係顯示對複數個矽基 半導體進行摻雜製程,藉以使複數個矽基半導體分別 201251054 轉變成至少一 P型半導體與至少一 N型半導體;第一 D圖係顯示在p型半導體、>^型半導體與基板上形成 一介電層;第一 E圖係顯示對介電層進行一平坦化製 程’藉以使P型半導體與N型半導體外露,並使介^ 層轉變為至少一用以分隔P型半導體與N型半導體之 介電元件;第一 F圖係顯示在p型半導體與N型半 導體與介電元件上依序堆豐一本質層、一第二電極與 一保護層。 如第一 A圖所示,在本發明第一實施例中,係先 提供一基板11,基板11的材料可為玻璃、透明樹脂 或其他合適之透明材質。上述之透明樹脂可為聚對苯 二曱酸乙二酯(polyethylene terephthalate,PET)、聚 萘二曱酸乙二酯(polyethylene naphthalate,PEN)、聚 碳酸酯(polycarbonate,PC) ' 聚醚(polyethersulfone, PES)、聚醯亞胺(polyimide,PI)。 然後,可在基板11上堆疊一第一電極層12。第 一電極層12的材料可為透明導電氧化物,且透明導 電氧化物可為銦錫氧化物(indium tin oxide,IT0)、氧 化在呂鋅(A1 doped ZnO,AZO)、銦鋅氧化物(indium zinc oxide,IZO)或其他透明導電材料。此外,第一電極 層12的形成方法可為藏鏟法(sputtering)、化學氣相 沈積法(chemical vapor deposition,CVD)或蒸鑛法 (evaporation) ° 接著,可繼續在第一電極層12上形成一矽基半 導體層13。矽基半導體層13的材料可為非晶矽或微 晶矽。同時,矽基半導體層13的形成方法可為化學 氣相沈積法。 如第一 A圖與第一 B圖所示,在形成矽基半導 9 201251054 體層13之後,可利用化學钱刻(含電化學姓刻)、光 學蝕刻、光學切割或其組合等方式對第一電極層12 與矽基半導體層13加以圖案化,藉以使第一電極層 12與矽基半導體層13轉變為複數個第一電極(二 B圖中僅標示四個第一電極121、122、123盥12 與複數個梦基半導體(第一 B圖中僅標示四财基半 導體13卜132、133與134)。其中,矽基半導體131、 132、133與134係分別堆疊於第一電極以卜122、 123 與 124 上。 如弟一 B圖與第一 C圖所示,接著,可 ^體^卜❿⑶與⑼進行一換雜製程’使石夕 基半導體13卜132、133與134分別轉變成至少一 p 型半導體與至少一 N型半導體。在第一 B圖盥第一 c ^ 矽基半導體131與133係分別轉變為兩個p 半導體131P與133P ;矽基半導體132與134係 轉變為兩個N型半導體132N與 134N。其中,p =31P與1料所摻雜的材料可為選、自於元素週 ,月表中IIIA族兀素的群組,如硼(B)'鋁(A1)、鎵 銦(In)或鉈(T1);N型半導體1321^與134N中) 的^料可為選自於元素表中VA族元素的群組雜I For most of the current solar cells, most of them need to be installed in a fixture. In practice, the fixture may be the top or side wall of the building or the base or bracket of the solar powered system. In order to save the volume occupied by the shipment, and to make it easier to dream about the object of the divination, it is generally desirable that the solar cell be able to be thinner and lighter, that is, the solar cell can be made thinner. Based on the above-mentioned knowledge, 'in current solar cells, 'there are generally P-type semiconductor layers, intrinsic layers and N-type semiconductor layers' and P-type semiconductor layers, intrinsic layers and N-type semiconductor layers. The system is vertically stacked into a ρθΙΝ stack structure to form a photoelectric conversion layer. However, since the 'P-type semiconductor layer, the intrinsic layer, and the N-type semiconductor layer are in accordance with the 201251054' in the pIN stack structure, the thickness of the light-converting layer may not be thinned. The solar cells that can be transported in this way will result in a significant increase in the cost of warehousing and shipping (4) labor costs and the cost of assembly during assembly. SUMMARY OF THE INVENTION The technical problems and objects to be solved by the present invention are as follows: the layer and the order of the ρ·-type semi-conductive layer, the essence of the reason, resulting in the deuteration of the solar cell, the main type of the present invention: The body-positive battery and the manufacturing method thereof, the p-energy battery=degree conductor laterally spaced configuration 'to reduce the sun, the technical means for solving the problem of the invention: paragraph pass i ί明ί fί technical hand used by the technical hand The d-energy battery includes a substrate, a plurality of H-dipoles, a semiconductor, at least an -N-type semiconductor, two intrinsic layers, and a second electrode. The above complex and n-type are on the substrate. At least a plurality of p-type semiconductors are stacked on the plurality of first electrode type semiconductors and N, respectively, and laterally separating p from the intrinsic layer. N f semiconductor system is used in the first electrode 6 201251054. In a preferred embodiment of the present invention, Eight materials including the oxidized stone eve, the nitrite and the oxynitride 电 电 电 电 电 可 至少 至少 至少 至少 至少 。 。 雷 。 。 。 。 。 。 。 。. The first sun-light conductive oxide. Above the second electrode. Further, the layer is laminated on a glass or a transparent resin. The material of the substrate and the protective layer can be covered by the technical problem of the method. The manufacturing method of the W battery is reversed and the first electric circuit is formed in the first base and the plurality of electrodes. For the formation of at least one p-type 舻=type II semi-conducting body, and in the p-type semiconductor and (2) element, thereby separating the p-type semiconducting == conductor. After taking the 'P-type semiconductor, N-type input S ϊ ϊ ϊ an essential layer; and forming a -7" electrode on the intrinsic layer. Preferably, the technical hand used to continue to provide the protection segment on the second electrode is the same as that of the other solar cell = and a -electrode is formed on the substrate. Then, an intrinsic layer is formed on the electrode, and the P-type 5 small P-type semiconductor and at least one type of semiconductor are opened on the intrinsic layer, and the 一'-N-type semiconductor phase gate 13J ^ 1 semiconductor system and the upper eight C 'The p-type semiconductor and the μ semiconductor form a second electrode, thereby forming a plurality of second bodies S between: a type t conductor and a semiconductor: a dielectric: semiconductor. Preferably, a protective layer is provided on the electrode and the dielectric element. As apparent from the above description, in the manufacturing method of the Y / according to the present invention, the solar power is arranged in a laterally spaced relationship. 7 510 电极 电极 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 The P-type semiconductor and the N-type semiconductor are laterally spaced apart from each other between the first electrode (or the second electrode) and the intrinsic layer; therefore, the solar cell fabricated by the present invention can be made lighter and thinner than conventional solar cells. To achieve the requirements of thinning. Obviously, by the technical means provided by the invention, the fabricated solar cell can be more easily shipped and assembled, thereby greatly reducing the space cost in storage and shipment, and saving the assembly cost required for assembly. The specific embodiments used will be further illustrated by the following examples and drawings. [Embodiment] The method for manufacturing a solar cell provided by the present invention can be widely applied to the production of a plurality of solar cells, and the combined embodiments thereof are numerous, so it is not repeated here--only two of them are listed. The preferred embodiment will be specifically described. Referring to FIGS. 1A to 1F, there are shown a series of manufacturing method diagrams of a solar cell according to a first embodiment of the present invention. The first A is shown in the first embodiment of the present invention, first providing a substrate, and sequentially stacking a first electrode layer and a germanium-based semiconductor layer on the substrate; the first B-picture shows the first electrode The layer is patterned with the germanium-based semiconductor layer to form a plurality of first electrodes and a plurality of germanium-based semiconductors; the first C-picture shows a doping process for the plurality of germanium-based semiconductors, thereby making the plurality of germanium-based semiconductors respectively 201251054 Converting into at least one P-type semiconductor and at least one N-type semiconductor; the first D-picture shows a dielectric layer formed on the p-type semiconductor, the >-type semiconductor and the substrate; the first E-picture shows the dielectric layer a planarization process 'to expose the P-type semiconductor and the N-type semiconductor, and to convert the dielectric layer into at least one dielectric element for separating the P-type semiconductor from the N-type semiconductor; the first F-picture is shown in the p-type semiconductor An intrinsic layer, a second electrode and a protective layer are sequentially stacked on the N-type semiconductor and the dielectric element. As shown in Fig. 1A, in the first embodiment of the present invention, a substrate 11 is provided, and the material of the substrate 11 may be glass, transparent resin or other suitable transparent material. The above transparent resin may be polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC) 'polyether (polyethersulfone) , PES), polyimide (PI). Then, a first electrode layer 12 may be stacked on the substrate 11. The material of the first electrode layer 12 may be a transparent conductive oxide, and the transparent conductive oxide may be indium tin oxide (IT0), oxidized in A1 doped ZnO (AZO), indium zinc oxide ( Indium zinc oxide, IZO) or other transparent conductive materials. In addition, the first electrode layer 12 may be formed by sputtering, chemical vapor deposition (CVD) or evaporation. Then, the first electrode layer 12 may continue to be formed on the first electrode layer 12. A germanium-based semiconductor layer 13 is formed. The material of the bismuth-based semiconductor layer 13 may be amorphous germanium or microcrystalline germanium. Meanwhile, the method of forming the germanium-based semiconductor layer 13 may be a chemical vapor deposition method. As shown in FIG. 1A and FIG. B, after the formation of the sulfhydryl semiconducting layer 9 201251054 body layer 13, the chemical engraving (including electrochemical etching), optical etching, optical cutting, or a combination thereof may be used. An electrode layer 12 is patterned with the bismuth-based semiconductor layer 13 to convert the first electrode layer 12 and the bismuth-based semiconductor layer 13 into a plurality of first electrodes (only four first electrodes 121, 122 are indicated in FIG. 123盥12 and a plurality of Moon-based semiconductors (only the four-base semiconductors 13b, 132, 133, and 134 are labeled in the first B-picture), wherein the germanium-based semiconductors 131, 132, 133, and 134 are stacked on the first electrode, respectively. Bu 122, 123 and 124. As shown in Fig. 1 and Fig. C, the following can be done by ^^^(3) and (9) to make a replacement process, so that Shi Xiji Semiconductor 13 Bu 132, 133 and 134 respectively Converting into at least one p-type semiconductor and at least one N-type semiconductor. In the first B-picture, the first c^-based semiconductors 131 and 133 are respectively converted into two p-semiconductors 131P and 133P; the germanium-based semiconductors 132 and 134 are transformed Two N-type semiconductors 132N and 134N, wherein p = 31P and 1 doped The material may be selected from the group of elements, the group of group IIIA halogens in the monthly table, such as boron (B) 'aluminum (A1), gallium indium (In) or tantalum (T1); N-type semiconductor 1321^ and 134N The middle material may be a group miscellaneous selected from the VA group elements in the element table

= = (Ρ)、砷(As)、銻(Sb)或鉍(Bi)。較佳者,p型 導體131P係與Μ半導體132N彼此分隔並 ^ 型半導體132N係與P型半導體1331>彼此分隔·ρ 半導體i33P係與N型半導體⑶心此分隔並匹配I ,如第一 D圖所示,在進行摻雜製程後, =導體131P與133P、N型半導體⑽與U4N以 二11上形成-介電層14,且介電層14的材料可 匕括氧化矽、氮化矽與氮氧化矽中之至少一者。 如第- D圖與第- E圖所示,在形成介電層η 201251054 半導體131P ^Π3Ρ進平坦化製程,藉以使Ρ型 外露,if祛人:1/1以及Ν型半導體132Ν與134Ν 卜:並使"電層14轉變為至少一介電元件(第一 ε ^中所標示者為三個介電元件⑷、142幻43弟)。1 I村坦化製程可利用機械研磨(含化學輔助 機械研磨)或化學蝕刻等方式進行。 件二製程所形成之介電元 型半導體132N之間 與型半導體133P之間以及P型半導 |二3〗;二型,體134N之間,藉以分隔= = (Ρ), arsenic (As), antimony (Sb) or antimony (Bi). Preferably, the p-type conductor 131P and the germanium semiconductor 132N are separated from each other and the semiconductor 132N and the P-type semiconductor 1331 are separated from each other. The semiconductor i33P and the N-type semiconductor (3) are separated and matched with each other, such as the first D. As shown in the figure, after the doping process, = conductors 131P and 133P, N-type semiconductors (10) and U4N form a dielectric layer 14 on the second layer 11, and the material of the dielectric layer 14 may include tantalum oxide and tantalum nitride. And at least one of bismuth oxynitride. As shown in Fig. D and Fig. E, in the formation of dielectric layer η 201251054 semiconductor 131P ^ Π 3 into the planarization process, so that the Ρ type exposed, if祛: 1 / 1 and Ν type semiconductor 132 Ν and 134 卜 卜: and convert the "electric layer 14 into at least one dielectric element (the first ε ^ is labeled as three dielectric elements (4), 142 phantom 43 brothers). 1 I village can be processed by mechanical grinding (including chemically assisted mechanical grinding) or chemical etching. Between the dielectric-type semiconductors 132N formed by the second process and the type semiconductor 133P and between the P-type semi-conductors | 2 3; the second type, the body 134N, thereby separating

半導體132N、P型半導體⑽與N =- F、圖所示’在形成介電元件i4i、M2與 141、Μ後’、可進一步在P型半導體131P、介電元件 入型半導體I32N、介電元件142、p型半導體 二質:!5=434,_4Ν 上以Ξ 造出-太陽能電圣16與一保護層17,藉以製 方法^為非晶梦或微晶石夕’其形成 咖型半導體層⑽與 ,, 牛蜍體層i32N與134N以及本質屑15孫 以將進入太陽能電池;的光 區;本質層15係作為光產生電子-電 明導16的材料可為透明導電氧化物,且透 201251054 马濺鍍法、化與洛a 材料可為诚干^ 積法或蒸鑛法。保護層17的 2 、透明樹脂或其他合適之透明材質。 可製發明,共之製造方法 一其故U 險此電池1,且太陽能電池1包含 個i-带坧3數個第一電極(如第一 F圖所示的四 導體第—,124)、至少—Ρ型半 Ν型i、導體導體(如第- F圖所示的兩個 的三個介電元件14卜]42與⑷)、-本 貝層15、一第二電極16與一保護層17。 二電極121、122、123與124係彼.此相間地配 ίίίϊ板U上;”半導體1311>與133P係分別 ^宜;弟一電極121與i23;N型半導體132N與134N 係分別堆疊於第一電極122與124。 、介電元件141、142與143係配置於基板η上, 並且分別位於p型半導體131p與N型半導體132N 之間、N型半導體132N與P型半導體133P之間以及 P型半導體133P與N型半導體134N之間,藉以分隔 P型半導體131P、N型半導體132N、P型半導體133P 與N型半導體134N。 本質層15係堆疊於p型半導體π 1P、介電元件 141、N型半導體132N、介電元件142、P型半導體 133P、介電元件143與N型半導體134N上,第二電 極16係堆疊於本質層15上,保護層π係堆疊於第 二電極16上。由於在太陽能電池1中,各組成元件 之材料均已在上述之製造方法中揭露,因此,以下不 再予以贅述。 12 201251054 除了以上所揭露的製造方法之外,本發明還提供 了另一種太(¼能電池的製造方法。請繼續參閱第二A 圖至第二G圖,其係顯示本發明第二實施例所提供之 另一種太陽能電池的一系列製造方法示意圖。第二A 圖係顯示在本發明第二實施例中,係先提供一基板, 並依序在基板上堆疊一第/電極、一本質層與一矽基 半導體層;第二B圖係顯示將矽基半導體層加以圖案 化,藉以形成數個矽基半導體;第二C圖係顯示對複 數個矽基半導體進行摻雜製程,藉以使複數個矽基半 導體分別轉變成至少一p塑半導體與至少一N型半導 體,第一 D圖係顯示在p变半導體與n型半導體上 形成複數個第二電極;第二E圖係顯示在第二電極與 本質層上形成一介電層;第二F圖係顯示對介電層進 行一平坦化製程,藉以使第二電極外露,並使介電層 轉變為至少一用以分隔P塑半導體與N型半導體之介 電元件;第二G圖係顯示在第二電極與介電元件上堆 疊一保護層。 如第二A圖所示,在本發明第二實施例中,係先 提供一基板21,基板21的材料可為玻璃、透明樹脂 或其他合適之透明材質。上述之透明樹脂可為聚對苯 二曱酸乙二酯(polyethylene terephthalate,PET)、聚 萘二曱酸乙二酯(polyethylene naphthalate,PEN)、聚 碳酸醋(polycarbonate,PC)、聚醚(polyethersulfone, PES)、聚醯亞胺(polyimide,PI)。 接著,可在基板21上堆疊一第一電極22,在第 一電極22上堆疊一本質層23,並可在本質層23上堆 疊一矽基半導體層24。第一電極22的材料可為透明 導電氧化物,其可為銦錫氧化物、氧化鋁鋅、銦鋅氧 化物或其他透明導電材料。第一電極22的形成方法 13 201251054 可為濺鍍法、化學氣相沈積法或蒸鍍法。本質層23 的材料可為非晶石夕或微晶;ε夕,且本質層23的形成方 法可為化學氣相沈積法。同時,石夕基半導體層24的 形成方法亦可為化學氣相沈積法。 如第二B圖所示,在形成矽基半導體層24後, 可利用化學蝕刻(含電化學蝕刻)、光學蝕刻、光學 切割或其組合等方式對矽基半導體層24加以圖案 化’藉以使石夕基半導體層24轉變為複數個石夕基半導 體(第二B圖中僅標示四個石夕基半導體241、242、 243 與 244)。 如第二B圖與第二C圖所示,接著,可對石夕基 半導體241、242、243與244進行一摻雜製程,使石夕 基半導體241、242、243與244分別轉變成至少一 p 型半導體與至少一 N型半導體。在第二b圖與第二c 圖中,矽基半導體241與243係分別轉變為兩個p型 半導體241P與243P ;矽基半導體242與244係分別 轉變為兩個N型半導體242N與244N。其中,P型半 導體241P與243P中所摻雜的材料可為選自於元素週 期表中IIIA族元素的群組,如硼(B)、鋁(A1)、鎵(Ga)、 銦(In)或鉈(ΤΙ) ; N型半導體242N與244N中所摻雜 的材料可為選自於元素週期表中VA族元素的群組, 如磷(P)、砷(As)、銻(Sb)或鉍(Bi)。較佳者,P型半 導體241P係與N型半導體242N彼此分隔並匹配;N 型半導體242N係與P型半導體243P彼此分隔;P型 半導體243P係與N型半導體244N彼此分隔並匹配。 如第二D圖所示’在形成p型半導體241P與243P 以及N型半導體242N與244N之後,可在P型半導 體241P與243P以及N型半導體242N與244N上分 別形成一第二電極’藉以形成複數個上述之第二電 201251054 極。在第二D圖中,顯係示形成四個第二電極25a、 25b、25c 與 25d。且第二電極 25a、25b、25c 與 25d 係分別堆疊於P型半導體241P、N型半導體242N、 P型半導體243P與N型半導體244N上。此外,第二 電極25a、25b、25c與25d的材料可為透明導電氧化 物,且透明導電氧化物可為銦錫氧化物、氧化鋁鋅、 銦鋅氧化物或其他透明導電材料。 如第二E圖所示,在形成第二電極25a、25b、 25c與25d之後,可繼續在第二電極25a、25b、25c 與25d以及本質層23上形成一介電層26,且介電層 26的材料可包括氧化矽、氮化矽與氮氧化矽中之至少 一者。 如第二E圖與第二F圖所示,在形成介電層26 後,可對介電層26進行一平坦化製程,藉以使第二 電極25a、25b、25c與25d外露,並使介電層26轉 變為至少一介電元件(第二F圖中所標示者為三個介 電元件261、262與263)。其中,上述之平坦化製程 可利用機械研磨(含化學輔助機械研磨)或化學蝕刻 等方式進行。 由第二F圖可知,經由上述製程所形成之介電元 件261、262與263係配置於本質層23上,並且分別 位於P型半導體241P與N型半導體242N之間、N 型半導體242N與P型半導體243P之間以及P型半 導體243P與N型半導體244N之間,藉以分隔P型 半導體241P、N型半導體242N、P型半導體243P與 N型半導體244N。 如第二G圖所示,在形成介電元件261、262與 263之後,可繼續在第二電極25a、介電元件261、第 15 201251054 二電極25b、介電元件262 263與第二電極25d上形成極25c、介電元件 一太陽能電池2。保護岸27層27,藉以製造出 脂或其他合適之透明材曰質。$材料可為玻璃、透明樹 第識者 ’在比對 本發明所揭露之兩種§亥都能輕以理解,雖然 -t ^ It : Γ ^ ^ 之保護層27相同,太陽能電池冗能電池2 此電池2之基板21的材料與太陽 是太陽能電池1的倒置牡構由,月b電池2正 第一雷以二 # ’其中’太陽能電池1之 ΐ第:123與124相當於太陽能電二 ϊ ,25d,太陽能電池1之 ?極16相當於太陽能電池2之第一電極22。 通常二’相#舉凡在所屬技術領域中具有 ,易理解,相較於習知太陽能電池,由Hi 所提供之太陽能電池〗或2的製 ' 型半導體在第一電^中一實= 2了if(如第二實施例)與本質層之間橫向分隔 配置迴因此,可使本發明所製作出之太陽能電池1或 2車父各知太陽能電池更為輕薄,藉以達到薄型化 (°,而易見地,藉由本發明所提供之技術手段 ,所製作出之太陽能電池i或2更易於裝運與组裝, ,七大幅節省倉儲與裝運時的空間成本,並且 裝時所需花冑的組裝成本。 ^ 藉由上述之本發明實施例可知,本發明確具產業 七之,用價值。惟以上之實施例說明’僅為本發明之 車又佳貫施例說明,舉凡所屬技術領域中具有通常知識 16 201251054 【圖式簡單說明】 1_顯示在本發明第—實施例中,係先提供一 基板,並依序在基板上堆4-第-電極層斑一 矽基半導體層; 〃 1圖_示將第—電極層㈣基半導體層加以 =以形成複數個第-電極與複數卿 圖係.4不對複數個々基半導體進行推雜製 程’藉以使複數個碎基半導體分別轉變成至少 一P型半導體與至少一N型半導體; D圖係顯示在p租〗末道 * Π +導體、N型半導體與基板上 开> 成一介電層; E圖係顯示對介電層進行一平坦化製程,藉以使 導體與N型半導體外露,並使介電層轉 艾為至>、一用以分隔P型半導體與N型半導 體之介電元件; F=顯示在P型半導體與N型半導體與介電 二上依序堆疊一本質層、-第二電極與-保 濩層; 第 第 第 第 第 第 201251054 第 第二 第 第 第 第 係顯示在本發明第二實施例 基板,並依序在基板上堆疊先棱仪一 質層與—石夕基半導體層; ;極本 •B圖係顯示將矽基半導體層加以圖案 成數個矽基半導體; ' 9 . 7 ‘ C '係顯示對複數個石夕基半導體進行摻雜製 私’糟以使複數偏夕基半導體分別轉變成 一P型半導體與至少一N型半導體; D圖係顯示在p型半導體與n型半導體 複數個第二電極; ’成 E圖係顯示在第二電極與本f層上形成一介 層; F圖係顯示對介電層進行—平坦化製程,藉以使 第二電極外露,並使介電層轉變為至少一用以 分隔P型半導體與N型半導體之介電元 以及 , 第 )圖係: 護層。 示在第二電極與介電元件上堆 疊一保 【主要元件符號說明】 1 11 12 121 、 122 、 123 、 124 太陽能電池 基板 第—電極層 第—電極 18 201251054 13 131 、 132 、 133 、 134Semiconductor 132N, P-type semiconductor (10) and N = - F, as shown in 'forming dielectric elements i4i, M2 and 141, after '', further in P-type semiconductor 131P, dielectric-in-type semiconductor I32N, dielectric Element 142, p-type semiconductor binary: !5=434, _4Ν 上 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造 造The layers (10) and, the burdock body layers i32N and 134N and the intrinsic chip 15 will enter the solar cell; the intrinsic layer 15 as the light-generating electron-electricity guide 16 material may be a transparent conductive oxide, and 201251054 The method of sputtering, crystallization and Luo a can be made by honesty or steaming. Protective layer 17 of 2, transparent resin or other suitable transparent material. It can be invented, and the manufacturing method is the same as the battery 1, and the solar cell 1 includes a plurality of first electrodes (i.e., the four conductors shown in the first F-figure, 124). At least - Ρ type semi-Ν type i, conductor conductor (such as two dielectric elements 14 shown in Figure - F) 42 and (4)), - Ben shell 15, a second electrode 16 and a protection Layer 17. The two electrodes 121, 122, 123 and 124 are connected to each other. The semiconductor 1311> and the 133P system are respectively suitable; the first electrode 121 and the i23; the N-type semiconductors 132N and 134N are stacked respectively. An electrode 122 and 124. The dielectric elements 141, 142 and 143 are disposed on the substrate η and are respectively located between the p-type semiconductor 131p and the N-type semiconductor 132N, between the N-type semiconductor 132N and the P-type semiconductor 133P, and P. The P-type semiconductor 131P, the N-type semiconductor 132N, the P-type semiconductor 133P, and the N-type semiconductor 134N are separated between the type semiconductor 133P and the N-type semiconductor 134N. The intrinsic layer 15 is stacked on the p-type semiconductor π 1P, the dielectric element 141, On the N-type semiconductor 132N, the dielectric element 142, the P-type semiconductor 133P, the dielectric element 143, and the N-type semiconductor 134N, the second electrode 16 is stacked on the intrinsic layer 15, and the protective layer π is stacked on the second electrode 16. Since the materials of the respective constituent elements have been disclosed in the above-described manufacturing method in the solar cell 1, they will not be described below. 12 201251054 In addition to the manufacturing method disclosed above, the present invention provides another (1⁄4 A method for manufacturing a battery. Please refer to the second to second G drawings, which are schematic views showing a series of manufacturing methods of another solar cell according to a second embodiment of the present invention. In the second embodiment of the present invention, a substrate is first provided, and a first electrode, an intrinsic layer and a germanium-based semiconductor layer are sequentially stacked on the substrate; and the second B-picture shows that the germanium-based semiconductor layer is patterned. By forming a plurality of germanium-based semiconductors; the second C-picture shows a doping process for a plurality of germanium-based semiconductors, whereby a plurality of germanium-based semiconductors are respectively converted into at least one p-plastic semiconductor and at least one N-type semiconductor, first D The figure shows that a plurality of second electrodes are formed on the p-variable semiconductor and the n-type semiconductor; the second E-picture shows a dielectric layer formed on the second electrode and the intrinsic layer; and the second F-picture shows the dielectric layer a planarization process for exposing the second electrode and converting the dielectric layer into at least one dielectric component for separating the P plastic semiconductor from the N-type semiconductor; the second G pattern is shown on the second electrode and the dielectric component Pile up As shown in FIG. 2A, in the second embodiment of the present invention, a substrate 21 is provided first, and the material of the substrate 21 may be glass, transparent resin or other suitable transparent material. Polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), poly Polyimide (PI). Next, a first electrode 22 may be stacked on the substrate 21, an intrinsic layer 23 may be stacked on the first electrode 22, and a germanium-based semiconductor layer 24 may be stacked on the intrinsic layer 23. The material of the first electrode 22 may be a transparent conductive oxide which may be indium tin oxide, aluminum zinc oxide, indium zinc oxide or other transparent conductive material. Method of Forming First Electrode 22 13 201251054 may be a sputtering method, a chemical vapor deposition method, or an evaporation method. The material of the intrinsic layer 23 may be amorphous or microcrystalline; and the formation of the intrinsic layer 23 may be a chemical vapor deposition method. Meanwhile, the formation method of the Shi Xiji semiconductor layer 24 may also be a chemical vapor deposition method. As shown in FIG. 2B, after the germanium-based semiconductor layer 24 is formed, the germanium-based semiconductor layer 24 can be patterned by chemical etching (including electrochemical etching), optical etching, optical cutting, or a combination thereof. The Shi Xiji semiconductor layer 24 is transformed into a plurality of Shih-ki semiconductors (only four Shih-kiu semiconductors 241, 242, 243 and 244 are indicated in the second B-picture). As shown in FIG. 2B and FIG. 2C, a doping process can be performed on the Shih-Xi semiconductors 241, 242, 243, and 244 to convert the Shih-Xi semiconductors 241, 242, 243, and 244 into at least A p-type semiconductor and at least one N-type semiconductor. In the second and second c-pictures, the germanium-based semiconductors 241 and 243 are converted into two p-type semiconductors 241P and 243P, respectively; and the germanium-based semiconductors 242 and 244 are converted into two N-type semiconductors 242N and 244N, respectively. The material doped in the P-type semiconductors 241P and 243P may be selected from the group consisting of Group IIIA elements of the periodic table, such as boron (B), aluminum (A1), gallium (Ga), and indium (In). Or 铊(ΤΙ); the material doped in the N-type semiconductors 242N and 244N may be selected from the group consisting of VA elements in the periodic table, such as phosphorus (P), arsenic (As), antimony (Sb) or铋 (Bi). Preferably, the P-type semiconductor 241P and the N-type semiconductor 242N are spaced apart from each other and matched; the N-type semiconductor 242N and the P-type semiconductor 243P are separated from each other; and the P-type semiconductor 243P and the N-type semiconductor 244N are spaced apart from each other and matched. As shown in FIG. 2D, after forming the p-type semiconductors 241P and 243P and the n-type semiconductors 242N and 244N, a second electrode ' can be formed on the P-type semiconductors 241P and 243P and the N-type semiconductors 242N and 244N, respectively. A plurality of the above-mentioned second electric 201251054 poles. In the second D diagram, four second electrodes 25a, 25b, 25c and 25d are formed. Further, the second electrodes 25a, 25b, 25c, and 25d are stacked on the P-type semiconductor 241P, the N-type semiconductor 242N, the P-type semiconductor 243P, and the N-type semiconductor 244N, respectively. Further, the material of the second electrodes 25a, 25b, 25c and 25d may be a transparent conductive oxide, and the transparent conductive oxide may be indium tin oxide, aluminum zinc oxide, indium zinc oxide or other transparent conductive material. As shown in FIG. E, after forming the second electrodes 25a, 25b, 25c and 25d, a dielectric layer 26 may be formed on the second electrodes 25a, 25b, 25c and 25d and the intrinsic layer 23, and dielectrically The material of layer 26 can include at least one of cerium oxide, cerium nitride, and cerium oxynitride. As shown in the second E and second F, after the dielectric layer 26 is formed, a planarization process can be performed on the dielectric layer 26, so that the second electrodes 25a, 25b, 25c, and 25d are exposed, and the second electrodes 25a, 25b, 25c, and 25d are exposed. The electrical layer 26 is transformed into at least one dielectric component (the ones indicated in the second F diagram are three dielectric components 261, 262 and 263). Among them, the above flattening process can be carried out by mechanical polishing (including chemical assisted mechanical polishing) or chemical etching. As can be seen from the second F diagram, the dielectric elements 261, 262, and 263 formed through the above process are disposed on the intrinsic layer 23, and are respectively located between the P-type semiconductor 241P and the N-type semiconductor 242N, and the N-type semiconductors 242N and P. Between the type semiconductors 243P and between the P-type semiconductor 243P and the N-type semiconductor 244N, the P-type semiconductor 241P, the N-type semiconductor 242N, the P-type semiconductor 243P, and the N-type semiconductor 244N are separated. As shown in the second G diagram, after forming the dielectric elements 261, 262, and 263, the second electrode 25a, the dielectric element 261, the 15th 201251054 second electrode 25b, the dielectric element 262 263, and the second electrode 25d may continue. A pole 25c, a dielectric element, and a solar cell 2 are formed. Protect the shore 27 layers 27 to produce fat or other suitable transparent material. The material can be glass, transparent tree idiots' can be understood in comparison with the two § hai disclosed in the present invention, although the protective layer 27 of -t ^ It : Γ ^ ^ is the same, the solar cell battery 2 The material of the substrate 21 of the battery 2 and the sun are the inverted structure of the solar cell 1, and the battery of the b battery 2 is the first thunder to two # 'where the 'the solar cell 1 is the first: 123 and 124 are equivalent to the solar power diode, 25d, the pole 16 of the solar cell 1 corresponds to the first electrode 22 of the solar cell 2. Generally, the two 'phases' are in the technical field, and are easy to understand. Compared with the conventional solar cells, the solar cell provided by Hi or the type II semiconductor is in the first electric field. If (as in the second embodiment) is disposed laterally separated from the intrinsic layer, the solar cell 1 or 2 of the solar cell produced by the present invention can be made thinner and thinner, thereby achieving thinning (°, and Conveniently, by the technical means provided by the present invention, the fabricated solar cell i or 2 is easier to ship and assemble, and the space cost for storage and shipment is greatly reduced, and the assembly cost of the flower basket is required. It can be seen from the above embodiments of the present invention that the present invention has the value of the industry and the use of the present invention. However, the above embodiments are merely illustrative of the preferred embodiment of the present invention, and are generally used in the technical field. Knowledge 16 201251054 [Simplified description of the drawings] 1_ shows that in the first embodiment of the present invention, a substrate is first provided, and a 4-first-electrode layer of a semiconductor layer is sequentially stacked on the substrate; 〃 1 _ show will - the electrode layer (four)-based semiconductor layer is applied to form a plurality of first-electrode and complex-numbered patterns. 4 does not perform a hybrid process for a plurality of germanium-based semiconductors, whereby a plurality of fragment-based semiconductors are respectively converted into at least one P-type semiconductor and at least An N-type semiconductor; D-picture is shown in the end of the p-rent * Π + conductor, N-type semiconductor and substrate open > into a dielectric layer; E-picture shows a planarization process on the dielectric layer, so that The conductor and the N-type semiconductor are exposed, and the dielectric layer is turned into a >, a dielectric element for separating the P-type semiconductor from the N-type semiconductor; F=displayed in the P-type semiconductor and the N-type semiconductor and the dielectric II The intrinsic layer, the second electrode and the -protective layer are sequentially stacked on the first layer; the second and the second layer are shown in the second embodiment of the present invention, and are sequentially stacked on the substrate. a prismatic layer and a Shi Xiji semiconductor layer; the polarbook B shows that the germanium-based semiconductor layer is patterned into a plurality of germanium-based semiconductors; '9 . 7 ' C ' shows multiple pairs of Shi Xiji Semiconductors doping The complex eclipse semiconductor is respectively converted into a P-type semiconductor and at least one N-type semiconductor; the D-picture is shown in a plurality of second electrodes of the p-type semiconductor and the n-type semiconductor; the 'E-picture is displayed on the second electrode and the f-layer Forming a via layer on the upper surface; F-picture showing a planarization process on the dielectric layer, thereby exposing the second electrode, and converting the dielectric layer into at least one dielectric element for separating the P-type semiconductor from the N-type semiconductor and , the first picture system: protective layer. Displayed on the second electrode and the dielectric element. [Main component symbol description] 1 11 12 121 , 122 , 123 , 124 Solar cell substrate First electrode layer First electrode 18 201251054 13 131 , 132 , 133 , 134

131P 、 133P131P, 133P

132N、134N 14 141、142、143 15 16 17 2 21 22 23 24 241 、 242 、 243 、 244132N, 134N 14 141, 142, 143 15 16 17 2 21 22 23 24 241 , 242 , 243 , 244

241P ' 243P241P ' 243P

242N ' 244N 25a、25b、25c、25d 26 261 、 262 、 263 27 矽基半導體層 矽基半導體 P型半導體 N型半導體 介電層 介電元件 本質層 第二電極 保護層 太陽能電池 基板 第一電極 本質層 矽基半導體層 矽基半導體 P型半導體 N型半導體 第二電極 介電層 介電元件 保護層 19242N ' 244N 25a, 25b, 25c, 25d 26 261 , 262 , 263 27 矽 based semiconductor layer 矽 based semiconductor P type semiconductor N type semiconductor dielectric layer dielectric element intrinsic layer second electrode protective layer solar cell substrate first electrode essence Layer germanium semiconductor layer germanium-based semiconductor P-type semiconductor N-type semiconductor second electrode dielectric layer dielectric element protective layer 19

Claims (1)

201251054 七 、申請專利範圍 1. 一種太陽能電池,包括: 一基板; ,數個第—電極’係彼此機地配置於該基板上. trp型半導體,係堆疊於該些第—電極之至少-者· 二N型半導體,係堆叠於該些第—電極之至少— =,並與該Ρ型半導體相匹配; 半導件’係配置於該基板上,並且位於該卩型 與該Ν型ϋ =半導體之間,藉以分隔該卩型半導體 一 疊型半導體、該Ν型半導體與該 一第二電極,係堆疊於該本質層上。 申明專利範圍第1項所述之太陽能電池,1中嗲介電 元件的材料包括氧切、統賴氮氧化”之 者。 20 201251054 5. 如申請專利範圍第1項所述之太陽能電池,其中該基板 的材料包括玻璃或透明樹脂。 6. 如申請專利範圍第1項所述之太陽能電池,更包括一保 護層,且該保護層係堆疊於該第二電極上。 7. 如申請專利範圍第6項所述之太陽能電池,其中該保護 層的材料包括玻璃或透明樹脂。 8. —種太陽能電池的製造方法,包括以下步驟: ⑻提供一基板; % (b) 在該基板上形成複數個彼此相間之第一電極; (c) 在該些第一電極上分別形成至少一 P型半導體與至 少一 N型半導體; (d) 在該P型半導體與該N型半導體之間形成至少一介 電元件,藉以分隔該P型半導體與該N型半導體; (e) 在該P型半導體、N型半導體與該介電元件上形成 一本質層;以及 (f) 在該本質層上形成一第二電極。 9. 如申請專利範圍第8項所述之太陽能電池的製造方法, 21 201251054 在該步驟(f)之後,更包括-步驟⑻,且該步驟_在該 弟二電極上提供一保護層。 10. —種太陽能電池的製造方法,包括以下步驟: (a) 提供一基板; (b) 在該基板上形成一第一電極; (c) 在该第一電極上形成一本質層; (d) 在該本質層上形成至少一 p型半導體與至少一 n型 半導體,且該P型半導體係與該N型半導體相間; (e) 在該P型半導體與該N型半導體上分別形成一第二 電極’藉以形成複數個上述之第二電極;以及 (f) 在該P型半導體與該N型半導體之間形成至少一介 電兀件’藉以分隔該P型半導體與該N型半導體。 如申專利範圍第10項所述之太陽能電池的製造方 法’在5亥步驟(f)之後,更包括一步驟(g),且該步驟(g) 係在#第二電極與該介電元件上提供-保護層。 22201251054 VII. Patent application scope 1. A solar cell comprising: a substrate; a plurality of first electrodes are disposed on the substrate on each other. The trp type semiconductor is stacked on at least the first electrode a two N-type semiconductor stacked on at least the = electrodes of the first electrodes and matched with the germanium semiconductor; the semiconductor 14' is disposed on the substrate and located at the germanium type and the germanium type Between the semiconductors, the germanium-type semiconductor stack semiconductor, the germanium semiconductor and the second electrode are stacked on the intrinsic layer. A solar cell according to the first aspect of the invention, wherein the material of the dielectric element of the first embodiment includes oxygen oxidizing and oxidizing the nitrogen. 20 201251054 5. The solar cell of claim 1, wherein The material of the substrate includes a glass or a transparent resin. The solar cell of claim 1, further comprising a protective layer, and the protective layer is stacked on the second electrode. The solar cell according to Item 6, wherein the material of the protective layer comprises glass or a transparent resin. 8. A method for manufacturing a solar cell, comprising the steps of: (8) providing a substrate; and (b) forming a plurality on the substrate. a first electrode interposed therebetween; (c) forming at least one P-type semiconductor and at least one N-type semiconductor on the first electrodes; (d) forming at least one between the P-type semiconductor and the N-type semiconductor a dielectric element for separating the P-type semiconductor from the N-type semiconductor; (e) forming an intrinsic layer on the P-type semiconductor, the N-type semiconductor and the dielectric element; and (f) in the essence Forming a second electrode thereon. 9. The method for manufacturing a solar cell according to claim 8, 21 201251054, after the step (f), further comprising - the step (8), and the step _ Providing a protective layer. 10. A method of manufacturing a solar cell, comprising the steps of: (a) providing a substrate; (b) forming a first electrode on the substrate; (c) forming on the first electrode An intrinsic layer; (d) forming at least one p-type semiconductor and at least one n-type semiconductor on the intrinsic layer, and the P-type semiconductor is interposed between the N-type semiconductor; (e) the P-type semiconductor and the N-type Forming a second electrode ' on the semiconductor to form a plurality of the second electrodes; and (f) forming at least one dielectric element between the P-type semiconductor and the N-type semiconductor to separate the P-type semiconductor from The N-type semiconductor. The method for manufacturing a solar cell according to claim 10, further comprising a step (g) after the step 5 (f), and the step (g) is at the #second electrode Provided with a protective layer on the dielectric element. 22
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI746424B (en) * 2014-09-05 2021-11-21 美商太陽電子公司 Improved front contact heterojunction process for fabricating solar cells and solar cells thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI746424B (en) * 2014-09-05 2021-11-21 美商太陽電子公司 Improved front contact heterojunction process for fabricating solar cells and solar cells thereof

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