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V J 六、發明說明： 【發明所屬之技術領域】 本申請案為2007年12月14日提出申請之美國專利申 請第11/956, 962號案之分割案，前者亦為2007年3月23 曰申請之第11/690, 443號案（現為專利號第7, 524, 686號） 的部分延續案（CIP)，前者為2006年12月29曰申請之第 11/618,468號案（現為專利號第7, 563, 625號）的部分延續 ，（CIP) ’前者為2005年1月11日申請之第ii/〇32,880 號案（現為專利號第7, 186, 580號）的部分延續案（CIP)，上 述全部於此納入參考。 本發明係為一種發光二極體，特別是一種可改善光萃 取的新的發光二極體結構。 【先前技術】 發光二極體（Light Emitting Diode, LED)是一個 要的固♦嗔元件類別，這類別的固態元件可以將電能轉換邊 光’、&的發光二極體提供一個主動層（active layer)， $個主動層由失在兩個相面對摻雜層的半導體材料構成。 w 偏壓（bias)施加穿過這些摻雜層時，電洞和電子这 入这個主動層，並且在它們重新結合的時候產生光。這個 ^動層所產生的光向所有的方向發射，並且光通過所有曝 露表面離開半導體晶片。 ^著半導體材料的改良，半導體元件的效率也跟著獲 3 201248919 得改善。新的發光二極體由例如氮化鋁銦鎵（InA1GaN)的 材料組成’可提供從紫外光（ultraviolet)到琥拍光 (amber)頻譜的有效照明。相對於傳統光源，許多這類新 的發光二極體不但能更有效率地將電能轉換成光，而且更 為可靠。隨著發光二極體的改良，預期它們將在許多的應 用中取代傳統的光源。這些應用包括例如交通號誌，戶外 或室内顯示器’汽車頭燈及尾燈，傳統的室内照明等等。 傳統發光二極體的效率受限於它們無法將所有在主動 層產生的光給發射出來。當發光二極體被通電時，從主動 層朝所有方向發出的光，以許多不同的角度抵達發射表 面。相對於環境空氣（n=l. 0)或是包覆的環氧樹脂（n« 1.5)，典型的半導體材料具有高折射率〜2. 2-3. 8)。根 據司乃耳定律（Snell’ sLaw)，當光以相對於表面普通方 向（surface normal direction)’在一定的臨界角度内， 從具有高折射率的區域到具有低折射率的區域時，光將穿 過較低折射率區域。超過臨界角度的光將不會穿過，而將 發生全反射。在發光二極體的情況中，全反射的光將繼續 在發光二極體中反射，直到被吸收為止。由於這樣的現象， 許多傳統發光二極體產生的光並沒有發射出來，因而降低 了其效能。 其中一種減少全反射光比例的方式是集中在發光二極 體表面以隨機，紋理（random texturing)的形式，製造光 散射（light scattering)。這種隨機紋理在表面形成圖案， 是在反應式離子银刻（reactive ion etching)中，透過 使用次微米（sub micron)直徑的聚苯乙稀（p〇iyStyrene) 4 201248919 球體在發光二極體表面作為遮罩（mask)而達成。有這樣 紋理的表面具有跟光波長等級（order)的特性，且根據隨 機干擾效應（random interference effect)，以非司乃爾 定律預測的方式對光進行折射跟反射。這樣的做法已經被 發現能夠改良發射效率達到9%至30%。 根據美國專利號碼6,821，804所討論的，表面紋理的 其中一個缺點是阻礙了發光二極體中電流的有效傳遞。對 於具有紋理的電極層（electrode layer )，例如p型氮化 鎵（p-typeGaN)，其具有較差的導電性。對於比較小的元 件或是具有比較良好導電性的元件來說，來自p型跟η型 層接點的電流將傳遞到相對應層。對於比較大的元件或是 比較差導電性材料組成的元件，電流將無法從接點傳遞通 過這些層。這樣的結果將會造成，一部分的主動層將無法 接收到電流’並且將不會發射光。為了讓電流均勻地注入 離子區域，由具有導電性質材料構成的傳遞層（spreading layer)可以被設置在表面。然而，這樣的傳遞層常常需要 是光學透明的（optically transparent)，以便讓光能夠 穿過該層。當隨機表面結構被導入在發光二極體的表面 時，無法輕易沉積有效薄的並且光學透明的電流傳遞物 (current spreader)。 另外 •種從發光二極體增加光萃取（Hght extract ion)的方法是，在發射表面或内部介面（i&打⑽丄 in—)導入週期的圖案（peri〇dical _^η)，將 光從被陷在内部的角度，重新導向到由該表_ 期決定而定義出的模式（m〇de)。這樣的做法可以 ° >可田科 201248919 雷姆（Krames)等人的美國專利號碼5,779, 924的專利。 這樣的技巧是隨機紋理表面的一個特殊例子，只是這樣的 做法中’干擾的效果將不再隨機，並且這樣的表面會將光 搞合到特定的模式或是方向。這種做法的其中一個缺點 是’這樣的結構不容易被製造出來，因為這樣的表面形狀 跟圖案必須一致並且小到跟發光二極體單一波長等級。這 樣的圖案也會跟上面所討論的情況相同，在沉積光學透明 的電流傳遞層時具有一定的難度。 為了增加光萃取，也有一種做法是在發射層的中央將 發光二極體的發射表面形狀設計成半球型。雖然這樣的結 構能增加發射光的數量，組裝上卻同時也是困難地。在西 佛瑞斯（Scifres)跟伯漢（Burnham)的美國專利號碼 3, 954, 534中，有介紹在每個發光二極體的上方設置相對 半球體，以構成發光二極體陣列的方法。這些半球體在基 底（substrate)上形成，並且在它們上方長出一個二極體 陣列（diode array)。這種方法的其中一個缺點是，這樣 做會局限在基底界面（substrate interface)形成結構， 並且這個結構的上移（lift off)將會導致製造成本的增 加。此外，每個半球體具有一個發射層直接在其上方，這 樣也需要精密準確的製造能力。 美國專利號碼5,431,766揭露了一種在沒有水與氧氣 下的矽（Si)的光電化學（Photo_electrochemical)氧化 及溶解。在無水氫氟一氰甲烷（HF_acetonitrile，MeCN) 溶液中，儀刻率與光電流跟最高達至少600mW/cm2的光強度 直接成比例，而產出了每分鐘4微米（microns/min)的空 201248919 間選擇性蝕刻率。由於電子從高能反應中間物 (intermediates)注入，每矽分子中發生四個電子交換的 反應’伴隨者超過3.3的量子產率（quantum yield)。 美國專利號碼5, 793, 062揭露了一種結構，以改良從 發光二極體進行光萃取（light extraction)。這種結構包 括了光學不可吸收層，以重新將光從接點（contact)之類 的吸收區域導向離開’並且也將光導向發光二極體的表 面。這個結構的一個缺點是’非吸收層需要形成直角度下 切層（undercut strait angle layers)，而這樣的下切層 在許多材料系統中都是難以製造的。 美國專利號碼6, 744, 071揭露了具有相對端點結構 (opposed terminal structure)的氮化物半導體元件， 其端點彼此相對。此氮化物半導體元件包括了在支持基底 (supporting substrate)上按次排列的導電層、第一端 點、具有發光層的氮化物半導體以及第二端點。該第一端 點及第一絕緣保護層設置於該導電層與該氮化物半導體的 第一導電類型氮化物半導體層之間。 美國專利號碼6,821,804揭露了發光二極體，在這個 發光二極體上或在其中設置了光萃取結構，以改良效能。 Μ的光萃取結構提供了表面’用以將光反射、折射或散射 到能夠使光更適合於脫離進入封骏（package)的角度。這 樣的結構可以是光萃取元件或是分散層（仏印酿 layer)的陣列。這些光萃取元件可， 並且安置在不同的位置，以增加相對於傳統發光二極體更 201248919 高的發光二極體效能。這些分散層提供了光的散射中心， 並且也可以被安置在許多的位置。 進一步在美國專利6, 821,804討論的另一種改良光萃 取的方法中’在發光二極體發射表面上的薄膜金屬層裡， 光子（photon)被耦合（couple)進入表面等離子體模式 (surface plasmon mode )，然後再被射回轄射模式 (radiated mode)。這些結構依靠從半導體射出的光子柄 合到金屬層的表面等離子體，然後進一步耦合到最後萃取 出的光子。由於這個週期性的結構是具有淺溝槽深度（小 於0.1_)的一維刻劃光栅，這類元件的缺點還包括製造 上的困難。此外’整體外部量子效率（Quantum Efficiency) 也是低的（1· 4-1. 5%) ’這可能是因為光子到表面等離子體 (surface plasmon)以及表面等離子體到環境光子轉換機 制的低效率所造成。這個結構也存在著如上所述，電流傳 遞層所會發生的相同困難。光萃取可以透過設定發光二極 體晶片側表面的角度’以形成一個倒立的切割金字塔，進 而達到改善。設定角度的表面對於被陷在基底材料内的全 反射光，提供了一個射出的表面。使用這樣的方法，根據 顯示結果’外部量子效率在氮化鋁銦鎵材料系統可以提升 35%到50%。這樣的方法對於明顯比例的光被陷在基底的元 件是有用的。對於在藍寶石（sapphire)基底上長成的氮 化鎵元件，由於許多的光被陷在氮化鎵薄膜，使得設定發 光二極體晶片的侧面角度並不能帶來所想要的改善效果。 另外還有一種改良光萃取的方法是光子回收（ph〇t〇n recycling)。這個方法依靠具有高效率主動層的發光二極 201248919 體，可以容易的將電子跟電洞轉換成光，且反向亦同。全 反射光反射離開發光二極體的表面並且打到該主動層，在 該主動層轉換回電子電洞對（electron-hole pair)。由於 該主動層的高效率，電子電洞對幾乎立刻重新轉換為光， 並且再一次以隨機方向進行發射。一定比例的回收光將在 臨界角度内打到發光二極體的發射表面，並且脫離。發射 回到主動層的光，則會再經歷一次相同的流程。 【發明内容】 本發明揭露組裝半導體發光二極體元件的系統與方 法，其透過在發光二極體元件上形成η型氮化鎵（n-GaN) 層來改良從發光二極體元件内部進行光萃取的效能。 上述系統的實作，可包括一個或多個下列的内容。發 光二極體晶圓的η型氮化鎵層透過光電化學 (photo-electrochemical)氧化跟蝕刻的流程進行粗糙化 (rough.en)。發光二極體的晶圓包括例如銅，鎢，鉬等導 電基底（conductive substrate);—個或多個外延層 (epitaxial layer);—個或多個歐姆接點（〇hmic contact)以及反射金屬層（reflective metal layer)介 於該外延層與該導電基底（例如鎳，金，鉑，鉻，鈦，鈀 以及銀）之間；在自由站立發光二極體（free standing LED) 側壁，例如二氧化矽、四氮化三矽或氮氧化矽的保護層； 以及在η型氮化鎵層上的η-型電極。光電化學氧化與蝕刻流 程可以在水性溶液的系統、一個照明系統以及一個電力偏 壓（electrical bias)系統中進行。此水性溶液可以是氧 9 201248919 化劑（oxidizing agent)，並且可以是酸性或鹼性溶液。 氧化劑可以疋過氧化氮（H2〇2)、過硫酸钟（K2S2〇8) —個 或多個在其他成分中的組合。酸性溶液可以是硫酸、氫氟 酸、鹽酸.、磷酸、硝酸及醋酸中一個或多個的組合。鹼性 溶液可以是例如氫氧化鉀、氫氧化鈉、氨水中一個或多個 的混合。照明可以藉由具有波長從可見光到紫外線頻譜的 汞或氙的弧光燈（arc lamp)系統來達成。照明可以曝露 在η-型三型氮化物半導體上，以強度每平方公分小於2〇〇 毫瓦的方式進行。電力偏壓可以施加在導電基底，並且電 壓控制在-10到+ 10伏特。氧化主導 (oxidation-dominant )、姓刻主導（etching-dominant)， 或其相結合的反應，可以透過改變水溶液的成分、電力變 壓以及照明的強度來進行控制，以達到η型氮化鎵表面的粗 糙度的最佳化。在粗糙化流程之後，無秩序的紋理形態 (non-ordered textured morphology)也被揭示。 粗縫化流程可以施加在晶圓級η型氮化鎵上垂直發光 二極體（up vertical LED)曝露出的η型氮化鎵上。在基 於氮化鎵的發光二極體外延層薄膜傳到導電基底後，就在η 型氮化鎵層上形成η型電極（例如鉻/鎳）。η型金屬塾（metal pad)不止作為歐姆接點（ohmic contact)，也作為後續 粗糙化流程的遮罩（mask)。透過光電化學 (photo-electrochemical, PEC)進行的粗糙化流程，是 在η型電極（n-electrode)金屬化之後進行的。在照明下 以及導電基底被電力偏壓下’晶圓被浸泡在水性溶液中。 水性溶液是氧化劑以及酸性或驗性溶質的組合。n型氣化録 201248919 的粗糙化表面將露出無序紋理形態，其並不像金字塔、錐 形或半全面（semi-rounded)的形態。藉由改變溶液組成、 偏壓以及照明強度，粗糙機制可以透過氧化主導或蝕刻主 導反應來控.制。表面均方根（RMS)粗糙度控制在〇 〇5um 到2個次微米（submicron)。粗糙化的表面尺寸（surface dimension)可以選擇大約1/2又，以最適合進行散光。在 另外的實施例中’粗糙表面的有效折射率大約在2. 〇〜2. 5。 粗糖化表面包括下述一個或多個優點。粗縫化的表面 是在氮化鎵的表面創造了一個有效的粗糙表面，以從内部 萃取出更多的光。相對於平面的發光二極體，具有無序紋 理表面的發光二極體，光的萃取可以達到兩倍以上的改良。 這樣的發光二極體可以在相同的晶片尺寸/電源消耗 比例下提供更多的光。或者，替代的做法也可以將發光二 極體做的更小，而仍然能夠滿足相同的光輸出要求，並且 因為較小的尺寸會消耗更少的能量以及實際面積（real estitate) ’因而能夠帶來更多的節省。發光二極體可以用 標準流程的方式進行組裝，這使得這樣發光二極體相對於 傳統的發光二極體，具有很高的成本競爭優勢。 本發明的一個實施例是一種方法。這個方法一般包括 提供發光二極體晶圓組合（wafer assembly)，將遮罩 (mask)加在η型摻雜層的表面，在η型掺雜層的表面進行 蝕刻，使得蝕刻坑（pit)在表面形成，移除遮罩，並且對 於包括蝕刻坑的η型摻雜層進行粗糙化或紋理化的處理。發 光二極體晶圓組合通常包括導電基底、位在導電基底上的ρ 11 201248919 型摻雜層、位在P型摻雜層上的主動層以及位在主動層上的 η型摻雜層。 本發明的另一個實施例是一種方法。這個方法一般包 括在發光二極體晶圓的表面上加遮罩，蝕刻發光二極體晶 圓的表面，使得蝕刻坑在表面形成，移除遮罩，以及在包 含了钱刻坑的發光二極體晶圓表面進行粗糙化或紋理化的 處理。 本發明的另一個實施例是一種方法。這個方法一般來 說包括提供發光二極體晶圓組合，次發光二極體晶圓組合 具有複數個發光二極體堆疊（stack)位在導電基底上（每 個發光二極體堆疊一般包括了一p型摻雜層位在導電基底 上，一用來發光的主動層位在p型摻雜層上，一n型摻雜層 位在主動層上）；在各發光二極體堆疊加一保護層覆蓋11 型#雜層表面的選擇部分（selected portion);透過粗縫 化與紋理化至少一個處理，來改變11型摻雜層的表面，其中 所述保護層在改變過程保護了每一個發光二極體堆疊的選 擇部分；以及移除保護層。 本發明的另一個實施例是一種方法。這個方法一般來 說包括了提供發光一極體晶圓組合，其包括了複數個發光 二極體堆疊被設置在一個導電基底上（每個發光二極體堆 疊典型包括被設在導電基底上的P型摻雜層，一主動層設置 在P型摻雜層上用來發光’以及一η型摻雜層設置在主動層 上）；各發光二極體晶圓施加一保護層來覆蓋η型摻雜層的 選擇部分；將具有保護層的π型摻雜層的表面浸泡在電解溶 液（electrolytic solution)中；在導電基底施加偏壓電VJ VI. Description of the Invention: [Technical Field of the Invention] This application is a division of the US Patent Application No. 11/956, 962 filed on Dec. 14, 2007, the former also being March 23, 2007. Partial continuation (CIP) of Application No. 11/690, 443 (now Patent No. 7, 524, 686), the former being Case No. 11/618,468 of December 29, 2006 (currently Partial continuation of Patent No. 7, 563, 625, (CIP) 'The former is part of the ii/〇32,880 application (currently Patent No. 7, 186, 580) filed on January 11, 2005. The continuation case (CIP), all of which is incorporated herein by reference. The present invention is a light-emitting diode, and more particularly a novel light-emitting diode structure which improves light extraction. [Prior Art] Light Emitting Diode (LED) is a type of solid-state component, and this type of solid-state component can provide an active layer for the light-emitting diode of the electric energy conversion edge lighter, & Active layer), the active layer consists of a semiconductor material that is lost in two facing doped layers. When bias is applied across these doped layers, holes and electrons enter the active layer and produce light when they recombine. The light generated by this layer is emitted in all directions and the light exits the semiconductor wafer through all exposed surfaces. With the improvement of semiconductor materials, the efficiency of semiconductor components has also improved with the acquisition of 201248919. The new light-emitting diode consists of a material such as aluminum indium gallium nitride (InA1GaN), which provides efficient illumination from the ultraviolet to the amber spectrum. Many of these new LEDs are more efficient at converting electrical energy into light than traditional light sources, and are more reliable. With the improvement of light-emitting diodes, it is expected that they will replace conventional light sources in many applications. These applications include, for example, traffic signs, outdoor or indoor displays, automotive headlights and taillights, traditional indoor lighting, and the like. The efficiency of conventional light-emitting diodes is limited by the inability to emit all of the light generated in the active layer. When the light-emitting diode is energized, light emitted from the active layer in all directions reaches the emission surface at many different angles. 8)。 The typical semiconductor material has a high refractive index ~ 2. 2-3. 8). According to Snell's Law, when light is within a certain critical angle with respect to the surface normal direction, from a region with a high refractive index to a region with a low refractive index, the light will Pass through the lower refractive index region. Light above the critical angle will not pass through and total reflection will occur. In the case of a light-emitting diode, the totally reflected light will continue to be reflected in the light-emitting diode until it is absorbed. Due to such a phenomenon, the light generated by many conventional light-emitting diodes is not emitted, thereby reducing its efficiency. One way to reduce the proportion of total reflected light is to focus on the surface of the light-emitting diode to produce light scattering in the form of random texturing. This random texture is patterned on the surface in a reactive ion etching process using a submicron diameter polystyrene (P〇iyStyrene) 4 201248919 sphere in a light-emitting diode The surface is achieved as a mask. A surface having such a texture has a characteristic of a light wavelength order, and refracts and reflects light in a manner predicted by non-Sinell's law according to a random interference effect. Such practices have been found to improve emission efficiency by 9% to 30%. One of the disadvantages of surface texture is that it hinders the efficient transfer of current in the light-emitting diode, as discussed in U.S. Patent No. 6,821,804. For textured electrode layers, such as p-type gallium nitride (p-type GaN), it has poor conductivity. For relatively small components or components with better conductivity, the current from the p-type and n-type layer contacts will be transferred to the corresponding layer. For larger components or components with poorer conductivity materials, current will not pass through the layers from the contacts. The result of this will be that some of the active layers will not be able to receive current 'and will not emit light. In order to uniformly inject a current into the ion region, a spreading layer composed of a material having a conductive property may be disposed on the surface. However, such transfer layers often need to be optically transparent to allow light to pass through the layer. When a random surface structure is introduced on the surface of the light-emitting diode, an effective thin and optically transparent current spreader cannot be easily deposited. In addition, a method of increasing the Hght extract ion from the light-emitting diode is to introduce a periodic pattern (peri〇dical _^η) on the emitting surface or the internal interface (i& (10) 丄in-) From the perspective of being trapped inside, it is redirected to the mode defined by the table _ period (m〇de). Such an approach can be patented by U.S. Patent No. 5,779,924 to Krames et al. Such a technique is a special case of a random texture surface, except that the effect of the 'interference' will no longer be random, and such a surface will align the light to a particular pattern or direction. One of the disadvantages of this approach is that such a structure is not easily fabricated because such a surface shape must conform to the pattern and be as small as the single wavelength level of the light-emitting diode. Such a pattern would be the same as discussed above, with some difficulty in depositing an optically transparent current transfer layer. In order to increase the light extraction, it is also possible to design the emission surface shape of the light-emitting diode into a hemispherical shape in the center of the emission layer. Although such a structure can increase the amount of emitted light, it is also difficult to assemble. In U.S. Patent No. 3,954,534, the disclosure of the entire disclosure of the entire disclosure of the disclosure of the disclosure of the disclosure of the entire disclosure of the entire disclosure of the disclosure of the disclosure of . These hemispheres are formed on a substrate and a diode array is grown over them. One of the disadvantages of this approach is that this is limited to the formation of a structure at the substrate interface, and the lift off of this structure will result in an increase in manufacturing costs. In addition, each hemisphere has an emissive layer directly above it, which also requires precise and accurate manufacturing capabilities. U.S. Patent No. 5,431,766 discloses photoelectrochemical oxidation and dissolution of bismuth (Si) in the absence of water and oxygen. In an anhydrous HF-acetonitrile (MeCN) solution, the illuminance and photocurrent are directly proportional to the light intensity of up to at least 600 mW/cm2, resulting in an empty space of 4 micrometers per minute (microns/min). Selective etch rate between 201248919. Since electrons are injected from high-energy reaction intermediates, a four-electron exchange reaction occurs in each molecule, accompanied by a quantum yield of more than 3.3. U.S. Patent No. 5,793,062 discloses a structure for improving light extraction from a light-emitting diode. Such a structure includes an optically non-absorbable layer to redirect light away from the absorbing region, such as a contact, and also directs light to the surface of the light-emitting diode. One disadvantage of this structure is that the 'non-absorbent layer needs to form undercut strait angle layers, and such undercut layers are difficult to manufacture in many material systems. U.S. Patent No. 6,744,071 discloses a nitride semiconductor device having an opposite terminal structure, the ends of which are opposite each other. The nitride semiconductor device includes a conductive layer sequentially arranged on a supporting substrate, a first end point, a nitride semiconductor having a light emitting layer, and a second end point. The first end point and the first insulating protective layer are disposed between the conductive layer and the first conductive type nitride semiconductor layer of the nitride semiconductor. U.S. Patent No. 6,821,804 discloses a light-emitting diode on or in which a light extraction structure is provided to improve performance. The chirped light extraction structure provides a surface' to reflect, refract or scatter light to an angle that would make the light more suitable for detachment into the package. Such a structure may be an array of light extraction elements or a dispersion layer. These light extraction elements are, and can be placed in, different locations to increase the efficiency of the LEDs that are higher than the conventional LEDs 201248919. These dispersion layers provide a scattering center for light and can also be placed in a number of locations. In another method of improving light extraction discussed in U.S. Patent No. 6,821,804, in the thin film metal layer on the emitting surface of the light emitting diode, photons are coupled into a surface plasmon mode. ), and then shot back to the radiated mode. These structures rely on the photons from the semiconductor to the surface plasmons of the metal layer and then further couple to the last extracted photons. Since this periodic structure is a one-dimensional scribed grating having a shallow trench depth (less than 0.1 Å), the disadvantages of such components include manufacturing difficulties. In addition, 'the overall external quantum efficiency (Quantum Efficiency) is also low (1·4-1. 5%) 'This may be due to the low efficiency of photon to surface plasmon and surface plasmon to ambient photon conversion mechanism. Caused. This structure also has the same difficulties that occur in the current transfer layer as described above. The light extraction can be improved by setting the angle ' of the side surface of the light-emitting diode wafer' to form an inverted cutting pyramid. The angled surface provides an exit surface for the totally reflected light trapped within the substrate material. Using such a method, the external quantum efficiency can be increased by 35% to 50% in the aluminum indium gallium nitride material system according to the display result. Such an approach is useful for a significant proportion of the light trapped in the substrate. For a gallium nitride element grown on a sapphire substrate, since a large amount of light is trapped in the gallium nitride film, setting the side angle of the light-emitting diode wafer does not bring about the desired improvement effect. Another method of improving light extraction is photon recovery (ph〇t〇n recycling). This method relies on a light-emitting diode 201248919 body with a high-efficiency active layer, which can easily convert electrons and holes into light, and the reverse direction is also the same. The totally reflected light is reflected off the surface of the light-emitting diode and hits the active layer where it is switched back to the electron-hole pair. Due to the high efficiency of the active layer, the electron hole pair is re-converted to light almost immediately and again in a random direction. A certain proportion of the recovered light will hit the emitting surface of the light-emitting diode within a critical angle and will detach. Emissions Back to the active layer of light, the same process will be experienced again. SUMMARY OF THE INVENTION The present invention discloses a system and method for assembling a semiconductor light emitting diode device, which is improved from the inside of a light emitting diode device by forming an n-type gallium nitride (n-GaN) layer on the light emitting diode device. The efficiency of light extraction. The implementation of the above system may include one or more of the following. The n-type gallium nitride layer of the light-emitting diode wafer is roughened by a photo-electrochemical oxidation and etching process. The wafer of the light emitting diode includes a conductive substrate such as copper, tungsten, molybdenum, etc.; one or more epitaxial layers; one or more ohmic contacts and reflective metal a reflective metal layer between the epitaxial layer and the conductive substrate (eg, nickel, gold, platinum, chromium, titanium, palladium, and silver); on the free standing LED side wall, such as two a protective layer of ruthenium oxide, tetraruthenium hydride or ruthenium oxynitride; and an η-type electrode on the n-type gallium nitride layer. The photoelectrochemical oxidation and etching process can be carried out in an aqueous solution system, an illumination system, and an electrical bias system. This aqueous solution may be an oxygen 9 201248919 oxidizing agent and may be an acidic or alkaline solution. The oxidizing agent may be a combination of nitrogen oxide (H2〇2), persulfate clock (K2S2〇8), or a combination of other components. The acidic solution may be a combination of one or more of sulfuric acid, hydrofluoric acid, hydrochloric acid, phosphoric acid, nitric acid, and acetic acid. The alkaline solution may be, for example, a mixture of one or more of potassium hydroxide, sodium hydroxide, and ammonia. Illumination can be achieved by an arc lamp system with mercury or helium having a wavelength from visible to ultraviolet. The illumination can be exposed to the η-type tri-type nitride semiconductor in a manner that the intensity is less than 2 毫 milliwatts per square centimeter. The power bias can be applied to the conductive substrate and the voltage is controlled between -10 and +10 volts. Oxidation-dominant, etching-dominant, or a combination of reactions can be controlled by varying the composition of the aqueous solution, the power transformation, and the intensity of the illumination to achieve an n-type gallium nitride surface. The optimization of the roughness. After the roughening process, a non-ordered textured morphology is also revealed. The roughing process can be applied to the n-type gallium nitride exposed on the wafer-level n-type gallium nitride on the vertical vertical LED. After the gallium nitride-based light-emitting diode epitaxial film is transferred to the conductive substrate, an n-type electrode (e.g., chromium/nickel) is formed on the n-type gallium nitride layer. The n-type metal pad acts not only as an ohmic contact but also as a mask for the subsequent roughening process. The roughening process by photo-electrochemical (PEC) is carried out after the n-electrode metallization. The wafer is immersed in an aqueous solution under illumination and under the electrical bias of the conductive substrate. The aqueous solution is a combination of an oxidizing agent and an acidic or a test solute. The roughened surface of the n-type gasification record 201248919 will reveal a disordered texture morphology that is not like a pyramid, cone or semi-rounded morphology. By varying the composition of the solution, the bias voltage, and the intensity of the illumination, the roughness mechanism can be controlled by oxidation-dominated or etched-lead reactions. The surface root mean square (RMS) roughness is controlled from 5 um to 2 submicron. The roughened surface dimension can be chosen to be approximately 1/2 again to best suit astigmatism. 5。 The effective refractive index of the rough surface is about 2. 〇 ~ 2. 5. The coarsely saccharified surface includes one or more of the following advantages. The roughened surface creates an effective rough surface on the surface of the gallium nitride to extract more light from the interior. Compared to planar light-emitting diodes, light-emitting diodes with disordered textured surfaces can achieve more than twice the improvement in light extraction. Such a light-emitting diode can provide more light at the same wafer size/power consumption ratio. Alternatively, alternatives can also make the LEDs smaller, while still meeting the same light output requirements, and because smaller sizes consume less energy and real estitate' Come for more savings. The light-emitting diodes can be assembled in a standard process, which makes such light-emitting diodes have a high cost competitive advantage over conventional light-emitting diodes. One embodiment of the invention is a method. The method generally includes providing a light emitting diode wafer assembly, applying a mask to the surface of the n-type doped layer, and etching the surface of the n-type doped layer to make an etch pit Formed on the surface, the mask is removed, and the n-type doped layer including the etch pit is roughened or textured. The luminescent diode wafer combination typically includes a conductive substrate, a ρ 11 201248919 type doped layer on the conductive substrate, an active layer on the P-type doped layer, and an n-type doped layer on the active layer. Another embodiment of the invention is a method. The method generally includes masking a surface of the light emitting diode wafer, etching a surface of the light emitting diode wafer, forming an etching pit on the surface, removing the mask, and emitting light in the pit containing the money. The surface of the polar wafer is roughened or textured. Another embodiment of the invention is a method. The method generally includes providing a light emitting diode wafer combination, the secondary light emitting diode wafer combination having a plurality of light emitting diode stacks on the conductive substrate (each of the light emitting diode stacks generally includes A p-type doped layer is on the conductive substrate, an active layer for emitting light is on the p-type doped layer, and an n-type doped layer is on the active layer; and one is added to each of the light-emitting diode stacks The protective layer covers a selected portion of the surface of the type 11 impurity layer; the surface of the 11-type doped layer is changed by roughing and texturing at least one process, wherein the protective layer protects each of the layers during the changing process a selected portion of the stack of light emitting diodes; and removing the protective layer. Another embodiment of the invention is a method. The method generally includes providing a light-emitting one-pole wafer assembly including a plurality of light-emitting diode stacks disposed on a conductive substrate (each of the light-emitting diode stacks typically including a conductive substrate) a P-type doped layer, an active layer disposed on the P-type doped layer for emitting light and an n-type doped layer disposed on the active layer; each of the light emitting diode wafers applying a protective layer to cover the n-type a selected portion of the doped layer; immersing the surface of the π-type doped layer having the protective layer in an electrolytic solution; applying a bias voltage to the conductive substrate
S 12 201248919 力；並且照射η型摻雜層的表面，使得發生光電化學氧化與 蝕刻，因而對η型摻雜層的表面進行粗糙化。其中，保護層 在照射的過程中，保護了每一個發光二極體晶圓堆疊的的 選擇部分。 本發明的另一個實施例是一種方法。這個方法一般來 說包括了提供發光二極體晶圓組合’其包括了複數發光二 極體晶粒（die);以及對此複數發光二極體晶粒的每—個 的發光表面所需要的部分進行改變，此係透過選擇性地進 行粗糙化及紋理化中至少一個處理，且其中各晶粒具有一 保留部分未進行改變。 本發明的另一個實施例是一種方法。這個方法一般來 說’包括提供發光二極體晶圓組合，在η型摻雜層的表面施 加遮罩’餘刻η型摻雜層的表面，使得突起（protuberances) 仍然保留在蝕刻的表面，其中突起的側表面形成相對於n 型摻雜層超過90度的角度；移除遮罩；以及對於包括突起 的η型摻雜層的姓刻表面進行粗糖化或紋理化的處理。此發 光二極體晶圓組合一般包括導電基底；被設置於導電基底 上的Ρ型摻雜層；被設置於ρ型摻雜層上的主動層；以及被 設置於主動層上的η型摻雜層。 本發明的另一個實施例是一種方法。這個方法一般來 說，括，在發光二極體晶圓表面施加遮罩；對此發光二極 曰圓表面進行蝕刻，使得突起保持在蝕刻表面，其中突 ^的側表面相對Μη型摻雜層的蝕刻表面，形成具有超過9丨 :角度；移除遮罩；以及對於帶有突起的發光二極體晶 圓餘刻表面進行粗糙化或紋理化。 13 201248919 本發明的另一個實施例提供了 一種發光二極體的結 構。此種發光二極體的結構一般包括一多層半導體結構用 來發光，此結構的表面具有複數突起，其中這些突起的側 表面相對於此多層半導體結構的表面，形成了超過90度的 角度。此結構的表面以及這1犬起被粗縫化或紋理化以增 加表面積。 【實施方式】 圖1顯示一個系統範例，用來進行光電化學 (photo-electrochemical，PEC)氧化跟蝕刻的處理。電 解液的特性是格外重要’尤其是要確保高速蝕刻率跟確保 蝕刻率可以跟光強度成比例。光電化學蝕刻處理是透過圖1 所示的系統進行的。在這個系統中’光由光源投射到發光 二極體晶圓的表面，該發光二極體晶圓安置在載座 (holder) 10上’且由鉗子12固定住，並跟電解液16保持 接觸。光強度可以選擇性改變，以選擇性改變蝕刻率這 個單元（cell)可以有多種不同的幾何設定（ge〇metric configuration) ’並且可以用任何—種材料，只要適合承 載發光二極體晶圓以及含有具有離子的電解液即可。這個 單元的特定設定可以最佳化，以進行大批量的工業應用。 參考電極14(例如白金電賴）穿過單㈣主體延伸^電解 ㈣。參考電極Η建立參考電·_並且經常由金屬線所 形成，例如白金或銀線。為了方便起見，可Μ氯化亞采 (WD電極（SCE)，或從任何其他的電極機制而形 201248919 發生在單元裡頭的電化學反應是由一個電化學檢測儀 (potentiostat)提供電力及監測，這是熟悉該項技藝者 所周知的。電化學檢測儀包含電流偵測器，以串聯方式跟 來源電壓（source voltage)連接，以施加電動勢 (potential)穿過電極，並且包含〆個連接’可以將電化 學檢測儀跟半導體晶圓相連接。這樣的連接可以透過任何 的钻結（bonding)方式固定到半導體晶圓。 在圖1所示系統中進行光電化學蝕刻處理時，半導體晶 圓成為氧化還原的一部分。半導體晶圓可以作為陽極 (anode) ’並且反電極（counter-electrode)可以作為 陰極（cathode)。電動勢被施加在晶圓上。參考電極14 是用在製程中’以量測跟監控電動勢。蝕刻的發生，來自 於在半導體晶圓跟電解液16界面，光產生洞 (photogenerated hole)的分解反應。 圖2A顯示具有金屬遮罩的第一樣本，在不同時間，進 行氧化主導（oxidation-dominant)條件下的表面剖面示 意圖。這個樣本晶圓包括基底（substrate) 3〇，氮化錄薄 膜32，以及具有粗糙化表面的金屬遮罩34。具有金屬遮罩 的樣本的表面剖面示意圖中，圖2B顯示的是氧化主導條件 200秒，圖2C顯示的是400秒，而圖2D顯示的是6〇〇秒。 圖3例示具有金屬遮罩的第二樣本的表面剖面，經由蝕 刻主導（etching dominant)條件，在不同時間下的示意 圖。樣本晶圓包括基底30,氮化鎵薄膜32,以及具有粗經 化表面的金屬遮罩34。圖3B例示在氧化主導條件下2〇〇秒且 15 201248919 有金屬遮罩樣本的表面剖面示意圖’圖3C為400秒，而圖3D 為600秒。 圖4例示垂直發光二極體晶圓（vertical-LEDwafer)。 發光二極體上示例的η型氮化鎵之多層外延層結構，顯示位 在金屬基底70上，其在本實施例可以是厚銅層。在金屬基 底70上形成的多層外延層結構包括η型氮化鎵基礎層8〇， MQW主動層78’以及反射/接觸層（reflector/contact layer) 74。η型氮化鎵基礎層80具有例如4微米 (micron) 的厚度。 多層外延層可以藉由設置η型氮化鎵部分（例如n型氮 化鎵層80)在載體基底（carrier substrate)(未圖示） 上而形成，沉積主動層（例如MQW主動層78)在η型氮化鎵 部分上，並且沉積ρ型氮化鎵部分（例如ρ型氮化鎵層76) 在主動層上，沉積第一個或多個金屬層（例如反射/接觸層 74)，運用遮罩層（未圖示），並且蝕刻金屬、ρ型氮化鎵 層、主動層以及η型氮化鎵層。遮罩接著被移除，沉積隔離 層（passivation layer)(例如層84)，並且隔離層在ρ 型氮化鎵上的一部分被移除，以曝露出該第一個或多個金 屬層。可沉積第二個或多個金屬層（例如詹72)，沉積金 屬基底（例如金屬基底70)，載體基底（未圖示）被移除 以曝露出η型氮化鎵部分，並且η型氮化鎵部分被粗糙化。 MQW主動層78可以是氮化銦鎵/氮化鎵MQW主動層。一旦 電力能源被灌入η型氮化鎵基礎層80以及接觸層74之間， MQW主動層78可以被激化，並且因此產生光。產出的光可以 有250nm到600nm的波長。ρ型層76可以是p+S氮化鎵基礎 201248919 層’例如P+型氮化鎵’ p+型氮化銦 + 並且其厚度可以在0.05〜〇 5微平。鋁銦鎵層’ U.b微水圖5顯不垂直發光二極體 行粗糙化的橫切剖面圖。如圖5跟圖6所示，盖： 紋理形態在η型氮化鎵表面形成。 圖5顯示的是，圖4的發光二極體金屬層上粗 =1面圖，而圖6顯示粗糙化表面的掃描電子顯微鏡 (SEM)的衫像示意圖。表面的變化有效地粗糙化了表面，並 且導向-個面向更好折射率的空氣的匹配。這樣 是，讓發光二極體獲得了更好的内部光萃取效果。 雖然本發明已經配合實施例進行相當詳細的描述 他的做法健是可行.在另—替代實施财，氮化錄層 的表面可使用球/球體（ball/sphere)或濕式/乾式钱 術來進行粗糙化的處理。熟悉該項技術的人所了解者，亦 可使用其他使用光萃取元件陣列（LEEarray)的發光二極 體的設計。新的發光二極體可以有不同的光萃取元件 (light extracting element)陣列的組合且可有散光層 (disperser layer)。光萃取元件可以有不同的形狀、^ 寸以及在相鄰光萃取元件間的空間，並且可以在不同的位 置安置。相似地，散光層可以用不同的材料製作，並且可 以安置在不同的位置。因此，所附的申請專利範圍中的精 神與範圍應該不只偈限在上面說明的實施例。 另一個表面粗棱化技術的示例 根據本發明實施例用來增加發光二極體光萃取的技 術，可在發光二極體半導體晶粒被放置到晶圓或部分的晶 圓組合時加以運用。這些技術可以用在任何的發光二極體 17 201248919 晶圓或包括多個晶粒的晶圓組合，並在此提供的是以垂直 發光二極體（vertical LED)的情況作為例子。在以下的 圖示中’雖然只有顯示三個垂直發光二極體的晶粒，但是 其代表發光二極體晶圓上多個晶粒。 請參考圖8，其提供了具有複數個垂直發光二極體晶粒 700的發光二極體晶圓組合722以及一個導電基底718，或是 厚導電層（thick conductive layer, TCL)。垂直發光二 極體晶粒700可包括數個複合半導體外延層，這些外延層由 例如三族或五族化學元素，例如氮化鎵、氮化鋁、氮化銦 或相似物組成。導電基底718可包含任何適合的金屬或金屬 合金’例如銅、鎳、鎳-鈷、銀、金、銅-銘、銅-鉬、鎮/ 銅、銅/鎳-鈷/銅、銅/鎳-鈷/銅/鎳-鈷、或鎳/銅-銦。 發光二極體晶圓組合722可以有反射層71〇設置在導電 基底718上，例如p型氮化鎵的p型摻雜層7〇8設置在反射層 710上，用來發光的主動層706設置在p型摻雜層708上，以 及例如η型氮化鎵的η型摻雜層704設置在主動層7〇6上。在 某些實施例中，可以省略反射層710。舉例來說，在某些實 施例中，可用隔離層712位在垂直發光二極體之間，以在晶 粒分離時保護垂直發光二極體的晶粒。 在這個階段，表面720可以是實質上平坦，並且在從上 面或側面看發光二極體晶圓組合722時，在η型摻雜層7〇4， 不會有太多的表面變化。雖然有些從主動層7〇6射出的光 724在這個處理階段可以從η型摻雜層的表面72〇發射，但這 些抵達表面720的光724假如超過了臨界角度，根據司乃爾 201248919 定律，將不太可能穿過，並且將會發生全反射。進一步的 處理將能帶來比較好的結果β 因此，如圖8所示，遮罩726可以用在η型摻雜層7〇4的 表面720，並且表面720可以接著進行蝕刻以改良〇型摻雜的 表面區域以增加垂直發光二極體晶粒7〇〇的光萃取。蝕刻可 以透過濕式蝕刻、光改良式（ph〇t〇enhanced)濕式蝕刻、 乾式蝕刻（例如導電耦合電漿/反應離子蝕刻，ICP/RIE) 或是其組合。遮罩726的組成可以是任何適合的材料，只要 硬到足夠抵擋重複的蝕刻。其材料例如鎳、二氧化矽、氡 化矽或光阻（photoresist)。遮罩726可以根據需要進行 各種圖案化’使得表面720可以被選擇性蝕刻。在一些實施 例中，舉例來說，遮罩726可以為格狀（grids) '棋盤狀 (如圖示）、蜂巢狀、三角形、矩形或其他多邊形圖案。 在一些實施例中’可以組合一個特定多邊形的不同尺寸， 或不同多邊形的不同尺寸，以對遮罩726進行圖案化。 在η型摻雜層704的表面720被蝕刻後，遮罩726可以被 移除’而留下如圖9Α所示的晶圓組合。表面720可以有若干 個钮刻坑728,其中材料被移除，而留下若干齒狀結構73〇， 以形成如一維圖不橫切面形成梳子形狀的表面。餘刻坑728 與齒狀結構730的棋盤圖案例示在圖9Α的上視圖中。由於钱 刻坑728與齒狀結構730所構成的表面區域（Β)比圖7中〇 型摻雜層704的表面區域（Α)來的大’所以這些特徵可以 改良光射出率。因此，經過這樣的處理階段，根據司乃爾 定律以及全反射定律，更多的光724可以從表面萃取出來。 201248919 對於圖9B所例示的一些實施例，η型摻雜層704可以向 幾乎全部的方向進行蝕刻，這使得蝕刻坑728的深度可以逼 近主動層，在ί至10奈米内。所產生的表面激化特徵 (surface exciting features, SEF) 732可以增加其狀態 (states)的密度及發光二極體半導體自發發射率。這些 表面激化特徵也可以導致表面激化特徵/量子井耦合的改 善。因此’光萃取可以得到進一步的改善。 對於其他使用圖8遮罩726的實施例，表面720可以透過 化學濕式蝕刻進行蝕刻。由於許多用在發光二極體組裝的 複合半導體材料（例如氮化鎵）的晶體特性，六角金字塔 結構會在圖9C所示的η型摻雜層704形成。因此，濕式蝕刻 以及六角形金字塔結構的尺寸可以被良好的控制著。 請參考_，在某些實施例中，圖8所示具有遮罩的發 ^域晶圓組合可以全雜刻穿透η型摻雜層7()4、主動 =二姓:摻Γ7°8。在這樣的情況下’將會形成微碟 =▲1 環（mie]。七ng)的垂直發光二極艘 :才：_碟、微環以及奈米柱（nanorod ΪΓΓί面相對於圖7的n型摻雜層_表_，都具有 “光因此’這些結構可以提供相較於傳統垂 發先一極體更多的光萃取。對於一4 分實施例 請參照圖10,在圖9A (或其他上述的實 跟橫切面所㈣㈣㈣_表祕可其= 20 201248919 糙化或紋理化，以增加表面積，因此，可以更增加光萃取 的量。在某些實施例中，具有圖案化蝕刻坑728的表面72〇 可以用任何適合的技術進行粗糙化，例如包括濕式蝕刻、 光改良濕式蝕刻、乾式蝕刻或上面提過的光電化學氧化與 蝕刻。在一些其他的實施例中，可透過次微米尺寸物件（例 如聚苯乙烯球體）運用在具有蝕刻坑728表面的n型摻雜層 的表面720 ’而增加η型摻雜層7〇4的表面積。 另一個表面粗糙化技術的示例 傳統表面粗縫化技術及一些這裡與上面描述的技術， 有可此導致不穩定的正向電壓（forward v〇itage，Vf)， 並且在從發光二極體晶圓組合製造出的發光二極體元件 中，造成漏電流（1 eakage current)的增加。透過只在發 光一極體晶圓組合表面的特定區域進行粗糙化，本發明的 實施例提出的技術可增加發光二極體的光萃取，同時不會 導致正向電壓的不穩定或是漏電流。再一次說明的是，這 樣的技術可以運用在任何的發光二極體晶圓或是包括多個 晶粒的晶圓組合，且垂直發光二極體晶粒只是作為範例說 明。 回到圖7，其可提供具有多個垂直發光二極體晶粒700 以及導電基底718的發光二極體晶圓組合722。發光二極體 晶圓組合722可以有反射層710設置在導電基底718上、p型 摻雜層708設置在反射層710上、用來發光的主動層706設置 在P型摻雜層708上、以及η型摻雜層704設置在主動層705 上。在一些實施例中，可以省略反射層710。在這個階段， η型摻雜層704的表面720實質上為平坦。 21 201248919 清參考圖11A ’保護層1200可以加到圖7的發光二極體 組合j22。保護層12〇〇可以是圖案化的結構，例如作為遮 罩，可以覆蓋垂直發光二極體晶粒7〇〇的邊緣以及所米口型 ，雜層704的表面720上’用來作為n電極的指定區域。在一 些實施例中’保護層可以覆蓋相鄰的垂直發光二極體晶粒 700以及介於晶粒7〇〇間的材料（例如街道區域（s计饮七 areas))。用來抵擋化學處理跟保護在下面的材料，保護 層200了以疋有機或非有機、光敏（ph〇t〇sensitive)或 非光敏，並且可以由任何適合的材料組成，例如聚合物、 聚醜亞胺（P〇lymide)、光阻（ph〇tGresist) 、環氧樹脂、 U~8、NR-7、AZ5214E、熱塑膠（therm〇plastic)、氮化 矽、二氧化矽、氧化鋅、五氧化二鈕、二氧化鈦、次氟酸 (HF0)或氧化鎂（Mg〇)。 若保護層1200被運用在發光二極體晶圓組合722，可後 續進行η型摻雜層704的表面72〇的粗糙化，以及/或如上所 描述的處理，以改良η型摻雜層的表面區域，因而增加圖11Β 所示垂直發光二極體晶粒700的光萃取。粗糙化及/或紋理 化表面720，可透過任何增加表面積的適合技巧達成，例如 濕式蝕刻、光改良濕式蝕刻、乾式蝕刻或上面提過的光電 化學氧化與蝕刻處理。保護層1200可以容許對表面720選擇 性的粗糙化以及/或紋理化，以避免正向電壓的不穩定以及 避免漏電流。 在η型摻雜層704的表面選擇被粗糖化以及/或紋理化 後，可以移除保護層1200 ’如圖lie所示。接著，η電極121〇 可以加到圖11D所示的垂直發光二極體晶粒7〇〇。由保護層S 12 201248919; and irradiating the surface of the n-type doped layer such that photoelectrochemical oxidation and etching occur, thereby roughening the surface of the n-type doped layer. Among them, the protective layer protects the selected portion of each of the LED stacks during the illumination. Another embodiment of the invention is a method. This method generally includes providing a light emitting diode wafer combination that includes a plurality of light emitting diode dies; and for each of the luminescent surfaces of the plurality of luminescent diode dies Partial changes are made by selectively performing at least one of roughening and texturing, and wherein each of the grains has a remaining portion that is not altered. Another embodiment of the invention is a method. This method generally includes 'providing a combination of light-emitting diode wafers, applying a mask on the surface of the n-type doped layer to the surface of the n-type doped layer, such that the protuberances remain on the etched surface, Wherein the side surface of the protrusion forms an angle of more than 90 degrees with respect to the n-type doped layer; the mask is removed; and the process of rough saccharification or texturing is performed on the surname surface of the n-type doped layer including the protrusion. The light emitting diode wafer assembly generally includes a conductive substrate; a Ρ-type doped layer disposed on the conductive substrate; an active layer disposed on the p-type doped layer; and an n-type doping disposed on the active layer Miscellaneous layer. Another embodiment of the invention is a method. The method generally includes applying a mask on the surface of the light-emitting diode wafer; etching the surface of the light-emitting diode to keep the protrusion on the etched surface, wherein the side surface of the protrusion is opposite to the Μ-type doped layer The etched surface is formed to have an angle of more than 9 ;; the mask is removed; and the surface of the surface of the light-emitting diode wafer with protrusions is roughened or textured. 13 201248919 Another embodiment of the present invention provides a structure of a light emitting diode. The structure of such a light-emitting diode generally comprises a multilayer semiconductor structure for emitting light, the surface of the structure having a plurality of protrusions, wherein the side surfaces of the protrusions form an angle of more than 90 degrees with respect to the surface of the multilayer semiconductor structure. The surface of this structure and the 1 dog are roughed or textured to increase the surface area. [Embodiment] Fig. 1 shows an example of a system for performing photo-electrochemical (PEC) oxidation and etching treatment. The characteristics of the electrolyte are particularly important', especially to ensure high-speed etch rates and to ensure that the etch rate can be proportional to the light intensity. Photoelectrochemical etching is performed through the system shown in Figure 1. In this system, 'light is projected by the light source onto the surface of the light-emitting diode wafer, which is placed on the holder 10' and held in place by the forceps 12 and kept in contact with the electrolyte 16. . The light intensity can be selectively changed to selectively change the etch rate. The cell can have a variety of different geo-metric configurations and can be used with any material as long as it is suitable for carrying a light-emitting diode wafer and It may contain an electrolyte having ions. The specific settings of this unit can be optimized for high volume industrial applications. The reference electrode 14 (e.g., platinum electroplating) extends through the single (four) body to electrolysis (4). The reference electrode Η establishes a reference electric _ and is often formed of a metal wire such as a platinum or silver wire. For convenience, the cesium chloride (SCE), or from any other electrode mechanism, 201248919, the electrochemical reaction occurring in the cell is powered and monitored by an electrochemical detector (potentiostat). This is well known to those skilled in the art. The electrochemical detector includes a current detector connected in series with a source voltage to apply an electromotive force through the electrode and including a connection. The electrochemical detector can be connected to the semiconductor wafer. Such a connection can be fixed to the semiconductor wafer by any bonding method. When photoelectrochemical etching is performed in the system shown in Fig. 1, the semiconductor wafer becomes Part of the redox. The semiconductor wafer can serve as an anode' and the counter-electrode can act as a cathode. The electromotive force is applied to the wafer. The reference electrode 14 is used in the process to measure And monitoring the electromotive force. The etching occurs from the interface between the semiconductor wafer and the electrolyte 16 and the photogenerated hole Figure 2A shows a first sample with a metal mask, at various times, a schematic representation of the surface profile under oxidation-dominant conditions. This sample wafer consists of a substrate 3 〇, nitrided. The film 32, and the metal mask 34 having a roughened surface. In the schematic cross-sectional view of the sample having the metal mask, FIG. 2B shows the oxidation dominant condition for 200 seconds, FIG. 2C shows 400 seconds, and FIG. 2D shows 6 sec. Figure 3 illustrates a surface profile of a second sample having a metal mask, illustrated by etching dominant conditions at different times. The sample wafer includes a substrate 30, a gallium nitride film 32. And a metal mask 34 having a roughened surface. Figure 3B illustrates a schematic cross-sectional view of a metal mask sample of 2 sec and 15 201248919 under oxidation-dominated conditions, Figure 3C is 400 seconds, and Figure 3D is 600 seconds. Figure 4 illustrates a vertical-emitting diode (vertical-LED wafer). The multilayer epitaxial layer structure of the n-type gallium nitride illustrated on the light-emitting diode is shown on the metal substrate 70. The embodiment may be a thick copper layer. The multilayer epitaxial layer structure formed on the metal substrate 70 includes an n-type gallium nitride base layer 8 〇, an MQW active layer 78', and a reflector/contact layer 74. The gallium nitride base layer 80 has a thickness of, for example, 4 micrometers. The multilayer epitaxial layer can be formed on a carrier substrate by providing an n-type gallium nitride portion (for example, an n-type gallium nitride layer 80) (not shown). Formed on top, depositing an active layer (eg, MQW active layer 78) on the n-type gallium nitride portion, and depositing a p-type gallium nitride portion (eg, p-type gallium nitride layer 76) on the active layer, depositing the first One or more metal layers (e.g., reflective/contact layer 74), a mask layer (not shown) is applied, and the metal, p-type gallium nitride layer, active layer, and n-type gallium nitride layer are etched. The mask is then removed, a passivation layer (e.g., layer 84) is deposited, and a portion of the spacer layer on the p-type gallium nitride is removed to expose the first or more metal layers. A second or more metal layers (eg, Zhan 72) may be deposited, a metal substrate (eg, metal substrate 70) deposited, a carrier substrate (not shown) removed to expose the n-type gallium nitride portion, and n-type nitrogen The gallium portion is roughened. The MQW active layer 78 can be an indium gallium nitride/gallium nitride MQW active layer. Once the power source is poured between the n-type gallium nitride base layer 80 and the contact layer 74, the MQW active layer 78 can be energized and thus produce light. The light produced can have a wavelength of 250 nm to 600 nm. The p-type layer 76 may be a p+S gallium nitride base 201248919 layer 'e.g., a P+ type gallium nitride' p+ type indium nitride + and may have a thickness of 0.05 to 5 microlevels. Aluminum indium gallium layer 'U.b micro water diagram 5 shows a cross-sectional view of the roughened cross section of the non-vertical light emitting diode. As shown in FIG. 5 and FIG. 6, the cover: texture form is formed on the surface of the n-type gallium nitride. Fig. 5 shows a rough =1 surface view of the light-emitting diode metal layer of Fig. 4, and Fig. 6 shows a SEM image of the roughened surface. The change in surface effectively roughens the surface and directs the matching of air to a better refractive index. This allows the LED to achieve better internal light extraction. Although the invention has been described in considerable detail in connection with the embodiments, it is feasible to practice it. In another alternative implementation, the surface of the nitrided layer can be ball/sphere or wet/dry type. Perform roughening treatment. Those skilled in the art will also be able to use other LEDs using LEEarray. The new light emitting diodes can have a combination of different arrays of light extracting elements and can have a disperser layer. The light extraction elements can have different shapes, sizes, and spaces between adjacent light extraction elements, and can be placed at different locations. Similarly, the astigmatism layer can be made of different materials and can be placed in different locations. Therefore, the spirit and scope of the appended claims should not be limited to the embodiments described above. Another Example of Surface Roughening Techniques Techniques for increasing light-emitting diode light extraction in accordance with embodiments of the present invention can be utilized when light-emitting diode semiconductor dies are placed onto a wafer or a portion of a wafer combination. These techniques can be applied to any of the light-emitting diodes 17 201248919 wafers or wafer combinations comprising a plurality of dies, and the case where vertical LEDs are provided here is exemplified. In the following illustration, although only the crystal grains of three vertical light-emitting diodes are shown, they represent a plurality of crystal grains on the light-emitting diode wafer. Referring to FIG. 8, a light emitting diode wafer assembly 722 having a plurality of vertical light emitting diode patterns 700 and a conductive substrate 718, or a thick conductive layer (TCL), is provided. The vertical light emitting diode die 700 can include a plurality of composite semiconductor epitaxial layers composed of, for example, a Group III or Group 5 chemical element such as gallium nitride, aluminum nitride, indium nitride, or the like. Conductive substrate 718 can comprise any suitable metal or metal alloy 'e.g., copper, nickel, nickel-cobalt, silver, gold, copper-min, copper-molybdenum, town/copper, copper/nickel-cobalt/copper, copper/nickel- Cobalt/copper/nickel-cobalt, or nickel/copper-indium. The light emitting diode wafer assembly 722 may have a reflective layer 71 disposed on the conductive substrate 718. For example, a p-type doped layer 7〇8 of p-type gallium nitride is disposed on the reflective layer 710, and an active layer 706 for emitting light. An n-type doped layer 704 disposed on the p-type doped layer 708 and, for example, n-type gallium nitride is disposed on the active layer 7〇6. In some embodiments, reflective layer 710 can be omitted. For example, in some embodiments, an isolation layer 712 can be positioned between the vertical light emitting diodes to protect the grains of the vertical light emitting diode during grain separation. At this stage, the surface 720 can be substantially flat, and there will be no excessive surface variations in the n-type doped layer 7〇4 when the light-emitting diode wafer assembly 722 is viewed from above or from the side. Although some of the light 724 emerging from the active layer 7〇6 can be emitted from the surface 72〇 of the n-type doped layer during this processing stage, the light 724 arriving at the surface 720 exceeds the critical angle, according to the law of Sinell 201248919, It is unlikely to pass through and total reflection will occur. Further processing will result in better results. Thus, as shown in Figure 8, a mask 726 can be used on the surface 720 of the n-type doped layer 7A4, and the surface 720 can be subsequently etched to improve the erbium type doping. The hetero surface area is extracted by light that increases the vertical light-emitting diode grains 7〇〇. The etching may be by wet etching, light-improved wet etching, dry etching (e.g., conductive coupling plasma/reactive ion etching, ICP/RIE), or a combination thereof. The composition of the mask 726 can be any suitable material as long as it is hard enough to withstand repeated etching. Its material is, for example, nickel, ruthenium dioxide, ruthenium osmium or photoresist. Mask 726 can be patterned as desired' so that surface 720 can be selectively etched. In some embodiments, for example, the mask 726 can be a grid 'checkerboard (as shown), honeycomb, triangle, rectangle, or other polygonal pattern. In some embodiments, different sizes of a particular polygon, or different sizes of different polygons, can be combined to pattern mask 726. After the surface 720 of the n-doped layer 704 is etched, the mask 726 can be removed' leaving a wafer combination as shown in Figure 9A. The surface 720 can have a plurality of buttonholes 728 in which the material is removed leaving a plurality of toothed structures 73〇 to form a surface that forms a comb shape such that the one-dimensional view does not cross-section. The checkerboard pattern of the residual pit 728 and the toothed structure 730 is illustrated in the upper view of FIG. Since the surface area (Β) of the pit 728 and the tooth structure 730 is larger than the surface area (Α) of the 掺杂-type doped layer 704 in Fig. 7, these features can improve the light emission rate. Thus, after such a processing stage, more light 724 can be extracted from the surface according to Snell's law and Total Reflection Law. 201248919 For some of the embodiments illustrated in Figure 9B, the n-doped layer 704 can be etched in substantially all directions, which allows the depth of the etch pit 728 to approach the active layer, within 10 nanometers. The resulting surface excitation features (SEF) 732 can increase the density of its states and the spontaneous emissivity of the LED semiconductor. These surface intensification features can also lead to improvements in surface intensification features/quantum well coupling. Therefore, 'light extraction can be further improved. For other embodiments using the mask 726 of Figure 8, the surface 720 can be etched by chemical wet etching. The hexagonal pyramid structure is formed in the n-type doped layer 704 shown in Fig. 9C due to the crystal characteristics of many composite semiconductor materials (e.g., gallium nitride) used in the assembly of the light-emitting diodes. Therefore, the size of the wet etching and the hexagonal pyramid structure can be well controlled. Please refer to _. In some embodiments, the masked wafer combination shown in FIG. 8 can penetrate the n-type doped layer 7() 4, active = two surnames: Γ7°8 . In this case, 'the micro-disc = ▲ 1 ring (mie). Seven ng) vertical light-emitting diodes: only: _ disc, micro-ring and nano-column (nanorod ΪΓΓί face relative to the n-type of Figure 7 The doped layer_table_, both have "light so" these structures can provide more light extraction than the conventional vertical first pole. For a quarter embodiment please refer to Figure 10, in Figure 9A (or other The above-described real cross section (4) (4) (4) _ table secret = 20 201248919 roughening or texturing to increase the surface area, therefore, the amount of light extraction can be increased. In some embodiments, with patterned etch pits 728 Surface 72 can be roughened by any suitable technique, including, for example, wet etching, light modified wet etching, dry etching, or photoelectrochemical oxidation and etching as mentioned above. In some other embodiments, the submicron is permeable. A size object (e.g., a polystyrene sphere) utilizes the surface 720' of the n-doped layer having the surface of the etch pit 728 to increase the surface area of the n-type doped layer 7A4. Another example of surface roughening technique is a conventional surface rough Sewing technology and Some of the techniques described herein and described above have a forward voltage (Vf) that can cause instability, and cause leakage current in a light-emitting diode component fabricated from a combination of light-emitting diode wafers. An increase in (1 eakage current). The technique proposed by the embodiment of the present invention can increase the light extraction of the light-emitting diode without causing a positive direction by roughening only in a specific region of the surface of the light-emitting monopole wafer assembly. Voltage instability or leakage current. Again, this technology can be applied to any LED wafer or a combination of wafers with multiple dies, and the vertical LED dies are only By way of example, returning to Figure 7, a light emitting diode wafer assembly 722 having a plurality of vertical light emitting diode patterns 700 and a conductive substrate 718 can be provided. The light emitting diode wafer assembly 722 can have a reflective layer 710. Disposed on the conductive substrate 718, the p-doped layer 708 is disposed on the reflective layer 710, the active layer 706 for emitting light is disposed on the P-type doped layer 708, and the n-type doped layer 704 is disposed on the active layer 705. . In some embodiments, the reflective layer 710 can be omitted. At this stage, the surface 720 of the n-type doped layer 704 is substantially flat. 21 201248919 Clear reference to FIG. 11A 'The protective layer 1200 can be added to the light emitting diode combination of FIG. J22. The protective layer 12A may be a patterned structure, for example, as a mask, covering the edge of the vertical light-emitting diode die 7〇〇 and the mouth-shaped shape, and the surface 720 of the impurity layer 704 is used as a designated area of the n-electrode. In some embodiments, the 'protective layer can cover adjacent vertical light-emitting diode grains 700 and materials between the grains 7 (for example, street areas (s 7 areas) . Used to withstand chemical processing and to protect the underlying material, the protective layer 200 is organic or non-organic, photosensitive (photosensitive) or non-photosensitive, and may be composed of any suitable material, such as a polymer, ugly. P〇lymide, photoresist (ph〇tGresist), epoxy resin, U~8, NR-7, AZ5214E, thermoplastic (therm〇plastic), tantalum nitride, cerium oxide, zinc oxide, five Oxidation of two buttons, titanium dioxide, hypofluoric acid (HF0) or magnesium oxide (Mg〇). If the protective layer 1200 is applied to the LED array 722, the surface 72〇 of the n-doped layer 704 may be subsequently roughened, and/or processed as described above to improve the n-doped layer. The surface area, thus increasing the light extraction of the vertical light emitting diode die 700 shown in Figure 11A. The roughened and/or textured surface 720 can be achieved by any suitable technique for increasing the surface area, such as wet etching, light modified wet etching, dry etching, or the above-described optoelectronic chemical oxidation and etching processes. The protective layer 1200 can allow for selective roughening and/or texturing of the surface 720 to avoid instability of the forward voltage and to avoid leakage currents. After the surface of the n-type doped layer 704 is selected to be coarsely saccharified and/or textured, the protective layer 1200' can be removed as shown in FIG. Next, the n-electrode 121A can be applied to the vertical light-emitting diode die 7A shown in Fig. 11D. Protective layer
S 22 201248919 1200覆蓋的指定n電極區域可以提供實質上平坦的表面，用 來搞接到η電極1210 ’因此，相對於傳統方式粗縫化的指定 區域，這樣的做法能改善穩定性。在一些實施例中，η電極 1210可以在加上保護層12〇〇之前就先形成，並且在粗糙化 以及/或紋理化的過程，由保護層12〇〇進行覆蓋。 在一些其他的實施例中，選擇性的粗糙化以及/或紋理 化可以無需保護層_即可達成。舉例來說，次微米尺寸 物件’例如聚苯乙締球體，可以加在除了選擇區域以外的 發光-極體aB圓組合722的表面，例如垂直發光二極體晶粒 700的邊緣以及指定給n電極mG的區域1他尚未知道的 技術也可以藉此用來選擇性地對於發光二極體晶圓組合 722的特定部分進行⑽切及/或紋理化。 另一個進行表面粗糙化技術的示例 藉由在上面分別描述過的圖8]〇形成钱刻坑，相對於 傳統的發光一極體’額外的粗縫化可以增加η型摻雜層704 的表面72=及㈣坑728基座（base)的表面積（並且因 此增加光萃取）。圖12例示的掃描電子顯微鏡（SEM)影 1700，說明了 -個這樣的_坑？28以及粗糙化的表面。然 了與侧奶8底座賴度的肖度，以及 ^ 704的表面別約·的角度。使用上述表面粗輪 術’陡侧牆12G2可以維持相對平滑，因此限制了如 這麼做所能達到的光萃取。 了從發光二極體增加光萃 ’而這樣的牆會造成進一 據此，本發明的實施例提供 取的技術，不需要形成陡峭的膽 23 201248919 步粗糙化或紋理化的困難。再一次說明，這樣的技術可以 用在任何的發光二極體晶圓或包括多個晶粒的晶圓組合， 且在此，垂直發光二極體晶粒只是用來作為範例。 請回頭參考圖7，其提供具有多個垂直發光二極體晶粒 700以及導電基底718的發光二極體晶圓組合722。此發光二 極體晶圓組合可以有反射層710設置在導電基底718上、p 型摻雜層708設置在反射層710上、用來發光的主動層706 設置在p型摻雜層708、以及設置在主動層706上的η型摻雜 層704。在一些實施例中，可以省略反射層710。在這個階 段，η型摻雜層704可以保持實質上平坦。 現在請參照圖13，遮罩1300可以用在垂直發光二極體 晶粒700的η型摻雜層704的表面720。遮罩1300可以包括複 數個高升的中空凸端（hollow nub) 1302，以一定圖案排 列。中空凸端1302可以是任何三維形狀，例如圓頂、長方 體、圓柱體或角柱體（例如六角形角柱），並且不同的凸 端1302可以具有不同的形狀。凸端1302可以進行各種想要 的圖案化，使得表面720可以被選擇性地蝕刻。在一些實施 例中’遮罩1300的中空凸端1302可以排列成具有固定行列 的陣列，以對角模式、鋸齒模式、隨機模式、看起來隨機 模式或是任何其他想要的模式。遮罩13〇〇的組成可以是任 何適合的材料，例如鎳、二氧化矽、氮化矽、光阻及其他 相似物，只要夠硬可以抵擋蝕刻有害的效果。在一些實施 例中，遮罩1300可以由熱處理阻擋物（heat_treated resist)組成’以產出所想要形狀的中空凸端13〇2。 24 201248919 在遮罩1300被加到發光二極體晶圓組合之後，η型摻雜 層704的表面720可以被進一步钱刻，以改善η型摻雜層的表 面區域，以達成垂直發光二極體7〇〇更多的光萃取。蝕刻可 以透過濕式飯刻、光改良濕式姓刻、乾式姓刻（例如感應 耦合電漿/反應離子蝕刻，ICP/RIE)、或是其各種組合。 在一些包括了 η型摻雜氮化鎵的η型摻雜層的實施例中，餘 刻可以使用氯（chlorine)來達成。當表面72〇被蝕刻的時 候，遮罩1300也可以被侵钱。遮罩13〇〇的中空凸端13〇2可 以容許留下η型摻雜層704的半導體材料，並且在蝕刻進行 中負責中空部分的形狀。 在η型摻雜層704的表面720被蝕刻後，遮罩1300的任何 殘餘材料可被移除，而留下如圖14Α所示的晶圓組合。蝕刻 表面可以有若干突起（protuberance ) 1400，例如點狀、 螺絲狀（stud)、腫塊（bump)或高升的部分，在蝕刻過 程中’在遮罩1300的中空凸端13〇2下的多層外延層的半導 體材料被保留下來。當蝕刻進行中，遮罩1300可以增加侵 餘’導致突起具有更陡峭的侧表面。圖14A所示的放大影像 14〇2顯示了陡峭的側表面14〇4，以及角度0在蝕刻表面與 已知的陡峭侧表面1404之間如何大於90度。在一些實施例 中’遮罩1300的凸端i3〇2做成中空圓頂形狀之處，其所造 成的大起1400的形狀大部分是圓錐體（cone)的平截頭體 (frustum)。在一些其他實施例中，當遮罩13〇〇的凸端13〇2 破做成中空長方體時，其所造成的突起1400大多數像是矩 形金字塔的平戴頭體（frustum)。 25 201248919 在蝕刻表面720突起1400的圖案顯示在圖14A的上視圖 中。這些特徵可以改良光發射率，因為突起1400所形成的 表面積（B)大於如圖7所示實質上平坦的η型摻雜層704的 表面積（Α)。因此，在這樣的處理階段下，根據司乃爾定 律以及全反射定律，更多的光724可以從表面萃取出來。 現在請參考圖14Β ’在圖14Α中例示的上視圖與放大圖 中所例示的η型摻雜層704的蝕刻表面720可進一步被粗縫 化或紋理化，以增加表面積，因此，光萃取可以更多。在 一些實施例中，蝕刻表面720以及突起1400的上表面與側表 面可以透過任何適合的技術再進行粗縫化，例如包括濕式 钱刻、光改良濕式蝕刻、乾式蝕刻或上面提過的光電化學 氧化與蝕刻處理。在一些其他的實施例中，可以透過加上 多本乙稀球體之類的次微米尺寸物件來進一步增加η型掺 雜層704的表面積，例如對於具有上表面與陡峭側表面突起 1400的η型摻雜層的表面72〇進行操作。更進一步對於表 面進行粗糙化以及/或紋理化，可以讓主動層發出的光 724，能夠以更淺的角度從垂直發光二極體晶粒700的發射 表面脫離。 办圖15例不的掃描電子顯微鏡影像1500，顯示了粗糙化 =起1400，就如那些在圖14Β所示的一樣。由於粗糖化以 化處理而導人具有陡Λ肖表面1404的突起1400,在 掃描電子顯微鏡影像1500跟蝕刻坑728的掃描電 :==:像1700時，可以觀察到光滑平面(例如 ’ ^的效果。因此，相對於傳統技術或上面所述的The specified n-electrode region covered by S 22 201248919 1200 can provide a substantially flat surface for bonding to the n-electrode 1210', thus improving stability compared to the designated region of the conventional manner. In some embodiments, the n-electrode 1210 can be formed prior to the addition of the protective layer 12, and covered by the protective layer 12? during the roughening and/or texturing process. In some other embodiments, selective roughening and/or texturing may be achieved without the need for a protective layer. For example, a sub-micron sized object, such as a polystyrene sphere, may be applied to the surface of the luminescent-polar body aB circle combination 722 other than the selected region, such as the edge of the vertical illuminating diode die 700 and assigned to n The region 1 of the electrode mG, which is not yet known, can also be used to selectively (10) cut and/or texture a particular portion of the LED array 722. Another example of performing the surface roughening technique can form the surface of the n-type doped layer 704 with respect to the conventional light-emitting body's additional roughing by forming the money pits in FIG. 8 respectively described above. 72 = and (d) the surface area of the pit 728 base (and thus increased light extraction). The scanning electron microscope (SEM) image 1700 illustrated in Fig. 12 illustrates one such _ pit? 28 and roughened surface. However, the angle of the base with the side of the milk 8 and the angle of the surface of the ^ 704 are different. The use of the above-described surface roughing wheel 'steep side wall 12G2' can maintain relatively smooth, thus limiting the light extraction that can be achieved as such. The addition of light from the light-emitting diodes and such walls can cause further improvements in the practice of the present invention, without the need to form steep ridges. Again, such a technique can be used with any light emitting diode wafer or wafer combination comprising multiple dies, and here the vertical light emitting diode dies are used merely as an example. Referring back to Figure 7, a light emitting diode wafer assembly 722 having a plurality of vertical light emitting diode dies 700 and a conductive substrate 718 is provided. The light emitting diode wafer assembly may have a reflective layer 710 disposed on the conductive substrate 718, a p-type doped layer 708 disposed on the reflective layer 710, an active layer 706 for emitting light disposed on the p-type doped layer 708, and An n-type doped layer 704 disposed on the active layer 706. In some embodiments, the reflective layer 710 can be omitted. At this stage, the n-type doped layer 704 can remain substantially flat. Referring now to Figure 13, a mask 1300 can be used on the surface 720 of the n-type doped layer 704 of the vertical light emitting diode die 700. The mask 1300 can include a plurality of high rise hollow nubs 1302 arranged in a pattern. The hollow male end 1302 can be any three-dimensional shape, such as a dome, a cuboid, a cylinder, or a corner cylinder (e.g., a hexagonal corner post), and the different male ends 1302 can have different shapes. The male end 1302 can be subjected to various desired patterns such that the surface 720 can be selectively etched. In some embodiments, the hollow male ends 1302 of the mask 1300 can be arranged in an array having a fixed array, in a diagonal mode, a sawtooth mode, a random mode, a seemingly random mode, or any other desired mode. The composition of the mask 13 can be any suitable material such as nickel, cerium oxide, tantalum nitride, photoresist, and the like, as long as it is hard enough to withstand the harmful effects of etching. In some embodiments, the mask 1300 can be composed of a heat_treated resist to produce a hollow convex end 13〇2 of a desired shape. 24 201248919 After the mask 1300 is applied to the light emitting diode wafer assembly, the surface 720 of the n-type doped layer 704 can be further engraved to improve the surface area of the n-type doped layer to achieve a vertical light emitting diode Body 7 〇〇 more light extraction. The etching may be by wet rice etching, light-modified wet-type etching, dry-type etching (e.g., inductively coupled plasma/reactive ion etching, ICP/RIE), or various combinations thereof. In some embodiments including an n-type doped layer of n-type doped gallium nitride, the residue can be achieved using chlorine. When the surface 72 is etched, the mask 1300 can also be invaded. The hollow convex end 13〇2 of the mask 13〇〇 can allow the semiconductor material of the n-type doped layer 704 to be left, and is responsible for the shape of the hollow portion in the etching process. After the surface 720 of the n-type doped layer 704 is etched, any residual material of the mask 1300 can be removed leaving a wafer combination as shown in FIG. The etched surface may have a number of protuberances 1400, such as punctuated, studed, bumped or raised portions, which are multilayered under the hollow convex end 13〇2 of the mask 1300 during etching. The layer of semiconductor material is retained. As the etch is in progress, the mask 1300 can increase the ablation' resulting in the protrusion having a steeper side surface. The magnified image 14〇2 shown in Fig. 14A shows the steep side surface 14〇4, and how the angle 0 is greater than 90 degrees between the etched surface and the known steep side surface 1404. In some embodiments, the convex end i3〇2 of the mask 1300 is shaped as a hollow dome, and the shape of the large 1400 that is formed is mostly a frustum of a cone. In some other embodiments, when the convex end 13〇2 of the mask 13 is broken into a hollow rectangular parallelepiped, the protrusion 1400 caused by it is mostly like a frustum of a rectangular pyramid. 25 201248919 The pattern of protrusions 1400 on the etched surface 720 is shown in the top view of Figure 14A. These features can improve the light emissivity because the surface area (B) formed by the protrusions 1400 is larger than the surface area (Α) of the substantially flat n-type doped layer 704 as shown in FIG. Therefore, at such a processing stage, more light 724 can be extracted from the surface according to Snell's law and total reflection law. Referring now to FIG. 14A, the etched surface 720 of the n-type doped layer 704 illustrated in the upper and enlarged views illustrated in FIG. 14A may be further roughened or textured to increase the surface area, and thus, light extraction may be performed. More. In some embodiments, the etched surface 720 and the upper and side surfaces of the protrusions 1400 may be roughened by any suitable technique, including, for example, wet etching, light modified wet etching, dry etching, or the above. Photoelectrochemical oxidation and etching treatment. In some other embodiments, the surface area of the n-doped layer 704 can be further increased by the addition of a plurality of sub-micron sized objects such as a thin sphere, such as for an n-type having an upper surface and a steep side surface protrusion 1400. The surface 72 of the doped layer is operated. Further roughening and/or texturing the surface allows the light 724 emitted by the active layer to be detached from the emitting surface of the vertical light-emitting diode die 700 at a shallower angle. A scanning electron microscope image 1500 of 15 cases is shown, showing a roughening = 1400, as shown in Figure 14A. Since the coarse saccharification leads to a protrusion 1400 having a steep surface 1404, a scanning plane of the scanning electron microscope image 1500 and the etching pit 728: ==: like 1700, a smooth plane can be observed (for example, '^ Effect. Therefore, compared to conventional techniques or as described above
S 26 201248919 紋理化的突 技術，透過本發明實施例形成具有_化或 起，可以進一步增加光萃取。 雖然本發明已經透過舉例以及較佳實施例的介 了；月楚的描述’但是應該了解的是，本發明並不限；$ =的内容。相反地，本發明企圖涵蓋不同的修改跟相ς 的女排以m並且附加㈣料利範圍目此應該以 廣的方式進行解讀，以涵蓋所有這類的修改以及相似的安 排與流程。 【圖式簡單說明】 =1顯不-個範例系統’用來執行光電化學氧化與㈣（ 的處理。 圖2A-2D顯示在不同時間進行氧化3 遮罩的第一樣本表面的剖面示意圖。 顯示在不同時間進賴刻主導條件，—個具有金 题罩的第二樣本表面的剖面示意圖。 員不具有頂層n型氮化鎵層的垂直發光二極體晶圓的結 不在對曝露㈣氮化鎵層進行粗糙化垂直發光二極體 曰曰圓的橫切面示意圖。 2員示掃描電子顯微鏡圖表，顯示n型氣化錄表面的無序 ’硬形態。 圖 7!s _ 雜與不在表面粗糙化之前，發光二極體晶圓組合的n型摻 句的表面區域，以及根據本發明實施例的發射光的路徑。 27 201248919 =根進據行本::實施例，_示在圖7的，層表面上用 示在對圖8的η型摻雜層進行飯 圖9Α根據本發明實施例，_ 刻後的表面區域。 圖9Β根據本發明實施例，_示在對㈣ 發的改良，實質上通過了，摻縣並接近㈣^表面激 圖9C根據本發明實施例，_示在對則進行化曰 :冓型。推雜層的表面區域，因此在表面形成了六== 二 =本發明實施例，_示在對圖8進行餘 極體的圓組合’通過了哎換雜層、主動層與ρ型摻雜層 圖10根據本發明實施例，_示在對嶋的 糖化的η型摻雜層的表面區域。 β面進仃粗 示根據本發明實施例，使用保護層改變η型摻雜 圖12的掃描電子顯微鏡影像顯示根據本發明實施例的 蝕刻坑的光滑壁，以及關於圖1〇的粗糙表面。 圖13根據本發明實施例，顯示用圓項遮罩在圖▲型捧雜 層進行姓刻》 ” 圖14Α根據本發明實施例，顯示在圖13的蝕刻後的η型 層及突起的陡峭壁增加的表面積。 ” 圖14Β根據本發明實施例，顯示在圖14Α的具有突起的蝕刻 表面粗糙化之後，η型摻雜層增加的表面積。 χΙS 26 201248919 Textured protrusion technology, formed by the embodiment of the invention, can further increase light extraction. Although the present invention has been described by way of example and preferred embodiments, the description of the present invention is to be understood that the invention is not limited to the contents of the invention. On the contrary, the present invention attempts to cover different modifications and contradictory women's volleyballs in m and the additional (four) material profit range should be interpreted in a broad manner to cover all such modifications and similar arrangements and processes. [Simple description of the diagram] =1 shows that - an example system 'is used to perform photoelectrochemical oxidation and (4) (the processing. Figure 2A-2D shows a schematic cross-sectional view of the first sample surface of the oxidation 3 mask at different times. Shows the dominant conditions at different times, a cross-sectional view of the surface of a second sample with a gold cap. The junction of a vertical light-emitting diode wafer without a top-layer n-type gallium nitride layer is not exposed to (tetra) nitrogen. The gallium layer is a schematic diagram of the cross-section of the roughened vertical light-emitting diode circle. The 2 member shows a scanning electron microscope chart showing the disordered 'hard shape of the n-type gasification recording surface. Figure 7!s _ Miscellaneous and non-surface Prior to roughening, the surface area of the n-type admixture of the light-emitting diode wafer combination, and the path of the emitted light according to an embodiment of the present invention. 27 201248919 = Roots of the data: Example, _ is shown in Figure 7. The surface of the layer is shown in Fig. 8 for the n-type doped layer of Fig. 8. According to the embodiment of the invention, the surface area after the engraving is shown. Figure 9A shows the improvement of the (four) hair according to an embodiment of the invention. Substantially passed, mixed with counties (4) Surface Excitation 9C According to an embodiment of the present invention, _ is shown in Fig. 曰: 冓 type. The surface area of the urging layer, thus forming six == two on the surface = the embodiment of the invention, _ is shown in Figure 8 shows a circular combination of a remnant body 'passed through a hafnium exchange layer, an active layer and a p-type doped layer. Figure 10 shows the surface area of the n-doped layer of glycated n-type doped in accordance with an embodiment of the present invention. The surface of the etched electron microscope according to an embodiment of the present invention is shown in FIG. According to an embodiment of the present invention, the display is surrounded by a circle item in the shape of the pattern of the ▲ type, and the last step of the etched n-type layer and the protrusion is increased according to the embodiment of the present invention. Surface area. Figure 14A shows the increased surface area of the n-type doped layer after roughening of the etched surface with protrusions in Figure 14A, in accordance with an embodiment of the present invention.
S 28 201248919 圖15的掃描電子顯微鏡影像，顯示了根據本發明實施例， 關於圖14B粗糙化後的突起。 【主要元件符號說明】 電解液16 鉗子12 參考電極14 基底（substrate) 30 氮化鎵薄膜32 金屬遮罩34 金屬基底70 η型氮化鎵基礎層80 MQW主動層78 層84 層72 接點層 ρ-層 76 接觸層74 保護層1200 η電極1210 發光二極體晶圓組合722 垂直發光二極體晶粒700 導電基底718 29 201248919 反射層710 主動層706 P型摻雜層708 η型摻雜層704 隔離層712 電子顯微鏡影像1500 掃描電子顯微鏡影像1700S 28 201248919 The scanning electron microscope image of Fig. 15 shows the protrusions after roughening with respect to Fig. 14B in accordance with an embodiment of the present invention. [Main component symbol description] Electrolyte 16 Pliers 12 Reference electrode 14 Substrate 30 Gallium nitride film 32 Metal mask 34 Metal substrate 70 η-type gallium nitride base layer 80 MQW active layer 78 layer 84 layer 72 Contact layer Ρ-layer 76 contact layer 74 protective layer 1200 n electrode 1210 light emitting diode wafer combination 722 vertical light emitting diode die 700 conductive substrate 718 29 201248919 reflective layer 710 active layer 706 P type doped layer 708 n-type doping Layer 704 isolation layer 712 electron microscope image 1500 scanning electron microscope image 1700