TW201248804A - Bumping process and structure thereof - Google Patents

Bumping process and structure thereof Download PDF

Info

Publication number
TW201248804A
TW201248804A TW100117669A TW100117669A TW201248804A TW 201248804 A TW201248804 A TW 201248804A TW 100117669 A TW100117669 A TW 100117669A TW 100117669 A TW100117669 A TW 100117669A TW 201248804 A TW201248804 A TW 201248804A
Authority
TW
Taiwan
Prior art keywords
layer
outer peripheral
peripheral wall
copper
wall
Prior art date
Application number
TW100117669A
Other languages
Chinese (zh)
Other versions
TWI440150B (en
Inventor
Lung-Hua Ho
Chih-Ming Kuo
Kun-Shu Chuang
Original Assignee
Chipbond Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipbond Technology Corp filed Critical Chipbond Technology Corp
Priority to TW100117669A priority Critical patent/TWI440150B/en
Publication of TW201248804A publication Critical patent/TW201248804A/en
Application granted granted Critical
Publication of TWI440150B publication Critical patent/TWI440150B/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Bumping process comprises the steps: providing a substrate having a surface, a plurality of pads and a first passivation layer; forming a metal layer with copper onto the pads and the first passivation layer, the metal layer with copper has a plurality of first zones and a plurality of second zones; forming a photoresist layer to the metal layer with copper; patterning the photoresist layer to form a plurality of openings and the openings are correspond to the first zones; forming a plurality of copper bumps into the openings, each of the copper bumps cover each of the first zones and each of the copper bumps cover has a first top surface; forming a connector layer onto the first top surfaces, the connector layer has s second top surface and includes a Ni layer and a Au layer; removing the photoresist layer; removing the second zones to expose the first passivation layer and making the first zones form a UBM layer, wherein each of the UBM layer has a first outer wall, each of the copper bumps has a second outer wall, the connector layer has a third outer wall, and there is a first distance between the third outer wall and the second outer wall, there is a second distance between the third outer wall and the first outer wall. There is a space between the connector layer and the first passivation layer, the first outer wall and the second outer wall are surround by the space, and the space has a first space part and a second space part; forming a second passivation layer onto the second top surface of the connector layer, the first outer walls of the UBM layers, the second outer wall of the copper bumps, the third outer walls of the connector layer, the first passivation layer, the first space part and the second space part; removing the second passivation layer of the second top surface of the connector layer, the third outer walls of the connector layer and the first passivation layer, and make a first protecting ring into the first space part and a second protecting ring into the second space part.

Description

201248804 六、發明說明: 【發明所屬之技術領域】 [0001] 本發明係有關於一種凸塊製程,特別係有關於一種 可防止短路之凸塊製程。 【先前技術】 [0002] 如第1A至1H圖,習知凸塊製程係至少包含下列步驟 :首先,請參閱第1A圖,提供一基板10,該基板10係具 有一表面11、複數個設置於該表面11之銲墊12及一形成 於該表面11之保護層13,該保護層13係顯露該些銲墊12 Θ ;接著,請參閱第1B圖,形成一含銅金屬層20於該些銲 墊12及該保護層13 ;之後,請參閱第1C圖,形成一光阻 層30於該含銅金屬層20 ;接著,請參閱第1D圖,圖案化 該光阻層30以形成複數個開口 31 ;之後,請參閱第1E圖 ,形成複數個銅凸塊40於該些開口 31内,各該銅凸塊40 係具有一第一外周壁41 ;接著,請參閱第1F圖,形成一 導接層50於該些銅凸塊40 ;之後,請參閱第1G圖,移除 該光阻層30,最後,請參閱第1H圖,利用蝕刻方法移除 ❹ 未被該些銅凸塊40覆蓋之該含銅金屬層20以形成一凸塊 下金屬層21,各該凸塊下金屬層21係具有一第二外周壁 21a,然在進行移除未被該些銅凸塊40覆蓋之該含銅金屬 層20的步驟時,由於該些銅凸塊40之材質係包含有銅, 因此該些銅凸塊40會同時與該含銅金屬層20—起被蝕刻 而導致該些銅凸塊40之該些第一外周壁41產生凹陷之情 形,且該些凸塊下金屬層21之該些第二外周壁21a凹陷之 程度更大於該些銅凸塊40之該些第一外周壁41,此外, 由於該些第一外周壁41及該些第二外周壁21a凹陷且裸露 100117669 表單編號 A0101 第 5 頁/共 21 頁 1002029703-0 201248804 ,因此容易造成銅離子游離之現象而導致短路之情形發 生。 【發明内容】 [0003] 本發明之主要目的係在於提供一種凸塊製程,其包 含提供一基板,該基板係具有一表面、複數個銲墊及一 第一保護層,該些銲墊係設置於該表面,該第一保護層 係形成於該表面並顯露該些銲墊;形成一含銅金屬層於 些銲墊及該第一保護層,該含銅金屬層係具有複數個第 一區及複數個第二區;形成一光阻層於該含銅金屬層; 圖案化該光阻層以形成複數個開口,該些開口係對應該 些第一區;形成複數個銅凸塊於該些開口内,各該銅凸 塊係覆蓋該含銅金屬層之各該第一區且各該銅凸塊係具 有一第一頂面;形成一導接層於該些銅凸塊之該些第一 頂面,該導接層係具有一第二頂面且該導接層係包含有 一鎳層及一接合層,該鎳層係位於該銅凸塊與該接合層 之間;移除該光阻層;移除該含銅金屬層之該些第二區 以顯露出該第一保護層,並使該含銅金屬層之各該第一 區形成一凸塊下金屬層,其中各該凸塊下金屬層係具有 一第一外周壁,各該銅凸塊係具有一第二外周壁,該導 接層係具有一第三外周壁,該第三外周壁與該第二外周 壁之間係具有一第一間距,該第三外周壁與該第一外周 壁之間係具有一第二間距且該導接層及該第一保護層之 間係具有一容置空間,該容置空間係環繞該第一外周壁 及該第二外周壁,且該容置空間係具有一對應於該第一 外周壁之第一容置部及一對應於該第二外周壁之第二容 置部;形成一第二保護層於該導接層之該第二頂面、該 100117669 表單編號A0101 第6頁/共21頁 1002029703-0 201248804 些凸塊下金屬層之該些第一外周壁、該些銅凸塊之該些 第二外周壁、該導接層之該第三外周壁、該第一保護層 、該第一容置部及該第二容置部;以及移除位於該導接 層之該第二頂面、該導接層之該第三外周壁及該第一保 護層之該第二保護層,以使位於該第一容置部之該第二 保護層形成一第一保護環及使位於該第二容置部之該第 二保護層形成一第二保護環。由於環繞該些凸塊下金屬 層之該些第一容置部係形成有該些第一保護環,環繞該 些銅凸塊之該些第二容置部係形成有該些第二保護環,201248804 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a bump process, and more particularly to a bump process capable of preventing short circuit. [Prior Art] [0002] As shown in FIGS. 1A to 1H, the conventional bump process system includes at least the following steps: First, referring to FIG. 1A, a substrate 10 having a surface 11 and a plurality of settings is provided. a solder pad 12 on the surface 11 and a protective layer 13 formed on the surface 11, the protective layer 13 is exposed to the pads 12; then, referring to FIG. 1B, a copper-containing metal layer 20 is formed thereon. a solder pad 12 and the protective layer 13; thereafter, referring to FIG. 1C, a photoresist layer 30 is formed on the copper-containing metal layer 20; then, referring to FIG. 1D, the photoresist layer 30 is patterned to form a plurality of Openings 31; afterwards, referring to FIG. 1E, a plurality of copper bumps 40 are formed in the openings 31, each of the copper bumps 40 having a first outer peripheral wall 41; and then, refer to FIG. A conductive layer 50 is formed on the copper bumps 40; afterwards, please refer to FIG. 1G to remove the photoresist layer 30. Finally, refer to FIG. 1H, and remove the germanium by the etching method. 40 covering the copper-containing metal layer 20 to form an under bump metal layer 21, each of the under bump metal layers 21 having a second outer layer The wall 21a, when the step of removing the copper-containing metal layer 20 not covered by the copper bumps 40 is performed, since the materials of the copper bumps 40 comprise copper, the copper bumps 40 At the same time, the copper-containing metal layer 20 is etched to cause the first outer peripheral walls 41 of the copper bumps 40 to be recessed, and the second outer peripheral walls 21a of the under bump metal layers 21 are formed. The recesses are greater than the first outer peripheral walls 41 of the copper bumps 40. Further, since the first outer peripheral walls 41 and the second outer peripheral walls 21a are recessed and exposed 100117669, the form number A0101 is 21 pages 1002029703-0 201248804, so it is easy to cause the copper ion to be free and cause a short circuit. SUMMARY OF THE INVENTION [0003] The main object of the present invention is to provide a bump process, comprising providing a substrate having a surface, a plurality of pads and a first protective layer, the pads are set Forming a first protective layer on the surface and exposing the pads; forming a copper-containing metal layer on the pads and the first protective layer, the copper-containing metal layer having a plurality of first regions And a plurality of second regions; forming a photoresist layer on the copper-containing metal layer; patterning the photoresist layer to form a plurality of openings, the openings corresponding to the first regions; forming a plurality of copper bumps thereon Each of the copper bumps covers each of the first regions of the copper-containing metal layer and each of the copper bumps has a first top surface; forming a conductive layer on the copper bumps a first top surface, the guiding layer has a second top surface, and the guiding layer comprises a nickel layer and a bonding layer, the nickel layer is located between the copper bump and the bonding layer; a photoresist layer; removing the second regions of the copper-containing metal layer to expose the first protective layer And forming the first region of the copper-containing metal layer into a sub-bump metal layer, wherein each of the under bump metal layers has a first outer peripheral wall, and each of the copper bumps has a second outer peripheral wall. The guiding layer has a third outer peripheral wall, the first outer peripheral wall and the second outer peripheral wall have a first spacing, and the third outer peripheral wall and the first outer peripheral wall have a second Between the guiding layer and the first protective layer, the accommodating space surrounds the first outer peripheral wall and the second outer peripheral wall, and the accommodating space has a corresponding a first receiving portion of the first outer peripheral wall and a second receiving portion corresponding to the second outer peripheral wall; forming a second protective layer on the second top surface of the guiding layer, the 100117669 form number A0101 The first outer peripheral wall of the under bump metal layer, the second outer peripheral walls of the copper bumps, the third outer peripheral wall of the conductive layer, the first a protective layer, the first receiving portion and the second receiving portion; and removing the first portion located in the guiding layer a top surface, the third outer peripheral wall of the guiding layer, and the second protective layer of the first protective layer, so that the second protective layer located in the first receiving portion forms a first protective ring and is located The second protective layer of the second receiving portion forms a second guard ring. The second protection rings are formed around the second accommodating portions of the copper bumps by forming the first protection rings around the first accommodating portions of the underlying metal layers. ,

[0004] Ο 100117669 因此可避免該些凸塊下金屬層之該些第一外周壁及該些 銅&塊之該些第二外周壁裸露而造成銅離子游離導致短 路之情形。 【實施方式】 請參閱第2Α至2J圖,其係本發明之一較佳實施例, 一種凸塊製程,其至少包含下列步驟:首先,請參閱第 2八圖’提供一基板,該基板110係具有一表面111、 複數個銲墊112及一第一保護層113,該些銲墊112係設 置於該表面111,該第一保護層113係形成於該表面U1 並顯露該些銲墊112,該基板110之材質矽可選自於鍺化 矽基板、砷化鎵基板或藍寶石基板其中之一,該第一保 護膚113之材質係可選自於二氧化石夕、氣切、氣氧化矽 或其混合體其中之-;接著,請參閱第2Β圖形成一含 銅金屬層120於些銲墊112及該第一保護層U3 ,該含銅 金屬層120係具有複數個第一區121及複數個第二區122 ;之後,明參閱第2C圖,形成一光阻層13〇於該含銅金屬 層120,接著,請參閱第2D圖,圖案化該光阻層13〇以形 表單煸號Α0101 第7頁/共21頁 1002029703-0 201248804 成複數個開口 131,該些開口 131係對應該些第一區121 :之後,請參閱第2E圖,形成複數個銅凸塊14〇於該些開 口 131内,各該銅凸塊140係覆蓋該含銅金屬層12〇之各 該第一區121且各該銅凸塊140係具有一第一頂面141; 接著,請參閱第2F圖,形成一導接層15〇於該些銅凸塊 140之該些第一頂面141,該導接層15〇係具有一第二頂 面151且該導接層150係包含有一錄層152及一接合層153 ’ β亥錄層152係位於該銅凸塊140與該接合層153之間, 該接合層153之材質係可選自於金 '銀或鉛其中之一,在 本實施例中,該接合層153之材質係為金;之後,請參閱 第2G圖,移除該光阻層130 ;接著,請參閱第211圖,移除 該含銅金屬層120之該些第二區122以顯露出該第一保護 層113,並使該含銅金屬層120之各該第一區121形成一 凸塊下金屬層123,其中各該凸塊下金屬層123係具有一 第一外周壁123a,各該銅凸塊14〇係具有一第二外周壁 142,該導接層150係具有一第三外周壁154,該第一外 周壁123a係具有一第一外周長U,該第二外周壁142係 具有一第二外周長L2,該第三外周壁154係具有一第三外 周長L3,該第二外周長L3係大於該第二外周長L2,該第 二外周長L2係不小於該第一外周長!^,該第三外周壁154 與該第一外周壁142之間係具有一第一間距μ,該第三外 周壁154與該第一外周壁1233之間係具有一第二間距… ,該第二間距D2係不小於該第一間距D1,該導接層15〇及 該第一保護層113之間係具有一容置空間s,該容置空間s 係環繞該第一外周壁123a及該第二外周壁142,且該容置 空間s係具有一對應於該第一外周壁12仏之第一容置部Sl 100117669 表單編號A0101 第8頁/共21頁 ιηηο 201248804 Ο[0004] Ο 100117669 Therefore, it is possible to prevent the first outer peripheral walls of the under bump metal layers and the second outer peripheral walls of the copper & blocks from being exposed to cause copper ions to be dissociated to cause a short circuit. [Embodiment] Please refer to Figures 2 to 2J, which is a preferred embodiment of the present invention, a bump process comprising at least the following steps: First, please refer to Figure 2A to provide a substrate, the substrate 110 The soldering pad 112 is disposed on the surface 111, and the first protective layer 113 is formed on the surface U1 and exposes the solder pads 112. The soldering pads 112 are disposed on the surface 111. The material of the substrate 110 can be selected from one of a bismuth telluride substrate, a gallium arsenide substrate or a sapphire substrate. The material of the first protective skin 113 can be selected from the group consisting of sulfur dioxide, gas cutting, and gas oxidation.矽 or a mixture thereof -; then, referring to FIG. 2, a copper-containing metal layer 120 is formed on the pads 112 and the first protective layer U3, the copper-containing metal layer 120 having a plurality of first regions 121 And a plurality of second regions 122; then, referring to FIG. 2C, a photoresist layer 13 is formed on the copper-containing metal layer 120, and then, referring to FIG. 2D, the photoresist layer 13 is patterned to form a form.煸号Α0101 Page 7 of 21 page 1002029703-0 201248804 A plurality of openings 131, The openings 131 are corresponding to the first regions 121. After that, referring to FIG. 2E, a plurality of copper bumps 14 are formed in the openings 131, and each of the copper bumps 140 covers the copper-containing metal layer 12〇. Each of the first regions 121 and each of the copper bumps 140 has a first top surface 141. Next, referring to FIG. 2F, a first conductive layer 15 is formed on the first portions of the copper bumps 140. The top surface 141, the conductive layer 15 has a second top surface 151, and the conductive layer 150 includes a recording layer 152 and a bonding layer 153'. The copper layer 152 is located on the copper bump 140. Between the bonding layers 153, the material of the bonding layer 153 may be selected from one of gold 'silver or lead. In the embodiment, the material of the bonding layer 153 is gold; then, refer to FIG. 2G. The photoresist layer 130 is removed; then, referring to FIG. 211, the second regions 122 of the copper-containing metal layer 120 are removed to expose the first protective layer 113, and the copper-containing metal layer 120 is Each of the first regions 121 forms an under bump metal layer 123, wherein each of the under bump metal layers 123 has a first outer peripheral wall 123a, and each of the copper bumps 14 a second outer peripheral wall 142 having a third outer peripheral wall 154 having a first outer perimeter U, the second outer peripheral wall 142 having a second outer perimeter L2 The third outer peripheral wall 154 has a third outer perimeter L3, the second outer perimeter L3 being greater than the second outer perimeter L2, and the second outer perimeter L2 is not less than the first outer perimeter! The first outer peripheral wall 154 and the first outer peripheral wall 142 have a first spacing μ, and the third outer peripheral wall 154 and the first outer peripheral wall 1233 have a second spacing ..., the second spacing D2 Not less than the first spacing D1, the guiding layer 15 and the first protective layer 113 have an accommodating space s surrounding the first outer peripheral wall 123a and the second outer peripheral wall. 142, and the accommodating space s has a first accommodating portion S1 100117669 corresponding to the first outer peripheral wall 12 Form No. A0101 Page 8 / Total 21 pages ιηηο 201248804 Ο

及一對應於s亥第一外周壁142之第二容置部S2 ;之後,請 參閲第21圖,形成一第二保護層16〇於該導接層15〇之該 第二頂面151、該些凸塊下金屬層123之該些第一外周壁 123a、該些銅凸塊140之該些第二外周壁〗42、該導接層 150之該第三外周壁154、該第一保護層113、該第一容 置部S1及該第二容置部S2,該第二保護層160係可選自於 氧化物或氮化物其中之一,在本實施例中,該氮化物係 可為II化梦,該氧化物係可為二氧化石夕;最後,請參閱 第2J圖,移除位於該導接層15〇之該第二頂面151、該導 接層150之該第三外周壁154及該第一保護層113之該第 二保護層160,以使位於該第一容置部81之該第二保護層 16〇开>成一第一保護環161,及使位於該第二容置部μ之 該第二保護層16〇形成一第二保護環162以形成一凸塊結 構1 0 0,且該第一保護環161係連接該第二保護環16 2。 由於環繞該些凸塊下金屬層123之該些第一容置部si係形 成有該些第一保護環161,環繞該些銅凸塊14〇之該些第 二容置部S2係形成有該些第二保護環162,因此該些凸塊 下金屬層123之該些第一外周壁123a及該些銅凸塊140之 該些第二外周壁142並無裸露,故可避免銅離子游離而造 成短路之情形。 較佳地,在本實施例中’該第一保護環丨61係具有一 第一環壁161a,該第二保護環162係具有一第二環壁 162a,該第一環壁161a、該第二環壁162a及該第三外周 壁1 5 4係為平齊。 本發明之保護範圍當視後附之申請專利範圍所界定 者為準,任何熟知此項技藝者,在不脫離本發明之精神 100117669 表單編號A0101 第9頁/共21頁 1002029703-0 201248804 明之保護 和範圍内所作之任何變化與修改’均屬於本發 範圍。 【圖式簡單說明】 [0005] 第1A至1H圖:習知凸塊製程之戴面示意圖。 第2A至21® .依據本發明之—較佳實施例,—種&塊製 程之截面示意圖。 [0006] 【主要元件符號說明】 10基板 12銲墊 20含銅金屬層 21 a第二外周壁 31開口 41第一外周壁 100凸塊結構 111表面 113第一保護層 121第一區 123凸塊下金屬層 130光阻層 140銅凸塊 142第二外周壁 151第二頂面 153接合層 160第二保護層 161a第一環壁 11表面 U保護層 21凸塊下金屬層 3〇光阻層 40銅凸塊 5〇導接層 110基板 112銲墊 12〇含銅金屬層 122第二區 123a第一外周壁 1 31 開口 141第一頂面 150導接層 W2鎳層 154第三外周壁 161第一保護環 162第二保護環 100117669 表單編號A0101 第10頁/共21頁 1002029703-0 201248804 162a第二環壁 D1 | D2 第二間距 L1第 L2 第二外周長 L3 % S 容置空間 S1第 S2 第二容置部 一間距 一外周長 三外周長 一容置部 Ο 100117669 表單編號Α0101 第11頁/共21頁 1002029703-0And a second accommodating portion S2 corresponding to the first outer peripheral wall 142 of the shai; and then, referring to FIG. 21, a second protective layer 16 is formed on the second top surface 151 of the guiding layer 15? The first outer peripheral wall 123a of the under bump metal layer 123, the second outer peripheral walls 42 of the copper bumps 140, the third outer peripheral wall 154 of the conductive layer 150, the first The protective layer 113, the first accommodating portion S1 and the second accommodating portion S2, the second protective layer 160 may be selected from one of an oxide or a nitride. In the embodiment, the nitride system It can be a dream, the oxide system can be a sulphur dioxide eve; finally, please refer to FIG. 2J to remove the second top surface 151 of the conductive layer 15 、, the conductive layer 150 The third outer peripheral wall 154 and the second protective layer 160 of the first protective layer 113 are such that the second protective layer 16 located in the first receiving portion 81 is opened and formed into a first guard ring 161, and is located The second protective layer 16 of the second accommodating portion 〇 forms a second guard ring 162 to form a bump structure 100, and the first guard ring 161 is connected to the second guard ring 16 2 . The first receiving portions 161 surrounding the plurality of copper bumps 14 are formed by the first receiving portions 161. The second receiving portions S2 surrounding the copper bumps 14 are formed. The second protection ring 162, the first outer peripheral wall 123a of the under bump metal layer 123 and the second outer peripheral walls 142 of the copper bumps 140 are not exposed, so that copper ions can be prevented from being released. And the situation caused by a short circuit. Preferably, in the present embodiment, the first guard ring 61 has a first ring wall 161a, and the second guard ring 162 has a second ring wall 162a, the first ring wall 161a, the first The second ring wall 162a and the third outer peripheral wall 154 are flush. The scope of the present invention is defined by the scope of the appended claims, and any person skilled in the art, without departing from the spirit of the invention, 100117669, Form No. A0101, Page 9 of 21, 1002029703-0 201248804 And any changes and modifications made in the scope are within the scope of this report. [Simple Description of the Drawings] [0005] Figures 1A to 1H: Schematic diagram of the wearing of the conventional bump process. 2A to 21®. A schematic cross-sectional view of a & block process in accordance with a preferred embodiment of the present invention. [Major component symbol description] 10 substrate 12 pad 20 containing copper metal layer 21 a second outer peripheral wall 31 opening 41 first outer peripheral wall 100 bump structure 111 surface 113 first protective layer 121 first region 123 bump Lower metal layer 130 photoresist layer 140 copper bump 142 second outer peripheral wall 151 second top surface 153 bonding layer 160 second protective layer 161a first ring wall 11 surface U protective layer 21 under bump metal layer 3 〇 photoresist layer 40 copper bump 5 〇 conductive layer 110 substrate 112 pad 12 〇 copper-containing metal layer 122 second region 123a first outer peripheral wall 1 31 opening 141 first top surface 150 conductive layer W2 nickel layer 154 third outer peripheral wall 161 First guard ring 162 second guard ring 100117669 Form No. A0101 Page 10 / Total 21 page 1002029703-0 201248804 162a Second ring wall D1 | D2 Second pitch L1 L2 Second outer perimeter L3 % S accommodating space S1 S2 Second accommodating part: one pitch, one outer circumference, three outer circumferences, one accommodating part Ο 100117669 Form No. 1010101, Page 11 of 21, 1002029703-0

Claims (1)

201248804 七、申請專利範圍: 1 . 一種凸塊製程,其至少包含: 提供一基板,該基板係具有一表面、複數個銲墊及一第一 保護層’該些銲墊係設置於該表面,該第一保護層係形成 於該表面並顯露該些銲墊; 形成一含銅金屬層於些銲墊及該第一保護層,該含銅金屬 層係具有複數個第一區及複數個第二區; 形成—光阻層於該含銅金屬層; 圖案化該光阻層以形成複數個開口,該些開口係對應該些 第一區; 形成複數個銅凸塊於該些開口内,各該銅凸塊係覆蓋該含 銅金屬層之各該第一區且各該銅凸塊係具有一第一頂面; 形成一導接層於該些銅凸塊之該些第—頂面,該導接層係 具有一第二頂面且該導接層係包含有一鎳層及一接合層, 該鎳層係位於該銅凸塊與該接合層之間; 移除該光阻層; 移除該含銅金屬層之該些第二區以顯露出該第一保護層, 並使該含銅金屬層之各該第一區形成—凸塊下金屬層其 中各該凸塊下金屬層係具有一第一外周壁,各該銅凸塊係 具有一第二外周壁,該導接層係具有一第三外周壁,該第 二外周壁與該第一外周壁之間係具有一第一間距,該第三 外周壁與該第一外周壁之間係具有—第二間距且該導接層 及該第一保護層之間係具有一容置空間,該容置空間係環 繞該第一外周壁及該第二外周壁’且該容置空間係具有一 對應於該第一外周壁之第一容置部及—對應於該第二外周 100117669 表單編號A0101 第12頁/共21頁 1002029703-0 201248804 壁之第二容置部; 形成一第二保護層於該導接層之該第二頂面、該些凸塊下 金屬層之該些第一外周壁'該些銅凸塊之該些第二外周壁 、該導接層之該第三外周壁、該第一保護層、該第一容置 部及該第二容置部;以及 移除位於該導接層之該第二頂面、該導接層之該第三外周 壁及該第一保護層之該第二保護層,以使位於該第一容置 部之該第二保護層形成一第一保護環及使位於該第二容置 部之該第二保護層形成一第二保護環。 2 .如申請專利範圍第1項所述之凸塊製程,其中該第三外周 壁係具有一第三外周長,該第二外周壁係具有一第二外周 長,該第一外周壁係具有一第一外周長,該第三外周長係 大於該第二外周長,該第二外周長係不小於該第一外周長 〇 3 .如申請專利範圍第1項所述之凸塊製程,其中該第二間距 係不小於該第一間距。 4 .如申請專利範圍第1項所述之凸塊製程,其中該第二保護 層係選自於氧化物或氮化物其中之一。 5 .如申請專利範圍第4項所述之凸塊製程,其中該氮化物係 可為氮化矽、氮氧化矽或其混合體其中之一。 6 .如申請專利範圍第4項所述之凸塊製程,其中該氧化物係 可為二氧化矽、氮氧化矽或其混合體其中之一。 7 .如申請專利範圍第1項所述之凸塊製程,其中該第一保護 環係具有一第一環壁,該第二保護環係具有一第二環壁, 該第一環壁、該第二環壁及該第三外周壁係為平齊。 8 . —種凸塊結構,其至少包含: 100117669 表單編號A0101 第13頁/共21頁 1002029703-0 201248804 一基板,其係具有一表面、複數個銲墊及一第一保護層, 該些銲墊係設置於該表面,該第一保護層係形成於該表面 並顯露該些銲墊; 複數個凸塊下金屬層,各該凸塊下金屬層係具有一第一外 周壁; 複數個銅凸塊,其係形成於該些凸塊下金屬層上,各該銅 凸塊係具有一第一頂面及一第二外周壁; 一導接層,其係形成於該些銅凸塊之該些第一頂面,該導 接層係具有一第二頂面及一第三外周壁,且該導接層係包 含有一鎳層及一接合層,該鎳層係位於該銅凸塊與該接合 層之間,其中該第三外周壁與該第二外周壁之間係具有一 第一間距,該第三外周壁與該第一外周壁之間係具有一第 二間距且該導接層及該第一保護層之間係具有一容置空間 ,該容置空間係環繞該第一外周壁及該第二外周壁,且該 容置空間係具有一對應於該第一外周壁之第一容置部及一 對應於該第二外周壁之第二容置部; 一第一保護環,其係形成於該第一容置部;以及 一第二保護環,其係形成於該第二容置部。 9 .如申請專利範圍第8項所述之凸塊結構,其中該第一保護 環係連接該第二保護環。 10 .如申請專利範圍第8項所述之凸塊結構,其中該第一保護 環係具有一第一環壁,該第二保護環係具有一第二環壁, 該第一環壁、該第二環壁及該第三外周壁係為平齊。 100117669 表單編號A0101 第14頁/共21頁 1002029703-0201248804 VII. Patent application scope: 1. A bump process comprising at least: providing a substrate having a surface, a plurality of pads and a first protective layer, wherein the pads are disposed on the surface The first protective layer is formed on the surface and exposes the solder pads; forming a copper-containing metal layer on the solder pads and the first protective layer, the copper-containing metal layer having a plurality of first regions and a plurality of a second region; forming a photoresist layer on the copper-containing metal layer; patterning the photoresist layer to form a plurality of openings, the openings corresponding to the first regions; forming a plurality of copper bumps in the openings Each of the copper bumps covers each of the first regions of the copper-containing metal layer and each of the copper bumps has a first top surface; forming a conductive layer on the first top surfaces of the copper bumps The guiding layer has a second top surface and the guiding layer comprises a nickel layer and a bonding layer, the nickel layer is located between the copper bump and the bonding layer; removing the photoresist layer; Removing the second regions of the copper-containing metal layer to expose the first protective layer, And forming, in each of the first regions of the copper-containing metal layer, a lower under bump metal layer, wherein each of the under bump metal layers has a first outer peripheral wall, each of the copper bumps having a second outer peripheral wall, The guiding layer has a third outer peripheral wall having a first spacing between the second outer peripheral wall and the first outer peripheral wall, and a second spacing between the third outer peripheral wall and the first outer peripheral wall And the accommodating space surrounds the first outer peripheral wall and the second outer peripheral wall ′ and the accommodating space has a corresponding to the first a first receiving portion of the outer peripheral wall and corresponding to the second outer circumference 100117669 Form No. A0101 Page 12 / 21 pages 1002029703-0 201248804 Second receiving portion of the wall; forming a second protective layer on the guiding The second top surface of the layer, the first outer peripheral walls of the under bump metal layers, the second outer peripheral walls of the copper bumps, the third outer peripheral wall of the conductive layer, the first a protective layer, the first receiving portion and the second receiving portion; and removing the first portion located in the guiding layer a second top surface, the third outer peripheral wall of the conductive layer, and the second protective layer of the first protective layer, so that the second protective layer located in the first receiving portion forms a first protective ring and The second protective layer located in the second receiving portion forms a second guard ring. 2. The bump process of claim 1, wherein the third outer peripheral wall has a third outer perimeter, the second outer peripheral wall having a second outer perimeter, the first outer peripheral wall having a first outer perimeter, the third outer perimeter being greater than the second outer perimeter, the second outer perimeter being no less than the first outer perimeter 〇3. The bump process of claim 1 wherein The second spacing is not less than the first spacing. 4. The bump process of claim 1, wherein the second protective layer is selected from one of an oxide or a nitride. 5. The bump process of claim 4, wherein the nitride is one of tantalum nitride, hafnium oxynitride or a mixture thereof. 6. The bump process of claim 4, wherein the oxide is one of cerium oxide, cerium oxynitride or a mixture thereof. 7. The bump process of claim 1, wherein the first guard ring has a first ring wall, the second guard ring has a second ring wall, the first ring wall, the first ring wall The second annular wall and the third peripheral wall are flush. 8. A bump structure comprising at least: 100117669 Form No. A0101 Page 13 of 21 1002029703-0 201248804 A substrate having a surface, a plurality of pads and a first protective layer, the solder a pad is disposed on the surface, the first protective layer is formed on the surface and the pads are exposed; a plurality of under bump metal layers, each of the under bump metal layers having a first peripheral wall; a plurality of copper a bump formed on the underlying metal layer, each of the copper bumps having a first top surface and a second outer peripheral wall; a conductive layer formed on the copper bumps The first top surface, the guiding layer has a second top surface and a third outer peripheral wall, and the guiding layer comprises a nickel layer and a bonding layer, and the nickel layer is located on the copper bump Between the bonding layers, wherein the third outer peripheral wall and the second outer peripheral wall have a first spacing, the third outer peripheral wall and the first outer peripheral wall have a second spacing and the guiding Between the layer and the first protective layer, there is an accommodating space, and the accommodating space is surrounded a first outer peripheral wall and the second outer peripheral wall, and the accommodating space has a first accommodating portion corresponding to the first outer peripheral wall and a second accommodating portion corresponding to the second outer peripheral wall; a guard ring formed on the first receiving portion; and a second guard ring formed in the second receiving portion. 9. The bump structure of claim 8, wherein the first guard ring is connected to the second guard ring. 10. The bump structure of claim 8, wherein the first guard ring has a first ring wall, the second guard ring has a second ring wall, the first ring wall, the first ring wall The second annular wall and the third peripheral wall are flush. 100117669 Form No. A0101 Page 14 of 21 1002029703-0
TW100117669A 2011-05-20 2011-05-20 Bumping process and structure thereof TWI440150B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW100117669A TWI440150B (en) 2011-05-20 2011-05-20 Bumping process and structure thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW100117669A TWI440150B (en) 2011-05-20 2011-05-20 Bumping process and structure thereof

Publications (2)

Publication Number Publication Date
TW201248804A true TW201248804A (en) 2012-12-01
TWI440150B TWI440150B (en) 2014-06-01

Family

ID=48138829

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100117669A TWI440150B (en) 2011-05-20 2011-05-20 Bumping process and structure thereof

Country Status (1)

Country Link
TW (1) TWI440150B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9177830B1 (en) 2014-07-25 2015-11-03 Chipbond Technology Corporation Substrate with bump structure and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9177830B1 (en) 2014-07-25 2015-11-03 Chipbond Technology Corporation Substrate with bump structure and manufacturing method thereof

Also Published As

Publication number Publication date
TWI440150B (en) 2014-06-01

Similar Documents

Publication Publication Date Title
TWI305378B (en) Die seal structure for reducing stress induced during die saw process
US20210202437A1 (en) Package structure and manufacturing method thereof
JP6108698B2 (en) Method for manufacturing solid-state imaging device
TW200705632A (en) Method for forming high reliability bump structure
TW200605225A (en) Methods for fabricating pad redistribution layer and copper pad redistribution layer
CN102306635A (en) Semiconductor apparatus and manufacturing method thereof
TW200719420A (en) Bump structures and methods for forming solder bumps
US10817700B2 (en) Optical fingerprint recognition chip package and packaging method
TWM410659U (en) Bump structure
CN101057324B (en) Semiconductor device and method for manufacturing semiconductor device
CN102867757A (en) UBM etching methods for eliminating undercut
TW201248804A (en) Bumping process and structure thereof
JP2011114133A (en) Semiconductor device, and method of manufacturing the same
KR20150000040A (en) Thin film transistor substrate and Method of manufacturing the same
JP2008172060A (en) Semiconductor device and its manufacturing method
JP2005285853A (en) Semiconductor wafer, manufacturing method thereof, and manufacturing method of semiconductor device
TW201005826A (en) Semiconductor device, semiconductor chip, manufacturing methods thereof, and stack package
EP1925028B1 (en) Protective barrier layer for semiconductor device electrodes
JP6178561B2 (en) Method for manufacturing solid-state imaging device
CN107342261B (en) Semiconductor device and method for manufacturing the same
CN102800599B (en) Projection process and structure thereof
US9711469B2 (en) Semiconductor structure having recess and manufacturing method thereof
TW201203338A (en) Semiconductor device and manufacturing method therefor
TWI511246B (en) Bumping process and structure thereof
TWM397681U (en) Circuit board with a removing area