201248352 六、發明說明： 【發明所屬之技術領域】 本發明相關於一種校正訊號偏移的方法及相關傳輸系 統’尤指一種校正行動產業處理器介面中訊號偏移的方法及 相關傳輸系統。 【先前技術】 隨著科技的演進，電子資訊產品需要使用高速串列傳輸 技術來支援越來越大的資料傳輸量，例如使用移動產業處理 器介面（Mobile Industry Processor Interface，MIPI )、行動顯 示數位介面（Mobile Display Digital Interface, MDDI)及通 用序列匯流排（Universal Serial Bus，USB)等傳輸技術。其 中’ MIPI規定了一個差分時脈通道(clock lane)和可擴展（數 量從一個到四個）的資料通道(data lane)，可根據處理器和周 邊f求來調節資料速率，並被廣泛地應用在智慧型手機或個 人數位助理（Personal Digital Assistant，PDA)等手持裝置。 第1圖為先前技術中一傳輸系統之示意圖。傳輸系統 10採用四資料通道之MIPI，其包含有一主控端（host side) 電路HS、傳輸通道200〜204，以及一用戶端（client side) 電路CS。主控端電路HS包含有傳送電路110〜114 ’分別 用來傳送一時脈訊號CLK及資料訊號DATA1〜DATA4。用 201248352 戶端電路CS包含有接收電路310〜314,分別用來接收時脈 訊號CLK及資料訊號DATA1〜DATA4。傳送電路11〇〜114 分別透過傳輸通道200〜204來將時脈訊號CLK及資料訊號 DATA1〜DATA4傳送至接收電路310〜314。 第2A〜2D圖為先前技術傳輸系統10運作時之訊號圖， 顯示了時脈訊號CLK和資料訊號DATA1〜DATA4之波形。 用戶端電路CS會在時脈訊號CLK之上升邊緣或下降邊緣讀 取資料訊號DATA1〜DATA4。建立時間（setup time ) Ts為 時脈訊號CLK之上升邊緣和資料訊號DATA1〜DATA4之上 升邊緣之間的最短時間，或是時脈訊號CLK之下降邊緣和 資料訊號DATA1〜DATA4之下降邊緣之間的最短時間。保 持時間（hold time) TH為時脈訊號CLK之上升邊緣和資料 訊號DATA1〜DATA4之下降邊緣之間的最短時間，或是時 脈訊號CLK之下降邊緣和資料訊號DATA1〜DATA4之上升 邊緣之間的最短時間。 在理想情況下，時脈訊號CLK和資料訊號DATA1之相 位平衡，亦即TS=TH，如第2A圖所示。然而在實際應用上， 可此因為傳輸通道200〜204的長度或負載不對稱、傳送電 路110〜114的輸出不對稱、接收電路31〇〜314的負载不對 稱，或是主控端電路HS及用戶端電路CS之間存在之阻抗 不連續等種種因素，MIDI中存在偏移（skew )，造成時脈訊 201248352 號CLK及資料訊號DATA1〜DATA4到達用戶端電路cs的 時間不相同。舉例來說，時脈訊號CLK之相位可能會領先 資料訊號DATA2(TS<TH)，如第2B圖所* ;時脈訊號CLK 之相位可能會落後資料訊號DATA3 (TS>TH)，如第2C圖所 不；時脈訊號CLK和資料訊號DATA4之相位差可能會大於 單位週期UI(Ts<〇)，如第犯圖所示。 —在實際應用中，MIDI通常包含複數個資料傳輸通道， 3脈訊號與複數筆資料訊號間存在不同程度的相位領先 s、落後在時脈訊號頻率逐漸提升的趨勢下，訊號偏移的容 曰二間（建立時間Ts和保持時間TH)越來越窄，因此容易 導致貝料操取錯誤。為了維持資料傳輸的正確率，需要 杈正MIPI中訊號偏移之方法。 【發明内容】 本發明提供—種校正一行動產業處理器介面中訊號偏移 方法，包含有在—校正模式下，透過該行動產業處理器 —次夺脈通道和—資料通道分別傳送一時脈訊號和一 庫:整該時脈訊號和該第一資料訊號之相位以分 才對應之-測試時旅訊號和一第一 脈訊號來_第-測試資心t第依 該資料If 據4第—擷取資料求出對應於該時脈通道洋 一最佳相位關係;以及在-正常模式下傳送; 201248352 時脈訊號和該㈣訊號時，依據該最佳相位_來調整該時 脈通道和該龍通道之訊號延遲。 纟本&日^提供—種使用一行動產業處理器介面之傳輸系 充” 一主控i^電路，用來透過該行動產業處理器介 面，Γ第一通道和1二通道分別傳送一時脈訊號和一資 料心虎’、肖戶端電路，用來依據—最佳相位關係來調整該 第一通道和該第二通道之減延遲，其包含-接收電路，用 來接收A時脈訊號和該資料訊號；—校正電路，用來調整該 時脈訊號和該資料訊號之相位以分別提供相對應之一測試 時脈sfl號和一測试資料訊號、依據該測試時脈訊號來擷取該 測試資料訊號以得到一擷取資料，並依據該擷取資料求出該 最佳相位關係。 【實施方式】 第3A圖為本發明實施例一傳輸系統20之示意圖。傳輸 系統20採用四資料通道之MIPI ’包含有一主控端電路HS、 傳輸通道200〜204及一用戶端電路CS。主控端電路HS包 含有傳送電路110〜114，分別用來傳送一時脈訊號CLK及 資料訊號DATA1〜DATA4。用戶端電路CS包含有接收電路 310〜314和一校正電路300，接收電路310〜314分別用來 接收時脈訊號CLK及資料訊號DATA1〜DATA4，而校正電 路300用來校時脈訊號CLK及資料訊號DATA1〜DATA4之 201248352 間的訊號偏移。傳送電路110〜114各包含兩低功率傳送器 LP—ΤΧ和一高速傳送器HS_TX，而接收電路310〜314各包 含兩低功率接收器LP_RX和一高速接收器HS__RX。低功率 傳送器LP_TX和低功率接收器LP__RX可處理低功率狀態之 單端（singled-ended )訊號，高速傳送器HS_TX和高速接收 器HS_RX則可處理南速之差動（differential )訊號。因此， 傳送電路110〜114可分別透過傳輸通道2〇〇〜204將序列差 動時脈訊號CLK及資料訊號DATA1〜DATA4傳送至接收電 路 310〜314 。 第3B圖為本發明實施例之傳輸系統2〇中校正電路3〇〇 之功能方塊圖。校正電路300包含延遲單元DLO〜DL4、序 列至並列（serial-to-parallel)轉換單元S2P1〜S2P4、一除頻 器CD、一儲存單元320、一比較單元33〇、一計算單元34〇， 以及一控制單元350。校正電路300可對時脈訊號CLK或資 料訊號DATA1〜DATA4進行不同程度的訊號延遲’再求出 每一通道的資料正確區域（pass z〇ne )，進而求出每一通道 之最佳延遲時間。 第4圖為校正電路300運作時之流程圖，其包含下列步 驟： 步驟410 :進入校準模式，執行步驟420。 步驟420 :求出一偏移校準表，執行步驟43〇。 201248352 步驟430··依#料校準表求出對應於每—通道之資料正 確區域，執行步驟44〇。 步驟44〇:依據每—咨粗τ ^ 貝科正確區域判斷相對應之通道是否 杈正成功；若是，執行步驟450 ;若否，執行 步驟470。 步驟450.求出每一資粗下遗, ^貢科正確區域之中心點，並依此求出 母一通道之最佳相位關係，執行步驟460。 步驟460:進入正常模式，並依據每一通道之最佳相位關 係來調整時脈訊號或相對應資料訊號之相位。 步驟470 .判定校正失敗。 在步驟410進入校準模式後，延遲單元DL〇〜DL4可分 別提供時脈訊號CLK及資料訊號DATA1〜DATA4不同程度 的说號延遲。在不同訊號延遲條件下，時脈訊號CLK和資 料訊號DATA1〜DATA4之間的相位關係如第5圖所示。在 此實施例中，延遲單元DL0〜DL4可提供31組偏移調整階 段S0〜S30 :偏移調整階段S0代表時脈訊號和資料訊號皆 延遲0個單位時間Td ;偏移調整階段si〜S15代表時脈訊 號分別延遲1〜15個單位時間Td，而資料訊號DATA1〜 DATA4皆延遲〇個單位時間Td;偏移調整階段S16〜s3〇 代表時脈訊號延遲〇個單位時間Td，而資料訊號Datai〜 DATA4各分別延遲1〜15個單位時間Td。每一偏移調整階 丰又白對應至一特定時脈延遲索引（_ 15〜15之間的整數）。 201248352 第6A〜6D圖為在不同訊號延遲條件下之訊號圖。為了 說明方面，僅以時脈訊號CLK和資料訊號DATA1為例。第 6A和6B圖顯示了在偏移調整階段S0〜S15内各訊號之時序 圖，而第6C和6D圖顯示了在偏移調整階段SO、S16〜S30 内各訊號之時序圖。 在第6A圖所示之實施例中，主控端電路HS會透過傳送 電路110傳送時脈訊號CLK至用戶端電路CS之接收電路 310，且透過傳送電路111傳送「01010101」之資料訊號 DATA1至用戶端電路CS之接收電路311。接著，延遲單元 DL0會以0個單位時間Td來延遲時脈訊號CLK，延遲單元 DL1會分別以0〜15個單位時間Td來延遲資料訊號 DATA1，進而提供一測試時脈訊號CLK0’和16筆測試資料 訊號DT0’〜DT15’。用戶端電路CS可在測試時脈訊號 CLK’之上升/下降邊緣擷取測試資料訊號DT0，〜DT15’， 從每一測試資料訊號可擷取到8個序列位元BT1〜BT8，再 透過序列至並列轉換單元S2P1分別匯整為並列資料DP0〜 DP15。 在第6B圖所示之實施例中，主控端電路HS會透過傳送 電路110傳送時脈訊號CLK至用戶端電路CS之接收電路 310,且透過傳送電路111傳送「00110011」之資料訊號DATA1 11 201248352 至用戶端電路CS之接收電路311。接著，延遲單元dl〇會 以〇個單位時間Td來延遲時脈訊號CLK，延遲單元DL1會 分別以0〜15個單位時間Td來延遲資料訊號DATA1，進而 提供一測試時脈訊號CLK0’和16筆測試資料訊號DT0，〜 DT15,。用戶端電路CS可在測試時脈訊號CLK，之上升/下 降邊緣擷取測试資料訊號DT0’〜Π)Τ15，，從每一測試資料 訊號可擷取到8個序列位元ΒΤ1〜ΒΤ8，再透過序列至並列 轉換單元S2P1分別匯整為並列資料DP0〜DP15。 在第6C圖所示之實施例中，主控端電路Hs會透過傳送 電路110傳送時脈訊號CLK至用戶端電路cs之接收電路 31〇，且透過傳送電路111傳送「〇1〇1〇1〇1」之資料訊號 DATA1呈用戶端電路CS之接收電路311。接著，延遲單元 DL0會分別以〇〜15個單位時間Td來延遲時脈訊號CLK， 延遲單元DL1會以〇個單位時間Td來延遲資料訊號 DATA1，進而提供16筆測試時脈訊號CLK0,〜CLK15,和 -測試資料訊號謂，。戶端電路Cs可在測試時脈訊號 CLK0〜CLK15之上升/下降邊緣擷取測試資料訊號DT〇，， 依據每〆測試時脈訊號CLK0,〜CLK15,可分別擷取到8個 序列位元BT1〜BT8，再透過序列至並列轉換單元S2pl分 別匯整為並列資料DP0〜DP15。 在第6D圖所示之實施例中’主控端電路Hs會透過傳送 1 12 201248352 電路110傳送時脈訊號CLK至用戶端電路CS之接收電路 310，且透過傳送電路111傳送「00110011」之資料訊號〇八丁八1 至用戶端電路CS之接收電路311。接著，延遲單元DL0會 依序以0〜15個單位時間Td來延遲時脈訊號CLK，延遲單 元DL1會以〇個單位時間Td來延遲資料訊號DATA1，進而 提供16筆測試時脈訊號CLK0，〜CLK15,和一測試資料訊 號DT0’。用戶端電路CS可在測試時脈訊號CLK0，〜 CLK15’之上升/下降邊緣擷取測試資料訊號DT0’，依據每 一測試時脈訊號CLK0’〜CLK15,可分別擷取到8個序列位 元BT1〜BT8，再透過序列至並列轉換單元S2P1分別匯整 為並列資料DP0〜DP15。 第7圖為匯整第6A〜6D圖結果之圖表。比較單元33〇 可比較每一筆擷取資料和相對應期待資料之值，再依此產生 對應於每一偏移調整階段和不同值資料訊號之比較結果 和R2。如比較結果R1顯示，「01010101」資料訊號DATA1 在經過偏移調整階段S0〜S30處理後，會包含兩個資料正確 區域’亦即時脈延遲索引-6〜3之間和14〜15之間；如比較 結果R2顯示，「00110011」資料訊號DATA1在經過偏移調 整階段S0〜S30處理後，會包含單一資料正確區域，亦即時 脈延遲索引-6〜3之間。在決定最佳相位關係時，複數個資 料正確區域會增加判斷難度。因此，本發明之比較電路會對 R1和R2執行特定邏輯運算’例如執行AND運算（R1&R2) 13 201248352 可確保每一期待資料只有單一資料正確區域。針對每一偏移 調整階段，本發明可依據一特定資料訊號之結果（R1或R2) 來決定最佳相位關係；或者，本發明可同時依據不同特定資 料訊號之結果（R1和R2)來決定最佳相位關係。 第8A〜8B圖和第9A〜9B圖說明了本發明校正電路300 執行步驟420〜470時之運作。第6A〜6D圖和第7圖所示 前述實施例以資料訊號DATA1來作說明，在以相同方式對 資料訊號DATA2〜DATA4經過偏移調整階段S0〜S30處理 後，可在步驟420求出一偏移校準表，並將其存入儲存單元 320。 第8A圖和第9A圖顯示了兩種情況下得到的偏移校準 表。REG1〜4為儲存單元310内之32位元暫存器，分別用 來儲存傳輸通道201〜204之校準結果，其中”1”代表資料正 確區域，而”0”代表資料錯誤區域。 在第8B圖和第9B圖中，步驟431〜439為計算單元340 執行步驟430之運作，其詳細步驟說明如下： 步驟431 :將暫存器REG1〜REG4内存資料D1 ( A)〜 D4 (A)向右平移一位元，以分別得到資料 D1(B)〜D4(B)。 步驟432 :將資料D1 ( A)〜D4( A)分別和資料D1 (B) 14 201248352 〜D4(B)進行AND運算，以分別得到資料 D1(C)〜D4(C)〇 步驟433 :將資料D1 (c)〜D4 (c)向右平移一位元， 以分別得到資料D1 ( D )〜〇4 ( D )。 步驟物：將資料D1(C)〜D4(C)分別和資料m⑼ 〜D4(D)進行X0R運算，以分別得到資料 D1 (E)〜D4 (E)。 步驟435:將資料D1 (E)〜D4(E)向左平移一位元， 以分別得到資料D1 (F)〜D4 (F)。 在步驟440中，本發明會計算資料D1 (F)〜D4⑺ =有位元之總值嶋。若讀為2則判定校正成功，接 者執订步驟450以依據資料D1 (F)〜D4(f)中 ==對應中心點，並依此求出每一通道如 二=8A〜8B圖所示；若SUM不為2則會執行步驟47〇 州疋权正失敗，如第9Λ和9B圖所示。 中可在求出每-通道之最佳相位關係後，本發明在步驟偏 時模式’ ^依據每—通道之最佳相位關係來調整 子脈讯諕或相對應資料訊號之相位。 定值傳輸通道，本發明可針對—個或多個特 之續訊切柯㈣段的偏移輕，再求 、之最佳相位_'，因此驗據每—通道之 : 15 201248352 來調整時脈訊號或相對應資料訊號之相位。 綜上所述，在非理想傳輸環境下，即使MIDI中每一通道 存在不同程度的訊號偏移，本發明能同步所有訊號的時序， 進而確保資料讀取之正確性。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為先前技術中一傳輸系統之示意圖。 第2A〜2D圖顯示了先前技術之傳輸系統運作時之訊號圖。 第3A圖為本發明實施例中一傳輸系統之示意圖。 第3B圖為本發明實施例之傳輸系統中一校正電路之功能方 塊圖。 第4圖為本發明實施例之校正電路運作時之流程圖。 第5圖為在不同訊號延遲條件下時脈訊號和資料訊號之間的 相位關係。 第6A〜6D圖為在不同訊號延遲條件下校正結果之訊號圖。 第7圖為匯整第6A〜6D圖結果之圖表。 第8A〜8B圖和第9A〜9B圖為本發明實施例之校正電路運 作時之示意圖。 16 201248352 【主要元件符號說明】 10 ' 20 傳輸系統 300 校正電路 320 儲存單元 330 比較單元 340 計算單元 350 控制單元 200〜204 傳輸通道 110〜114 傳送電路 310 〜314 接收電路 200〜204 傳輸通道 CD 除頻器 HS 主控端電路 CS 用戶端電路 LPTX 低功率傳送器 HS_TX 高速傳送器 LPRX 低功率接收器 HS_RX 高速接收器 DLO 〜DL4 延遲單元 S2P1〜S2P4 序列至並列轉換單元 410〜470 步驟 17201248352 VI. Description of the Invention: [Technical Field] The present invention relates to a method for correcting signal offset and related transmission system, particularly a method for correcting signal offset in a mobile industry processor interface and a related transmission system. [Prior Art] With the evolution of technology, electronic information products need to use high-speed serial transmission technology to support the increasing volume of data transmission, such as the use of mobile industry processor interface (MIPI), mobile display digital Transmission technologies such as the Mobile Display Digital Interface (MDDI) and the Universal Serial Bus (USB). Among them, 'MIPI specifies a differential clock lane and a scalable data lane from one to four, which can adjust the data rate according to the processor and peripheral requirements, and is widely used. It is used in handheld devices such as smart phones or personal digital assistants (PDAs). Figure 1 is a schematic diagram of a transmission system of the prior art. The transmission system 10 employs four data channel MIPIs including a host side circuit HS, transmission channels 200-204, and a client side circuit CS. The main control circuit HS includes transmission circuits 110 to 114' for transmitting a clock signal CLK and data signals DATA1 to DATA4, respectively. The 201248352 terminal circuit CS includes receiving circuits 310 to 314 for receiving the clock signal CLK and the data signals DATA1 to DATA4, respectively. The transmission circuits 11A to 114 transmit the clock signal CLK and the data signals DATA1 to DATA4 to the receiving circuits 310 to 314 through the transmission channels 200 to 204, respectively. 2A to 2D are signal diagrams of the prior art transmission system 10, showing waveforms of the clock signal CLK and the data signals DATA1 to DATA4. The client circuit CS reads the data signals DATA1 to DATA4 at the rising edge or the falling edge of the clock signal CLK. Setup time Ts is the shortest time between the rising edge of the clock signal CLK and the rising edge of the data signals DATA1~DATA4, or between the falling edge of the clock signal CLK and the falling edge of the data signals DATA1~DATA4. The shortest time. The hold time TH is the shortest time between the rising edge of the clock signal CLK and the falling edge of the data signals DATA1 to DATA4, or between the falling edge of the clock signal CLK and the rising edge of the data signals DATA1 to DATA4. The shortest time. In an ideal case, the phase of the clock signal CLK and the data signal DATA1 are balanced, that is, TS = TH, as shown in Fig. 2A. However, in practical applications, the length or load of the transmission channels 200 to 204 may be asymmetric, the output of the transmission circuits 110 to 114 may be asymmetric, the load of the receiving circuits 31 to 314 may be asymmetric, or the main control circuit HS and There are various factors such as the discontinuity of impedance between the user circuit CS, and there is a skew in the MIDI, which causes the time of the CLK of the clock No. 201248352 and the data signals DATA1 DATA4 to reach the user circuit cs. For example, the phase of the clock signal CLK may lead the data signal DATA2 (TS < TH), as shown in Figure 2B; the phase of the clock signal CLK may be behind the data signal DATA3 (TS > TH), such as the 2C The phase difference between the clock signal CLK and the data signal DATA4 may be greater than the unit period UI (Ts < 〇), as shown in the first map. - In practical applications, MIDI usually contains a plurality of data transmission channels. There are different degrees of phase lead between the 3-pulse signal and the complex data signals, and the signal frequency is gradually increased under the trend of increasing the frequency of the clock signal. The two rooms (the settling time Ts and the holding time TH) are getting narrower and narrower, so it is easy to cause errors in the operation of the bedding. In order to maintain the correct rate of data transmission, it is necessary to correct the signal offset in MIPI. SUMMARY OF THE INVENTION The present invention provides a method for correcting a signal offset in a mobile industry processor interface, including transmitting, in an in-correction mode, a clock signal through the mobile industry processor-second pulse channel and data channel, respectively. And a library: the phase of the clock signal and the first data signal are corresponding to each other - the test time travel signal and a first pulse signal _ the first test traits t according to the data If the data is 4 Extracting data to determine the optimal phase relationship corresponding to the clock channel; and transmitting in the normal mode; and transmitting the clock channel and the dragon according to the optimal phase_ when transmitting the 201248352 clock signal and the (four) signal The signal delay of the channel.纟本&日^ provides a transmission system that uses a mobile industry processor interface. A master i^ circuit is used to transmit a clock through the mobile industry processor interface, the first channel and the second channel. a signal and a data heart, a Xiaohuo terminal circuit for adjusting the delay of the first channel and the second channel according to an optimal phase relationship, the inclusion-receiving circuit for receiving the A clock signal and The data signal is used to adjust the phase of the clock signal and the data signal to provide a corresponding test clock sfl number and a test data signal, respectively, according to the test clock signal The data signal is tested to obtain a data, and the optimal phase relationship is obtained according to the data. Embodiment 3A is a schematic diagram of a transmission system 20 according to an embodiment of the present invention. The transmission system 20 uses four data channels. The MIPI 'includes a master terminal circuit HS, transmission channels 200 to 204, and a subscriber circuit CS. The master terminal circuit HS includes transmission circuits 110 to 114 for transmitting a clock signal CLK and The signal DATA1~DATA4. The client circuit CS includes receiving circuits 310-314 and a correction circuit 300. The receiving circuits 310-314 are respectively used for receiving the clock signal CLK and the data signals DATA1 DATA DATA4, and the correction circuit 300 is used for calibration. The signal offset between the clock signal CLK and the data signal DATA1~DATA4 between 201248352. The transmission circuits 110-114 each include two low power transmitters LP-ΤΧ and one high-speed transmitter HS_TX, and the receiving circuits 310-314 each include two lows. Power receiver LP_RX and a high speed receiver HS__RX. Low power transmitter LP_TX and low power receiver LP__RX can handle single-ended (singled-ended) signals in low power state, high speed transmitter HS_TX and high speed receiver HS_RX can handle south The differential signals are transmitted. Therefore, the transmitting circuits 110 to 114 can transmit the sequence differential clock signal CLK and the data signals DATA1 to DATA4 to the receiving circuits 310 to 314 through the transmission channels 2 to 204, respectively. The figure is a functional block diagram of the correction circuit 3〇〇 in the transmission system 2〇 of the embodiment of the invention. The correction circuit 300 includes delay units DLO~DL4, sequence to juxtaposition The serial-to-parallel conversion units S2P1 to S2P4, a frequency divider CD, a storage unit 320, a comparison unit 33A, a calculation unit 34A, and a control unit 350. The correction circuit 300 can be used for the clock signal CLK. Or the data signals DATA1~DATA4 perform different signal delays' and then find the correct data area (pass z〇ne) of each channel, and then find the optimal delay time of each channel. FIG. 4 is a flow chart of the operation of the correction circuit 300, which includes the following steps: Step 410: Enter the calibration mode and perform step 420. Step 420: Find an offset calibration table and perform step 43. 201248352 Step 430 · According to the material calibration table, find the correct data area corresponding to each channel, and perform step 44〇. Step 44: Determine whether the corresponding channel is successful according to the correct area of each of the τ^Beco; if yes, go to step 450; if no, go to step 470. Step 450: Find the center point of the correct area of each of the resources, and determine the optimal phase relationship of the parent channel, and perform step 460. Step 460: Enter the normal mode, and adjust the phase of the clock signal or the corresponding data signal according to the optimal phase relationship of each channel. Step 470. Determine that the calibration failed. After entering the calibration mode in step 410, the delay units DL 〇 DL DL4 can provide different degrees of delay of the clock signal CLK and the data signals DATA1 DATA DATA4, respectively. The phase relationship between the clock signal CLK and the data signals DATA1 to DATA4 is as shown in Fig. 5 under different signal delay conditions. In this embodiment, the delay units DL0 DL DL4 can provide 31 sets of offset adjustment stages S0 S S30: the offset adjustment stage S0 represents that the clock signal and the data signal are delayed by 0 unit time Td; the offset adjustment stage si~S15 The clock signal is delayed by 1~15 unit time Td, and the data signals DATA1~ DATA4 are delayed by unit time Td; the offset adjustment stage S16~s3〇 represents the delay of the clock signal by unit time Td, and the data signal Datai~DATA4 are each delayed by 1~15 unit time Td. Each offset adjustment step corresponds to a specific clock delay index (an integer between _ 15 and 15). 201248352 Figures 6A to 6D are signal diagrams under different signal delay conditions. For the sake of explanation, only the clock signal CLK and the data signal DATA1 are taken as an example. Figs. 6A and 6B show timing charts of signals in the offset adjustment stages S0 to S15, and Figs. 6C and 6D show timing charts of signals in the offset adjustment stages SO, S16 to S30. In the embodiment shown in FIG. 6A, the master terminal circuit HS transmits the clock signal CLK to the receiving circuit 310 of the client circuit CS through the transmitting circuit 110, and transmits the data signal DATA1 of "01010101" through the transmitting circuit 111 to The receiving circuit 311 of the client circuit CS. Then, the delay unit DL0 delays the clock signal CLK by 0 unit time Td, and the delay unit DL1 delays the data signal DATA1 by 0~15 unit time Td, respectively, thereby providing a test clock signal CLK0' and 16 pens. Test data signals DT0'~DT15'. The client circuit CS can capture the test data signals DT0, DT15' at the rising/falling edge of the test signal CLK', and can extract 8 sequence bits BT1 BTBT8 from each test data signal, and then transmit the sequence. The parallel conversion unit S2P1 is merged into parallel data DP0 to DP15, respectively. In the embodiment shown in FIG. 6B, the master terminal circuit HS transmits the clock signal CLK to the receiving circuit 310 of the client circuit CS through the transmitting circuit 110, and transmits the data signal DATA1 of "00110011" through the transmitting circuit 111. 201248352 to the receiving circuit 311 of the client circuit CS. Then, the delay unit dl 延迟 delays the clock signal CLK by a unit time Td, and the delay unit DL1 delays the data signal DATA1 by 0 to 15 unit time Td, respectively, thereby providing a test clock signal CLK0' and 16 Pen test data signals DT0, ~ DT15,. The client circuit CS can capture the test data signal DT0'~Π)Τ15 at the rising/falling edge of the test signal signal CLK, and can extract 8 serial bits ΒΤ1~ΒΤ8 from each test data signal. The sequence-to-parallel conversion unit S2P1 is again merged into parallel data DP0 to DP15. In the embodiment shown in FIG. 6C, the master terminal circuit Hs transmits the clock signal CLK to the receiving circuit 31〇 of the client circuit cs through the transmitting circuit 110, and transmits “〇1〇1〇1 through the transmitting circuit 111. The data signal DATA1 of 〇1" is the receiving circuit 311 of the client circuit CS. Then, the delay unit DL0 delays the clock signal CLK by 〇15 times unit time Td, and the delay unit DL1 delays the data signal DATA1 by one unit time Td, thereby providing 16 test clock signals CLK0, CLK15 , and - test data signal, said. The terminal circuit Cs can capture the test data signal DT〇 at the rising/falling edge of the test signal signals CLK0~CLK15, and can obtain 8 serial bits BT1 according to each test pulse signal CLK0, ~CLK15. ~BT8, and then through the sequence to parallel conversion unit S2pl are merged into parallel data DP0~DP15. In the embodiment shown in FIG. 6D, the main control circuit Hs transmits the clock signal CLK to the receiving circuit 310 of the customer circuit CS through the transmission 1 12 201248352 circuit 110, and transmits the data of "00110011" through the transmission circuit 111. The signal is received from the receiving circuit 311 of the subscriber circuit CS. Then, the delay unit DL0 delays the clock signal CLK by 0 to 15 unit time Td in sequence, and the delay unit DL1 delays the data signal DATA1 by one unit time Td, thereby providing 16 test clock signals CLK0, CLK15, and a test data signal DT0'. The client circuit CS can capture the test data signal DT0' at the rising/falling edge of the test signal pulse signals CLK0, CLK15', and can respectively capture 8 serial bits according to each test clock signal CLK0'~CLK15. BT1 to BT8 are further integrated into parallel data DP0 to DP15 through the sequence-to-parallel conversion unit S2P1. Figure 7 is a graph showing the results of Figures 6A to 6D. The comparing unit 33 〇 can compare the values of each of the captured data and the corresponding expected data, and then generate a comparison result and R2 corresponding to each offset adjustment phase and different value data signals. If the comparison result R1 shows that the "01010101" data signal DATA1 will be processed after the offset adjustment stage S0~S30, it will contain two data correct areas 'also between the immediate pulse delay index -6~3 and 14~15; If the comparison result R2 shows that the "00110011" data signal DATA1 is processed by the offset adjustment stages S0 to S30, it will contain a single data correct area, and the instantaneous pulse delay index is between -6 and 3. When determining the optimal phase relationship, the correct area of multiple data will increase the difficulty of judgment. Therefore, the comparison circuit of the present invention performs a specific logical operation on R1 and R2. For example, performing an AND operation (R1 & R2) 13 201248352 ensures that each expected data has only a single data correct region. For each offset adjustment phase, the present invention can determine the optimal phase relationship based on the result of a particular data signal (R1 or R2); alternatively, the present invention can simultaneously determine the results (R1 and R2) of different specific data signals. The best phase relationship. Figures 8A-8B and 9A-9B illustrate the operation of the calibration circuit 300 of the present invention when performing steps 420-470. The foregoing embodiment shown in FIGS. 6A to 6D and FIG. 7 is described by the data signal DATA1. After the data signals DATA2 to DATA4 are processed in the offset adjustment stages S0 to S30 in the same manner, a step 420 can be found. The calibration table is offset and stored in storage unit 320. Figures 8A and 9A show the offset calibration tables obtained in both cases. REG1~4 are 32-bit registers in the storage unit 310 for storing the calibration results of the transmission channels 201-204, respectively, where "1" represents the data correct area and "0" represents the data error area. In FIG. 8B and FIG. 9B, steps 431-439 perform the operation of step 430 for the computing unit 340, and the detailed steps thereof are as follows: Step 431: The memory data D1 (A) to D4 (A) of the registers REG1 to REG4 are stored. ) Shift one bit to the right to get the data D1(B)~D4(B) respectively. Step 432: AND data D1 (A) to D4 (A) and data D1 (B) 14 201248352 to D4 (B), respectively, to obtain data D1 (C) ~ D4 (C) respectively, step 433: Data D1 (c) to D4 (c) Shift one bit to the right to obtain data D1 (D) ~ 〇 4 (D), respectively. Step: The data D1 (C) to D4 (C) and the data m (9) to D4 (D) are subjected to X0R operation to obtain data D1 (E) to D4 (E), respectively. Step 435: Shift the data D1 (E) to D4 (E) to the left by one bit to obtain the data D1 (F) to D4 (F), respectively. In step 440, the present invention calculates data D1 (F) ~ D4 (7) = total value of bits 嶋. If the reading is 2, it is determined that the calibration is successful, and the step of binding is performed to determine the corresponding center point according to the data in the data D1 (F) to D4 (f), and according to this, each channel is determined as the second=8A~8B map. If SUM is not 2, then step 47 will be executed and the failure will be as shown in Figures 9 and 9B. After determining the optimal phase relationship for each channel, the present invention adjusts the phase of the sub-pulse or the corresponding data signal according to the optimal phase relationship of each channel in the step-time mode. The fixed value transmission channel, the invention can be used for one or more special continuation cut Ke (four) segment offset light, and then the optimal phase _', so the test per channel: 15 201248352 to adjust The phase of the pulse signal or the corresponding data signal. In summary, in a non-ideal transmission environment, even if there is a different degree of signal offset in each channel of MIDI, the present invention can synchronize the timing of all signals, thereby ensuring the correctness of data reading. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the patent scope of the present invention are intended to be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram of a transmission system in the prior art. Figures 2A to 2D show signal diagrams of prior art transmission systems in operation. FIG. 3A is a schematic diagram of a transmission system in an embodiment of the present invention. Fig. 3B is a functional block diagram of a correction circuit in the transmission system of the embodiment of the present invention. Figure 4 is a flow chart showing the operation of the correction circuit in the embodiment of the present invention. Figure 5 shows the phase relationship between the clock signal and the data signal under different signal delay conditions. Figures 6A to 6D are signal diagrams of the correction results under different signal delay conditions. Figure 7 is a graph showing the results of Figures 6A to 6D. 8A to 8B and 9A to 9B are diagrams showing the operation of the correction circuit in the embodiment of the present invention. 16 201248352 [Description of main component symbols] 10 ' 20 Transmission system 300 Correction circuit 320 Storage unit 330 Comparison unit 340 Calculation unit 350 Control units 200 to 204 Transmission channels 110 to 114 Transmission circuits 310 to 314 Reception circuits 200 to 204 Transmission channel CD Frequency converter HS master circuit CS client circuit LPTX low power transmitter HS_TX high speed transmitter LPRX low power receiver HS_RX high speed receiver DLO ~ DL4 delay unit S2P1 ~ S2P4 sequence to parallel conversion unit 410 ~ 470 Step 17