201246532 六、發明說明： 【發明所屬之技術領域】 本發明是有關於-種半導體元件及其製造方法，且特 別是有關於-種包括雙載子接合電^體(_秦細比⑽ transistor，BJT)之半導體元件及其製造方法。 【先前技術】 nur^力又，5 ’利用金屬氧化物半導體場效電晶體 火·町卜驅動需要較大電流之記憶體時，MOSFET通 車又大尺寸才有足夠南的驅動能力，因而造成佈局面 心9加在要求凡件積集度愈來愈高的情況下，尺寸隨 32ΓΓΕΤ已無法提供記憶體大電流，造成元件的 知作速度及效能受影響。 【發明内容】 有鑑於此，本發明接供—^ ^ , & '、種半導體元件及其製造方 ^在k小的佈局設計中財高驅動能力。 本發明提出一種半導體元侔 井區、第二導電型之多個第:^„第-導㈣之 閘極、第一導電型之多個第二品、弟-導電型之多個 井區配置於基底中。第一 以及多個隔離結構。 區沿π 和配置於井區中，第-摻雜 上，f甲魅著不°同於第3目^^列。。閘極配置於基底 排列’其中一個第-摻雜區電性連接互 201246532 相鄰兩f•之間的第-摻雜區中。各隔 I。構刀別配置於相㈣第_換雜區之間的基 本發明另提出-種半導體元件的製造方法: =驟。於基底中形成多個隔離結構，隔離結構^著第— 伸且互相平行排列。於基底中形成具有第—導Ϊ型 ，’各第-摻雜區分別形成於相鄰兩隔離結構之^。; 導電型之多個問極，閑極沿著不同於i 方向之方向延伸且互相平行排列，其中 接至一個閘極。於井區中形成 』 各第二擦雜區分別形成於相鄰= 之間的第一摻雜區中。 基於上述’本發明之半導體元件及其製造方法利用現 ，在基底巾配置垂直式魏子接面電晶體 元件財。科，細議胞整合在 又，子接面電曰曰曰體(BJT)的上方，可以在不增加元件尺寸的 =日守’藉由同驅動能力的雙載子接面電晶體(B JT)提供大電 I 給記憶胞’因此可有效提升元件積集度效能。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例，並配合所附圖式作詳細說明如下。 、 【實施方式】 圖^是依照本發明之一實施例之一種半導體元件佈局 白、上視不思圖。為簡化圖相清楚說明，圖1是繪示接雜 201246532 區、閘極與隔離結構的佈局。圖2A是沿著圖1中A-Λ，線 段的剖面示意圖。圖2B是沿著圖1中B-B，線段的剖面示 意圖。圖2C是沿著圖1中C-C，線段的剖面示意圖。圖2D 是沿著圖1中D-D，線段的剖面示意圖。圖2E是沿著圖i 中E_E’線段的剖面示意圖。 請同時參照圖1及圖2A至圖2E，半導體元件1〇〇例 如是雙载子接合電晶體(BJT)。半導體元件100包括具有第 一導電型之井區104、多個隔離結構106、具有第二導電型 之多個第—摻雜區108、具有第二導電型之多個閘極11〇 以及具有第一導電型之多個第二摻雜區112。 井區104例如是p型井區，其配置於基底丨〇2中。基 底102例如是P型基底或N型基底，其可為矽基底或其他 半導體基底。在一實施例中，井區104中的摻雜濃度約為 1〇15/cm2 至 l〇17/cm2 之間。 隔離結構106配置於基底102中。隔離結構1〇6沿著 第一方向m延伸且互相平行排列，因而定義出多個主動 區。隔離結構106例如是淺溝渠隔離(STI)結構。 第一摻雜區108例如是N型摻雜區，其配置於井區 104中第摻雜區108沿著第一方向D1延伸且互相平行 排列。各第—摻雜區1〇8分別配置於相鄰兩個隔離結構106 之間f井區1Q4中’換言之’隔離結構106與第-摻雜區 1〇8是以交替排列的方式而配置於基底102巾。此外，隔 離、^ 106的深度例如是會狀第—摻雜區⑽的深度， 以使付相鄰兩個第一摻雜區刚彼此能夠確實地被隔離結 201246532 構106分離。在《„ 咕 度約為至^推雜區108中的_農 ㈣例如是N+閘極’其配置於基底脱上。閘 方向Dr不者门弟―方向D2延伸且互相平行排列，其中第二 =二：第8:方向D1。如此-來，閘請例如是 丄工具有多個重疊處。特別說 .且每個第ί摻僅對應電性連接至-個閘極 110〇 11Π 區108曰分別電性連接至不同的閘極 ? 的材料例如是摻雜多晶矽戋全屬矽化物。雖 然閘極110與第一摻 夕巧屬石夕化物雖 極110中的摻雜、!；！！ 1具有相同的導電型態’但閘 在一每施w 大於苐—摻雜區108的摻雜濃度。 1021W^： 110 10-/Cm^ 以及ΐ m Π:的周圍更可選擇性地配置間隙壁111 a 於二==其中間隙_配置 二===一，頂蓋層 接雜區112例如是>㈣ τ ，、體而.弟一 -摻雜區⑽與區⑽的佈局而配置在第 實施例中，第二摻雜[^3 =外的基底碰中。在一 l〇2〇/cm2之間。 中的摻雜濃度約為l〇18/cm2至 201246532 在-實施例中，半導體元件励更包括介電声 :置於基底1〇2上。介電層114例如是具有多曰個開口 a’且開口 ii4a對應配置於第一摻雜區1〇8與 的電性連接處。開口 114&例如是分布錢此電性 -摻雜區108與閘極no㈣疊處，使得第一推雜 能夠與相對應的閘極11G直接接觸而達到電性連接之 ^料介電層114的材料例如是氧化梦、氮化石夕或高介電i a在此說明的是，半導體元件1〇〇中的p型井區ι〇4例 如是：為共集極(common collect〇r)，N型第一摻雜區⑽ 例^是作為共基極(common base)，p+型第二摻雜區！ η例 如是作為射極(emitter)，因㈣錢直式pNp㈣雙載子 接面電晶體(BIT)。由於第—摻雜區⑽與閘極UG且有和 同的導電型態，且每個第—摻雜區⑽可以分別透過介電 層114的開口 114a與不同的閘極11〇直接接觸而電性連 接丄因此位於開口 114a處的第—摻雜區⑽與閘極11〇 的又界即可作為基極接觸窗(base c〇ntact)。而外部電路能 夠藉由閘極110來施加偏壓至相對應的第一摻雜區1〇8。 ^此外，本發明之半導體元件除了上述實施型態以外， 還包括上述雙載子接合電晶體田汀）的應用。圖3是本發明 ，另=實施例之-種半導體元件佈局的上才見示意圖。圖4 疋化著圖3中A-A’線段的剖面示意圖。為簡化圖示以清楚 說明，圖3中主要讀示摻雜區、閘極、記憶胞與位元線 的佈局，在圖3及圖4中’和圖i及圖2A相同的構件則 8 201246532 使用相同的標號並省略其說明。 請參照圖3及圖4，在此實施例中，半導體元件300 例如是結合雙載子接合電晶體(BJT)與記憶體之結構。除了 如圖1所示之半導體元件1〇〇外，半導體元件3〇〇更包括 多個§己憶胞302、多個導電插塞304以及多條位元線306。 記憶胞302配置於基底1〇2上，因此其例如是位於雙 載子接合電晶體(BJT)之上方。記憶胞302分別耦接至第二 f雜區112 ^記憶胞3 02例如是電阻式記憶胞(RRAM)、相 =化記憶胞(PCM)、磁性記憶體(MRAM)或其他兩端點記 憶體(tw〇-terminal memory)。詳言之，在一實施例中，記憶 胞302包括下電極3〇2a、可變電阻層3〇沘以及上電極 302c。下電極3〇2a及上電極302c的材料分別例如是金屬 或矽。位於下電極302a與上電極3〇2c之間的可變電阻層 302b例如是會在不同的溫度下進行相變化，歧會在不同 的狀悲‘件下改Μ其電卩辑，而#彡成如金屬/絕緣層/金屬 (=ΙΜ)之堆疊結構。可變電阻層3〇2b的材料可以選用金屬 氧化物如 NiOx、TiQx、Nb2Q5、彻3、«风、 C〇〇，摻雜絡㈣鈦礦（Cr d〇ped㈣賴恤〇χ如201246532 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor element and a method of fabricating the same, and more particularly to a type including a bi-carrier bonding electron (10) transistor, BJT) semiconductor device and method of manufacturing the same. [Prior Art] nur^ force, 5', when using a metal oxide semiconductor field effect transistor, fire, and sound, when driving a memory that requires a large current, the MOSFET is opened to a large size to have sufficient south driving capability, thus causing layout. The face center 9 is added to the requirement that the accumulation of the parts is getting higher and higher, and the size can not provide the large current of the memory with the 32 ΓΓΕΤ, which causes the speed and performance of the component to be affected. SUMMARY OF THE INVENTION In view of the above, the present invention provides a high-power driving capability in a layout design with small k--^, &', a semiconductor device, and a manufacturer thereof. The invention provides a plurality of well regions of a semiconductor element well region, a second conductivity type, a gate electrode of the first conductivity type, a plurality of second products of the first conductivity type, and a plurality of well regions of the first conductivity type In the substrate, the first and a plurality of isolation structures are arranged along the π and in the well region, and the first doping is not the same as the third mesh. The gate is arranged on the substrate. 'One of the first-doped regions is electrically connected to each other in the first-doped region between 201246532 and the adjacent two f•. The basic invention of each spacer I is disposed between the phase (four) _changing region A method for fabricating a semiconductor device is proposed: a step of forming a plurality of isolation structures in a substrate, the isolation structures being first extended and arranged in parallel with each other. Forming a first conductivity type in the substrate, each of the first doping The regions are respectively formed in two adjacent isolation structures; a plurality of conductive poles of the conductive type, the idle poles extending in a direction different from the i direction and arranged in parallel with each other, wherein the gates are connected to one gate. Each of the second erase regions is formed in the first doped region between adjacent = respectively. Based on the above-mentioned 'half of the present invention The body element and the manufacturing method thereof are used, and the vertical Weizi junction transistor element is disposed in the base towel. The unit is integrated, and the sub-junction electric body (BJT) is above the Increasing the component size = 日守' provides a large power I to the memory cell by the dual-carrier junction transistor (B JT) with the driving capability. Therefore, the component integration efficiency can be effectively improved. To make the above features of the present invention The advantages and the advantages of the invention are described in detail below with reference to the accompanying drawings. [Embodiment] FIG. 2 is a layout of a semiconductor device in accordance with an embodiment of the present invention. Figure 1 is a schematic view showing the layout of the junction 201246532, the gate and the isolation structure. Figure 2A is a cross-sectional view along the line A-Λ in Figure 1. Figure 2B is along the line. Figure 2C is a cross-sectional view of a line segment along line CC of Figure 1. Figure 2D is a cross-sectional view of the line segment along DD in Figure 1. Figure 2E is along E_E' in Figure i Schematic diagram of the line segment. Please refer to Figure 1 and Figure 2A simultaneously. 2E, the semiconductor device 1 is, for example, a bipolar junction transistor (BJT). The semiconductor device 100 includes a well region 104 having a first conductivity type, a plurality of isolation structures 106, and a plurality of first conductivity type. The doped region 108, the plurality of gates 11A having the second conductivity type, and the plurality of second doping regions 112 having the first conductivity type. The well region 104 is, for example, a p-type well region, which is disposed on the substrate 丨〇2 The substrate 102 is, for example, a P-type substrate or an N-type substrate, which may be a germanium substrate or other semiconductor substrate. In one embodiment, the doping concentration in the well region 104 is about 1〇15/cm2 to l〇17/ Between cm2 The isolation structure 106 is disposed in the substrate 102. The isolation structures 1〇6 extend along the first direction m and are arranged in parallel with each other, thereby defining a plurality of active regions. The isolation structure 106 is, for example, a shallow trench isolation (STI) structure. The first doped region 108 is, for example, an N-type doped region disposed in the well region 104, and the first doped region 108 extends along the first direction D1 and is arranged in parallel with each other. Each of the first doped regions 1〇8 is disposed between the adjacent two isolation structures 106 in the well region 1Q4. In other words, the isolation structure 106 and the first doped region 1〇8 are arranged in an alternating manner. Substrate 102 towel. In addition, the depth of the isolation, 106 is, for example, the depth of the first doped region (10) such that the adjacent two first doped regions are immediately separated from each other by the isolation structure 201246532. In the „ 咕 degree to ～ 推 区 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 108 = 2: 8th: Direction D1. So, the gate is, for example, a plurality of overlaps of the tool. In particular, each of the electrodes is electrically connected to only one gate 110〇11Π. The materials electrically connected to the different gates, for example, are doped polysilicones, which are all germanium compounds. Although the gate 110 and the first doped scorpion are of the doping compound, although doped in the pole 110, !!!! Having the same conductivity type 'but the gate is greater than the doping concentration of the erbium-doped region 108 per watt. 1021W^: 110 10-/Cm^ and ΐ m Π: the spacers can be selectively disposed around the spacer 111 a in the second == wherein the gap _ configuration two === one, the top cover layer junction region 112 is, for example, > (d) τ, the body and the first-doped region (10) and the region (10) are arranged in the first In an embodiment, the second doping [^3 = the outer substrate hits. Between 1 〇 2 〇 / cm 2 . The doping concentration in the range is about l 〇 18 / cm 2 to 201246532 in the embodiment, The semiconductor component further includes a dielectric sound: disposed on the substrate 1 〇 2. The dielectric layer 114 has, for example, a plurality of openings a' and the openings ii4a are correspondingly disposed at the electrical connection of the first doped regions 1 〇 8 The opening 114& is, for example, a distribution of the electrically-doped region 108 and the gate no (four), such that the first dopant can be in direct contact with the corresponding gate 11G to electrically connect the dielectric layer 114. The material is, for example, oxidized dream, nitrided or high dielectric ia. Here, the p-type well ι4 in the semiconductor element 1 is, for example, a common collector, The first doped region (10) is exemplified as a common base, and the p+ type second doped region! η is, for example, an emitter, because the (four) money straight pNp (four) bipolar junction junction transistor (BIT) Since the first doped region (10) and the gate UG have the same conductivity type, and each of the first doped regions (10) can pass through the opening 114a of the dielectric layer 114 and the different gate 11 respectively. The direct contact and the electrical connection 丄 thus the boundary between the first doped region (10) and the gate 11 位于 at the opening 114a can serve as a base contact window (b) The external circuit can apply a bias voltage to the corresponding first doping region 1 〇 8 by the gate 110. Further, the semiconductor device of the present invention includes the above in addition to the above embodiment. The application of the double-carrier bonding transistor Tatin. Figure 3 is a schematic view of the layout of a semiconductor device according to another embodiment of the present invention. Figure 4 is a schematic cross-sectional view of the A-A' line segment of Figure 3. For the sake of simplification of the illustration, the layout of the doping region, the gate, the memory cell and the bit line is mainly read in FIG. 3, and the same components as in FIG. 3 and FIG. 2A are shown in FIG. 3 and FIG. 201246532 The same reference numerals are used and the description thereof is omitted. Referring to FIG. 3 and FIG. 4, in this embodiment, the semiconductor device 300 is, for example, a structure in which a bipolar junction transistor (BJT) and a memory are combined. In addition to the semiconductor device 1 shown in FIG. 1, the semiconductor device 3 further includes a plurality of CMOS cells 302, a plurality of conductive plugs 304, and a plurality of bit lines 306. The memory cell 302 is disposed on the substrate 1〇2 so that it is, for example, located above the bipolar junction transistor (BJT). The memory cells 302 are respectively coupled to the second impurity region 112. The memory cells are, for example, a resistive memory cell (RRAM), a phase memory cell (PCM), a magnetic memory (MRAM), or other two-terminal memory. (tw〇-terminal memory). In particular, in one embodiment, the memory cell 302 includes a lower electrode 3〇2a, a variable resistance layer 3〇沘, and an upper electrode 302c. The materials of the lower electrode 3A2a and the upper electrode 302c are, for example, metal or tantalum, respectively. The variable resistance layer 302b located between the lower electrode 302a and the upper electrode 3〇2c, for example, undergoes a phase change at different temperatures, and the difference will be changed under different conditions, and #彡It is a stacked structure of metal/insulation/metal (=ΙΜ). The material of the variable resistance layer 3〇2b may be selected from metal oxides such as NiOx, TiQx, Nb2Q5, 3, «wind, C〇〇, doped complex (tetra) titanium ore (Cr d〇ped (4).
SrZr〇3、（Ba，Sr)Ti〇3、SrTi〇3，摻雜銅的 Mg〇x、A地、 Zr〇2 ’ 摻雜紹的 ZnO ’ 或 Pr〇7Ca〇3Mn〇3 (pcM〇)等。 導電插塞304貝配置於記憶胞3〇2與第二推雜區⑴ =。在-實施例中，介電層114還具有多個開口 mb， =配置於第二摻雜區112的上方，以使導電插塞綱能 夠契相對應的第二按雜區！ 12直接接觸而達到電性連接之 201246532SrZr〇3, (Ba,Sr)Ti〇3, SrTi〇3, doped copper Mg〇x, A, Zr〇2' doped ZnO' or Pr〇7Ca〇3Mn〇3 (pcM〇) Wait. The conductive plug 304 is disposed in the memory cell 3〇2 and the second dummy region (1)=. In an embodiment, the dielectric layer 114 further has a plurality of openings mb, which are disposed above the second doped region 112 so that the conductive plugs can correspond to the second doped regions! 12 direct contact to achieve electrical connection 201246532
效果。換§之，記憶胞302的下電極3〇2a可藉此透過導電 插塞304而與第二摻· 112 f性連接，而能夠使雙載子 接面電晶體(BJT)提供的電流通過第二摻雜區112及導電 插塞304而到達記憶胞3〇2。導電插塞3〇4的材料例如I 位7G線306例如是沿著第二方向D2延伸且互相平行 排列，且各位元線306分別配置於相鄰兩閘極11〇之 ±。位元線3〇6例如是與其下方之記憶胞迎 的上电極慨電性連接，且每—條位元線鄉可以 c第二方向D2上的多個記憶胞302,因而可以藉由 銘1Γ6來控制記憶胞302。位元線306的材料例如是 匕外，在此貫施例中，第一摻雜區⑽除了可作為錐 擊T)㈣㈣卜，其還可料控制記憶胞 子接的是’藉由將㈣提健大驅動電流之雙載 D電日日體(ΒΠ〇整合在記憶胞302的下方，而 件尺寸的情況下同時維持元件的特性表現Γ可助於 縮小半導體元件的佈局面積。 、 來說^1之線段Α·Α，、β·Β，的剖面示意圖 下所述之丰導體兀件的製造流程主要是以利田厶 ^化物半導體(腦)製程來形成本發明之半導體元^ 使4習此項技術者能夠據以實 之範園。至於其他構件的形成方式及二 201246532 術領域中具有通常知識者所知的技術製作，而不限於下述 實施例所述。 圖5A至圖8A及圖5B至圖8B是依照本發明之一實 施例之一種半導體元件的製造方法之剖面示意圖。其中， 圖5A至圖8A所繪示的是沿著圖1之線段A-A’的剖面， 而圖5B至圖8B所繪示的是沿著圖1之線段B-B’的剖面。 請參照圖5A及圖5B，提供具有第一導電型之基底 502，其例如是P型基底或是N型基底。於基底5Ό2中形 成多個隔離結構506’隔離結構506沿著第一方向D1延伸 且互相平行排列。隔離結構106例如是淺溝渠隔離(STI) 結構。接著，於基底502中形成具有第一導電型之井區 504。井區504例如是p型井區。在一實施例中，形成井 區504所使用的摻質為硼，植入能量約為12〇 KeV至3〇〇effect. In other words, the lower electrode 3〇2a of the memory cell 302 can be connected to the second doping 112 through the conductive plug 304, and the current supplied by the bipolar junction transistor (BJT) can pass. The two doped regions 112 and the conductive plugs 304 reach the memory cells 3〇2. The material of the conductive plug 3〇4, for example, the I-bit 7G line 306 extends, for example, along the second direction D2 and is arranged in parallel with each other, and the individual element lines 306 are respectively disposed at ±2 of the adjacent two gates 11〇. The bit line 3〇6 is, for example, electrically connected to the upper electrode of the memory cell below it, and each of the bit lines can be a plurality of memory cells 302 in the second direction D2, and thus can be illustrated by 1Γ6 to control the memory cell 302. The material of the bit line 306 is, for example, a crucible. In this embodiment, the first doped region (10) can be used as a taper T) (4) (4), and it can also be controlled to control the memory cell to be 'by (4) The double-load D-electric Japanese body of the large drive current (ΒΠ〇 is integrated under the memory cell 302, while maintaining the characteristic characteristics of the component while the size of the component can help to reduce the layout area of the semiconductor component. The manufacturing process of the abundance conductor element described in the cross-sectional view of the line segment Α·Α, β·Β, is mainly based on the Litian 厶 化物 semiconductor (brain) process to form the semiconductor element of the present invention. The technique can be made by the skilled person. As for the formation of other members and the technical production known to those skilled in the art in the 201246532 art field, it is not limited to the following embodiments. Fig. 5A to Fig. 8A and Fig. 5B to FIG. 8B are schematic cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the present invention, wherein FIG. 5A to FIG. 8A are cross-sectional views taken along line AA' of FIG. 5B to 8B is a line BB along the line of FIG. Referring to Figures 5A and 5B, a substrate 502 having a first conductivity type is provided, which is, for example, a P-type substrate or an N-type substrate. A plurality of isolation structures 506' are formed in the substrate 5Ό2. One direction D1 extends and is arranged parallel to each other. The isolation structure 106 is, for example, a shallow trench isolation (STI) structure. Next, a well region 504 having a first conductivity type is formed in the substrate 502. The well region 504 is, for example, a p-type well region. In one embodiment, the dopant used to form the well region 504 is boron and the implantation energy is about 12 〇 KeV to 3 〇〇.
KeV之間’且其摻雜濃度約為1〇12/(：1112至1〇n/cm2之間。 之後，於井區504中形成具有第二導電型之多個第一 摻雜區508。第一摻雜區508例如是摻雜區。第一摻 雜區508分別形成於相鄰兩個隔離結構5〇6之間，且沿著 第一方向D1延伸且互相平行排列。第一換雜區，的形 成方法例如是以隔離結構5〇6為罩幕，對基底5〇2進行離 子植入製程，以於隔離結構5〇6所暴露出的基底5〇2中形 成自我對準的(self_aligned)第一摻雜^ 5〇8。在一實施例 ^形成第-摻雜區姻所使用的播質為碟，植入能量約 至至180 Μ之間’且其摻雜濃度約為WW ⑽之間。此外，第一摻雜區爾的摻雜深度會比 201246532 隔離結構506的深度還要淺。 #請參照圖6A及圖6B，於基底502上形成介電層514。 接著，對介電層514進行圖案化，以移除部分介電層Θ514， 2於二電層514中形成多個開口 5Ma。開口 別暴 露出每個第一摻雜區5〇8的部分上表面，且一個第一摻雜 區508上例如是僅對應形成一個開口 M4a。 _請參照圖7A及圖7B’於基底502上形成具有第二導 電型之多個閘極510。閘極51〇例如是N+閘極，且沿著不 同於第-方向D1之第二方向D2延伸且互相平行排列。問 極510的形成方法例如是先於介電層514上形成一層導體 層，接著再對此導體層進行圖案化製程，以獲得所^的問 極510圖案。由於介電層514具有多個暴露出第一換雜區 5〇8部分上表面之開口 5Ma，因此形成在介電層514上之 ，極510可以透過開σ 514a與相對應的第一換雜區遍 直:接觸而達到電性連接之效果。其中，—個第—推雜區 5〇8例如是僅電性連接至一個閘極51〇，且第一摻雜區· 生連接至不同的閘極510。閘極510的材料例如是 =夕金屬，，在一實施例中，閘極510中的 ，雜浪度約為1()2W之間，且大於第一換雜 區508的摻雜濃度。 一 卷，後’於閘極510的兩側壁上還可選擇性地形成間隙 二，’510上可選擇性地形成頂蓋層511b，以 閘極51〇,周圍。間隙壁511a的材料例如是氧化矽或 鼠石夕’頂盍層511b的材料例如是氧化石夕或氮化石夕。/ 12 201246532 及圖8B’於井區504中形成具有第一導 二摻雜區512。第二摻雜區512例如是料摻 雜品’且〃分別形成於相鄰兩個閘極510之間的第一摻雜區 中第一摻雜區512的形成方法例如是以閘極51〇及 其間隙壁5lla為罩幕’對基底5〇2進行離子植入製程，以 於間隙壁511 a的外側基底5 〇 2中形成自我對準的第二摻雜 區5/2。值得一提的是，第二摻雜區512的製作可以與M〇s 製程中的源極汲極區的製作同時進行。在一實施例中，形 成第二摻雜區512所使用的摻質為砷，植入能量約為^ Ke二至2 3〇之間，且其摻雜濃度約為1〇15/Cm2至 1016/cm2之間。至此，即完成如圖i及圖2A至圖2£所示 之PNP型的雙載子接面電晶體(bjt)結構（半導體元件 特別說明的是’在完成雙載子接面電晶體(BJT)的製作 之後，還可以選擇性地在雙載子接面電晶體(BJT)上方形 記憶體。以下，將利用沿著圖3之線段A_A，的剖面示‘圖 來說明形成如圖4所示之半導體元件的製造流程。圖9至 圖10是依照本發明之另一實施例之一種半導體元件的掣 造方去之剖面示意圖。圖9至圖1〇所繪示的是沿著圖$ 之線段A-A，的剖面，主要用以說明接續在圖8A之後所進 行的製程步驟，且相同的構件則使用相同的標號並省略 説明。 〜 請參照圖9，移除暴露出的介電層514，而於介電展 514中形成多個開口 514b。開口 514b例如是暴露出第二： 13 201246532 雜區512的上表面。接著，於暴露出的第二掺雜區512上 形成導電插塞904。導電插塞904的材料例如是鎢。 請參照圖10，於基底5〇2上形成多個記憶胞9〇2。記 憶胞9〇2例如是分別對應形成於導電插塞，丨，而可透 過導，插塞9G4電性她至第二摻雜區512。記憶胞9〇2 例如疋電阻式記憶胞、相變化記憶胞、磁性記憶胞(MRAM) 或其他需要較大電流驅動之記憶體。在一實施例中，記憶 胞902包括下電極9〇2a、上電極9〇2c以及位於下電極9〇2a 與上電極902c之間的可變電阻層9〇孔，而形成如金屬/絕 緣層/金屬（MIM)之堆疊結構。 之後，於基底502上形成多條位元線906，即完成如 圖3及圖4所示之結合雙載子接合電晶體(BJT)與記憶體之 結構（半導體元件300)。各位元線906分別形成於相鄰兩 個閘極510之間的記憶胞902上，因此位元線906例如是 沿著第二方向D2延伸且互相平行排列。如此一來，每一 條位元線906可以電性串接其下方沿著第二方向d2上的 多個記憶胞902，因而可以藉由位元線906來控制記憶胞 902。位元線906的材料例如是鋁。 須注思的是’上述實施例是以p型表示第一導電型， 以N型表示第二導電型為例來進行說明，但本發明並不以 此為限。本發明其他實施例亦可以將第一導電型置換成N 型並將第二導電型置換成P型以形成半導體元件，熟知本 領域之技術人員當可依據前述實施例而知其應用及變化， 故於此不再贅述。 201246532 综上所述，本發明之半導體元件及其製造方法至少具 有下列優點： ^ L上述實施例之半導體元件是在基底中配置作為 二木極之井區、作為共基極之第―摻雜區以及作為射極第 二掺雜區而構成垂直式雙载子接面電晶體(BJT)，且藉由使 ，極能夠與相對應的第—摻雜區直接接_作為基極接觸 窗，因此能夠使元件尺寸縮到最小。此外，由於雙載子接 面電晶〒ΒΧΓ)具：t較高的鶴能力，因此將其整合在記憶 ίΐ方還能夠在縮小佈局面積的同時，提供記憶胞較ϋ 電k，有助於提升元件效能。 2.上述實施例之半導體元件的製造方法 且僅需透過增加少姆而能夠= 商早且可大幅提升記憶體元件的積缝。 从 ，然本發明已以實_揭露如上，然其麵用 tie ^ i:’當可作些許之更動㈣，故本 月之保4關當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 視示=是依照本發明之一實施例之半導體元件佈局的上 =2A是沿著圖！中以，線段的剖面示意圖。 圖2B是沿著圖i中抑，線段的剖面示意圖。Between the KeVs and their doping concentration is between about 1 〇 12 / (: 1112 to 1 〇 n / cm 2 . Thereafter, a plurality of first doped regions 508 having a second conductivity type are formed in the well region 504 . The first doping region 508 is, for example, a doping region. The first doping regions 508 are respectively formed between the adjacent two isolation structures 5〇6, and extend along the first direction D1 and are arranged in parallel with each other. The formation method of the region is performed, for example, by using the isolation structure 5〇6 as a mask, and the substrate 5〇2 is subjected to an ion implantation process to form self-aligned in the substrate 5〇2 exposed by the isolation structure 5〇6 ( Self_aligned) first doping ^5〇8. In one embodiment, the first doped region is used to form a dish, the implantation energy is between about 180 Å and the doping concentration is about WW. In addition, the doping depth of the first doped region may be shallower than the depth of the 201246532 isolation structure 506. #Please refer to FIGS. 6A and 6B to form a dielectric layer 514 on the substrate 502. The dielectric layer 514 is patterned to remove a portion of the dielectric layer 514, 2 to form a plurality of openings 5Ma in the second electrical layer 514. The openings do not expose each of the first a portion of the upper surface of the impurity region 5〇8, and a first doping region 508, for example, only correspondingly forms an opening M4a. _Please refer to FIG. 7A and FIG. 7B′ to form a plurality of second conductivity type on the substrate 502. The gate 510. The gate 51 is, for example, an N+ gate, and extends in a second direction D2 different from the first direction D1 and arranged in parallel with each other. The formation of the gate 510 is formed, for example, on the dielectric layer 514. a layer of conductor layer, and then patterning the conductor layer to obtain a pattern of the 510. Since the dielectric layer 514 has a plurality of openings 5Ma exposing the upper surface of the portion of the first variator 5〇8, Therefore, the electrode 510 is formed on the dielectric layer 514, and the pole 510 can pass through the opening σ 514a and the corresponding first impurity-changing region: the effect of the electrical connection is achieved by contact; wherein, the first-thumb structure 5〇8 For example, it is electrically connected only to one gate 51A, and the first doping region is connected to a different gate 510. The material of the gate 510 is, for example, a metal, in one embodiment, the gate 510 The mid-wavelength is between about 1 () 2 W and greater than the doping concentration of the first change-over region 508. A roll, then 'on both sides of the gate 510, a gap 2 can be selectively formed, and a cap layer 511b can be selectively formed on the '510, with the gate 51〇 surrounding. The material of the spacer 511a is, for example, The material of the yttrium oxide or the yttrium layer 511b is, for example, oxidized or yttrium oxide. / 12 201246532 and FIG. 8B' is formed in the well region 504 with the first conductive doped region 512. The second doping The formation of the first doped region 512 in the first doped region, such as the gate 51 and its spacer, is the formation of the first doped region 512 in the first doped region between the adjacent two gates 510, respectively. 5lla is the mask screen' ion implantation process for the substrate 5〇2 to form a self-aligned second doped region 5/2 in the outer substrate 5 〇2 of the spacer 511a. It is worth mentioning that the fabrication of the second doping region 512 can be performed simultaneously with the fabrication of the source drain region in the M〇s process. In one embodiment, the dopant used to form the second doping region 512 is arsenic, the implantation energy is between about 2 and 2 3 Å, and the doping concentration is about 1 〇 15 / Cm 2 to 10 16 . Between /cm2. At this point, the PNP type bipolar junction transistor (bjt) structure as shown in FIG. 1 and FIG. 2A to FIG. 2 is completed (the semiconductor element is specifically described as 'completed double-contact junction transistor (BJT) After the fabrication, it is also possible to selectively form a square memory on the bipolar junction transistor (BJT). Hereinafter, a cross-sectional view along the line A_A of FIG. 3 will be used to illustrate the formation of FIG. FIG. 9 to FIG. 10 are schematic cross-sectional views showing a fabrication of a semiconductor device in accordance with another embodiment of the present invention. FIG. 9 to FIG. The section of the line AA is mainly used to describe the process steps subsequent to that shown in FIG. 8A, and the same components are denoted by the same reference numerals and the description is omitted. 〜 Referring to FIG. 9, the exposed dielectric layer 514 is removed. A plurality of openings 514b are formed in the dielectric display 514. The opening 514b is, for example, exposed to the upper surface of the second: 13 201246532 impurity region 512. Next, a conductive plug 904 is formed on the exposed second doped region 512. The material of the conductive plug 904 is, for example, tungsten. Please refer to FIG. Forming a plurality of memory cells 9〇2 on the substrate 5〇2. The memory cells 9〇2 are respectively formed on the conductive plugs, respectively, and are permeable, and the plugs 9G4 are electrically connected to the second doped region. 512. The memory cell 9〇2 is, for example, a resistive memory cell, a phase change memory cell, a magnetic memory cell (MRAM), or other memory that requires a larger current drive. In one embodiment, the memory cell 902 includes a lower electrode 9〇 2a, the upper electrode 9〇2c, and the variable resistance layer 9 located between the lower electrode 9〇2a and the upper electrode 902c are formed to form a stacked structure such as metal/insulation layer/metal (MIM). Thereafter, on the substrate 502 A plurality of bit lines 906 are formed thereon, that is, the structure of the combined bipolar bonding transistor (BJT) and the memory (semiconductor element 300) as shown in FIGS. 3 and 4 is completed. The bit lines 906 are formed adjacent to each other. The memory cells 902 between the two gates 510, and thus the bit lines 906 extend, for example, along the second direction D2 and are arranged parallel to each other. Thus, each of the bit lines 906 can be electrically connected in series with the lower edge thereof. A plurality of memory cells 902 in the second direction d2 are thus controllable by bit line 906 Recalling cell 902. The material of the bit line 906 is, for example, aluminum. It is to be noted that the above embodiment is described by taking the p type as the first conductivity type and the N type as the second conductivity type as an example, but the present invention It is not limited thereto. Other embodiments of the present invention may also replace the first conductivity type with the N type and the second conductivity type with the P type to form a semiconductor element, which is well known to those skilled in the art according to the foregoing embodiments. In view of the above, the semiconductor device of the present invention and the method of fabricating the same have at least the following advantages: ^ The semiconductor component of the above embodiment is disposed in the substrate as the second wood. a well region, a first doped region as a common base, and a second doped region as an emitter, forming a vertical bipolar junction transistor (BJT), and by virtue of The first doped region is directly connected to the base contact window, thereby enabling the component size to be minimized. In addition, due to the high carrier capacity of the double-carrier junction, it is better to integrate it into the memory. It can also provide a memory cell with a smaller memory area while reducing the layout area. Improve component performance. 2. The method of manufacturing a semiconductor device of the above-described embodiment, and it is only necessary to increase the number of smear and to increase the seam of the memory device. From the course of the invention, the invention has been disclosed above, but its use of tie ^ i: ' can be used to make some changes (4), so this month's warranty 4 is subject to the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS The display = the top of the semiconductor device layout according to an embodiment of the present invention = 2A is along the figure! In the middle, the cross-section of the line segment. Fig. 2B is a schematic cross-sectional view along the line segment of Fig. i.
S 15 201246532 圖2C是沿著圖1中C-C’線段的剖面示意圖。 圖2D是沿著圖1中D-D’線段的剖面示意圖。 圖2E是沿著圖1中E-E’線段的剖面示意圖。 圖3是依照本發明之另一實施例之半導體元件佈局的 上視示意圖。 圖4是沿著圖3中A-A’線段的剖面示意圖。 圖5A至圖8A是依照本發明之一實施例之種半導體 元件的製造方法之剖面示意圖。 圖5B至圖8B是依照本發明之一實施例之半導體元件 的製造方法之剖面示意圖。 圖9至圖10是依照本發明之另一實施例之半導體元 件的製造方法之剖面示意圖。 【主要元件符號說明】 100、300 :半導體元件 102、502 :基底 104、504 :井區 106、506 :隔離結構 108、508 :第一摻雜區 110、510 :閘極 llla、 511a :間隙壁 lllb、 511b :頂蓋層 112、512 :第二摻雜區 114、514 :介電層 16 201246532 114a、114b、514a、514b :開口 302、902 :記憶胞 302a、902a :下電極 302b、902b :可變電阻層 302c、902c :上電極 304、904 :導電插塞 306、906 :位元線 D1 :第一方向 D2 :第二方向S 15 201246532 Fig. 2C is a schematic cross-sectional view taken along line C-C' of Fig. 1. Fig. 2D is a schematic cross-sectional view taken along line D-D' of Fig. 1. Fig. 2E is a schematic cross-sectional view taken along line E-E' of Fig. 1. Figure 3 is a top plan view showing the layout of a semiconductor device in accordance with another embodiment of the present invention. Fig. 4 is a schematic cross-sectional view taken along line A-A' of Fig. 3. 5A through 8A are schematic cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the present invention. 5B to 8B are schematic cross-sectional views showing a method of fabricating a semiconductor device in accordance with an embodiment of the present invention. 9 to 10 are schematic cross-sectional views showing a method of fabricating a semiconductor device in accordance with another embodiment of the present invention. [Main component symbol description] 100, 300: semiconductor component 102, 502: substrate 104, 504: well region 106, 506: isolation structure 108, 508: first doping region 110, 510: gate 111la, 511a: spacer L11b, 511b: cap layer 112, 512: second doped region 114, 514: dielectric layer 16 201246532 114a, 114b, 514a, 514b: opening 302, 902: memory cell 302a, 902a: lower electrode 302b, 902b: Variable resistance layers 302c, 902c: upper electrodes 304, 904: conductive plugs 306, 906: bit line D1: first direction D2: second direction
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