TW201246511A - Memory with off-chip controller - Google Patents

Abstract

An integrated circuit memory device, including a memory circuit and a peripheral circuit, is described which is suitable for low cost manufacturing. The memory circuit and peripheral circuit for the device are implemented in different layers of a stacked structure. The memory circuit layer and the peripheral circuit layer include complementary interconnect surfaces, which upon mating together establish the electrical interconnection between the memory circuit and the peripheral circuit. The memory circuit layer and the peripheral circuit layer can be formed separately using different processes on different substrates in different fabrication lines. This enables the use of independent fabrication process technologies, one arranged for the memory array, and another arranged for the supporting peripheral circuit. The separate circuitry can then be stacked and bonded together.

Description

201246511 ,

TW6499PA VI. Description of the Invention: [Technical Field] The present invention relates to an integrated circuit memory device. [Prior Art] A high-density memory device is manufactured every time on an integrated circuit. The amount of data stored per unit area will be a key indicator. Therefore, when the critical dimension technology of the memory device has reached the bottleneck, in order to achieve a larger storage density per bit and lower the production cost per bit, the generally recommended method is to stack multiple levels of memory cells. In addition, new memory technologies, including phase change memory, ferromagnetic memory, and metal oxide based memory, require a range of different memory technologies. The manufacturing steps are followed by the fabrication of secondary peripheral circuits such as address decoders, state machines, and command decoders. Since both the memory array and the peripheral circuits require the fabrication steps, the production line for executing the memory device may be expensive or compromised by the circuitry that makes the peripheral circuitry. This will result in the use of higher order techniques to fabricate the integrated circuitry of the memory device, resulting in increased process cost. When the performance of the memory in the integrated circuit is increased, so that the manufacturing cost is higher, it is necessary to propose an integrated circuit memory structure with a low manufacturing cost.

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I W04VVPA SUMMARY OF THE INVENTION The integrated circuit memory device, including the memory circuit and a peripheral circuit, can be manufactured at low cost using the integrated circuit ticker device. The memory circuit and the peripheral circuit for the integrated circuit memory device are implemented in different layers in the stacked structure. The memory circuit layer and the peripheral circuit layers, including the interconnection surface II, can establish an electrical connection between the memory circuit and the peripheral circuits by matching of the interconnection surfaces. The memory circuit layer and the peripheral circuit layer can be formed on different substrates by different processes in different production lines. Therefore, independent process technology can be used, one process technology is used to fabricate the memory array, and the other process technology is used to fabricate peripheral circuits. The separate circuit can then be stacked or packaged in a method of fabricating a memory device as described herein, including forming a memory circuit that includes a plurality of memory cells. The memory circuit has a first interconnect surface, the first interconnect surface including a first set of interconnect locations. The interconnection locations in the first set of interconnect locations are electrically exposed to corresponding memory cells in the plurality of memory cells. The method also includes forming a peripheral circuit that provides a control signal for operating the memory circuit. The peripheral circuitry has a first interconnect surface and the second interconnect surface has a second set of interconnect locations. The method further includes connecting a first interconnect surface of the memory circuit to a second interconnect surface of the peripheral circuit such that the first set of interconnect locations in the interconnect locations are electrically coupled to the corresponding second set of interconnect locations Interconnect location. The memory device described herein includes a memory circuit that includes a plurality of memory cells. The memory circuit has a first interconnect surface, the first interconnect surface including a first set of interconnect locations. 201246511 in the first set of interconnection locations

The TW6499PA interconnect position is electrically coupled to a corresponding memory cell of the plurality of memory cells. The memory device also includes a peripheral circuit that provides control signals to operate the memory circuit. The peripheral circuitry has a second interconnect surface and the second interconnect surface has a second set of interconnect locations. a second interconnect surface of the peripheral circuit is coupled to the first interconnect surface of the memory circuit at an interconnect interface such that the interconnect locations in the first set of interconnect locations are electrically coupled to the corresponding second set of interconnects Connect the interconnected locations in the location. Other aspects and advantages of the present technology will be apparent from the following description, the detailed description, and the scope of the claims. [Embodiment] Embodiments of the present invention will be described in detail in conjunction with Figures 1-10 of the drawings. 1 is a block diagram of a simplified integrated circuit memory device 100. The integrated circuit memory device 100 includes a memory circuit 100 and a peripheral circuit 175, and the memory circuit and peripheral circuit system described herein. They are physically disposed separately on different layers of the device 100 and connected to each other through an interconnection interface 181. The term "joined" or "joining" as used herein refers to the arrangement of the memory circuit 110 to be attached, fixed, or otherwise physically connected to the peripheral circuit 175. This term encompasses that memory circuit 110 is directly attached to peripheral circuitry 175, such as by bonding. The vocabulary further encompasses that the memory circuit 110 is configured to indirectly connect to the peripheral circuit 175 through an interposer unit or component interposed between the memory circuit 110 and the peripheral circuit 175. The memory circuit 110 includes a memory array 160. . Word line (not drawn 201246511

1 W6499PA is shown arranged along the columns (c〇iumns) of the memory array 16〇. Bit lines (not shown) are arranged along the rows (r〇ws) of the memory array 16〇 for reading and programming the memory cells of the memory array 16 (not shown). As used herein, the term "access Hne" means a bit line 'source line', and/or a word line. The memory circuit 11 亦 may also include other circuits, such as high voltage transistors or drivers, which provide better performance when placed on the same wafer as the memory array. The memory circuit 110 includes an interconnect surface 182 having a set of interconnect locations 132. The interconnect location 132 is defined in the form of an electrical interconnect interface of the memory circuit 11 in the longitudinal direction. The figure depicts a smaller area of interconnecting surface 182, which may include thousands of interconnect locations 132. The interconnect locations 132 are coupled via conductors 130 to corresponding access lines in the memory array 160. Thus, the particular row or column selection of the memory array 160 is illustrated below. The memory array 160 can be implemented using a variety of different 2D or 3D memory structures, including the foregoing. The memory array 16 can also be implemented by different types of memory cells using access technologies such as floating gates, charge traps, stylized resistors, phase transitions, etc., and different types of memory cells include different random access memories. Body, read-only memory, and other non-volatile memory. In some embodiments, the memory array 16 is implemented using a stacked thin film transistor structure, such as, for example, U.S. Patent No. 7,473,589 and U.S. Patent No. 7,7,9,334. The disclosures of the two patents are hereby incorporated by reference.

The 201246511TW6499PA peripheral circuit 175 also includes an interconnect surface 18G having a set of interconnect locations 134. The interconnection location 13 = surface 180 is defined by the form of the longitudinal electrical interconnection π. ^The peripheral circuit I81 of the peripheral circuit 175 is disposed on the interconnection table * 182 and the interconnection surface 180. The interconnection position of the limbs 134 is the corresponding interconnection position of the limbs. The interconnection σ 181 can also be electrically _ _ 1 2 And interconnection location 134. In this way, the interconnect interface 雷Leizhen A 181 is connected longitudinally to the individual access line peripheral material 175 of the δ ** recall array 160 to improve the job title _ circuit, bias signal, timing signal , switching control signals, etc. The peripheral circuit 175 includes a conductor 162 that extends through a complementary interconnection table = and 18 〇, and an interconnection interface 181 that is coupled to the memory array (10). The sub-wire conductor 162 extends to a column of decoders 161. The conductor 164 is coupled to the row of the decoder 163 to the bit line in the memory array 160 through the lenticular surfaces 182 and 180, the interconnect interface 181, and the conductor 13A. The address of the bus 165 is provided to the column decoder ι 61 and the row decoder 163. In this embodiment, the sense amplifier and data input structure (d && _n n structures) 166 are coupled to the row decoder 163 via the data bus 167. The row decoder 163 and the sense amplifiers in block 166 can be arranged in a page buffer structure to allow for extensive and parallel read and write operations. The data input structure of the block 166 can be supplied through the data input line 171 by the input/output port on the integrated circuit memory. In the embodiment, other circuits 174 are included in the peripheral circuit 175. Other circuits are, for example, a general-purpose processor or a specific function application circuit, or a combination module, and the module can be used by the 201246511 memory array 160. To provide the function of a system-on-a-chip system. The data of the sense amplifier circuit of block 166 can be provided through the data output line 172' to the input/output ports on the peripheral circuit 175, or to other terminals internal or external to the integrated circuit 175. The implementation of the controller in this embodiment is the use of a bias arrangement state machine 169 to control the bias setting to provide a voltage, and the bias setting provides a voltage (Bias Arrangement).

Supply Voltages) are supplied or generated through a voltage supply or a supply in block 168. The bias settings provide voltages such as read and program voltages. Next, a bias voltage supply voltage and other control signals are provided to the memory device through the interconnect surface 182, the interconnect surface 18A, and the interconnect port 181'. The controller can be implemented using conventional, special purpose logic circuitry. In another embodiment, the controller includes a general purpose processor-integrated processor that can be implemented in the peripheral circuit 175, and the peripheral circuit 175: to execute a computer program to control the operation. In another embodiment, a combination of a logic circuit of a special material and a combination of a microprocessor is used to implement the controller. The physique; the various techniques of stacking the peripheral circuits 175 and the interconnection interface 180 establishes the electrical interconnection of the i-body 110 for the peripheral circuits 175. For example, pattern == to interconnect surface 182 and interconnect surface 18 can be applied. Both, the secondary application to the interconnect surface 182 and the material can be either a conductive adhesive or a solder surface 180. The conductors used (7) and the memory circuit (4) are connected to each other and then the peripheral circuits are stacked. 1 The interconnect surface 182 and the interconnect surface are also matched. In some implementations, you can use the penetrating Shi Xitong 201246511

The TW6499PA (Through-Silicon-Via, TSV) technology is used to perform, and the interface steps are as described in the U.S. Patent No. 7,683,459, the entire disclosure of which is hereby incorporated by reference. The way is incorporated into this article. In some embodiments, interconnect interface 181 includes an interposer between the interconnect surface 182 and the interconnect surface 180. The interposer is singularly comprised of a metal substrate of a metal layer disposed to conduct a signal between the interconnect surfaces, and the interposer includes, for example, a TSV technology of '°^'. The contact point including one side of the coupling interposer and the other side of the intervening layer, respectively, have interconnecting positions. The conductive elements are extended by the two-phase=between conductive path between the interconnecting points. In a private device, the interposer may include an additional circuit 'for example, a ^ 〆iSi body, a repeater, an conductors, a capacitor, and a layered memory. The signal connection between the peripheral circuits and the gamma of the memory, the memory circuit 110 and the peripheral circuit 175 are manufactured so that the process technology can separately manufacture the two (the memory circuit 110, another In the case of manufacturing a peripheral electrical system, it is necessary to select whether there is a process for manufacturing an interposer. J^Hard electricity can be used in different production lines to separate the edges/outsides of the rubber road 110 and the peripheral circuit 175. Different On the substrate, therefore, the edge-only electrical system uses logic only processes to make k ^ 杂 175. The simple logic process is used, for example, to form a static random access memory (SRAM). The process of making a more complex traditional memory system requires a combination of logic / $ two-way side-by-side. This embodiment can design a high-level parameter at a lower cost ^ 201246511

I W6499PA circuit 175. Similarly, the memory circuit 110 can be fabricated using memory architecture techniques without regard to the routing techniques of the peripheral circuitry 175. Even if the cost of using the bonding process is added, the memory circuit 110 and the peripheral circuit 175 are separately manufactured, and the net cost per memory cell can be considerably reduced. For example, it is assumed that the memory circuit 110 and the peripheral circuit 175 occupy the same die area, and the respective process technologies of the memory circuit 110 and the peripheral circuit 175 do not cover a common step. It is also assumed that the memory circuit 110 and the peripheral circuit 175 each need to form a 20 layer of material 'each layer of material requires a cost of $50. Under such an assumption, when the memory circuit 110 and the peripheral circuit 175 are manufactured together, the cost per wafer is close to (20*$50+20*$50)/1000, that is, $2. In contrast, the memory circuit 110 and the peripheral circuit 175 are separately formed, and the cost per wafer is close to (20*$50/2000)+(20*$50/2000)+the cost of stacking and bonding, that is, $1 plus The cost of the upper bonding process. Therefore, when the cost of the bonding circuit is less than $1, the memory circuit 110 and the peripheral circuit 175 are separately manufactured, which is lower in cost than the memory circuit 110 and the peripheral circuit 175 in a single wafer. The physical separation of the memory circuit 110 from the peripheral circuit 175 can also be modularized separately. Modularization can provide different operating modes, for example, different memory cells on the same memory device 100 for different modes. Read or write operation. Different modes of operation allow different memory cells to provide different memory characteristics. 2 is a block diagram of a simplified memory circuit 110. The memory circuit 110 includes a first set of memory cells 160-1 and a second set of memory cells 201246511, TW6499PA ''160-2. As shown in Fig. 2, the first set of memory cells Moq can be coupled to an interconnect surface 182 via conductor 130-1. The interconnect surface 182_丨 has a set of interconnect locations 132-1. The second set of memory cells 160-2 can be coupled to the interconnect surface 182-2 via conductors 130-2, and the interconnect surface 182-2 has a set of interconnect locations 132-2. Interconnect interface 181 between interconnect surface, interconnect surface 182 2 and interconnect surface 180 electrically connects a particular interconnect location 134 to a corresponding interconnect location 132-1 and interconnect location 132-2. The peripheral circuit 175 generates an operation signal for operating the first group of memory cells 16 〇 丨 and the second group of memory cells 160 _2. The operational signals are generated by control logic of peripheral circuitry 175 to perform an operational mode, such as a read or write operation for a first set of memory cells 160-1 and a second set of memory cells 16〇_2. In this embodiment, peripheral circuitry 175 produces different operational signals for the first set of memory cells (9) and the second set of memory cells 160-2. For example, the operation signal of the peripheral circuit 175 for performing the read operation on the first group of memory cells 16 〇 丨 may be different from the operation signal generated by the peripheral circuit 175 for the read operation of the first group of memory cells 160-2. For example, differences between operational signals may include differences in one or more logical sequences, differences in command sets, and differences in timing signals. Different modes of operation between the first set of memory cells 160-1 and the second set of memory cells 160-2 can be utilized to provide different memory characteristics. For example, the first set of memory cells 160-1 and the second set of memory cells 160-2 can have different types of memory cells, different array arrangements, different array sizes, and/or materials having different characteristics. For example, the first set of memory cells 160-1 can provide random access and

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The TW6499PA is set with a relatively short length of bit line and word line. Such a setting method can provide high programming/erasing speed, for example, can be applied to a RAM memory. The second set of memory cells 160-2 can be placed in a (NAND) or inverse (NOR) structure with relatively long bit lines and word lines. Such an arrangement can provide good array efficiency, for example, can be applied to flash memory. The use of modules of separate interconnect surface 182-1 and interconnect surface 182-2 also allows each set of memory cells to operate independently of one another. For example, a read operation can be performed on a set of memory cells while a programming operation is performed on another set of memory cells. Independent operation of the memory cell group can also reduce power consumption. For example, power can be supplied to only the memory cells of the memory characteristics in which the operation is to be performed. In some embodiments, memory cells 161-1 and 161-2 typically share peripheral circuitry 175. Alternatively, a similar module can be used for some or all of the circuitry in peripheral circuitry 175. For example, peripheral circuit 175 includes a group of sense amplifiers that have different operational characteristics, such as having different sensing speeds. In operation, a given set of sense amplifiers can then be connected or separated into different sets of memory cells, thus providing a number of different modes of operation. 3 is a schematic diagram of a portion of a typical stacked integrated circuit memory device 100 having the interconnect interface 181 described. In Fig. 3, the memory cell 200 in the memory array 160 is a SONOS_type charge trap memory cell. Alternatively, other forms of memory cells and/or other forms of memory arrays can be used. 13 201246511 TW6499PA ' ' ° Resonance array 160 includes a plurality of word lines 210 extending in a direction parallel to the first direction. As shown in Figure 3, the gate of the memory cell 2 is connected to the corresponding word line. Each of the word lines 21 is lightly connected to the corresponding word line interconnection position ma through the corresponding conductor 13A, and the interconnection position 132a is located on the interconnection table 182. The word line interconnect bits £132& are lightly connected to the corresponding wordline interconnect location n4a via interconnect interface 181, which is located on interconnect surface 18A. The word line interconnect location 134& is then coupled via conductor 162 to column decoder i61 (r〇wdec〇der). Through this, the "arrangement decoder 161 is responsive to the address of the address". This address is the address to which the voltage is applied to the selected word line 210. The extent and duration of the applied voltage is related to the operation being performed, such as a read operation or a program operation. The memory array 160 can also include a plurality of bit lines 220 that extend in a direction parallel to the second direction. As shown in FIG. 3, the source and drain regions of the memory cell 220 are connected to corresponding bit lines 220. Each of the bit lines 220 is coupled to a corresponding bit line interconnect location 132b via a corresponding conductor 130, and the bit line interconnect location 132b is located on the interconnect surface 182. Bit line interconnect locations 132b are coupled to corresponding bit line interconnect locations 134b via interconnect interface 181, which is located on interconnect surface 180. Bit line interconnect location 134b is coupled through conductor 164 to a column decoder 163. With this configuration, row decoder 163 is responsive to an address that is the address to which the voltage is applied to the selected bit line 220. 4 is a layout diagram of an embodiment of a memory circuit 130 in which the interconnection location 132 on the 'interconnecting surface 182 is coupled to a memory array 201246511

TW6499PA column 160. Figure 5 is a cross-sectional view of the X-X axis along line 210 in one embodiment of the memory circuit 13A. In the illustrated embodiment, the bit line 22A is disposed on the word line 21A. Contact plugs (e.g., 31 turns) are connected to bit lines 22A to be disposed on interconnects 132, and interconnect locations 132 are located on interconnect surface 182. In this embodiment, the bit line interconnect location 132b is in direct contact with the corresponding bit line interconnect location 134b, and the bit line interconnect location 13 is placed on the interconnect surface 18A of the peripheral circuitry 175. As previously described, through this configuration, row 163 is lightly coupled to conductor 164 to provide a voltage to the selected bit line. A contact plug (e.g., 320) is coupled to the word line 210 to a corresponding guide, extension (e.g., 33 turns). The corresponding conductive extension extends in the direction of the line: line 210 and is disposed on the bit line 22A. Contact plugs (e.g., 疋 34 〇) are then connected to the conductive extensions to corresponding word line interconnect locations 132a' and word line interconnect locations 132a are located on interconnect surface 182. As previously described, through this configuration, column decoder 161 is responsive to the application of a voltage to the address of selected word line 210. The ground and other decoders can also be lightly coupled to the memory circuit 110 in a manner similar to that required for the memory circuit 110. As shown in Fig. 4, a plurality of word line interconnection positions I32a are distributedly connected to the respective word lines 21A. Similarly, a plurality of bit line connection locations 132b can be connected to each of the bit lines 22(). These additional vertical interconnects can be used as a backup to provide redundancy to increase manufacturing yield. For example, when an error bit (five) bit is found, the error bit address can be pointed to these spare bit lines to improve the yield. Figures 6-8 illustrate a memory device forming a stacked integrated circuit 15 201246511 ..

The manufacturing flow chart of the TW6499PA, the integrated circuit memory device 100 includes a memory circuit 110 and a peripheral circuit 175 as described herein. Figure 6 is a diagram showing the result of forming a plurality of memory circuits u〇 on the first substrate. For example, the first substrate 400 may comprise polycrystalline or other semiconductor materials. Alternatively, the first substrate 400 may also include a non-semiconductor material such as cerium oxide (Si 〇 2), cerium carbide (siC), cerium nitride (SiN) or a epoxide. In another embodiment, the first substrate 4A may comprise a flexible substrate material, such as a plastic material. In some embodiments, the first substrate includes a substrate that can be reused, and additional memory circuits 110 are sequentially formed on the reused substrate. Although there are thousands of memory circuits 110 that can be formed on the first substrate 400, only two memory circuits 11 are shown for purposes of illustration in Figure 6. As is known in the art to which the present invention pertains, a standard process memory circuit 110 can be used to form the memory circuit. In general, the memory circuit can include memory cells, access lines (eg, word lines), bit lines and source lines, conductive plugs, doped semiconductor materials, advanced simons Advance memory materials, such as phase change materials, ferr〇 magnetic materiais, high-k dielectrics, and the like, and other structures for memory circuits. In some embodiments, memory circuit 11() includes a word line driver and a bit line precharge ueuitry. In some embodiments, some or all of the decoder circuitry can be formed on the memory circuitry. In other embodiments, such as the previous embodiment, the memory circuit 11A does not include a decoder circuit. Memory can be realized in different 2D or 3D memory structures. 201246511

TW6499PA Road 110, including the structure as previously described. The memory array 16 can also be implemented in a variety of different memory cells, including read-only memory, floating gates, and charge traps. In some embodiments, the memory circuit 110 is formed by a stacked thin-film transistor technology, such as described in U.S. Patent No. 7,473,589, and U.S. Patent No. 7,709,334, What has been disclosed in the foregoing description is incorporated herein by reference. An interconnection method includes the formation of an opening in the memory circuit 110 at a location of the interconnection location 132, as is the formation of a delta-resonance circuit. A contact plug can be formed in the opening such that the contact plug corresponds to an access line in the memory circuit 110. The superposed interconnect locations 132 are then patterned to contact the contact plugs, thereby forming interconnect surface 182. Interconnect surface 182 can include thousands of interconnect locations 132. However, for the sake of clarity, the Figure 6 is not shown in a continuous dimension, but only a few interconnects 132 are shown. Figure 7 shows the result of the peripheral circuit 175 being formed on a second substrate 41. The peripheral circuit 175 is configured to provide a control circuit, such as a bias signal, a timing signal, etc., for operation of the memory circuit 11 . A peripheral process 175 can be fabricated on the production line using a logic process to optimize the process. For example, the peripheral circuit 175 can include a decoder circuit, a page buffer, a charge pUmping circuit, a controller (eg, a state machine), other memory circuits (eg, for caching memory) A static random access memory, a general purpose processor, or a special purpose application circuit, and other conventional circuits that functionally support the integrated circuit memory. The same interconnection as described above can be used to fabricate the interconnection location 201246511.

The technique of TW6499PA 132 is coupled to form a interconnect location 134 that is coupled to a corresponding contact plug. Figure 8 illustrates the result of directly connecting the interconnect surface 182 of the memory circuit 110 to the interconnect surface 180 of the peripheral circuit 175. Such a connection provides that a particular interconnect location 134 is electrically coupled to a corresponding interconnect location 132. This connection also provides electrical isolation between the interconnect location 132 and the interconnect location 134. As such, peripheral circuitry 175 is connected longitudinally to each of the access lines of memory array 160. Peripheral circuitry 175 and memory circuitry 110 can be coupled using a variety of different techniques to create a longitudinal electrical interconnection including the foregoing. In this embodiment, the memory circuit 110 can be disposed in reverse on the peripheral circuit 175, with or without an interposer. Alternatively, the peripheral circuit Π5 may be disposed above the memory circuit 110 with or without an interposer. FIG. 9 illustrates another embodiment in which the memory circuit 110 is indirectly connected to the peripheral circuit 175 through the intermediate layer 800. In this case, the memory circuit 110 and the peripheral circuit 175 are connected through the interposer 800. The plurality of memory circuits 110 can also be stacked on each other such that the memory circuit 110 is a single device prior to being connected to the peripheral circuit 175. A cross-sectional view of a typical stacked structure 900 is shown in FIG. For example, openings 910 can be formed using TSV technology to interconnect respective memory circuits 110 that extend completely through stack structure 900. In other embodiments, one or more layers of the memory circuit layer and the peripheral circuitry may be included in the stacked structure as in FIG. In summary, although the present invention has been disclosed above in the preferred embodiment, 201246511

TW6499PA has the present invention. Those skilled in the art can make changes and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention is defined by the scope defined in the appended claims. °月专 [Simple description of the diagram] Figure 1 depicts a simplified block circuit memory device block diagram integrated circuit device includes a memory circuit and peripheral circuits, the memory described here The body circuit is connected to the peripheral circuit-interconnecting σ. FIG. 2 is a block diagram of a simplified memory circuit including a first group of memory cells and a second group of memory cells. Figure 3 is a schematic illustration of a portion of a typical memory device having the interconnected surfaces described. Fig. 4 is a layout view showing an embodiment of a memory circuit showing the arrangement relationship of interconnection positions on the interconnection surface. Figure 5 is a cross-sectional view showing an embodiment of a memory circuit. Figures 6-8 illustrate a manufacturing flow diagram of a memory device forming a stacked integrated circuit, the integrated circuit memory device including one of the memory circuits and a peripheral circuit described herein. Figure 9 is a schematic diagram showing another embodiment of indirectly connecting a memory circuit to a peripheral circuit through an interposer. Figure 10 is a cross-sectional view showing an embodiment of a stacked structure including a plurality of memories stacked on each other. 201246511 ·

TW6499PA [Description of main component symbols] 100: Device 110: Memory circuit 130, 130-1, 130-2: Conductors 132, 132-1, 132-2, 132a, 132b, 134, 134a, 134b: interconnection position

S 160 : Memory array 160-1 : first group of memory cells 160-2 : second group of memory cells 161 : column decoder 163 : row decoder 165 : address 166 : sense amplifier / data input structure 168 : Bias setting provides voltage 169 : State machine 171 : Data input 172 : Data output 174 : Other circuit 175 : Peripheral circuit 180 , 182 : Interconnect surface 181 : Interconnect interface 200 : Memory cell 210 : Word line 220 : Bit Line 20

Claims (1)

201246511 TW6499PA VII. Shenqing Patent Range: 1. A method for manufacturing a memory device, comprising: an I-to-11 memory circuit, the § memory circuit comprising a plurality of memory cells, the memory circuit having a first mutual The first interconnecting table 2 has a first set of interconnecting locations, and the plurality of interconnecting locations of the first set of interconnecting locations are electrically coupled to corresponding memory cells of the memory cells; a peripheral circuit, the peripheral circuit providing a control signal for operating the memory circuit, the peripheral circuit having a second interconnecting surface, the second interconnecting surface having a second set of interconnecting locations; and connecting the remote memory The first interconnect surface of the circuit to the first interconnect surface of the peripheral circuit. 2. The method of claim 1, wherein the first interconnecting surface is coupled to the second interconnecting surface in such a manner that the second interconnecting surface is disposed on the first interconnecting surface. 3. The method of claim 1, wherein the step of forming the memory circuit comprises: performing a first process to form the memory cells on a first substrate; and forming the peripheral circuit The performing-second process is performed to form the peripheral circuit on the second substrate, and the second process is different from the first process. 4. The method of claim 1, wherein: forming (4) the memory circuit comprises forming a first substrate of the memory; and forming the peripheral circuit comprises forming the peripheral circuit in a second a substrate, the second substrate being disposed separately from the first substrate. The method of claim 1, wherein the joining step comprises directly joining the first interconnecting surface to the second interconnecting surface. [The method of claim 1 wherein the first set is disposed on the first interconnect surface and the pattern is associated with the second set of interconnects on the second interconnect surface a further pattern-position that is disposed such that when the first interconnect surface is connected to the second interconnect surface, the interconnect locations in the first set of interconnect locations are aligned with the second set of interconnects A plurality of interconnection locations corresponding to the location. 7. The method of claim 4, wherein the step of attaching the first interconnect surface to the second interconnect surface further comprises: beta connecting the first interconnect surface of the memory circuit to An interposer such that the interconnection locations in the first set of interconnect locations are electrically-to a plurality of corresponding conductive elements on the interposer; and the second interconnect surface connecting the peripheral circuits to the The interposer is configured to electrically couple the plurality of interconnect locations in the second set of interconnect locations to the corresponding plurality of conductive elements on the interposer. 8. The method of claim 1, wherein: forming the memory circuit and forming the peripheral circuit comprises: forming one of the memory circuit and the peripheral circuit on a substrate and removing the And the one of the memory circuit and the peripheral circuit is on the substrate; and the step of connecting the first interconnect surface to the second interconnect surface includes removing the memory circuit and the peripheral circuit After the substrate, one of the memory circuit and the peripheral circuit is matched to another memory circuit of S 22 201246511 TW6499PA and another peripheral circuit. 9. The method of claim 1, wherein the peripheral circuit generates a plurality of first operational signals to operate one of the first memory cells of the memory cells and the peripheral circuit generates a plurality of second operational signals To operate a second memory cell of the memory cells, the first operational signals are different from the second operational signals. The method of claim 1, wherein: the memory circuit comprises a first array of the memory cells and a second array of the memory cells, the first array and the The second array has independent access lines and different access timings; and the peripheral circuits apply different timings to the first array and the second array. 11. The method of claim 2, wherein the memory circuit further comprises a plurality of access lines, the interconnection locations of the first set of interconnection locations being electrically coupled through the access lines Connect to the corresponding memory cells. & 12. A memory device comprising: - a memory circuit comprising a plurality of memory cells, the memory circuit having a - er-interconnect surface - the first interconnect surface having a first set of interconnect locations The plurality of interconnecting locations in the first set of interconnecting locations are electrically connected to the corresponding ones of the memory cells; and a peripheral circuit 'to provide a plurality of control signals to operate the memory circuit, _ The edge circuit has a second interconnection surface, the second interconnection table "the mask has a second set of interconnection locations; wherein the second interconnection surface of the peripheral circuit is connected to the interconnection interface 23 201246511 TW6499PA 13. The device of claim 12, wherein the device of claim 12, wherein the second interconnect surface is disposed on the first interconnect surface. The device of the present invention, wherein: the plurality of access lines and the memory cells of the memory circuit are formed on a first substrate by a first process; and the peripheral circuit is formed by a second process The second substrate The second process is different from the first process. The device of claim 12, wherein the second interconnect surface is directly bonded to the first interconnect surface. The device of claim a, wherein the first, and the interconnection location is disposed on the first interconnect surface in a pattern corresponding to the second set of interconnects on the second interconnect surface Another pattern of locations disposed such that when the first interconnect surface is connected to the second interconnect surface, the interconnect locations in the first set of interconnect locations are aligned to the second set of interconnects The plurality of interconnection locations corresponding to the position. 17. The apparatus of claim 12 further comprising a layer 2, the interposer having a first side and a second side, and a plurality of conductive elements extending Between the first side and the second side, wherein the first interconnect surface of the memory circuit is coupled to the first side of the interposer such that the interconnects in the first set of interconnect locations Positional electrical property: corresponding to the corresponding number on the first side of the interposer A conductive element; and a second 24 201246511 TW6499PA is coupled to a plurality of corresponding conductive elements on the second side of the intermediary. The apparatus of claim 12, wherein the peripheral circuit generates a plurality of first operation signals to operate one of the memory cells, and the peripheral circuit generates a plurality of second operation signals. The first operational signal is different from the second operational signals by the second memory cell in the cell of the 5th brother. 19. The device of claim 12, wherein the memory circuit comprises a plurality of memory cells - (d) and a second array of the memory cells, the first array and the second array Having separate access lines and different access timings; and the peripheral circuit applies + the same timing to the first train and the second array. The apparatus of claim 12, wherein the memory circuit further comprises a plurality of access lines, the first set of interconnection bits = the interconnection positions are electrically reduced by the (four) line Memory cell. One point 25