TW201245976A - Hardware acceleration components for translating guest instructions to native instructions - Google Patents

Abstract

A hardware based translation accelerator. The hardware includes a guest fetch logic component for accessing guest instructions; a guest fetch buffer coupled to the guest fetch logic component and a branch prediction component for assembling guest instructions into a guest instruction block; and conversion tables coupled to the guest fetch buffer for translating the guest instruction block into a corresponding native conversion block. The hardware further includes a native cache coupled to the conversion tables for storing the corresponding native conversion block, and a conversion look aside buffer coupled to the native cache for storing a mapping of the guest instruction block to corresponding native conversion block, wherein upon a subsequent request for a guest instruction, the conversion look aside buffer is indexed to determine whether a hit occurred, wherein the mapping indicates the guest instruction has a corresponding converted native instruction in the native cache.

Description

201245976 任 VI, invention description: [Related application reference] This application claims to be held on January 27, 2011 by Mohammad A.  The rights of the U.S. Provisional Patent Application Serial No. 61/436,966, the entire disclosure of which is incorporated herein by reference in its entirety in its entirety in The manner of reference is incorporated herein. BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates generally to digital computer systems, and more particularly to a system and method for translating instructions containing an instruction sequence. [Prior Art] Many types of digital computer systems implement software functionality by means of code transformation/translation or emulation. In general, even if the command is not in the "this machine" of the computer system, both translation and simulation involve the function of checking the software command and the functions and actions specified by the software instruction. In the case of translation, non-native instructions are translated into native instructions, and the native instructions are designed to be executed on the hardware of the computer system. Examples include prior art translation software and/or hardware that operate as industry standard x86 applications' to enable these applications to be executed on non-x86 or alternative computer architectures. In general, the translation process utilizes a large number of processor cycles, thus creating no additional burden. The loss of performance caused by the extra burden can substantially erase any benefits of the translation process. An attempt to solve this problem involves using GusMndme compilation) in a timely manner. Timely (JIT) compilation, also known as dynamic translation, is a way to improve the runtime perf〇rmance of the computer 201245976 program. Traditionally, computer programs have two runtime conversion modes: interpretation mode (9) terpretati〇 mode) or ΤΓΓ (timely) compilation/translation mode. Interpretation is a decoding procedure (decodingp_SS) that involves decoding an instruction one instruction at a time, transforming the client code into a native code at an additional burden lower than that of the town, but it produces a poorly performing transform code. In addition, 'interpretation is called with every instruction (i嶋(4). The jit compiler or translator represents a different interpretation path for money. In terms of IT conversion, the basin usually has a high _ 贞 ,, but It produces a more ridiculous turn decoding (translated^ =: in the look: yes, the translation is carried out as an interpretation to reduce = the best code after many times 'transfer to build to build on the body to #秘1 Many problems.] IT compiler program =:===: This can be used in the enemy application to create multiple mappings of round-trip tree trees and assign management extra negative L tongue. Membrane mapping (mem〇ry 〇atenCy Penalty ^ ^ ^ ^ ^ ^ ^ ^ Body and program (4) Security and the extra burden involved in the system memory interpretation program: turn 'after ^ start the program. The code can not be optimized. PRODUCT CODE, PRODUCTION [Description of the Invention] A specific embodiment of the present invention is implemented to implement a hardware based acceleration algorithm and apparatus for implementing a client instruction to the native reference 201245976. In a specific embodiment, the present invention is implemented as a hardware-based turn Accelerator (hardware based translation accelerator). The translation hardware accelerator comprises a base. a guest fetch logic component for accessing a plurality of client instructions; a guest fetch buffer that is consumed by the client fetch logic component and a branch prediction component 'for assembling the plurality of client instructions - a client instruction block (guest instructj〇n; and a plurality of conversion tables) coupled to the client fetch buffer for The client instruction block is translated into a corresponding native conversion block. The hardware-based translation accelerator additionally includes: a native cache 'which is coupled to the conversion table for Storing the corresponding local conversion block 'and a conversion lookaside buffer (conversi〇n 1〇〇k aside buffcr, CLB), which is reduced to the local cache, for storing the client instruction block to the corresponding The mapping of the local conversion block, when the towel is in the follow-up request for the client instruction, the conversion backup buffer is used to determine whether to occur - hit _, where the mapping indicates 4 彳彳 θ In the "local cache towel" - a corresponding converted native instmetimi. In response to the hit, the translation lookaside buffer forwards the translated native instruction for execution. „, the above is the inventive content, According to the necessity, it contains a simple and general description, so the heart, ·, ®!卩' is omitted, so those who are familiar with the technology should be aware of it, and only need to say 201245976. Other Advantages and Advantages [Embodiment] The order of the repair process, the implementation of the formula: "in the formula", puts forward many specific details, such as specific aspects, and connections. However, it should be understood that the present invention is not necessary. The use of these and other specific structures, elements, and other structures that have been omitted or not described in the specific details are not necessarily to be construed as unnecessarily obscuring the description. The appearance of "in the specific embodiment" that appears in Qiu Gu Guanzhong is not necessarily all the same as the other examples of mutual exclusion. In addition, the description may be made by some specific examples. Now, the various features of the specific embodiment are shown in the same way. Similarly, the description can be a necessary condition for a certain kind of complication. However, some parts of the following "implementation methods" are computer memory. The process, steps, logic blocks, processing, and other symbolic representations of the in-vivo data bits are presented in 201245976 by means of two methods and methods used by those skilled in the data processing techniques. f is communicated to other people who are familiar with the technology. Steps, logic blocks, programs, etc., which are performed by i, are here and are generally conceived as a quantity of instructions: a sequence of steps or a sequence of instructions. These steps are the steps required. Usually, 'but not-determined' these physical quantities take the form of electric or magnetic signals of the electric body, and can be conveniently used in computer systems, values, and yuan = yes (mainly, combined, compared, and otherwise manipulated. It has been confirmed When +, p is used for general use, these signals are called bits, symbols, characters, terms, numbers, etc. from all of these terms and her terms are intended to be Correspondence = month = significantly different from the following discussion, it should be understood that in the present invention;: external use such as processing (Pr 〇 _ _ or "access (four) (10) 丨哟" or "set: move by terminology, is Refers to a computer system or similar electrical and memory and other computer readable media. In the information storage, transmission or display device, it is also indicated that the object refers to the embodiment of the customer instruction architecture by greatly accelerating the architecture: The program of the native instructions is on the native processor. The specific embodiment of the present invention implements the conversion example using the hardware unit. The client instruction can come from a number of different instruction architectures. JavaScript, x86, MIPS, SPARC, etc. 〇·士让-=E* 201245976 The body is used to quickly transfer the 'and the pipeline to the native processor's hard multi-effect + _Cheng Chen _ _ _ _ _ _ _ _ _ _ _ _ _ Implement a flexible conversion program, which can be used as a input. In this implementation, the processor's second: can be controlled by the software' while using the hardware acceleration conversion processing, ΐίΐί"1 performance level. The solution achieves benefits in many aspects. It can be used in the implementation of the client architecture and the hardware architecture of each client architecture is accelerated by the hardware. Execute the miscellaneous AS activity. Acceleration can achieve customer instructions to execute the client application at a speed close to the native hardware speed. In the following description, Figure 4 to Figure 4 show the sequence of the customer's instruction and the handling of these customer instructions. The way of the near branch and the far branch within the sequence. Figure 5 - An overview of an exemplary hardware accelerated conversion processing system of one embodiment of the invention. This hair An exemplary sequence of instructions for operation of one embodiment. The sequence of instructions 100 as depicted in Figure 1 includes 16 instructions, starting from the top to the bottom of Figure 1. As can be seen in Figure 1, the sequence 100 includes four branch instructions 101. - 104. One of the embodiments of the present invention aims to process the entire group of instructions into a single atomic unit. This primitive unit is called a "block". The instruction block can be extended beyond Figure 1 16 instructions are displayed. In a specific embodiment, the block will include enough instructions to fill a fixed size (eg, 64 bytes, 128 201245976 bytes, 256 bytes exclusively) or until Export conditions (exjt c〇ncjiti〇n). In a specific embodiment, the exit condition of the end instruction block is to encounter a far branch instruction. As used in the description of the specific embodiments herein, a far branch refers to a branch instruction whose target address resides outside of the current instruction block. In other words, within a given client instruction block, the farther branch has a target that resides in some other block or in some other sequence of instructions outside of the given instruction block. Similarly, a closer branch refers to a branch instruction whose target address resides within the current instruction block. In addition, it should be noted that the native instruction block may contain more distant branches of multiple clients. These terms are further explained in the following discussion. 2 shows a schematic diagram depicting a block-based conversion procedure in which a client instruction block is converted to a native conversion block, in accordance with an embodiment of the present invention. As illustrated in Figure 2, the display converts a plurality of client instruction blocks 2〇1 into corresponding plurality of native conversion blocks 202. A specific embodiment of the present invention functions by converting instructions of a client instruction block into corresponding instructions of a local conversion block. Each block 2〇1 consists of a customer order. As mentioned above, these customer instructions can come from a number of different client instruction architectures (eg, Java or JavaScript, x86, MIPS, SPARC, etc.). Multiple client instruction blocks can be converted to one or more corresponding native conversion blocks. This conversion occurs on a per-instruction basis. Figure 2 also illustrates the manner in which client instruction blocks are combined into a sequence based on branch prediction. This attribute enables a particular embodiment of the present invention to combine a sequence of client instructions based on predictions of farther branches. Based on the far-end branch prediction, the customer instruction sequence 攸 个 customer-age block combination conjugate is converted into the corresponding local conversion zone 201245976 block. This practice will be explained in the steps of the town map 3 and Figure 4. Figure 3 illustrates a corresponding intent to translate a guest: each instruction into a native conversion block in accordance with an embodiment of the present invention. As shown in Figure 3, the customer command block resides in the guest, and the same as the 'this_change' resides in the _H 3G2. Figure 3 shows the attributes of a particular embodiment of the invention in which the target address of = is converted to the target health of the native branch instruction. For example, the customer's H曰 packet compensates for the offset (turnover) of the target address of a particular branch. “==Because the native instruction generates the functionality of the corresponding client instruction ^ : ίίϊί column. For example, the length of the client instruction can be different from its corresponding degree. Therefore, the conversion program calculates the corresponding local offset. This is shown in Figure 3. This shows the native offset or N-〇ffset. It should be noted that since the branch with the target in the client instruction block is not predicted (called the "closer branch"), The instruction sequence stream has not changed. Figure 4 is a schematic diagram showing the manner in which a native conversion block is processed to handle a farther branch in accordance with an embodiment of the present invention. As shown in Figure 4, the client instruction is depicted as a sequence of client instructions 401 in memory. Similarly, the native instructions are depicted as a native instruction sequence 402 in memory. In one embodiment, each instruction block (both client instruction block and native instruction block) ends with a far branch (e.g., even though the native block may contain more than one 201245976 client far branch). As mentioned above, the block will include enough instructions to fill a fixed size (such as '64 bytes, 128 bytes, 256 bytes, etc.), or until an exit condition is encountered, such as the last client far branch instruction . If several client instructions have been processed to combine the client instruction blocks and have not encountered a far branch, then the client is farther away to end the block. This far branch can jump to the next subsequent block as long as it jumps. This ensures that the instruction block ends with a branch leading to another native instruction block or another client instruction sequence in memory. Additionally, as shown in Figure 4, the block may include blocks that do not reside within its instruction sequence. The customer at the end is farther away from the branch. This is displayed by the client command remote branch 411 and the corresponding native command client far branch 412. In the particular embodiment of FIG. 4, the prediction takes the farther branch 411. Therefore, the instruction sequence jumps to the target of the far branch 4Π, the client instruction F. Similarly, in the corresponding native command, subsequent to the farther branch 412 is the native command F. The near branch is not predicted. Therefore, these closer branches do not change the sequence of instructions in the same way as the farther branches. In this manner, a particular embodiment of the present invention produces a trace of a translation block where each of the health blocks contains a number (eg, a 3_ side farther branch. This trajectory is based on a customer's far branch prediction. The embodiment towel, in the local conversion block _ the far branch includes the client address of the opposite address of the branch path. As described above, the instruction sequence is generated based on the far-distance split test until the corresponding local conversion area is executed. The block will only result. So 'once the wrong prediction is detected, check the wrong (4) branch to get the opposite of the opposite route. 201245976 The program then continues from the opposite client address, I rule too θ this way, this The specific embodiment of the invention allows the user's opposite client address to be copied from the farther branch. Therefore, 'if the far branch prediction result is the wrong recovery, the correct client instruction is found. Similarly, if ±main- Go to the far branch in the He Ling block, in the CLB; need; = "in the machine,.  The login point (emrypomt) of the target block. However, if a prediction of a mistake occurs, you need to insert a new login to the target block. This Wei system stores the CLB capacity (4) ad(9) as the target. Figure 5 shows a schematic diagram of an exemplary hardware accelerated conversion system 5〇〇, in accordance with the present invention - a specific implementation of the way in which the customer command block and its local conversion block are stored in the cache. As illustrated in Figure 5, the conversion (4) buffer 506 is used to cache the address mapping between the client and the local block; resulting in the most commonly encountered local conversion block through low latency availability. Access to processor 508. Figure 5 is a schematic diagram showing the manner in which a local conversion block that is frequently encountered is maintained in a high-speed low-latency cache (high-speed cache) (transition lookaside buffer 506). The components depicted in Figure 5 implement a hardware accelerated conversion process to achieve a higher level of performance. The client extraction logic unit 502 operates to extract a hardware-based guest instruction fetch unit from the system memory 5〇1. The client command for a given application resides in system memory 201245976. After the program is initialized, the hardware extracts the logical unit from the base client to prefetch the client instruction to the client extraction buffer 5〇3 +. The client extracts the 255 cumulative client instructions and then combines the instructions into client instruction blocks. These client instruction blocks are converted to the ride-local conversion block using conversion table 504. Conversion = The local command is accumulated in the local conversion buffer 5G5 until the local conversion block is completed. The local conversion block is then transferred to the local cache 5〇7, and the map is stored in the conversion lookaside buffer 5〇6. The local cache is then used to tear the native command to processor 508 for execution. In a specific embodiment, the functionality implemented by the logic unit 502 is extracted by the user. As this procedure continues, the translation lookaside buffer 5〇6 fills up the address map of the client block to the local area. The conversion lookaside buffer 5〇6 uses one or more algorithms (such as 'too close to the least (10) to ensure that the block is more often encountered in the buffer) and to devote a few blocks of mapping Buffer. In this way, the popular taxi machine-to-blockless mapping is stored in the conversion look-up buffer. In addition: ^, think, in the block, accurate (10) far away customer branch does not need to insert a new one in the coffee Mapping, because its target block is fixed in the single-mapped native block' thus saves the smaller capacity efficiency of the CLB structure. In addition, in the __ concrete implementation = 'construction CLB bribe stores the last customer-to-native address mapping This approach also preserves the smaller capacity efficiency of the CLB. Eight customer extraction logic 5〇2 view the conversion lookaside buffer 5% to determine if the client's finger: the address of the block has been converted to a native conversion block. The present invention provides hardware acceleration for conversion processing. Therefore, before the client address is extracted from the system and the body 501 to perform a new conversion, the 'customer extraction logic 502 14 201245976 will view the existence of the secret dumping. Block mapping. In the example, the conversion look-aside buffer is indexed by the customer address # or by the individual client address. The customer health module (10) is replaced by the address of the client instruction block of the block. The local conversion block map is indexed via the corresponding guest address range of its corresponding client instruction block. Therefore, the client extraction logic can compare the client address of the household and the conversion block to the individual customer bits of the conversion block ^ , the buffer material), to determine the pre-existing present = exists in the local cache 5 〇 7 stored in the location or in the code of Figure 6 fast if the pre-existing _ ship age in the local wire or code. Then the corresponding local age is transmitted directly from the silk. 'In this way, the popular customer instruction block (for example, the frequently executed guest has the pair that is maintained in the high-speed low-latency conversion backup buffer 5G6) ϋ The local conversion block mapping. With the light block being touched, the replacement of the two #) ensures that the popular block mapping continues after =::. Therefore, the customer extraction logic 502 can immediately identify the requested it. Take 507 for execution by processor 508. l ancient Supply, + · rigorous to because the travel to the system memory can be spent > 4 〇 to; ^ ^ many cycles, attributes (such as CLB, customer cycle or more. These jitter knives sequence prediction, The customer and the local branch are slowly screaming to the first (local cache) to allow the specific implementation of the invention to achieve customer-sponsored application performance to within 80% to 1% of the equivalent functional application performance. & Applicable 15 201245976 In a specific embodiment, the client extraction logic 〇2 repeatedly pre-fetches the client-side, the client-independent request from the processing benefit 508 (gUest instructi〇n request) The local conversion block can be accumulated in the conversion buffer "code buffer" (c〇nversi〇n buffer code cache) in the system memory 5〇1 for the less-used block. The conversion lookaside buffer 5〇6 also maintains the most commonly used = mapping. Therefore, if the requested client address is not mapped to a client address in the translation lookaside buffer, the client fetch logic can check the system memory 5 to determine if the client address corresponds to the native translation block stored therein. . In a specific embodiment, the translation lookaside buffer 〇6 is implemented as a cache and utilizes a cache coherency protocol (cache c〇herency pr〇t〇c〇1) to be stored in a higher-order cache. Large conversion buffers and system memory 5〇 maintain consistency. The native instruction map stored in the translation lookaside buffer 506 also whip back the higher order cache and system memory 501. The write back to the system memory maintains consistency. Therefore, a cache management protocol can be used to ensure that the popular local conversion block map is stored in the conversion lookaside buffer 506, and the unpopular native conversion mapping block is stored in the system memory 501. Therefore, a larger form of the conversion buffer 5〇6 resides in the system memory 501. In a particular embodiment, the exemplary hardware acceleration conversion system 500 can be implemented using a number of different virtual storage schemes. For example, a virtual storage scheme can be supported using a client instruction block and its corresponding native conversion block stored in the cache. Similarly, a translation lookaside buffer 506 for caching address mapping between a client and a native block can be used to support virtual storage schemes (e.g., virtual to physical § memory mapping management). 16 201245976=The specific implementation of the financial, Figure 5 _# Shi virtual: 'The use of it can receive a number of different instructions;: '] Software controlled, while using hardware acceleration conversion processing to achieve higher efficiency = H 吏The solution can handle and convert different customers: and each customer _ gets the benefits of hardware acceleration, high performance level. The example client architecture includes Java or Javascript, Qin MIPS, SPARC, and the like. In a specific embodiment, the "customer architecture" may be a native instruction (eg, 'from a native application/macro operation (macr〇〇perati〇n)), and the conversion program generates an optimized native instruction (eg, , optimize the native instruction / micro-operation (眶r〇-〇perati〇n)). The software control front end provides greater flexibility for the application to execute on the processor. The above-mentioned 'hard acceleration' can approach the client's instructions for executing the client application at the native hardware speed. Figure 6 shows a detailed example of a hardware accelerated conversion system 600 in accordance with an embodiment of the present invention. System 600 is executed in substantially the same manner as system 5 described above. However, system 600 displays additional details that illustrate the functionality of an exemplary hardware acceleration program. The system memory 601 includes a data structure including: a client code 602, a conversion lookaside buffer 603, an optimizer code (〇ρ-c〇d) 6〇4, and a converter code 605. And the local code cache 606. System 600 also displays a shared hardware cache 607 in which both client and native instructions are interleaved and shared. The client hardware cache 61 〇 grabs the most frequently contacted customer commands from the shared hardware cache 607. 201245976 Customer extraction logic 620 pre-fetching from customer 6 Settlement Extraction 620 and TLB 6〇9 interface, τ household refers to 7 customer address translated to corresponding entity customer 2:=== :::: Direct delivery to customer hard The body is fast 61. The client instruction fetched by the client extraction logic 62〇 is stored in the client extraction buffer 6ΐι. The conversion tables 6U and 613 include a substitute fleld and a control booth (C〇1 fldd) and operate to translate the client instructions received from the customer extraction buffer 611 into the native command layer (( 1 flap (four) plus can (6). The multiplexer (mUltiplexer) 6] 4 and 6ι5 transfer the converted local command to the local conversion buffer g 616. This machine is used to convert the native command to 616. The face blocks are then mixed with the native hardware cache 608 and the mapping is maintained in the translation lookaside buffer 630. The translation lookaside buffer 630 includes the following data structure: the client branch address ( Guest branch address 63, localized block range 633, converted block range 633, code cache and conversion look aside buffer management (four) 634, and dynamic branch A dynamic branch bias bit 635. The client branch address 631 and the native address 632 contain a range of client addresses indicating which of the corresponding local translation blocks reside in the translated extent 633. Management agreement The replacement strategy ensures that the popular local conversion block map resides in the translation lookaside buffer 630. The simultaneously unsealed local conversion block map resides in the translation lookaside buffer data structure 603 of the system memory 601. 201245976 In the case of System 500, it is attempted to ensure that the popular block map resides in the high speed low latency transition lookaside buffer 63. Thus, in one embodiment, when the extraction logic 640 or the client extraction logic 62 is viewed To extract the client address, the extraction logic 64 〇 first checks the client address to determine if the corresponding local conversion block resides in the native code cache 6〇6. This allows to determine whether the requested client address is There is a corresponding local conversion block in the local code cache 6〇 6. If the requested client address does not reside in the buffer 003 or 608, or the buffer M0, the client bit is extracted from the client code 6〇2 The address and a number of subsequent client instructions, and the conversion process are implemented via conversion tables 612 and 613. Figure 7 shows an auxiliary software-based accelerated conversion pipeline (secondary soft) in accordance with an embodiment of the present invention. An example of a hardware-accelerated conversion system 7A of the ware-based accelerated conversion pipeline. Components 711-716 include a software-implemented load store P^th which is, for example, in a special high-speed memory 760. As depicted in FIG. 7, the client mentions that the buffers 7, the conversion tables 712-713, and the local conversion buffer 716 contain special idle speeds. The allocation portion of the body 760 (aii〇cate(j p0rti〇n). In many respects, the 'special high-speed memory 76' is used as a very low-order (1〇w_level) fast cache (eg, L0 cache). The first header 761 illustrates the attributes that are accelerated by the loading of the storage path as opposed to the instruction fetch path (eg, from the october logic). The high-speed memory 760 includes the 201245976 special logic for comparison. Because of this, the software can implement the conversion acceleration. For example, in another embodiment, the towel is sewed and the pipeline is w executi〇n pipdine. The standard record of the manipulation storage component 711_716 is that the software executes the comparison instruction of the value of the component 711_716 or the plurality of SIMD registers and processes the comparison between the fields in the SiMD register in the processing n execution pipeline, And perform the mask operation (mask 〇perati〇n) and the result scan operation as needed. The load storage path can be implemented using a general purpose microprocessor hardware (such as, for example, using a comparison command that compares one to many). It should be noted that the memory 760 is accessed by an instruction having a special attribute or address range. As in the specific embodiment, the client fetch buffer has a ro for the gUest instruction entry. An ID is created for each customer order. This ID allows easy mapping from the client buffer to the native conversion buffer. Melon allows for easy calculation of customer offset to native offset, regardless of the different lengths of the customer's native command. This is done in Figure 3 above. In a specific embodiment, the ID is calculated from the hardware using a length decoder that calculates the length of the extracted client instruction. However, in the second, the functionality can be fulfilled by hardware or software. Heart', once the ID is assigned, the native instruction buffer can be accessed via the ID. The offset conversion of the customer offset to the native offset is still allowed. FIG. 8 shows a CLB combined code 20 201245976 in accordance with an embodiment of the present invention. The CLB is used to store a client address having a corresponding converted local address (stored in the code cache). Mapping (eg, client-to-native address mapping) In a particular embodiment, clb is indexed as part of the client address. Customer address can be divided into #财!丨, 赖 (tag), and 娜f (eg, memory contribution small (10). This customer address contains a standard weaving to identify the matching of the CLB item cap. If the life is on the label, then the dragon's item The pointer irrr) will be stored, and the reference code in the code cache (four) 杂 will be mixed into the corresponding conversion memory unit (for example, the corresponding block of the native age). _ should be the idea, the term "memory block" is used herein to refer to the size of the U-memory of the native instruction block. The size of the memory block can vary depending on the size of the hard local instruction block. + In the specific embodiment, 'about the code cache memory 8G6, with a set of fixed l, 6 £fe blocks (such as 'each memory block type has different size) assigned code faster in the system memory and all Lower-order hardware cache (for example, native hardware cache ^ hardware cache 6〇7) +, can be divided into several groups of code cache fast CLB can use the customer address for indexing and labeling Compare the way tag for the process "', and take the code cache chunk. 1 party ^ 8 description of the town cafe hardware cache 804 to depict the way x and mode y The two store customer address tags are stored. It should be noted that, in a specific embodiment, the indicator can be stored in the local code memory block through the i, ', and ° configuration, and the client address of the CLB node 21 201245976 a is completed. Local address mapping (eg, from client to native address mapping). Each mode is associated with a tag. CLB is indexed by client address 802 (including tags). When a lifetime is sent in CLB, the corresponding is returned. The indicator of the label. Use this "to display the memory of the index program. This is shown in Figure 8 with a line of text "Local address of the code memory block = Seg#+F(pt)", which represents the fact that the code's local address with the indicator and section The number changes. In this particular embodiment, a segment refers to the basis of the point in the memory for virtual mapping of the pointer scope (e.g., allowing the index array to be mapped to any region in the entity's memory). Or 'in a specific embodiment' can be via a line of text as shown in Figure 8 "The local address of the code memory block = seg # + index * (64 memory block size) + way # * (memory block size) The second method of display, the index code caches the memory. In this embodiment, the code cache can be organized into a way-structure matching CLB mode structuring so that there is a way between the CLB mode and the way the code caches the memory block. ι:1 mapping. When the life is in the specific CLB mode, the corresponding code memory block in the corresponding mode of the code cache has the local code. Still referring to Figure 8, if the index of the CLB is missed, it is possible to check if the higher level of the memory has a hit (e.g., 'L1 cache, L2 cache, etc.). If there is no life in these higher cache levels, the address in system memory 8〇1 is checked. In a specific embodiment, the 'Customer Index points to an item containing, for example, 64 memory blocks', the tags of each of the 64 memory blocks are read and compared to the customer tags to determine whether or not to be in life. This procedure is shown in Figure 8 by the dashed box 8〇5. If there is no hit after comparison with the tag in the system memory, 22 201245976 there is no conversion at any level of the memory, and the client instruction must be converted. In accordance with a specific embodiment of the present invention, the hierarchical levels of the memory of the client-to-machine instruction map are stored in a cache-like manner. This was originally from cache to cache_based _〇ry (for example, clb hardware cache, native fast ^ U and U cache, etc.). However, CLB also includes "code cache + CLB processing bit", which is used to implement client-to-native instruction mapping in system memory, and least, least (LRU) replacement management strategy. In a particular embodiment, the 'CLB management bit (e.g., (10) bit) is managed by the software. In this manner, all hierarchy levels of the memory are used to store the most recently used client-to-native instruction map. Correspondingly, this results in the same level of storage all of the most commonly encountered conversion native instructions. "Figure 8 also shows the dynamic branch offset value bits and/or branch history bits stored in the CLB. These dynamic branch bits are used to track the branches of the sequence for 5 and 4 families. Predicted behavior. Use these bits to track which branch predictions are most often correctly predicted, and which branch predictions are most often incorrectly predicted. CLB also stores conversion block range data. This data enables programs to make code faster. The conversion block range of the corresponding client instruction in the memory has been modified (eg, in the self-modifying code) becomes invalid. Figure 9 shows a physical storage stack cache implementation (physical storage) in accordance with an embodiment of the present invention. An exemplary flowchart of the stack cache implementation and client address to local address mapping. As depicted in Figure 9, the cache can be implemented as a physical storage stack 901. 23 201245976 Figure 9 illustrates the embodiment of the code Take the implementation of the variable fabric cache (wiabie structure cache). Depending on the requirements of different implementations, the variable structure cache can be completely hard. Implementation and control, full software implementation and control, or software forcing and control mixing with basic hardware enabled. Figure 9 illustrates a specific embodiment of managing allocation and replacement of customer-to-native address mapping and its actual physical storage towel The optimal balance between the translations of the corresponding translations is achieved. In this embodiment, this can be done by using a combination of indicators and a structure of a variable size memory block. ° Using a multi-mode tag array (ie lti_way tag array) Storing metrics for physical storage of different sized groups. Each time a specific storage size needs to be allocated (eg, where the storage size corresponds to the address), the groups corresponding to the storage blocks corresponding to the size are allocated accordingly. This allows the embodiment of the present invention to accurately allocate storage to store variable size instruction trajectories. Figure 9 shows how groups can belong to different sizes. No two exemplary group sizes: "Group size 4 Replacement candidate and "group size 2 replacement candidate". In addition to the label corresponding to the address, the indicator is also stored in the array of irons that map the address to the physical storage address. A tag can contain two or more subtags. For example, the first three of the label structures 9〇2 contain sub-labels ai(1), A2 C2 D2, and A3 B3, respectively, as shown. Thus 'label A2 B2 C2叱 contains group size 4, and label A1 B1 contains group size 2. Group size mask (4), such as Cong p also indicates the size of the group. The body can be managed like a stack, so that each time a new group is assigned, the new group is placed on top of the physical storage stack. The project is invalidated by overwriting the label of the project 24 201245976, thereby restoring the allocated space. Figure 9 also shows an extended mode tag structure (extended way ton stmcture) 903. In some cases, items in the tag structure 902 will have corresponding items in the extended mode tag structure 903. This depends on whether the project and tag structure have a defined extension mode bit (for example, set to one). For example, setting the extension mode bit of ^ indicates that there is a corresponding item in the extension mode label structure: The extension mode label structure allows the processor to extend the reference area (locality 〇f reference) in a different manner than the standard label structure. Thus, although the tag structure 902 (e.g., index (1)) is tagged in one way, it is in a different manner (e.g., indexed tag structure. In the n-type implementation, the index (1) can be distinguished in the index (k). Project. This is because, in most of the restrictions, the main tag structure and mode tag structure 903 is much larger, for example, 1 can cover Cong items (such as '10 bits) and (k) can cover 256 (such as , 8-bit). This makes the implementation of the present invention spliced for matching has become a very embarrassing way, 'If you can't hide in the standard, use the extended label structure to store the extra for the popular track. J ^ & 'This variable cache structure provides an efficient storage capacity of 25 201245976 compared to the fast stored data stored on the heap when needed only: the fixed entity data store of the parent cache set) Increasing β can also have an indication—a octet (for example, meaning that the set of clusters or groups of groups is a stack of uncoled collections that look like \r has not been accessed for a long time). In this wealth, these (bubble). At this time, the distribution index of the bubbles in the stacked storage can be allocated for the image. This program is to store the back door set to use these cold door sets (C〇ld set) P job ss), 1 in the Lai earn p: recycling and reuse program (10) the entire set of clearings after the stack is assembled, the memory block Belongs to the structure (not shown / exempted in Figure 9; promoted = „required mechanism for reuse and a collection of – to be mixed) is: every recycling process (where =====' and This v allows; === The new memory block allocation indicator and its stacking_ side are applied to the stacked t. The specific embodiment of Figure 9 is fully suitable for using standard memory. In fact, the memory is relatively This attribute is caused by the fact that the child is added to the metric by reading the indicator, reading the index, and assigning the address range. In this embodiment, no special cache is required as the base circuit structure. Note that, in a specific embodiment, the architecture of Figure 9 can be used to implement a #material cache and cache scheme that does not involve conversion or handle transformation. gj, this can be used Figure 9 26 201245976 ==:== rrr 〇 Its K is given to the corresponding group. The group mask ^ paper is matched by the subfieid of the customer instruction (subfieid) The specific group _ hair #魏. Fresh miscellaneous customer ^ ΓΓΓΓ::) Γ related bits, in order to specifically view the relevant bits. = Table first read the nucleus when reading the hood - the standard pair to the table = press = :=? is drawn from top to bottom) _ read in the direction of the right direction to match the style. Press i to give priority to the different masks checked by the superiority of the mask-tag storage:::C The function is to boast the first level table 1004 diagram in this way, each bit conversion table in the buffer, in which the conversion table of each level (9)t (bytest_) is sent to j to continuously detect the position of the slot. The form replaces the equivalent field of the machine when the relevant bit field of 2012 2012976 is detected. The form also generates an alternative program for the use of this level and the next level table (eg, level table 1004) (substituti〇n process) Control field. The next table uses the control field of the previous table to identify the next relevant bit field, which is replaced by the native equivalent field. The second level table can then generate a control block to help Level 1 form, and so on. Once all customer bit blocks are blocked with native bits The alternate 'instruction is fully translated and passed to the local conversion buffer. The native conversion buffer then writes the code cache, and its client-to-native address mapping is recorded in the CLB, as described above. Figure 11A shows this A schematic diagram of an exemplary pattern matching procedure implemented by a particular embodiment of the invention. The destination is determined by labels, patterns, and masks as depicted in Figure 11 A. The functionality of the pattern decoding includes performance bit comparisons (e.g., bitwise elements) X0R), the fulfillment bit AND (eg, bitwise AND), and subsequent check of all zeros (eg, the NOR of all bits). Figure 11B shows a schematic diagram of a SIMD scratchpad based pattern matching procedure in accordance with an embodiment of the present invention. As shown in Figure 11〇〇, four SIMD registers 11〇2-11〇5 are displayed. These registers implement the functionality of the style decoding program as shown. Parallel bit comparisons (e.g., 'bitwise X〇r') are performed on each of the tags using the incoming pattern 1101, and the result fulfills the bitwise AND of the mask (e.g., bitwise AND). The match indicator results are each stored as shown in their respective SIMD locations. Then performing the scan as shown, and scanning the first "true" encountered in the simd component is the component in which all i-bit equations (pi X〇r Ti) ANDMi = 〇 are true, where Pi is the corresponding style, Ti is the corresponding label of 201224976 and Mi is the corresponding mask. Figure 12 shows a diagram of a unified register file l2〇l in accordance with an embodiment of the present invention. As depicted in Figure 12, the unified scratchpad file 1201 includes a two-part 1202-1203 and an item selector (emry SeleCt) 1205. Unified Scratchpad File] 2〇1 Architecture to support hardware status update Speculation (architecture speculation). System-temporary file escrow can implement optimization shadow temporary #||(Gptimized and ^ (C_iUed) register state management program. This process needs to be in the temporary and approved scratchpad functionality, and not In the embodiment, any copy is copied. For example, it is provided in a specific 1205. In Figure 12, the field of the game is mostly from the item selector from part 1 and part/each register file project by respectively Between, the profit and the size of each item 构成 。. In any given part 2 of the self-part one, is the value from the bit, (four) _ _ ^ 5 for each = material date of drinking 4 Different combinations. The values of X and y bits are as follows: (8): R is invalid; 01: R is speculated; W: R is recognized; Π: R is recognized; Accreditation is invalid (after reading the request R, after) After reading the read request R) (after the item has read the read request R) (after reading the read request rule) 29 201245976 οο The influence of each instruction/event (impaet). After going back, U) 00 ϋ1 becomes 10. After the command "approval", G1 becomes 11 and 10 becomes 11. After the 1st response event (roUbackevent), 01 becomes 00, and the event stored in the register file item selector 1205 of Hi ίί is changed into a bit transition when the money is generated. Breaking: Si 2 can continue to execute in the shadow register state without temporarily storing paper 4. ^Sub-temporary 11 state ready for approval, update: save = the target selector causes the read from the part in the above manner = = start,: ''only need to update the scratchpad file item selector, then the heart TM_10 In the case of an exception, it can be returned to the nearest w (e〇mmit p. ♦ Similarly, the recognition point can move forward, and the error is only confirmed by the update of the temporary project. = Functionality does not require any cross-copying between the H-requests for 0. In this way, 4 temporary storage n can be recorded via the temporary 1205, HSSSR) and a number of approved registers (received ed Π i, SSSR material It Wei CR temporary storage boundary. In response, the SSSR state reverts to the CR register. ° 201245976 Figure 13 shows a speculative architectural state and transient state in accordance with an embodiment of the present invention. Schematic diagram of a unified shadow register file and pipeline architecture 1300. The specific embodiment of the present invention depicts a component that includes a support architecture 1300 that includes architectural push State instructions and results and support for transient instructions and results. As used herein, the recognized architecture state contains visible registers that can be accessed by programs executing on the processor (eg 'sbuy and write'). Ble register) and visible memory. Conversely, the speculative state of the architecture contains registers and/or memory that are not recognized and therefore not globally visible. In one embodiment, four are enabled by the architecture 13 A usage model is used. The first usage model includes architectural speculation of hardware state updates, as described above in the discussion of Figure 12. The second usage model includes dual scope usage (dua) sc〇pe usage. Can be used to extract 2 threads into the processor, one of which executes in the speculation and the other thread in the non-speculative state. Here we use the model towel, two fan threats It is extracted into the machine (4), and exists in the machine. In the fourth (4) includes instructions from one form to another form of JIT (and configuration ί ί used in this model, via software (such as 'JiT) heavy row The third usage model can be turned into, for example, client-to-native instruction translation, virtual 31 201245976 to machine-to-native instruction translation, or to remap/translate native microinstructions into more optimized native microinstructions. The usage model includes transient c〇ntext switching instead of archiving and restoring the previous environment after returning from the transient environment. This usage model is suitable for environment switching that can occur for several reasons. One such rationality is, for example, to accurately address exceptions through an exception handling environment (excepti〇n hanc|iing context). The second, third, and fourth usage models are further illustrated in the discussion of Figures 14-17 below. Referring again to Figure 13' architecture 1300 includes several components for implementing the four usage models described above. The unified shadow register file 1301 includes: a first part, an approved temporary benefit file 1302; a second part 'shadow register file 1303; and a third part, a latest indicator array 1304. It also includes a speculative retirement memory buffer (SMB) 1342 and a new indicator pay array 1341. The architecture 1300 includes a 〇ut of order architecture. Thus the architecture 1300 additionally includes a reorder buffer and retirement window 1332. The rearrangement and withdrawal window 1332 additionally includes a machine retirement pointer 1331, a ready bit array 1334', and a per instruction latest indicator, such as an indicator 1333. The first usage model, i.e., architectural speculation of hardware state updates, is further detailed in accordance with an embodiment of the present invention. As mentioned above, the architecture 1300 includes an out-of-order architecture. The hardware of architecture 1300 can recognize out-of-order instruction results (eg, out-of-order loading and out-of-order storage and out-of-order register updates). The architecture 1300 above utilizes the system-shadow register file in the 32 201245976 mode of Figure 12 to support speculative execution between the recognized temporary registers. In addition, the architecture 13 is speculatively executed using the speculative t^T^rculaxive ioad store buffer 1342. 〗 332 f:: will use these components with the rearrangement buffer and withdraw the window 1332, in order to allow its state to be properly withdrawn _ endorsement register file (10) and 2 body ^ 5 0 even if the machine Wei Wei method will put these components in (4) Withdrawal of the unified shadow register file and withdrawal of the memory buffer. For example, the racking case 1301 and the speculative memory 1342 are based on an example; the function of generating and retrieving the t° is such that the state of the register can be removed in an unordered manner by 1342. The speculation is withdrawn from the memory buffer disorder. As the speculative execution continues:: then the machine withdraws the indicator coffee to move forward until the trigger register is moved by its approval point forward. ^ The second memory buffer is retracted according to the machine (4) 1 = Shop___ _1332 1-7, Ready bit _ 1334 shows the pure line of = (10) ' __ 7" additional instructions to be executed. According to this, == _^ is allowed to proceed. Thereafter, if Exceptions such as Le Shi Wu and Li You 1 / Knife can reply to the instruction that occurred after Command 6. Or,

U ’ and * can occur exceptionally, and all instructions can be approved by phase J 133! Hey. ❹Recalling </ s> 33 201245976 A pound uses the latest indicator array 1341, the latest indicator array 13 〇 4 and the latest indicator does not match 13 』 3 to allow out-of-order execution. For example, even if instruction 2 is in the register $4 register, then the instruction 5 is ready to occur, and the loading of instruction 2 will be ignored. The latest load will replace the previous load with the latest indicator. A branch prediction or a case = trigger reply event occurs within the rearrangement buffer and withdrawal window 1332. As mentioned above, when a reply occurs, the system-shadow temporary storage 1301 will revert to its last approval point, and push = 1342 will be flushed. Know: from the 3rd to the processor, one of the threads executes in the speculative state, the second is = push:: in the execution ^ as shown in the schematic, 2 materials / obstruction, and M0 lion track. Architecture start = two two =

The mode is executed, and the other is in the SR/SM 34 201245976 Recalling the second (10) mode, reading and writing the approval register, and recording S; SR: memory. In SR/SM mode, the scratchpad writes into the punch (Lion 7 reads from the latest writes) and the memory writes back to the memory. The instance will be sorted by the current age (such as 'just) and pushed The post is ridiculous (eg, 1&gt;4〇2). Because the next category is extracted after the current category, 22: the text is attached to the importance of 'so both categories can be implemented in the machine. For example, in the O4G1 In the "Approved SSSR is CR", until the temporary benefit and the brother's memory are in CR mode, the code is executed in CR/CM mode. In =_, the code is executed in SR^M mode. , === := Reply. In this way, the two categories are executed simultaneously in the machine, but each is executed in a different mode and the register is read and written accordingly. Figure 15 shows a specific one according to the invention The schematic of the third usage model of the embodiment, 1·, which includes transient environment switching, does not have to archive and restore the previous environment after returning from the transient environment. As described above, this turns the reliance on for several reasons. Wei She.—The reason for this may be, for example, the precise handling of exceptions through exceptions. 4 The usage model occurs when the machine is performing transcoding and when it encounters an environment switch (eg, an exception in a transcoding or a subsequent code translation is required). In the current Van # (eg, before the exception) 'SSSR and SMB The state of the customer's architecture has not been approved yet. The current state is running in SR/SM mode. In the exception of the temple machine, the knife is switched to the exception handling (eXCepti〇n hancJler) (eg, converter) for precise processing Exception. Insert the reply, which causes the temporary storage of the ribs to be cr^. %: 35 201245976 is cleared. The converter code will run in the SR/CM mode. During the period, _ withdraw its environment back to the memory ^ The change = period is written and the CR is not updated. Thereafter, when the converter::: and = the return code is converted, the converter returns (eg, back, CR) ° during this procedure, the last approved The register status is in. This is shown in Figure 15〇〇, where the previous fan SS is recognized as CR. The current practice track (10) is speculative. Temporary = and 5 recalls and this snake turn is speculation Sexuality, and execution in sr/sm In this example 'exceptions occur in (4)(9)2 And the need to re-execute the code in the original order prior to translation. In this case, SSSR be replied and smb is emptying Next 'πτ code 1M) 3 performed. The JIT code restores sssr to the end of the current measurement and clears the SMB. Execute m in SR/CM mode. At the end of the mouse, SS^R is reverted to CR' and the current trajectory i 5〇4 is then re-executed in the translation order of the clerk. In this way, exceptions are accurately handled in the exact current order. B Figure 16 shows a diagram in accordance with the present invention - the exception to the exception in the sequence of bribes is that the subsequent code needs to be translated. As shown in diagram 1600, the previous age/track_farjumped to the untransferred. End with the destination. Before jumping to the far-away destination, the recognition of the ruler is cr. The Jir-weight code 1602 then executes a client instruction to translate the far-hop destination (e.g., to establish a native command ride trajectory). Execute ιτ in SR/CM mode. At the end of π, the scratchpad state is reverted from the SSSR to CR, and the new ^can' track 1603 translated by m begins execution. The new fan track continues in the mode from the last recognition point of the previous category/track 1601. 36 201245976 Figure π shows a schematic 1700 of a fourth usage model in accordance with an embodiment of the present invention that includes transient environment switching that does not require archiving and restoring the previous environment after returning from the transient environment. As mentioned above, this usage model is suitable for environmental switching that can occur for several reasons. One such reason may be, for example, processing the input or output via an exception handling environment. The garment schematic 1700 shows a case where the previous van/trajectory 1701 executed in the CR/CM mode ends with a call to the function F1. The scratchpad status up to this point is recognized as CR from the SSSR. The function F1 category/trajectory 17〇2 then begins to be performed speculatively in the SR/CM mode. The function F1 then ends with a return to the main category/destruction 1703. At this point, the scratchpad status is reverted from the SSSR to cr. : Fan *#/Exit 1703 Reentry is performed in CR/CM mode. Figure 18 shows a diagram of an exemplary microprocessor pipe (=iCr〇processor pipeiine) 18〇〇 in accordance with an embodiment of the present invention. The microprocessor pipeline 18〇°〇 includes a functional hardware conversion accelerator that implements the hardware acceleration conversion procedure described above. In the specific embodiment of FIG. 18, the hardware conversion accelerator is coupled to the extraction module ΐ8〇ι, followed by the decoding module 1802, the distribution module 18〇3, the dispatch module (this (10) is also mHe) 1804, and the execution module. Group 1805 and withdrawal module 1806. It should be noted that the microprocessor line 1 is merely an example of a pipeline for carrying out the above-described specificity of the present invention. Those skilled in the art will appreciate that other microprocessor pipelines including the functionality of the above described decoding modules can be implemented. The above description has been made with reference to specific embodiments for the purpose of illustration. However, the above discussion of the present invention is not intended to be exhaustive or to limit the scope of the invention. DETAILED DESCRIPTION OF THE INVENTION The principles and practicalities of the present invention should be relied upon by the best skilled in the art for various modifications to the intended use, and the present invention and various specific embodiments are used. The figures are illustrated in the drawings, and like reference numerals represent like elements. 1 shows an exemplary sequence of instructions that operates in accordance with an embodiment of the present invention. 2 shows a schematic diagram depicting a block-based translation procedure in which a client instruction block is converted to a native conversion block, in accordance with an embodiment of the present invention. 3 shows a schematic diagram illustrating the manner in which individual instructions of a client instruction block are converted to native instructions of a local conversion block in accordance with an embodiment of the present invention. 4 shows a schematic diagram illustrating the manner in which a local conversion block handles a farther branch in accordance with an embodiment of the present invention. Figure 5 shows a schematic illustration of an exemplary hardware accelerated conversion system in accordance with an embodiment of the present invention, which illustrates the manner in which client instruction blocks and their corresponding local conversion blocks are stored in a cache. Figure 6 shows a detailed example of a hardware accelerated conversion system in accordance with an embodiment of the present invention. Fig. 7 shows an example of a hardware acceleration conversion system having an auxiliary software acceleration conversion main line according to an embodiment of the present invention. Figure 8 is a diagram showing an exemplary flow chart illustrating the manner in which a CLB combines a code cache with a client command to a native command map stored in a memory in accordance with an embodiment of the present invention. 38 201245976 Figure 9 shows an illustrative flow diagram illustrating a physical storage stacked code cache implementation and client to native instruction mapping in accordance with an embodiment of the present invention. Figure 10 shows a schematic diagram depicting additional exemplary details of a hardware accelerated conversion system in accordance with an embodiment of the present invention. Figure 11A shows a schematic diagram of an exemplary pattern matching procedure implemented by a particular embodiment of the present invention. Figure 11B shows a schematic diagram of a SIMD scratchpad based pattern matching procedure in accordance with an embodiment of the present invention. Figure 12 is a schematic diagram of a register of a register according to the present invention. A specific embodiment includes a dual-use diagram showing the use of a model in accordance with the present invention. - The representation of the third usage model of a particular embodiment does not have to be labeled after returning from the transient environment. Figure 15 shows the intent according to the present invention' which includes transient environment switching and restoring the previous environment. The reason is that the follow-up program % _ is a schematic diagram of the case example of the example in the riding instruction sequence, which includes the transient ring &amp;# concrete embodiment of the fourth use model and the restoration of the previous environment 、 , ' After returning from the (4) environment, it is not necessary to check the figure 18 to show the pattern according to the first line of the present invention. Exemplary microprocessor tube 39 of a specific embodiment 201245976 [Main component symbol description] 100 instruction sequence 101~104 branch instruction 201 client instruction block 202 native conversion block 301 client instruction buffer 302 native instruction buffer 401 Client instruction sequence in memory 402 Native instruction sequence in memory 411 Customer instruction far branch 412 Corresponding local instruction client far branch 500 hardware acceleration conversion system 501 记忆 memory 502 client extraction logic unit 503 client Extraction buffer 504 conversion table 505 local conversion buffer 506 conversion backup buffer 507 local cache 508 processor 600 hardware acceleration conversion system 601 system memory 602 client code 603 conversion backup buffer 604 optimizer code 201245976 605 606 607 608 609 610 611 612 613 614 615 616 620 630 631 632 633 634 635 640 650 700 711 712 713 716

Converter code native code cache shared hardware cache buffer TLB client hardware cache client extraction buffer conversion table conversion table multiplexer multiplexer local conversion buffer client extraction logic conversion backup buffer conversion area Block Login Point Address Local Address Conversion Address Range Code Acquisition and Conversion Backup Buffer Management Bit Dynamic Branch Deviation Value Bit Extraction Log Processor Hardware Acceleration Conversion System Customer Extraction Buffer Conversion Table Conversion Table Machine conversion buffer 41 201245976 760 Special high-speed memory 801 记忆 memory 802 Customer address 804 CLB hardware cache 805 dotted line box 806 code memory 901 physical storage stack 902 label structure 903 extension mode label structure 1000 Hardware Acceleration Conversion System 1001 Line 1002 Table 1003 Table 1004 Second Level Table 1100 Not intended 1101 Incoming Style 1102~1105 SIMD Register 1201 Unified Register File 1202-1203 Part 1205 Item Selector 1300 Unified Shadow Register File and Pipeline Architecture 1301 Unified Shadow Register File 1302 Approval Scratchpad file 1303 Shadow register file 1304 Latest indicator array 1331 Machine retraction indicator 42 201245976 1332 Reorder buffer and retract window 1333 Latest indicator 1334 Ready bit array 1341 Latest indicator array 1342 Presumably recall memory buffer 1350 Visible memory 1400 Unintentional @ 1401 Current non-speculative category / Persecution 1402 New speculative category / Obstruction 1500 Not intended 1501 Previous category / Obstruction 1502 Current Fan Threat / Trajectory 1503 JIT Code 1504 Current Fan Ming /Track 1600 Schematic 1601 Previous Category / Execution 1602 JIT Code 1603 New Category / Track 1700 Schematic 1701 Previous Category / Track 1702 Function F1 Fan Hip / Obstruction 1703 Main Category / Execution 1800 Microprocessor Pipeline 1801 extraction module 1802 decoding module 1803 distribution module 43 201245976 1804 dispatch module 1805 execution module 1806 withdrawal module 1807 unified shadow register file 1808 speculative memory buffer 1809 global visible memory / cache 44

Claims (1)

201245976 VII. Patent application scope: 1. A hardware-based translation accelerator, including: 2: Household extraction logic component 'used to access a plurality of customer protection Bayi customer extraction buffers, coupled to the prediction component' The plurality of conversion tables for the plurality of customer age groups = the narrative and the - branch, which are connected to the client: the buffer household instruction block; the instruction block is translated into a corresponding local conversion block ; ° 'for the customer - the local cache, its _ to the conversion block; & material _ should be the local one conversion backup slower 'frequency limbs the native silk command block compilation The machine conversion block -_; Xiao stored in the customer which received the wheat backup buffer for a customer instruction to decide whether to occur - hit, the conversion has the corresponding - in the local cache - change the machine Wei The user instruction is executed in response to the hit, and the conversion backup buffer forwards the translated native instruction to request the hardware-based translation accelerator described in the first item of the patent scope, and the household access & logical access and processing The number of clients that are not related to the device . / i is a hardware-based translation accelerator as described in item 1, wherein the cache contains a cache of the most commonly encountered native conversion block of the age-old scarf. 'If, please patent scope! A hard-base translation accelerator, wherein a conversion buffer is maintained in the system 5 memory, and a cache consistency is maintained between the conversion lookaside buffer and the 45 201245976 conversion buffer. The hardware translation accelerator described in Li Fancai, &gt; is greater than the conversion backup, and (4) bribes to maintain consistency between the conversion buffer and the conversion backup buffer. • The hardware-based translation acceleration described in item 1 of the patent scope is 11 and its _ replacement buffer is implemented as _ to intermediate cache memory. &amp; R 円 low latency =, = for a processor to accelerate the translation of client instructions into the native command - each household extraction logic component 'used to access a plurality of client instructions; a customer extraction buffer, Transfer to the customer extraction prediction component, the _ branch 2 is connected to the customer extraction buffer, used to deduct the customer 7 volt block into a corresponding local conversion block; / 苳 ^ ^ machine cache , 纲卿嶋, _fine (four) local conversion-conversion backup buffer H, its _ to the local touch instruction block to the corresponding local conversion block - mapping; the age of the customer is received for a customer A subsequent buffer of the instruction to determine if a hit occurs, where the. The local cache has a corresponding conversion local command j (four) client instruction in the execution response _ hit, convert the backup buffer transfer _ the local instruction to 46 201245976 8. The system described in claim 7 Accessing the plurality of client instructions unrelated to the processor. The client (4) logical group 9 _, as described in the seventh paragraph of the patent, contains a replacement strategy to maintain a cache stored in the 1st-to-f backup buffer. The most commonly encountered local conversion block L, such as lit, is the system described in item 7, wherein in-system memory == the device, and in the conversion lookaside buffer and the conversion buffer ^ The system of claim 2, wherein the conversion buffer is greater than 2 switcher_ and uses a writeback strategy to maintain consistency between the switch buffer and the lookaside buffer. L2. The system of claim 7, wherein the conversion backup buffer is implemented as a high speed low latency cache memory for the pipeline. A microprocessor for a method of translating instructions, the microprocessor comprising: a microprocessor pipeline; a σ-body accelerator module coupled to the microprocessor pipeline, the hardware accelerator module The group further includes: an Bayi customer extraction logic component for accessing a plurality of client instructions; a client extraction buffer coupled to the client extraction logic component and a branch prediction component for combining the plurality of client instructions a client instruction block; 201245976 a plurality of conversion tables coupled to the client fetch buffer instruction block translated into a corresponding local conversion block; σ is used to cache the client a local machine, coupled Connect to the conversion table, the conversion block; the material _ should be the local machine - convert the reserve money to the local cache, and the mapping of the block to the corresponding local conversion block; After receiving a follow-up buffer for a customer instruction, the mosquito is a science-life towel, and the towel surface refers to green=the, and the local cache has a corresponding conversion local command; and The household deduction is in the execution of the response The hit 'the conversion lookaside buffer transmits the translated native instruction. 14. The microprocessor of claim 13 wherein the beta component accesses the plurality of client instructions unrelated to the microprocessor ^Customer Extraction Logic 15. The microprocessor of claim 13 wherein the diagnostic apparatus includes a (4) replacement strategy to maintain the most frequent storage of the towel: a version of the backup zone %% The present invention converts a system memory conversion buffer, the microprocessor of claim 13, wherein a conversion buffer is maintained in the body, and between the conversion buffer and the conversion buffer Maintaining the cache consistency. 17. The microprocessor of claim 16, wherein the read ~ is greater than the conversion lookaside buffer, and the write back strategy is used to convert between the buffer buffers and the backup buffer buffer A microprocessor as described in claim 3, wherein the conversion lookaside buffer is implemented as a high speed coupled to the microprocessor pipeline Fast when diving low 1^. The microprocessor according to claim 13 of the patent scope, wherein the hardware accelerator module and the parallel customer instruction extraction pipeline are instrucu〇n fetch pipeline) Parallel to a native microprocessor extraction pipeline (1) also functions as a microprocessor fetch pipeline. 20. A microprocessor that implements a translation instruction method, the microprocessor comprising: a microprocessor pipeline; 'It contains high-speed memory that touches the miscellaneous (four) tube and line, and the έ 加速 accelerator module additionally includes: a customer extraction logic 11 for accessing a plurality of client instructions; for extracting the memory of the customer by one The light is connected to the customer extraction logic and the plurality of accountant instructions are combined into a client instruction block; the corresponding local conversion=one rotation wire is used to translate the client instruction block into a one-local conversion delay _, secret Store _ where the n block for the -client command is received, the user command block to the corresponding local conversion block; the second index stores the guest to determine whether it occurs - hit, where trace, #, - turn The backup buffer fetches a - corresponding conversion native instruction X; and/or "the client instruction is in the local fast instruction in order to perform the response in response to the hit"; the buffer transmits the translated version 49 201245976 21. The microprocessor of claim 20, wherein the high speed memory comprises one of the microprocessors L0 cache. 22. The microprocessor of claim 20, wherein the accelerator module further comprises one of the microprocessors loading a storage instruction extraction path.