TW201243966A - Semiconductor device and method of forming insulating layer disposed over the semiconductor die for stress relief - Google Patents

Abstract

A semiconductor device has a semiconductor die and conductive layer formed over a surface of the semiconductor die. A first channel can be formed in the semiconductor die. An encapsulant is deposited over the semiconductor die. A second channel can be formed in the encapsulant. A first insulating layer is formed over the semiconductor die and first conductive layer and into the first channel. The first insulating layer extends into the second channel. The first insulating layer has characteristics of tensile strength greater than 150 MPa, elongation between 35-150%, and thickness of 2-30 micrometers. A second insulating layer can be formed over the semiconductor die prior to forming the first insulating layer. An interconnect structure is formed over the semiconductor die and encapsulant. The interconnect structure is electrically connected to the first conductive layer. The first insulating layer provides stress relief during formation of the interconnect structure.

Description

201243966 VI. INTRODUCTION OF THE INVENTION TECHNICAL FIELD The present invention relates generally to semiconductor devices, and more particularly to forming a wafer level chip scale having an insulating layer deposited on a semiconductor die for stress relaxation. Semiconductor device and method of package 'WLCSP> * [Prior Art] Semiconductor devices are commonly found in modern electronic products. The number and density of electrical components of semiconductor devices vary widely. Individual semiconductor devices typically include an electrical component such as a light emitting diode (LED), a small signal transistor, a resistor, a capacitor, an inductor, and a power metal oxide semiconductor field effect transistor (metal 〇xide semie(). Nduet()r field effect transistor, MOSFET). Integrated semiconductor devices typically contain hundreds to millions of electrical components. Examples of integrated semiconductor devices include a hard-to-manufacture device, a micro-processing n, a charge-capping device (CCD), a solar cell, and a digital micro-mirror device (4) g "al micro-mirror device (DMD)." A wide range of functions, such as high-speed computing, transmitting and receiving electromagnetic signals, control electronics...light conversion to electricity, generation for television display. Semiconductor devices appear in entertainment, communications, power conversion, networking, computers, and consumer In military applications, the use of semiconductor devices in the military (four) body device utilizes the electrical properties of the materials. The electrical properties of the materials. The atomic structure of the semiconductor material 201243966 allows the conductivity to be manipulated by applying an electric field or a base current or via a doping process. The conductivity of the semiconductor device is modulated by a semiconductor device. The semiconductor device includes active and passive electrical structures. The active structure includes bipolar and field effect transistors, which control the flow of current by changing the doping level and When an electric field or a base current is applied, the transistor promotes or limits the flow of current. Passive structure Including resistors, capacitors, inductors, which create the necessary relationship between voltage and electrical output to perform diverse electrical functions. Passive and active structures are electrically connected to form a circuit that enables the semiconductor device to perform high-accuracy calculations and other useful functions. Semiconductor devices are typically fabricated using two complex processes, namely front-end fabrication and back-end fabrication, involving hundreds of steps. Front-end fabrication involves the formation of multiple grains on the surface of a semiconductor wafer. For example, β is the same and contains circuitry that electrically connects the sway and passive components. Back-end fabrication involves separating individual dies from the completed wafer and packaging the dies to provide structural support and environmental isolation. The term "semiconductor die" as used herein refers to the singular and plural forms of the word, whereby a single semiconductor device and a plurality of semiconductor devices can be used. One goal of semiconductor manufacturing is to make smaller semiconductor devices. Devices other than j typically consume less power, have higher performance, and can be manufactured more efficiently. In addition, smaller semiconductor devices have a more occupied surface I*' which is desirable for smaller end products. The smaller 曰a grain size can be achieved by improving the front end process, which results in smaller, more dense active and passive components. The back-end process can be used to achieve a semiconductor device package with a small footprint by improving the electrical connection and packaging materials by 201243966. In a conventional fan-level wafer level chip scale package (F〇 WLCSp), a semiconductor die having a contact pad is mounted on a carrier. The encapsulant is deposited on the semiconductor grains and the carrier. The carrier is then removed and the combined interconnect structure is formed over the encapsulant and the semiconductor die. Semiconductor grains are subject to cracking, buckling, and other damage during the formation of the interconnect structure. The redistribution layer of the combined interconnect structure is prone to cracking under stress, especially due to temperature cycling (TC) and ingress into the grains. Cracking Problem During the temperature cycling (temperature cyc丨es (10) state, TCOB) on an insulative layer with an ultra-low dielectric constant (4), the crack can pass through the insulating layer to the semiconductor die and contact pads. And caused defects. Cracks can be transmitted from the edges and sidewalls of semiconductor grains

Fo-WLCSP is common.

SUMMARY OF THE INVENTION When forming WLCS

201243966 Body grain and encapsulation. The interconnect structure is electrically connected to the first conductive layer, and the first insulating layer provides stress relaxation during formation of the interconnect structure. In another embodiment, the present invention is a method of fabricating a semiconductor device comprising the following (4): providing a semiconductor die; forming a first conductive layer on a surface of the semiconductor die; forming a first insulating layer on the semiconductor die and a conductive layer; depositing an encapsulation on the semiconductor die; and forming an interconnect structure on the semiconductor die and the encapsulant. The interconnect structure is electrically connected to the first conductive layer, and the first insulating layer provides stress relaxation during formation of the interconnect junction #. In another embodiment, the present invention is a method of fabricating a semiconductor device comprising the steps of: providing a semiconductor die; forming a first conductive layer on a surface of the semiconductor die; depositing an encapsulant on the semiconductor die; Forming a first insulating layer on the semiconductor die and the first conductive layer; and forming an interconnect structure on the semiconductor die and the encapsulant. The interconnect structure is electrically connected to the first conductive layer ' and the first insulating layer provides stress relaxation during the formation of the interconnect junction. In another embodiment, the invention is a semiconductor device comprising a semiconductor die and a first conductive layer formed on a surface of the semiconductor die. The encapsulant is deposited on the semiconductor die. A first insulating layer is formed on the semiconductor die and the first conductive layer. The interconnect structure is formed on the semiconductor die and the encapsulant, the interconnect structure is electrically connected to the first conductive layer, and the first insulating layer provides stress relaxation during formation of the interconnect structure. The present invention is described in terms of one or more specific embodiments, and the same numerals represent the same or similar elements. While the present invention has been described in its preferred embodiments, the embodiments of the invention are intended to be The scope of the appended claims and the equivalents thereof are defined by the following claims. Semiconductor devices are typically fabricated using two complex processes: front-end manufacturing and back-end manufacturing. Front end fabrication involves the formation of multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. For example, the active electrical components of the transistors and diodes have the ability to control the flow of current. For example, a capacitive inductive resistor or a passive electrical component of a transformer creates the necessary relationship between voltage and current to perform a circuit function. The passive and active components are formed on the surface of the semiconductor wafer by a series of processing steps including doping, deposition, photolithography, etching, and planarization. Doping introduces impurities into the semiconductor material by techniques such as ion implantation or thermal diffusion. The doping process modifies the conductivity of the semiconductor material of the active device, converting the semiconductor material into an insulator, a conductor, or dynamically changing the conductivity of the semiconductor material in response to an electric field or a base current. The transistor contains an arrangement of varying doping species and extents that is necessary to enable the transistor to promote or limit the flow of current when an electric field or base current is applied. Active and passive components are formed from multiple layers of material having different electrical properties. The layers can be formed by a wide variety of deposition techniques, depending in part on the type of material to be deposited. For example, thin film deposition may involve chernical vapor deposition (CVD), material 201243966. Physical vaP〇r deposition (PVD), electrolytic plating, and electroless plating. Each layer is typically patterned to form the active component, the driven component, or the portion of the electrical connection between the components. The layers can be patterned using photolithography, which involves depositing a photosensitive material (such as a photoresist) on the layer to be patterned. The pattern is transferred from the reticle to the photoresist using light. In a specific aspect, a solvent is used to remove the portion of the photoresist pattern that is exposed to light' to expose the underlying portion of the portion to be patterned. In another embodiment, a solvent is used to remove the portion of the photoresist pattern that is not exposed to light (negative photoresist) and expose the underlying portion of the portion of the pattern to be patterned. Removing the rest of the photoresist leaves the patterned layer. Alternatively, some types of materials can be used, such as electroless or electrolysis, and the material is deposited directly into the area or hole formed by the previous deposition/synthesis process. (4) Patterning is the basic operation. It removes the top layer of the file on the surface of the semiconductor wafer. Some of the semiconductor wafers can be removed using photolithography, photomasks, masks, oxide or metal removal, photography and stereotyping, and microetching. First lithography involves patterning in a grating or reticle and transferring the pattern into the surface layer of the wafer. Photolithography is a two-step process that forms a horizontal dimension of the active and passive components on the surface of the semiconductor dome. The pattern on the grating or mask is transferred into the photoresist layer. The photoresist is: 'When it is exposed, it undergoes structural changes and (4) the qualitative change process occurs as a negative or positive acting photoresist: = Sex: = In the round surface, the semiconductor wafer top is removed: Not U The transfer took place in a time-sharing manner. The chemical nature of the photoresist causes the 9 201243966 photoresist to remain substantially π and resists removal by the chemical etch solution while the portion of the top of the semiconductor wafer that is not covered by the photoresist is removed. The process of forming, exposing, removing the photoresist, and removing portions of the semiconductor dome can be modified depending on the particular resist used and the desired result. The negative-acting photoresist is exposed to a photoresist and changed from a soluble state to an insoluble state in a process known as polymerization. Upon polymerization, the unpolymerized material is exposed to light or energy sources' and the polymer forms an etch-resistant crosslinked material. Most of the negative resister 'polymers are polyisoprene. Removal of the soluble portion (i.e., the unexposed portion) with a chemical solvent or developer leaves holes in the resist layer corresponding to the opaque pattern on the grating. If the pattern of the mask exists in an opaque area, it is called a clear field mask. In the case of a positive acting photoresist, the photoresist is exposed to a state which is known to be photolytic, and changes from a relatively insoluble state to an extremely soluble state. In the case of photolysis, the relatively insoluble resistance (4) is exposed to appropriate light energy and converted into a relatively soluble state. The photodissolved portion of the resist can be removed from the solvent during development. The basic positive-resistance polymer is a gradual ageing polymer, also known as the ageing varnish (4) Kt solvent or developer removes the soluble portion (ie, the exposed portion), corresponding to the grating under the resist layer (4) A hole in the transparent pattern. A masked case is called a dark-field mask if it exists in a transparent area. After removing the top of the semiconductor wafer that is not covered by the photoresist, the remaining portion of the photoresist is removed to leave a patterned layer. Alternatively, a twisted type of material can be used to pattern, for example, electroless or electrowinning techniques, while directly forming material into the area or hole formed by the previous deposition/etching process. Depositing the thin film material on the existing pattern can magnify the underlying pattern and create a non-uniform flat surface. A evenly flat surface is required to make smaller, tightly packed active and passive components. Flattening can be used to remove material from the wafer surface and create a flat surface. Flattening involves polishing the surface of the wafer with a polishing pad. Abrasive materials and relying chemicals are added to the wafer surface during polishing. The mechanical action of the abrasive combined with the chemical's corrosion removes any irregular surface pattern resulting in a uniform, flat surface. ...the penalty is completed from the normalization. One ~ from the π day four take the early crystals' and then encapsulate the grains to achieve structural support and environmental isolation. To singulate the die, the wafer is scribed and broken along a non-functional area of the wafer called a track or mine. The research day is rounded using a laser cutting tool or a saw blade. The 'single die is then mounted on the package substrate' which includes a pin-up or for interconnection with other system components. The contact pads formed in the semiconducting 2 are then connected to the junction (4) in the (4) package. Electrical connections can be made using solder bumps, pin bumps, conductive pastes or bond wires. The material is deposited on the package to provide: The completed package is then plugged into the electrical system and half of the power is used for other system components. The function of the device is shown in Fig. 2 as an exemplary electronic device 5. A printed circuit board (printed circuit) is mounted on the surface thereof. The electronic device is 52' and has a plurality of semiconductor packages. The semiconductor device can have a semiconductor package or a plurality of 201243966 semiconductor packages. Uses and β & exemplification, different kinds of semiconductor packages are shown in Figure 1. The electronic device 50 may be a separate system that uses a semiconductor package to perform one or more electrical functions, and optionally an electronic device 5 〇 is the secondary component of a larger system. For example, the electronic device 5 can be a mobile electro-metallurgy, a digital assistant (pDA), a digital video camera (Dvc), or other electronic communication. A part of the device. Alternatively, the electronic device 5 is a graphics card, a network interface card or other signal processing card, which can be inserted into the computer. The semiconductor package can include a microprocessor, a memory, and a specific application integrated circuit (appHcati). 〇n specific integrated circuit ' ASIC), logic circuit, analog circuit, RF circuit, separate device Other semiconductor dies or electrical components. Miniaturization and weight reduction are essential for these products to be accepted by the market. The distance between semiconductor devices must be reduced to achieve higher density. In Figure 1, PCB 52 provides a general substrate. The semiconductor package mounted on the PCB is structurally supported and electrically connected. The conductive signal line 54 is formed on the surface or layers of the PCB 52 by evaporation, electrolytic plating, electroless plating, screen printing or other suitable metal deposition process. Signal line 54 provides electrical communication between the semiconductor package, mounted components, and other external system components. The wire 54 is also connected to each semiconductor package by power and ground. In some embodiments, the semiconductor device There are two package levels. The first level package is a technology for mechanically and electrically attaching semiconductor chips to an intermediate carrier. The second level package involves mechanically and electrically attaching the intermediate carrier to the PCB. In other specific aspects, the semiconductor device may only Has a first level package, 12 201243966 where the die is directly mechanically and electrically mounted to the PCb. For illustrative purposes, several The level package (including bond wire seal % and flip chip 58) is shown on PCB 52. In addition, several second level packages, including ball grid array (BGA) 6〇, bump wafer carrier ( Bumper carrier carrier (BCC) 62, double-row package ('丨in_iine package DIP) 64, contact grid array (ian (j grid array, lga) 66, multi-chip module (MCM) 68 The quad flat n〇n-leaded package (QFN) 7-inch, four-sided flat package 72 is shown to be mounted on the pCB52i. Depending on the needs of the system, any combination of semiconductor packages constructed as any combination of the first and second level package types, as well as other electronic components, may be coupled to the PCB 52. In some embodiments, electronic device 50 includes a single attached semiconductor package, while other specific aspects require multiple interconnected packages. By incorporating __ or more semiconductor packages on a single-substrate, manufacturers can incorporate pre-fabricated components into electronic devices and systems. Because semiconductor packages include sophisticated functionality, & electronic devices can be fabricated using relatively inexpensive components and streamlined processes, the devices being serviced are less likely to fail, and are less expensive to manufacture, resulting in consumer expense. Also lower. Figure 2C shows a non-exemplary semiconductor package. Figure 2a illustrates the further steps of the DIP 64 installed on 2. The semiconductor die 74 includes an array of functions including analog or digital circuits, which are implemented as active devices formed in the die, a passive device, a conductive layer, a dielectric layer, and according to the Japanese The electrical design of the particles interacts, +A € transport. For example, the circuit may include one or more transistors formed in the region of the F 戸 region of the semiconductor die 74, and a circuit element of the winter body, the valley, the resistor, and the like. The contact pad % is made of a conductive material (for example, copper (Cu), tin (sn), recording (f), gold (four) or silver (Ag)) - or more layers, and is electrically connected to the semiconductor die μ The circuit components formed in the process. During the combination (10), the semiconductor die 74 is mounted on the intermediate carrier using a metal eutectic layer or an adhesive material (eg, thermal epoxy or epoxy). The 78° package includes an insulating packaging material such as a polymer or The conductors are bonded to the wires to provide an electrical connection between the semiconductor die Μ and the CB 52. The encapsulant is deposited on the package to prevent the fish and particles from entering the package and contaminating the die 74 or bond wires 82. To protect against environmental influences, Figure 2b illustrates further details of bcc 62 mounted on PCB 52. Semiconductor b particles 88 are mounted on carrier 90 using a bottom filler or epoxy adhesive material. Bond wire 94 provides contact Between % and % of a layer, package interconnect. Molding compound or encapsulant (10) is deposited on semiconductor germanium 88 and bond wires 94 to provide physical support for the device and electrically isolated contact pads 102 The surface of the PCB 52 is shaped to avoid oxidation using a suitable metal deposition process (e.g., electrolytic plating or electroless recording). The contact pads 1〇2 are electrically connected to - or more of the conductive signal lines M in the PCB 52. Bumps 1 〇4 formation The contact pad 98 of the BCC 62 is in contact with the contact 塾1〇2 of the pcB 52. In Fig. 2c, the semiconductor die 58 is facing down and is mounted on the intermediate carrier (1) & it is a flip-chip type - 纽纽·ί+ λ\ * i^· j. 罘 level packaging. The active area of the semiconductor die 58 is a three-class analog or digital circuit that is implemented as an active device, passive device, layer, dielectric layer formed according to the electrical design of the die. The circuit may include one or more transistors in the active region 108, a diode, a capacitor, a capacitor, a resistor, and other circuit components. The semiconductor die 58 is electrically and mechanically connected via the bump 110. Carrier 1〇6. BGA 60 is electrically and mechanically coupled to pCB 52, which is a second level package using a BGA version of bumps 12. The semiconductor die 58 is via bumps 110, signal lines II4, bumps 112. Electrically coupled to the conductive signal line 54 of the pCB 52. A molding compound or encapsulant i6 is deposited over the semiconductor die 58 and the carrier 106 to provide physical support and electrical isolation for the device. The flip chip semiconductor device provides the semiconductor Active device on die 58 to pcB 52 The short conductive path of the conductive path is used to reduce the signal transmission distance, reduce the capacitance, and improve the performance of the overall circuit. In another embodiment, the semiconductor die 58 can use a flip-chip type of first-level package without an intermediate carrier. 1〇6 is directly mechanically and electrically connected to the PCB 52. Figure 3a shows a semiconductor wafer 12A having a substrate material 122 (e.g., germanium, germanium, gallium arsenide, indium phosphide or tantalum carbide) to support the structure. Semiconductor dies or features 124 are formed on wafer 12 and separated by the inactive, inter-die wafer regions or saw streets 126 described above. The saw streets 126 provide a dicing area to singulate the semiconductor wafer 12 into individual semiconductor dies 124. Figure 3b shows a partial cross-sectional view of the semiconductor wafer 12A. Each of the semiconductor dies 124# has (four) 128 and an active surface, and the rear* includes an analog or digital circuit that implements an active device, a passive device that is formed in the die and is electrically connected in accordance with the electrical design and function of the die. , conductive layer,: electrical layer. For example, the circuit may include one or more electro-crystals H, diodes, and other circuit components formed in the active region to implement analog circuit 15 201243966 or a digital circuit, such as a dighal signal processor 'DSP )' ASIC, memory or other signal processing circuit. The semiconductor die 124 may also include an integrated passive device (iPD) such as an inductor, capacitor, or resistor for rf signal processing. Conductive layer 132 is formed on active surface 13A using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition process. Conductive layer 132 can be one or more layers of a Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 132 operates as a contact pad that is electrically coupled to circuitry on active surface 130. Contact pads 132 may be disposed at a first distance from the edge of semiconductor die 124 while being edged, as shown in Figure 3b. Alternatively, the contact pads 132 are offset in a plurality of columns such that the contact pads of the first column are disposed at a first distance from the edge of the die, and the contact pads of the second column interleaved with the first column are configured to A second distance from the edge of the grain. 3c' The insulating or dielectric layer 134 is formed on the active surface 130 and the conductive layer 132 using spin coating, spray coating, printing, layer 0 PVD, CVD, sintering or thermal oxidation. The insulating layer 134 comprises one or more layers. Cerium oxide (sad, tantalum nitride (Si3N4), niobium oxynitride (si〇N), antimony pentoxide (butazone 5), alumina (AhO3), benzocyclobutene (BCB), poly Amidoxime (ρι), polybenzoxazole (PB0), a dielectric substrate dielectric film, an organic polymer film or other material having similar insulating and structural properties. The etching process can be performed through the photoresist layer to remove portions. The insulating layer 134 is exposed to expose the conductive layer 132. The insulating or dielectric layer 136 is formed on the insulating layer 134 by spin coating, spraying, printing, lamination, PVD, CVD, sintering or thermal oxidation, as shown in Fig. 3d. In a specific aspect, the insulating layer 13 6 is applied as a blanket layer on the insulating layer 132. The insulating layer 136 comprises one or more layers of Si〇2, si3N4, SiQN,

Ta2〇5, Al2〇3, BCB, PI, PB0, a dielectric film of a polymer substrate, an organic polymer film or other material having similar insulating and structural properties. The insulating layer 136 is then cured. The insulating layer 136 operates as a stress relaxation layer to reduce cracking, buckling or other damage to the surface 13 of the semiconductor die 124 and the conductive layer 132 during the formation of the combined interconnect structure and for reliability. In particular, the insulating layer 136 has properties of high tensile strength greater than 1 〇〇 MPa at room temperature, high elongation between 2 〇 and 15 〇% at room temperature, and thickness 2 to 30. Micron (μιη). Figure 36 shows a specific aspect without the insulating layer 134, i.e., an insulating layer (Μ is formed on the active surface 130 and the conductive layer 132 for stress relaxation. In Figure 3f, the semiconductor wafer 12 is using a cutting tool (3) (for example, a saw) The sheet, the jet of water or the laser) is singulated into individual semiconductor crystals 12 through the mine channel 126. Figure 钧41; associated with Figure 1 and Wc to demonstrate the formation of WLCSp, which has a semiconductor crystal The insulating layer on the granules is used for stress relaxation. Figure 4a shows the temporary _ material (eg bite, polymer G, which contains a sacrificial substrate emulsified enamel or other suitable low cost rigid material and U structure. Interface A layer or double-sided tape 142 is formed on the carrier 14. The upper layer is then bonded to the film wire stop layer. The semi-guide from Figure μ is positioned and mounted on the interface layer and the body 140 using a pick and place operation, the field body The die 124 is mounted on the Gongxing surface 130 and is directed to the carrier. The ® 4b displays a semiconducting 140 to the exemplary portion of the reconstructed or reconstituted wafer 17 201243966 144. Figure 4c 'The encapsulant or molding compound 146 is printed using a paste , compression molding, transfer molding The liquid encapsulant is molded, vacuum layered, spin coated or other suitable applicator deposited on the semiconductor die 124 and the carrier. The encapsulant 146 may be a polymeric composite such as an epoxy with a filler, The epoxy acrylate having a filler or the polymer encapsulant 146 with a suitable filler is non-conductive and protects the semiconductor device from elements and contaminants of the external environment. In Figure 4d, the carrier 14 and the interface layer 142 are chemically bonded. The engraving, mechanical stripping, CMP, mechanical grinding, hot baking, ultraviolet light, laser scanning or fishing removal is removed to expose the insulating layer 136 and the encapsulant 146. After the carrier 140 is removed, the encapsulation is performed. The material 146 provides structural support for the semiconductor die 124. portions of the insulating layers 134 and 136 are removed by an etching process (not shown) having a patterned photoresist layer to expose the conductive layer 132. The etching process also removes portions. The encapsulant 146 reaches a level below the surface of the insulating layer 136, as shown in Figure 4d. Alternatively, portions of the insulating layers 134 and 136 are directly ablated by laser using a laser 148 (丨aser direct aMati〇n And removing to expose the conductive layer 132. After etching or LDA, the insulating layers 134 and 136 remain overlapping the conductive layer 132. In another embodiment, the deposition of the encapsulant 146 onto the semiconductor die 124 is formed. Insulating layers 134 and 136. In this case, a portion of the encapsulant 146 is removed to expose the active surface 130 and the conductive layer 132. The insulating layers 134 and 136 are then formed on the exposed active surface 13 and the conductive layer 132. The insulating layers 134 and 136 are removed by LDA or etching to expose the conductive layer 18 201243966 132» to Figure 4e, and the insulating or passivation layer ι5 is using Pvd, CVD, printing, spin coating, spray coating, screen printing or lamination. It is formed on the encapsulant 146 and the insulating layer i36. The insulating layer 150 includes one or more layers of Si 〇 2, Si 3 N 4 , Si 〇 N,

Ta2〇s, Ah〇3, polymer dielectric films or other materials with similar insulation and structural properties. A portion of the insulating layer 15 is removed by an etching process having a patterned photoresist layer to expose the conductive layer. Further, a portion of the insulating layer 150 and the insulating layers 134 and 136 are used by using the laser 148. The removal is to expose the conductive layer 132. In FIG. 4f, the conductive layer 152 is patterned on the insulating layer 150 and the conductive layer 132 using pvD, CVD, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition process. The conductive layer 152 may be a Or more layers of 1, (11, 811, 1^, VIII, VIII, or other suitable conductive material. A portion of the conductive layer 152 extends horizontally along the insulating layer 150 and is parallel to the semiconductor die 124 The active surface 130 is electrically interconnected laterally to the conductive layer 132. The conductive layer 152 operates as a fan-out redistribution layer (RDL) for the electrical signal of the semiconductor die 124. A portion of the conductive layer 152 is electrically Connected to conductive layer 132. Other portions of conductive layer 152 are electrically or electrically isolated, depending on the connectivity of semiconductor die 124. In Figure 4g, insulating or passivation layer 154 is PVD, CVD, printed, spin coated 'spraying, screen printing or laminating is formed on the insulating layer 15 and the conductive layer i 5 2 . The insulating layer 154 may be one or more layers of Si 〇 2, Si 3 N 4 ' si 〇 N, Ta 2 〇 5, AhO 3 , polymer dielectric film or other similar insulation and structure 19 201243966 Two materials. Part of the ... 54 is to have a patterned photoresist: Γ = Γ exposed conductive layer 152. Alternatively, part of the insulating layer m is removed using the LDA of the laser 148 to expose the conductive layer (5) In Figure 4h, the conductive bump material is deposited on the exposed conductive I 152 using an evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. The bump material: may be A, Sn, Ni, Au, Ag , pb, then, Cu, solder and combinations thereof, and optionally flux. For example, 'bump material can be eutectic s" puff, high lead solder or lead-free solder. Bump material using appropriate adhesion or bonding process In combination with the conductive layer 152. In particular, the bump material is remelted by heating the material above its melting point to form solder balls or bumps 156. For some applications, the bumps 156 are remelted twice. The electrical contact to the conductive layer 152 is improved. The bump 156 can also be compression bonded to the conductive layer 152. The bump 156 represents an interconnect structure that can be formed on the conductive layer 152. The interconnect structure can also use pin bumps, Microbumps or other electrical interconnections. Insulation layers 150 and 154, leads The combination of layer 152 and bumps 156 constitutes a combined interconnect structure 158 formed on semiconductor die 124 and encapsulant 146. Additional insulating layers and rd1 may be formed in combined interconnect structure 158 to interconnect to the semiconductor die 124 » Reconstituted wafer 144 is singulated into individual Fo_WLCSPs 160 by slab or laser cutting tool 159 via encapsulant 146 and combined interconnect structure 158. Figure 5 shows f〇_wLCSP 160 after singulation. Semiconductor die 124 is electrically coupled to an external device via a combined interconnect structure 158 that includes conductive layer 152 and bumps 156. In one embodiment, insulating layer 136 is formed over semiconductor die 124 prior to singulation from wafer 120. 20 201243966 properties of insulating layer 136 (ie, local tensile strength at room temperature greater than 100 MPa, high elongation at room temperature between 20 and 150%, thickness 2 to 30 microns) provide stress relaxation' In order to form a composite interconnection ^^β /廿a structure 158 (which includes the insulating layers 150 and 154, the conductive layer 152), cracks, / slaves, bends, and other damage to the crystal grains are reduced. Figure 6 shows the f〇-WLCSP 162 based on Figure 3 without the insulating layer 134. The semiconductor die 124 is electrically coupled to the external device via a combination of <〇, #^ A transport structure 158 (which includes conductive layer 152 and bump 156). In a particular aspect, the insulation is formed on the semiconductor die 124 prior to pre-evolving from the wafer 120. The properties of the insulating layer 136 (i.e., a high tensile strength f greater than 1 GG MPa at room temperature, a high elongation between 20 and 150%, and a thickness of 2 to 3 Å micrometers) provide stress relief to Cracks, enthalpy and other damage to the grains are reduced during formation of the combined interconnect structure 158 (which includes the insulating layers 15A and 154, the conductive layer 152). Figures 7a to 7g are associated with Figures 1 and 2a to 2C to illustrate another process for forming WLCSp having an insulating layer on the deposited conductor die for stress relaxation. Continued from Figure 3a, insulating or dielectric layer 17 The crucible is formed on the active surface 130 using spin coating, spray coating, printing, lamination, PVD, CVD, sintering or thermal oxidation, as shown in Figure 7a. The insulating layer 17A comprises one or more layers of Si〇2, Si3N4, SiON, Ta2〇5, Al2〇3, BCB, ρι, pB〇, a dielectric substrate dielectric film, an organic polymer film or the like Materials of insulating and structural properties. In one embodiment, the insulating layer 17 is 3 吣 or Si 〇 N. A portion of the insulating layer 17 is removed by an etching process having a patterned photoresist layer to expose the active surface 130. Conductive layer 172 is formed on insulating layer 17 and active surface 130 using PVD, CVD, electrolytic plating, electroless plating process 21 201243966 or other suitable metal deposition process. Conductive layer 172 can be one or more of A, Cu, Sn, N!, Au, Ag, or other suitable electrically conductive material. The conductive layer i72 operates as a contact pad which is in the vicinity of the insulating layer 17 and electrically connected to the circuit on the active surface 13A. In Figure 7b, an insulating or dielectric layer 176 is formed over the insulating layer i7 and the conductive layer 172 using spin coating, spray coating, printing, layer 0 PVD, CVD, sintering or thermal oxidation. The "specific" insulating layer 176 is applied as a blanket layer on the insulating layer 170 and on the conductive |! The insulating layer 176 comprises one or more SiO 2 , Si 3 N 4 , Si 〇 N, Ta 2 〇 5, Al 2 〇 3, BCB ρ ι, a dielectric film of a polymer substrate, an organic polymer film or other material having similar insulating and structural properties. . The insulating layer 176 is cured and the insulating layer 176 operates as a stress relaxation layer to reduce cracking, bending or other effects on the semiconductor die 124 during later formation of the combined interconnect structure. 172 damage. In particular, the insulating layer m has a property of high tensile strength at room temperature of 100 MPa, elongation at room temperature of 2 Torr to 15% by weight, and thickness of 2 to 30 μm. The semiconductor wafer 120 is singulated into individual semiconductor dies 124 via a mine track 126 using a cut-off and 7R, (e.g., a pellet, a jet of water, or a laser). Figure Temporary substrate or _18Q, which contains a sacrificial substrate, a polymer, an oxidized bond or other suitable low-cost rigid material :) Branch: Temple structure. An interface layer or double-sided tape 182 is formed on the carrier. The upper two is a temporary bonding film or a (four) stopping layer. The semiconductor grains m from _Mb are positioned and mounted on the interface layer 182 22 201243966 and the carrier 180 using a pick and place operation, and the action table * i3 指向 is directed to the carrier. The semiconductor die 124 mounted on the carrier _ constitutes a reconstituted wafer cassette 84. Figure 7d 'The encapsulant or molding compound 186 is deposited on the semiconductor die using paste printing, compression mode chlorine transfer molding, liquid encapsulation molding, vacuum lamination, spin coating or other suitable applicator. 124 and carrier 18 are on top. The package (d) 186 may be a polymeric composite such as an epoxy resin having a filler, a propylene acrylate having a filler, or a polymer having a suitable filler. The encapsulant 186 is non-conductive and protects the semiconductor device from elements and contaminants in the external environment. The carrier 180 and the interface layer 182 of FIG. 7e are removed by chemical etching, mechanical stripping, CMP, mechanical polishing, thermal baking, ultraviolet light, laser scanning, or erbium removal to expose the insulating layer i 76. The encapsulant 186 provides structural support for the semiconductor die 124 after the encapsulant 86 ^ removes the carrier 18 . A portion of the insulating layer 176 is removed by an etch process with a patterned photoresist layer to expose the conductive | The etching process also removes portions of the encapsulant 186 to a level below the surface of the insulating layer 丨76. Alternatively, a portion of the insulating layer 176 is removed using the LDA of the laser 188 to expose the conductive layer 172. After etching or LDA, insulating layer 176 remains superposed on conductive layer 172. In FIG. 7f, an insulating or passivation layer 19 is formed on the encapsulant 186, the insulating layer 176, and the conductive layer 172 using pVd, CVD, printing, spin coating, spray coating, screen printing, or lamination. The insulating layer 19 includes one or more layers of Si 2 , Μ #*, SiON, Ta 2 〇 5, 八 12 〇 3, a polymer dielectric film or other materials having similar insulating and structural properties. A portion of the insulating layer 9 is removed by an etching process having a patterned photoresist layer to expose the conductive layer 172. Alternatively, the insulating layer 1 90 of part 23 201243966 is removed by LDA to expose the conductive layer 172. Conductive layer 192 is patterned over insulating layer 190 and conductive layer 172 using PVD, CVD, sputtering, electrolytic keying, electroless bonding processes, or other suitable metal deposition processes. Conductive layer 192 can be one or more layers of A, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. A portion of the conductive layer 192 extends horizontally along the insulating layer 190 and is electrically interconnected parallel to the active surface 130 of the semiconductor die 124 to the conductive layer 172 in a lateral redistribution. Conductive layer 192 operates to fan out RDL for electrical signals of semiconductor die 124. A portion of the conductive layer 192 is electrically connected to the conductive layer 172. Other portions of conductive layer 192 are electrically or electrically isolated, depending on the connectivity of semiconductor wafer 124. In Figure 7g, an insulating or passivation layer 194 is formed over the insulating layer 19 and the conductive layer 192 using PVD, CVD, printing, spin coating, spray coating, screen printing or lamination. The insulating layer 194 may be one or more layers of si〇2, Si3N4, Si〇N,

TajO5, Ah〇3, polymer dielectric film or other materials with similar insulation and structural properties. A portion of the insulating layer 194 is removed by an etching process having a patterned photoresist layer to expose the conductive layer 192. Alternatively, a portion of the insulating layer 194 is removed by LD A to expose the conductive layer 192. The conductive bump material is deposited on the exposed conductive layer 192 using an evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. The bump material may be Al, Sn, Ni, Au, Ag, pb, Bi, Cu, solder, and combinations thereof, and a flux may be selected. For example, the bump material can be eutectic Sn/Pb, high lead solder or error free solder. The bump material is bonded to the conductive layer 192 using a suitable attachment or bonding process. In a specific aspect, the bump material is remelted by heating material 24 201243966 to its melting point to form solder balls or bumps 196. For some applications, the bumps 196 are re-dissolved twice to improve electrical contact to the conductive layer 92. The bump 1% can also be compression bonded to the conductive layer 192. Bumps 196 represent an interconnect structure that can be formed on conductive layer 192. The interconnect structure can also use pin bumps, microbumps, or other electrical interconnects. The combination of insulating layers 190 and 194, conductive layer 192, and bumps 196 constitutes a combined interconnect structure 1 98 formed on semiconductor die 124 and encapsulant 186. Additional insulating layers and RDL may be formed in the combined interconnect structure μ to interconnect to the semiconductor die 24 . The reconstituted wafer cassette 84 is singulated into individual Fo-WLCSPs 202 by the saw blade or laser cutting tool 200 via the encapsulant 186 and the combined interconnect structure 198. Figure 8 shows the F0_wlcsP 202 after singulation. The semiconductor dies 124, '' are electrically connected to the external device by a set of σ interconnect structures 198 (which include a conductive layer 192 and bumps 196). In one embodiment, an insulating layer 176 is formed over the semiconductor die 124 after singulation from the wafer 120. The properties of the insulating layer 176 (i.e., high tensile strength greater than 100 MPa at room temperature, high elongation between 20 and 150% at room temperature, and thickness 2 to 3 Å) provide stress relief. To reduce cracking, buckling, and other damage to the grains during formation of the composite interconnect structure 198 (which includes the insulating layers 19A and 194, the conductive layer 192). Figures 9a through 9g illustrate the process of forming a WLCSP having a plurality of insulating layers deposited on a semiconductor die for stress relaxation in conjunction with Figures 1 and 2a-2c. Following Figure 3a, an insulating or dielectric layer 2 1 is formed on the active surface 130 by spin coating, spraying, printing, lamination, PVD, CVD, sintering or thermal oxidation, as shown in Figure 9a. In one embodiment, the insulating layer is applied to the blanket layer on the active surface 130 of 201243966. The insulating layer 21 includes one or more layers of Si〇2, Si3N4, Si〇N, Ta2〇5, Ai2〇3, BCB, a dielectric film of a polymer substrate, an organic polymer film or the like having similar insulation. life,. Constructive material. The insulating layer 2 j 〇 is cured. The insulating layer 2 i is formed into a first stress relaxation layer to reduce cracks, bends, or other effects on the surface of the semiconductor die m: the damage of the conductive layer 212 during the later formation of the combined interconnect structure. In particular, the insulating layer 210 has properties of high tensile strength at room temperature of more than 100 MPa, high elongation at room temperature of 20 to 150%, and thickness of 2 to 3 Å. The conductive layer 212 is formed on the insulating layer 2iq using pVD, CVD, electrolytic ore, electroless ore plating, or other suitable metal deposition process. (d) Layer 212 may be one or more layers of A, Cu, Sn, Ni, Au, Ag or other suitable sigma conductive material. Conductive I 212 operates as a contact pad that is electrically connected to circuitry on active surface 130. In Figure 9b, an insulating or dielectric layer 216 is formed over the insulating layer 210 and the conductive layer 212 using spin coating, spray coating, printing, layer & VD C VD, sintering or thermal oxidation. In a specific aspect, the insulating layer 216 is applied as a blanket layer on the insulating layer 210 and the conductive layer 212. The insulating layer 2丨6 comprises -or more layers of Si〇2 Si3N4, SiON, Ta2〇5, Al2〇3' BCB, PI, PB0, dielectric substrate dielectric film, organic polymer film or other similar insulation And structural properties of the material. a Λ 4 insulating layer 216 is cured. The insulating layer 2 16 operates as a second stress relaxation layer to reduce cracking, ruthenium or other damage to the surface 13A and the conductive layer 212 of the semiconductor die 124 during the later formation of the combined interconnect structure. In particular, the insulating layer 216 has properties of high tensile strength from 26 201243966 to lone greater than 100 megapascals, high elongation between room temperature and -15% at room temperature, and thickness of 2 to 30 microns. The semiconductor wafer 120 is singulated into individual semiconductor dies 12 via saw streets 126 using a dicing tool 2 丨 8 (eg, a saw blade, a jet of water, or a laser). Figure 9c shows a temporary substrate or carrier 22 〇 that includes sacrificial A substrate material (such as tantalum, polymer, yttria or other suitable low cost rigid material) to support the structure. An interface layer or double-sided tape 222 is formed on the carrier 22 to serve as a temporary bonding film or etch stop layer. The semiconductor die 124 from Figures 9a-% is positioned and mounted on the interface layer 222 and carrier 220 using a pick and place operation with the active surface 13〇 directed toward the carrier. The semiconductor die 124 mounted on the carrier 220 constitutes a reconstituted wafer 224. In Figure 9d, the encapsulant or molding compound 226 is deposited on the semiconductor crystal using paste printing, compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, spin coating, or other suitable applicator. Granules 124 and on the carrier. The encapsulant 226 may be a polymeric composite such as an epoxy resin having a filler, an epoxy acrylate having a filler, or a polymer having a suitable filler. The encapsulant 226 is non-conductive and protects the semiconductor device from elements and contaminants of the external environment. In Figure 9e, the carrier 220 and the interface layer 222 are removed by chemical etching, mechanical stripping, CMP, mechanical polishing, thermal baking, ultraviolet light, laser scanning, or wet removal to expose the insulating layer 216 and the package. Seal 226. After the carrier 220 is removed, the encapsulant 226 provides structural support for the semiconductor die 124. A portion of the insulating layer 216 is removed by an etch process having a patterned photoresist layer to expose the conductive layer 212. The etching process also removes part of the encapsulant 27 201243966 2 2 6 to a level below the surface of the insulating layer 2 16 . Alternatively, a portion of the insulating layer 2 16 is removed using the LDA of the laser 228 to expose the conductive layer. 2 1 2 » After etching or LDA, the insulating layer 2 16 maintains the conductive layer 2 1 2 overlapping. In FIG. 9f, an insulating or passivation layer 230 is formed on the encapsulant 226, the insulating layer 216, and the conductive layer 212 using PVD, CVD, printing, spin coating, spray coating, screen printing, or lamination. The insulating layer 230 includes one or more layers of si〇2, Si3N4,

SiON, Ta2〇5, Ah〇3, polymer dielectric films or other materials with similar insulating and structural properties. A portion of the insulating layer 230 is removed by an etching process having a patterned photoresist layer to expose the conductive layer 212. Alternatively, a portion of the insulating layer 230 is removed by the LDA to expose the conductive layer 212. Conductive layer 232 is formed on insulating layer 230 and conductive layer 212 using a pvd, CVD 'mining, electrolytic electrowinning, electroless plating process, or other suitable metal deposition process to pattern. Conductive layer 232 can be one or more layers of Al, Cu, Sn, Ni, Au'Ag, or other suitable electrically conductive material. The conductive layer 2 3 2 of the blade extends horizontally along the insulating layer 230 and is electrically interconnected to the conductive layer 212 in a lateral redistribution parallel to the active surface 130 of the semiconductor die 124. Conductive layer 232 operates to fan out RDL for electrical signals of semiconductor die 124. A portion of the conductive layer 232 is electrically coupled to the conductive layer 212. The conductive layer 232 of the other P-die is electrically or electrically isolated, depending on the connectivity of the semiconductor wafer 124. In FIG. 9g, the insulating or passivation layer 234 is formed on the insulating layer 230 and the conductive layer 232 by using ρν〇, cvd, printing, spin coating, spray coating, screen printing or lamination. The insulating layer 234 may be one or more layers of Si. 〇 2, with the claw 'si〇N '

Ta2〇5, Al2〇3, polymer dielectric film or other material with similar insulation and structure 28 201243966. A portion of the insulating layer 234 is removed by an etch process with a patterned photoresist layer to expose the conductive layer 232. Alternatively, a portion of the insulating layer 234 is removed by [DA to expose the conductive layer 232. The conductive bump material is deposited on the exposed conductive layer 232 using an evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. The bump material may be Al, Sn, Ni, au, Ag, Pb, Bi, solder, and combinations thereof, and a lubricant may be used. For example, the bump material can be eutectic Sn/Pb, high lead solder, or no solder. The bump material is bonded to the conductive layer 232 using a suitable attachment or bonding process. In one embodiment, the bump material is remelted by heating the material to its melting point to form solder balls or bumps 236. For some applications, bumps 236 are remelted twice to improve electrical contact to conductive layer 232. Bumps 236 can also be compression bonded to conductive layer 232. Bumps 236 represent an interconnect structure that can be formed on conductive layer 232. The interconnect structure can also use pin bumps, microbumps, or other electrical interconnects. The combination of insulating layers 230 and 234, conductive layer 232, bumps 236 constitutes a combined interconnect structure 238 formed on semiconductor die 124 and encapsulant 226. Additional insulating layers and rd1 may be formed in combined interconnect structure 238. To interconnect to the semiconductor die 124. Reconstituted wafer 224 is singulated into individual Fo-WLCSPs 242 by saw blade or laser cutting tool 240 via encapsulant 226 and combined interconnect structure 238. Figure 10 shows the Fo-WLCSP 242 after singulation. Semiconductor die 124 is electrically coupled to an external device via a combined interconnect structure 238 that includes conductive layer 232 and bumps 236. In one embodiment, the insulating layers 210 and 216 are formed on the semiconductor die 124 prior to singulation from the wafer 120.绝29 201243966 The properties of the edge layer 21G~ 216 (that is, the high tensile strength at room temperature of 5 (10) MPa), the high elongation between 20 and 150 Å at room temperature, and the thickness = 3 〇 micron) Two layers of stress relaxation are provided to reduce cracking, buckling, and other damage to the grains during formation of the combined interconnect structure including insulating layers 230 and 234, conductive layer 232). The embodiment shown in Fig. 11 has two semiconductor dies on the sides and is disposed on the F 〇-w LCSP 25Mp - the semiconductor dies 124a are formed in the manner described in Figs. 3a to 3f. The other semiconductor die 124b is formed in the manner described in Figures 9a-9b. The two edge-biased semiconductor dies 124a, 124b are covered by an encapsulant 252, similar to Figures 4c and 9d. The combined interconnect structure 2 5 4 is formed on the semiconductor dies 124a and 124b, the insulating layers 136 and 216, and the encapsulant 252 in a manner similar to that of Figs. 4e to 4h and 9f to 9g. The composite interconnect structure 254 includes an insulating layer 256, a conductive layer 258, an insulating layer 260, and bumps 262. Figures 12a-121 relate to Figures 1 and 2a to 2c to demonstrate the process of forming a WLCSP having an insulating layer deposited on a semiconductor die and in a via formed in the die for stress relaxation. Following Fig. 3a, a plurality of channels or recesses 27 are formed in the track 126 of the semiconductor wafer 120 by using the LDA of the laser 272 and partially extend into the active surface 丨3〇, as shown in Fig. 2a. The width of the non-channel 270 is greater than the width of the sawway 126. In one embodiment, the channel 270 has a depth of 5 to 20 microns and extends along one or more saw streets 126 or completely surrounds the periphery of the semiconductor die 124. Figure 12b shows a plan view of a semiconductor wafer 120 with channels 270 formed to completely surround the periphery of the semiconductor die 124. In Figure 12c, an insulating or dielectric layer 274 is formed on the active surface ι3 使用 using spin coating, spray coating, printing, 30 201243966 lamination, PVD 'CVD, sintering or thermal oxidation. The insulating layer 274 includes one or more layers of Si〇2, si3N4, si〇N,

Ta205, Al2〇3, BCB, PI, PBO, polymeric substrate dielectric films, organic polymer films or other materials having similar insulating and structural properties. The - insulating layer 274 is Si #4 or SiON. A portion of the insulating layer 274 is removed by an etching process with a patterned photoresist layer to expose the active surface 130 °. The conductive layer 276 is formed using PVD, CVD, electrolytic ore, electroless ore processes, or other suitable metal deposition processes. The insulating layer 274 and the active surface 13 are on top. The conductive layer 276 may be one or more layers # a cu, sn,

Ni, Au, Ag or other suitable conductive material. Conductive layer 276 operates as a contact pad' which overlaps insulating layer 274 and is electrically coupled to circuitry on active surface 13A. Spin-on, spray, print, and layer are used in Figure 12d's insulating or dielectric layer 278. PVD, CVD, sintering or thermal oxidation is formed on the insulating layer and the conductive layer 276 and in the via 27". In one embodiment, the insulating layer 278 is applied as an insulating layer 274 and a blanket layer on the conductive layer m. The insulating layer 278 comprises one or more layers of _2, Si3N4, SiONO, Ta2 〇 5,

Al2〇3 BCB, PI, PB〇, a dielectric film of a polymer substrate, an organic polymer film or other material having similar insulating and structural properties. The insulating layer is cured. The insulating layer 278 operates as a stress relaxation layer to reduce cracking during the formation of the interconnect structure, or other damage to the surface 130 and the conductive layer 276 of the semiconductor die 278. In particular, the edge layer 278 has the properties of high tensile strength in the chamber, β 勹隹 to fox greater than 1 〇〇 MPa, high elongation in the chamber 31 201243966 between 20 and 150%, thickness 2 to 3 〇 micron The insulating layer 278 extends into the via 27 〇 to protect the sidewalls of the semiconductor die 124 adjacent to the active surface 13 3 by reducing cracking, f-warping or other damage during the later formation of the combined interconnect structure. The circle 120 is singulated into individual semiconductor dies (2) via a mine 126 using a cutting tool 279 (eg, a saw blade, a jet of water, or a laser). Figure 126 shows a temporary substrate or carrier 28 that contains a sacrificial base material ( For example, a crushed, polymer, oxidized wrinkle or other suitable low cost rigid material to support the structure. The interface layer or double-sided tape 282 is formed on the carrier 28〇 as a temporary bonding film or etch stop layer. ~ The 2d semiconductor sa 124 is positioned and mounted on the interface layer 282 and the carrier 28 using a pick and place operation, and the active surface 13 is directed to the carrier. The figure shows the semiconductor crystal #m mounted on the carrier 28 to reconstruct the exemplary portion. Or reconstituting the wafer 284. In Figure 12g, the encapsulant or molding compound 286 is printed using a paste 'compression molding, transfer molding' liquid encapsulation molding, vacuum lamination, spin coating or other suitable applicator It is deposited on the semiconductor die 124 and the carrier. The encapsulant 286 can be a polymeric composite such as a enamel tree with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler. The material 286 is non-conductive and protects the semiconductor device from elements and contaminants of the external environment. In Figure 12h, the carrier 280 and the interface layer 282 are chemically etched, mechanically stripped, CMP, mechanically ground, thermally baked, ultraviolet light. , laser scanning or fish removal to remove to expose the insulating layer 278 and the encapsulant 286. After the carrier 32 201243966 280 is removed, the 'encapsulant 286 provides for the bonding of the semiconductor die i24. Part of the insulation 278 is an etch process with a patterned photoresist layer removed to expose the conductive layer 276. The engraving process also removes portions of the encapsulant 286 to a level below the surface of the insulating layer 278. Alternatively, A portion of the insulating layer 278 is removed using a laser 288 6f; the LDA is removed to expose the conductive layer 276. After the etch or LDA, the insulating layer 278 is maintained overlying the conductive layer u6. For the circle 12i, the insulating or passivation layer 29 is pvd, cvd , printing, spin coating, spray coating, screen printing or lamination to form in the envelope, coffee, insulation,

On the conductive layer 276. The insulating layer 29〇 contains one or more layers called

SiON, Ta2〇5, Al2〇3, polymer dielectric films or other materials with similar insulating and structural properties. A portion of the insulating layer 29 is removed by an etching process having a patterned photoresist layer to expose the conductive layer 276. Alternatively, a portion of the insulating layer 290 is removed using the LDA of the laser 288 to expose the conductive layer 276. In circle 12j, conductive layer 292 is patterned over PVD, CVD, sputtering, electrolytic ore, electroless ore, or other suitable metal deposition process to form insulating layer 290 and conductive layer 276. Conductive layer 292 can be one or more layers #Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. A portion of the conductive layer 292 extends horizontally along the insulating layer 29 and parallels the active surface of the semiconductor die 124 to laterally redistribute the electrical interconnects 276. Conductive layer 292 operates as a fan for the presence of electrical signals for semiconductor particles 124. A portion of the conductive layer 292 is electrically connected to the conductive 曰 other. The conductive layer 292 is electrically or electrically isolated, depending on the connectivity of the semiconductor die 124. 33 201243966 In Figure I2k, an insulating or passivation layer 294 is formed on the insulating layer 29Q and the conductive layer state using pvD, cvd, printing, spin coating, spray coating, screen printing or lamination. The insulating layer 294 may be - or more layers of Si 〇 2, 乂 乂, 8 gamma, Ta 2 〇 5 Al 2 〇 3, polymer dielectric film or other materials having similar insulating and structural properties. An etch process with a patterned photoresist layer is removed to expose conductive layer 292. Alternatively, a portion of the insulating layer 294 is removed by the LDA to expose the conductive layer 292. The conductive bump material is deposited on the exposed conductive layer 292 using an evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. The bump material may be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, and a flux may be selected. For example, the bump material can be a eutectic Sn / Μ, high lead solder or lead-free solder bump material bonded to conductive layer 292 using a suitable attachment or bonding process. In one embodiment, the bump material is remelted by heating the material above its melting point to form solder balls or bumps. For some purposes, the bumps 296 are remelted twice to improve the electrical conductivity of the conductive layer 292. contact. The bumps 296 can also be compression bonded to the conductive layer 292. Bumps 296 represent an interconnect structure that can be formed on conductive layer 292. The interconnect structure can also use pin bumps, microbumps, or other electrical interconnects. The combination of insulating layers 290 and 294, conductive layer 292, and bumps 296 constitute a combined interconnect structure 298 formed over semiconductor die 124 and encapsulant 286. Additional insulating layers and RDL may be formed in the combined interconnect structure 298 to interconnect to the semiconductor die 124. Reconstituted wafer 284 is singulated into individual Fo-WLCSPs 302 by saw blade or laser cutting tool 300 via encapsulant 286 and combined interconnect structure 298. 34 201243966 Figure 13 shows the Fo-WLCSP 302 after simplification. Semiconductor die 1 24 is electrically coupled to an external device via a sigma interconnect structure 298 that includes conductive layer 292 and bumps 296. In one embodiment, an insulating layer 278 is formed over the semiconductor die 124 after singulation from the wafer 12. The properties of the insulating layer 278 (i.e., high tensile strength at room temperature greater than 100 MPa, high elongation between 20 and 150% at room temperature, thickness 2 to 3 Å micrometers) provide stress relief, To reduce cracking, warping, and other damage to the grains during formation of the composite interconnect structure 298, which includes the insulating layers 29A and 294, the conductive layer 292. In addition, insulating layer 278 extends into channel 270 to protect semiconductor die 124 adjacent sidewall edges of active surface 130 by reducing cracking, warping, or other damage during formation of composite interconnect structure 298. Figures 14a-14k are associated with Figures 1 and 2a-2c to illustrate another process for forming a WLCSP whose insulating layer is deposited on the grains and encapsulant and deposited in the channels formed in the grains. Following Figure 3a, conductive layer 310 is formed on active surface 130 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition process' as shown in Figure 14a. Conductive layer 310 can operate one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer 310 operates to electrically connect to the contact pads of the circuitry on active surface 13A. In this specific aspect, the conductive layer 31 has a high surface pear state, e.g., greater than 0.6 μm. A plurality of channels or recesses 312 are formed in the land 12 of the semiconductor wafer 12 and partially extend into the active surface 130 by using the LDA of the laser 314. The width of the channel 312 is greater than the width of the saw blade 126. In a particular aspect, channel 3 12 has a depth of 5 to 20 microns and extends along one or more saws 35 201243966 tracks 120 or completely surrounds the periphery of semiconductor die 124. Figure 14b shows a plan view of a semiconductor wafer 12A with channels 312 formed to completely surround the periphery of semiconductor die 146. The insulating or dielectric layer 3 16 is conformally applied to the active surface 130 and the conductive layer 312 using spin coating, spray coating, printing, lamination, PVD, CVD, sintering or thermal oxidation. The insulating layer 316 comprises one or more layers of 〇2, Sl3N4, SiON, Ta2〇5, Al2〇3, BCB, ρι, pB〇, a dielectric substrate dielectric film, an organic polymer film or the like having similar insulation. And structural properties of the material. The insulating layer 316 follows the undulating profile of the active surface 13A and the conductive layer 312. The insulating layer 316 has a high surface type to cover the conductive layer 31A. In FIG. 14d, the temporary planarization layer 318 is formed on the insulating layer 3i6 and the conductive layer 310 and formed in the via 312 by spin coating, spray coating, printing, lamination, PVD, CVD, firing, junction or thermal oxidation. In one embodiment, the planarization layer 318 is applied as a blanket over the entire semiconductor wafer 12 without patterning. The planarization layer 318 includes one or more layers of Si〇2, Si3N4, Si〇N, Τ&2〇5, Al2〇3, BCB, PI, PB〇, a dielectric substrate dielectric film, and an organic polymer film. Or other materials having similar insulating and structural properties. Temporary planarization layer 318 extends into channel 312. The semiconductor wafer 120 is singulated into individual semiconductor dies 124 via a mine track 126 using a cutting tool 3 19 (e.g., a saw blade, a jet of water, or a laser). Figure He shows a temporary substrate or carrier 32, which is a material, a polymer, an oxidized wrinkle or other suitable low material to support the structure. An interface layer or double-sided tape 322 is formed on the carrier as a temporary bonding film or etch stop layer. 36 201243966 from Figures (4) to (4) The semiconductor die 1 24 is positioned and mounted on the interface layer 322 and the carrier 320 by a rolling and placing operation using a pick-up and placing operation. The semiconductor die 124 mounted on the carrier 32G constitutes a reconstituted wafer 324. 14f & seal or molding compound 326 is deposited on the semiconductor die using paste printing, compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, spin coating or other suitable applicator The 124 #carrier 32 〇 upper encapsulation 16326 may be a polymeric composite material such as an epoxy resin having a filler, an epoxy acrylate having a filler, or a polymer having a suitable filler. Encapsulant 326 is non-conductive and protects the semiconductor device from elements and contaminants in the external environment. In FIG. 14g, the carrier 32 and the interface layer 322 are removed by chemical etching, mechanical stripping, CMP, mechanical polishing, thermal baking, ultraviolet light, laser scanning, or fish removal to expose the planarization layer 318. And encapsulant 326. After the carrier 320 is removed, the encapsulant 326 provides support for the semiconductor die 124. ° Figure 14h, the temporary planarization layer 318 is completely removed by a wet chemical removal process or an etching process with a patterned photoresist layer to expose the insulating layer 3 16 , the conductive layer 3 1 〇, the channel 3 ! 2 . A portion of the insulating layer 3 j 6 is removed by an etching process having a patterned photoresist layer to expose the conductive layer 3 . Further, the optional insulating portion 3丨6 of the germanium portion is removed using the LDA of the laser 328 to expose the conductive layer 3 10 . After the etch or LDA, the insulating layer 3 16 maintains the conductive layer 3 10 overlapping. In FIG. 14 , the insulating or passivation layer 330 is formed on the encapsulant 326 and the insulating layer 3 j 6 37 201243966 using PVD, CVD, printing, spin coating, screen printing or lamination, and formed on the channel 3 9 * , a ^ ^ hard road 312. Insulation layer 33〇 contains - or

Si02, Si3N4, Si〇N τη Ν, Ta205, Al2〇3, organic polymer or other materials with similar insulating and structural properties. The absolute (four) 330 is cured. The insulating layer 330 operates as a stress relaxation layer to reduce cracking, bay surface or other damage to the surface 13〇 and the conductive layer 3 1G of the semiconductor crystal during the formation of the combined interconnect structure. In particular, the insulating layer 33() has a property of a tensile strength of more than 100 Å at room temperature and a high elongation between 2 〇 and 15 〇% at room temperature. The ratio, the thickness on the semiconductor die 124 is 5 to 3 Å and the thickness on the encapsulant 326 is 2 to 35 microns. The insulating layer 33〇 extends into the channel 312 to protect the semiconductor die 124 adjacent to the sidewall edge of the active surface by reducing cracking, buckling or other damage during formation of the composite interconnect structure. A portion of the insulating layer 33 is removed by an etching process having a patterned photoresist layer to expose the conductive layer 3. Alternatively, a portion of the insulating layer 330 is removed using the LDA of the laser 328 to expose the conductive layer. 31〇. The conductive layer 332 is formed on the insulating layer 330 and the conductive layer 31 by using a PVD, CVD 'sputtering, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 332 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. A portion of the conductive layer 332 extends horizontally along the insulating layer 330 and is parallel to the active surface 半导体3 of the semiconductor die 124 to laterally redistribute electrical interconnections to the conductive layer 310. The conductive layer 332 operates to fan out rdl for electrically connecting the conductive layer 332 of the electrical signal portion of the semiconductor die 124 to the conductive layer 310. The other portions of conductive layer 332 are electrically or electrically isolated, depending on the connectivity of semiconductor die 124. 38 201243966 In FIG. 14k, an insulating or passivation layer 334 is formed on the insulating layer 33 and the conductive layer p using pVD, CVD, printing, spin coating, spray coating, screen printing or lamination. The insulating layer 334 may be one or more layers of si〇2, Si3N4, Si〇N,

Ta2〇5, ΑΙΑ3, polymer dielectric film or other materials with similar insulation and structural properties. A portion of the insulating layer 334 is removed by an etch process with a patterned photoresist layer to expose the conductive layer 332. Alternatively, a portion of the insulating layer 334 is removed by LDA to expose the conductive layer 332. The conductive bump material is deposited on the exposed conductive layer 332 using an evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. The bump material may be A, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, and a flux may be selected. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead free solder. The bump material is bonded to the conductive layer 332 using a suitable attachment or bonding process. The bump material is remelted by heating the material above its melting point to form solder balls or bumps 336. For some purposes, bumps 336 are reflowed twice to improve electrical contact to conductive layer 332. The bumps 336 can also be compression bonded to the conductive layer 332. Bumps 336 represent an interconnect structure that can be formed on conductive layer 332. The interconnect structure can also use pin bumps, microbumps, or other electrical interconnects. The combination of insulating layers 307 and 334, conductive layer 332, and bumps 336 constitute a combined interconnect structure 338 formed over semiconductor die 124 and encapsulant 326. Additional insulating layers and rdL may be formed in the combined interconnect structure 338 to interconnect to the semiconductor die 124. Reconstituted wafer 324 is singulated into individual Fo-WLCSPs 342 by saw blade or laser cutting tool 340 via encapsulant 326 and combined interconnect structure 338. 39 201243966 Figure 1 5 shows the Fo-WLCSP 342 after singulation. The semiconductor die I24 is electrically connected to the external device via the combined interconnect structure 3; 38 (which includes the conductive layer 332 and the bumps 336). The properties of the insulating layer 330 (i.e., high tensile strength greater than 1 MPa at room temperature, high elongation between 20 and 150% at room temperature, thickness 2 to 30 microns) provide stress relief To reduce cracking, warping, and other damage to the grains during formation of the combined interconnect structure 338, which includes the insulating layer 334 and the conductive layer 332. In addition, the insulating layer 33 extends into the vias 3 12 to protect the semiconductor die 124 adjacent to the sidewall edges of the active surface 130 by reducing cracking or other damage during formation of the interconnect interconnect structure 338. The insulating material 330 in the channel 312 also reduces bending during the formation of the combined interconnect structure 338. Figures 16a to 16d are associated with the figure! And 2a to 2C to demonstrate the process of forming WLCSp having an insulating layer deposited on the crystal grains and the encapsulant and deposited in the channels formed in the crystal grains and the envelope for stress relaxation. The encapsulant 326 continued from the portion 14h' of FIG. 14 is removed using the laser 346 to form a channel (4) adjacent to the encapsulation of the channel 312, as shown in FIG. Channel 348 extends along the - or more sides of semiconductor crystal 124 or completely surrounds the periphery of the die. In Fig. 16b, an insulating or passivation layer 35 is formed on the encapsulant and insulating layer 3 and formed in the via 31" using pvD', print coating, screen printing or lamination. The insulating layer 35 includes one or More layers 1

Si〇2, Si3N4, SiON, T. r\ 2 5, Al2〇3, organic polymers or other materials with similar insulating and structural properties. Insulation; I 350 is cured. The edge layer 35G operates as a stress relaxation layer to reduce cracking, miscellaneous or other damage to the surface i3〇 and the conductive layer 310 of the semiconductor die 124 during formation of the composite interconnect structure 40 201243966. In particular, the insulating layer 350 has a property of a high tensile strength of more than - million Pa at room temperature and a temperature of 2 at room temperature. The high elongation between ~= and the thickness on the encapsulant 326 is 2 to 3 μm. The insulating layer 350 extends into the channels 312 and 348 to protect the sidewalls of the semiconductor die 124 adjacent to the surface of the active surface φ 13G by reducing cracking, warping or other damage during formation of the composite interconnect structure. A portion of the insulating layer 35 is removed by an etching process having a patterned photoresist layer to expose the conductive layer 3ι. Alternatively, a portion of the insulating layer 35 is removed using a laser (10) # lda to expose the conductive layer 31. The conductive layer 352 of Fig. 16c' is patterned on the insulating layer 350 and the conductive layer 310 by patterning using pVD, cvd, sputtering, electrolytic plating, electroless plating, or other suitable metal deposition process. Conductive layer 352 can be one or more layers of A, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. A portion of the conductive layer 352 extends horizontally along the insulating layer 35 and is parallel to the active surface 13 of the semiconductor die 124 to be laterally redistributed to the conductive layer 310. Conductive layer 352 operates to fan out RDL for electrical signals of semiconductor die 124. A portion of the conductive layer 352 is electrically connected to the conductive layer 310. Other portions of conductive layer 352 are electrically or electrically isolated, depending on the connectivity of semiconductor die 124. The insulating or passivation layer 354 is formed on the insulating layer 35A and the conductive layer 352 using Pvd, CVD, printing, spin coating, spray coating, screen printing or lamination in Fig. 16d. The insulating layer 354 may be one or more layers of Si〇2, si3N4, Si〇N, Ta2〇5, ΑΙΑ3, a polymer dielectric film or other material having similar insulation and structural properties. A portion of the insulating layer 354 is removed by an etching process having a patterned photoresist layer to expose the conductive layer 352. Alternatively, a portion of the insulating layer 354 is removed by LDA to expose the conductive layer 352. The conductive bump material is deposited on the exposed conductive layer 352 using an evaporation, electrolytic plating 'electroless plating, ball drop or screen printing process. The bump material may be A, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, and combinations thereof, and a flux may be selected. For example, the bump material can be eutectic Sn / outer, high lead solder or lead free solder. The bump material is bonded to the conductive layer 352 using a suitable attachment or bonding process. In one embodiment, the bump material is remelted by heating the material to its melting point to form solder balls or bumps 356. For some uses, bumps 356 are reflowed twice to improve electrical contact to conductive layer 352. The bumps 356 can also be compression bonded to the conductive layer 352. Bumps 350 represent an interconnect structure that can be formed on conductive layer 352. The interconnect structure can also use pin bumps, microbumps, or other electrical interconnects. The combination of insulating layers 350 and 354, conductive layer 352, and bumps 356 constitutes a combined interconnect structure 358 formed on semiconductor die 124 and encapsulant 326. Additional insulating layers and RDL may be formed in the combined interconnect structure 3y to interconnect to the semiconductor die 124. Reconstituted wafer 324 is singulated into individual Fo-WLCSPs 362 by saw blade or laser cutting tool 360 via encapsulant 326 and combined interconnect structure 358. Figure 17 shows Fo-WLCSP 362 after singulation. Semiconductor die 124 is electrically coupled to an external device via a combined interconnect structure 358 that includes conductive layer 352 and bumps 356. The properties of the insulating layer 350 (i.e., high tensile strength at room temperature greater than 100 megapascals, high elongation 42 201243966 at room temperature between 20 and 150%, thickness 2 to 30 micro-seeking) provide stress relief In order to reduce the cracking, warping and other damage to the crystal grains during the formation of the combined interconnect fabric 35" including the insulating layer 354 and the conductive layer 352. Further, the 'insulating layer Μ extends into the channel 3 i 2 and 3 4 8 'protects the sidewalls of the semiconductor die 124 adjacent to the active surface = by forming a combined interconnect structure 35 or other damage. The insulating material 35g in the via 312 # 348 also forms the combined interconnect structure 358 Figures 18a to 18j are associated with Figures 1 and 2a to 2c to demonstrate the formation of a WLCSp& process having an insulating layer deposited on the die and encapsulant and deposited in a channel formed in the encapsulant For stress relaxation. Connected from the eye h, the conductive layer 370 is formed on the active surface 13 使用 using PVD, CVD, electrolytic plating, electroless plating process or other suitable metal deposition process as shown in the figure. The conductive layer 370 can be Is one or more layers of Mm

Au, Ag or other suitable conductive material. The conductive layer 37 is operated to electrically connect to the contact pads of the circuitry on the active surface 130. In Figure 18b, insulating or dielectric layer 372 is conformally applied to active surface 130 and conductive layer 370 using spin coating, spray coating, printing, lamination, PVD, CVD, sintering, or thermal oxidation. The insulating layer 372 includes one or more layers of si 〇 2

Sl3N4, SiON, Ta2〇5, Al2〇3, BCB, ρι, pB〇, a dielectric film of a polymer substrate, an organic polymer film or other material having similar insulating and structural properties. The insulating layer 372 follows the undulating profile of the active surface 13A and the conductive layer 37A. In Figure 18c, the temporary planarization layer 374 is formed on the insulating layer 3 72 and the conductive layer 201243966 electrical layer 370 using spin coating, spray coating, printing, lamination, P VD, C VD, sintering, or thermal oxidation. In one embodiment, the planarization layer 374 is applied as a blanket over the entire semiconductor wafer 120 without patterning. The planarization layer 374 comprises one or more layers of SiO 2 , Si 3 N 4 , SiON, Ta 205, Al 2 〇 3, BCB, PI, PBO 'polymer dielectric film, organic polymer film or other similar insulating and structural properties. material. The semiconductor wafer 120 is singulated into individual semiconductor dies 124 via saw streets 126 using a cutting tool 376 (e.g., saw blade, jet water column, or laser). Figure 18d shows a temporary substrate or carrier 38(R) comprising a sacrificial substrate material (e.g., tantalum, polymer, yttria or other suitable low cost rigid material) to support the structure. An interface layer or double-sided tape 382 is formed on the carrier 38〇 as a temporary bonding film or etch stop layer. The semiconductor die 124 from Figures i 8a - 8c is positioned and mounted on the interface layer 382 and carrier 380 using a pick and place operation with the active surface 13 指向 directed to the carrier. Semiconductor die mounted on carrier 380! 2 4 constitutes a reconstituted wafer 384. In Figure 18e, the encapsulant or molding compound 386 is deposited on the semiconductor die using paste printing, compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, spin coating, or other suitable applicator. 124 and carrier 38 are on top. The encapsulant 386 can be a polymeric composite material, such as an epoxy resin with a filler, an epoxy acrylate with a filler, or a polymer with a suitable filler. The encapsulant 386 is non-conductive and protects the semiconductor device from the external environment. Elements and contaminants. ^ ^ "Call/Baitiantian word etching, machine stripping, CMP, mechanical grinding, hot baking, UV light, laser scanning or radial removal to remove 'to expose the planarization layer 374 and package Seal 386. Encapsulation 386 provides structural support for semiconductor die 124 after removal of 201243966 • body 380. β In Fig. 18g, the temporary planarization layer 374 is completely removed by a wet chemical removal process or an etching process with a patterned photoresist layer to expose the insulating layer 372 and the conductive layer 37A. A portion of the encapsulant 386 is removed using a laser to form a channel 388 adjacent the encapsulation of the insulating layer 372. The channel 388 extends along one or more sides of the semiconductor die 124 or Completely surrounding the periphery of the die. Further, a portion of the insulating layer 372 is removed by an etching process having a patterned photoresist layer to expose the conductive layer 37. Alternatively, a portion of the insulating layer 372 may be laser 387. The LDA is removed to expose the conductive layer 37G. (d) or after the LDA 'the insulating layer 372 maintains the conductive layer 370 overlapping. Figure 18h 'Insulation or passivation layer 39〇 using Pvd, CVD, printing, spin coating, spraying, screen printing Or lamination is formed on the encapsulant 386, the insulating layer, the conductive layer 370, and formed in the channel 388. The insulating layer 39 includes one or more layers of Si 〇 2, Si 3 N 4 , SiON, Ta 2 〇 5, and Al 2 〇 3. An organic polymer or other material having similar insulating and structural properties. The insulating layer 39〇 = cured. The insulating layer 390 operates as a stress relieving layer to reduce cracking, warping or other during formation of the combined interconnect structure. The surface 130 and the surface of the semiconductor die 124 The damage of the electrical layer 372. In particular, the insulating layer 39 has a high tensile strength of more than 100 MPa at room temperature, a high elongation between 20 and 150% at room temperature, and a semiconductor die 124. The thickness is 2 to 30 microns and the thickness on the encapsulant 386 is 2 to 35 microns. The edge layer 390 extends into the channel 388' by reducing the cracking and bending of the period 45 201243966. Or other damage to protect the semiconductor die 124 adjacent to the sidewall edge of the active surface 130. A portion of the insulating layer 39 is removed by an etch process having a patterned photoresist layer to expose the conductive layer 37. Alternatively A portion of the insulating layer 390 is removed using the LDA of laser 387 to expose the conductive layer 370. Figure 18i 'The conductive layer 392 uses PVD, CVD, sputtering, electrolytic ore, electroless plating, or other suitable metal deposition process. A pattern is formed to form on the insulating layer 390 and the conductive layer 370. The conductive layer 392 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive material. Part of the conductive layer 392 Extending horizontally along the insulating layer 390 and The active surface 13 平行 parallel to the semiconductor die 1 24 is laterally redistributed electrically interconnected to the conductive layer 370. The conductive layer 392 operates to fan out rdL for the electrical signal of the semiconductor die 124. A portion of the conductive layer 392 The conductive layer 392 electrically connected to the conductive layer 3 70 is electrically or electrically isolated, depending on the connectivity of the semiconductor die 124. Figure 18j, the insulating or passivation layer 394 uses PVD, CVD, printing Formed on the insulating layer 39A and the conductive layer 392 by spin coating, spray coating, screen printing or lamination. The insulating layer 394 may be one or more layers of Si 〇 2, 8 丨 3 仏, Si 〇 N,

TajO5, gossip 2〇3, polymer dielectric film or other materials with similar insulation and structural properties. A portion of the insulating layer 394 is removed by an etch process with a patterned photoresist layer to expose the conductive layer 392. Alternatively, a portion of the insulating layer 394 is removed by LDA to expose the conductive layer 392. The conductive bump material is deposited on the exposed conductive layer 392 using an evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. The bump material may be 46 201243966 A1, Sn, Ni, AU, Ag, Pb, Bi, Cu, solder, and combinations thereof, and a flux may be selected. For example, the bump material can be eutectic Sri / Pb, high fault solder or no ship solder. The bump material is bonded to the conductive layer 392 using a suitable attachment or bonding process. In one embodiment, the bump material is remelted by heating the material above its melting point to form solder balls or bumps 396. The bump 396 is re-melted twice in some use to improve electrical contact to the conductive layer 392. The bumps 396 can also be compression bonded to the conductive layer 392. Bump 396 represents an interconnect structure that can be formed on conductive layer 392. The interconnect structure can also use pin bumps, microbumps, or other electrical interconnects. The combination of insulating layers 390 and 394, conductive layer 392, and bumps 396 constitutes a combined interconnect structure 3 98 formed over semiconductor die 124 and encapsulant 386. Additional insulating layers and rD1 may be formed in the combined interconnect structure 3 98 to interconnect to the semiconductor die 124. Reconstituted wafer 384 is singulated into individual Fo-WLCSPs 402 by saw blade or laser cutting tool 400 via encapsulant 386 and combined interconnect structure 398. Figure 19 shows f〇-WLCSP 402 after singulation. Semiconductor die 124 is electrically coupled to an external device via a combined interconnect structure 398 that includes conductive layer 392 and bumps 396. The properties of the insulating layer 390 (i.e., high tensile strength greater than 100 MPa at room temperature, high elongation between 20 and 150% at room temperature, thickness 2 to 30 microns) provide stress relief for The formation of the composite interconnect structure 398 (which includes the insulating layer 394 and the conductive layer 392) reduces cracking, warping, and other damage to the grains. In addition, the insulating layer 39 extends into the vias 386 to protect the semiconductor die 124 from adjacent the sidewalls 47 201243966 of the insulating layer 372 by reducing cracking or other damage during formation of the interconnect interconnect structure 398. The period of the insulating material 3 9 中 in the channel 3 8 8 reduces the bending. Also forming a combined interconnect structure 398

Although the present invention has been exemplified in detail, those skilled in the art will appreciate that modifications may be made to the male P or more specific aspects, without departing from the invention as set forth below. Fan Ming of the scope of patent application [Simple description of the diagram] Figure 1 shows the PCB, which has different types of equipment on the surface of the 奘 奘 ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; 代表性 代表性FIGS. 3a to 3f illustrate a semiconductor wafer having a plurality of semiconductor dies separated by a bead; FIGS. 4a to 4h exemplify a process of forming a WLCSP having a deposition on a semiconductor die Insulating layer for stress relaxation; FIG. 5 exemplifies Fo-WLCSP according to FIGS. 4a to 4h, which has an insulating layer deposited on a semiconductor die for stress relaxation; FIG. 6 exemplifies the Fo-WLCSP according to FIG. 3e, An insulating layer deposited on a semiconductor die for stress relaxation; FIGS. 7a-7g illustrate another process of forming a WLCSP having an insulating layer deposited on a semiconductor die for stress relaxation; FIG. 7a~7g of Fo -WLCSP having an insulating layer deposited on the semiconductor die for stress relaxation; Figures 9a to 9g demonstrate a process of forming a WLCSP having a plurality of deposited on the semi-conductive 48 201243966 bulk grains for stress relaxation Insulating layer; Figure 10 illustrates Fo-WLCSP according to Figures 9a to 9g having an insulating layer deposited on a semiconductor die for stress relaxation; Figure 11 illustrates a Fo-WLCSP having two semiconductor grains, each having An insulating layer deposited on a semiconductor die for stress relaxation; FIGS. 12a-121 illustrate a process of forming a WLCSP having insulation deposited on a semiconductor die and in a via formed in the die for stress relaxation Figure 13 illustrates a Fo-WLCSP according to Figures 12a-121 having an insulating layer deposited on a semiconductor die and in a via formed in the die for stress relaxation; Figures 14a-14k exemplify the formation of a WLCSP Another process having an insulating layer deposited on the aa particles and the encapsulant and in the channels formed in the grains; Figure 15 illustrates F0_WLCSP according to Figures 14a-14k, having deposited on the grains and encapsulant And Insulating layers in the channels formed in the grains; Figures 16a to 16d demonstrate the process of forming WLCSp with insulation deposited on the grains and encapsulant and in the channels formed by the grains and encapsulating sheets Figure 17 is not according to Figures 16a to 16d, which has a deposition on the semiconductor die and the encapsulant 1:2; 8/_0|^_ 匕 on the object and in the channel formed in the day grain Insulating layer; the process of forming WLCSp, which has an insulating layer deposited on the grain and encapsulation of the crystal 49 201243966 and in the channel formed by the encapsulation, and FIG. 19 is exemplified according to the figure i8a~18j• _wLCSP having an insulating layer deposited on the die and encapsulant and in the channels formed in the encapsulant. , [Main component symbol description] 50 52 54 56 58 Electronic device printed circuit board conductive signal wire bond wire package flip chip 60 62 64 66 68 70 ball grid array bump wafer carrier double row package junction grid array Wafer Module 72 74 76 78 80 Four-sided flat leadless package Four-sided flat package Semiconductor die contact pad Intermediate carrier wire bond wire 50 82 201243966 84 Encapsulant 88 Semiconductor die 90 Carrier 92 Underfill or epoxy adhesive Material 94 Bonding Line 96 Contact Pad 98 Contact Pad 100 Molding Compound or Encapsulant 102 Contact Pad 104 Bump 106 Intermediate Carrier 108 Active Area 110, 112 Bump 114 Signal Line 116 Molding Compound or Encapsulant 120 Semiconductor Wafer 122 substrate material 124, 124a, 124b semiconductor die or member 126 inactive inter-die wafer region or saw blade 128 back surface 130 surface conductive layer 134, 136 insulating or dielectric layer 138 cutting tool 201243966 140 temporary Substrate or carrier 142 interface layer or double sided tape 144 to reconstitute or reconstitute wafer 146 Encapsulant or Molding Compound 148 Laser 150 Insulation or Passivation Layer 152 Conductive Layer 154 Insulation or Passivation Layer 156 Solder Ball or Bump 158 Combined Interconnect Structure 160, 162 Fo-WLCSP 170 Insulation or Dielectric Layer 172 Conductive Layer 176 Insulation or Dielectric Layer 178 Cutting Tool 180 Temporary Substrate or Carrier 182 Interlayer or Double Sided Tape 184 Reconstituted Wafer 186 Encapsulant or Molding Compound 188 Laser 190 Insulation or Passivation Layer 192 Conductive Layer 194 Insulation or Passivation Layer 196 Solder Ball or Bump 52 201243966 198 Combined Interconnect Structure 200 Saw Blade or Laser Cutting Tool 202 Fo-WLCSP 210 Insulation or Dielectric Layer 212 Conductive Layer 216 Insulation or Dielectric Layer 218 Cutting Tool 220 Temporary Substrate or Carrier 222 Interface Layer or double-sided tape 224 Reconstituted wafer 226 Encapsulant or molding compound 228 Laser 230 Insulation or passivation layer 232 Conductive layer 234 Insulation or passivation layer 236 Solder ball or bump 238 Combined interconnect structure 240 Saw blade or thunder Shot cutting tool 242, 250 Fo-WLCSP 252 encapsulant 254 combined interconnect structure 256 insulating layer 258 conductive layer 260 insulating layer 53 20124 3966 262 Bump 270 Channel or Groove 272 Laser 274 Insulation or Dielectric Layer 276 Conductive Layer 278 Insulation or Dielectric Layer 279 Cutting Tool 280 Temporary Substrate or Carrier 282 Interlayer or Double Sided Tape 284 Reconstituted or Reconstituted Wafer 286 Encapsulant or molding compound 288 Laser 290 Insulation or passivation layer 292 Conductive layer 294 Insulation or passivation layer 296 Solder balls or bumps 298 Combined interconnect structure 300 Saw blade or laser cutting tool 302 Fo-WLCSP 310 Conductive layer 312 channel or groove 314 laser 316 insulating or dielectric layer 318 temporary planarization layer 54 201243966 319 cutting tool 320 temporary substrate or carrier 322 interface layer or double-sided tape 324 reconstituted wafer 326 encapsulant or molding compound 328 Laser 330 Insulation or Passivation Layer 332 Conductive Layer 334 Insulation or Passivation Layer 336 Solder Ball or Bump 338 Combined Interconnect Structure 340 Saw Blade or Laser Cutting Tool 342 Fo-WLCSP 346 Laser 348 Channel 350 Insulation or Passivation Layer 352 Conductive Layer 354 Insulation or Passivation Layer 356 Solder Ball or Bump 358 Combined Interconnect Structure 360 Saw Blade or Laser Cutting Tool 362 Fo-WLCSP 370 Conductive layer 372 Insulation or dielectric layer 55 201243966

374 Temporary planarization layer 376 Cutting tool 380 Temporary substrate or carrier 382 Interface layer or double-sided tape 384 Reconstituted wafer 386 Encapsulant or molding compound 387 Laser 388 Channel 390 Insulation or passivation layer 392 Conductive layer 394 Insulation or passivation Layer 396 Solder Ball or Bump 398 Combined Interconnect Structure 400 Saw Blade or Laser Cutting Tool 402 Fo-WLCSP 56

Claims (1)

201243966 VII. Patent application scope: 1. A method for fabricating a semiconductor device, comprising: providing a semiconductor die; forming a first conductive layer on a surface of the semiconductor die; depositing an encapsulant on the semiconductor die; forming a first insulating layer on the semiconductor die and the first conductive layer; and an interconnect structure on the semiconductor die and the encapsulant, wherein the interconnect structure is electrically connected to the first conductive layer, and the The first insulating layer provides stress relaxation during formation of the interconnect structure. 2. The method of claim 1, further comprising: forming a first channel in the semiconductor die; and forming a first insulating layer on the semiconductor die and the first conductive layer and In the first channel. 3. The method of claim 2, further comprising: forming a first channel in the encapsulant; and forming the first insulating layer on the semiconductor die and the first conductive layer and in the In the second channel. 4. The method of claim 1, further comprising: forming a channel in the semiconductor die; forming a second insulating layer on the δ-he semiconductor crystal before depositing the encapsulant and forming the first insulating layer Forming a second insulating layer on the second insulating layer and in the channel; depositing the encapsulant on the semiconductor die; 57 201243966 removing the second insulating layer to expose The second insulating layer; and the first insulating layer is formed on the semiconductor die and the first conductive layer and in the channel. 5. The method of claim 1, further comprising: forming a second insulating layer on the semiconductor die and the first conductive layer before depositing the encapsulant and forming the first insulating layer; a third insulating layer on the second insulating layer; depositing the encapsulant on the semiconductor die; forming a channel in the encapsulant; removing the third insulating layer to expose the second insulating layer; and forming the A first insulating layer is on the semiconductor die and the first conductive layer and in the via. 6. The method of claim </ RTI> wherein the first insulating layer has a tensile strength at room temperature of greater than 100 MPa, an elongation at room temperature of between 20 and 150%, and 2 to 3 Å. The characteristics of the thickness. 7. The method of claim i wherein the forming the interconnect structure comprises: forming a second conductive layer on the first insulating layer; and forming a first insulating layer on the first insulating layer and the second conductive sound on. 8. A semiconductor device comprising: a semiconductor die; a first conductive layer formed on a surface of the semiconductor die; an encapsulant deposited on the semiconductor die; a first insulating layer formed On the semiconductor die and the first conductive layer 58 201243966; and an interconnect structure formed on the semiconductor die and the encapsulant, the interconnect structure being electrically connected to the first conductive layer, and The first insulating layer provides stress relaxation during formation of the interconnect structure. 9. The semiconductor device of claim 8, further comprising a first via formed in the semiconductor die, wherein the first insulating layer is formed on the semiconductor die and the first conductive layer and In the first channel. 10. The semiconductor device of claim 9, further comprising a second channel in the envelope, wherein the first insulating layer is formed on the semiconductor die and the first conductive layer and In the second channel. 11. The semiconductor device of claim 9, further comprising a channel in the encapsulant, wherein the first insulating layer is formed on the semiconductor die and the first conductive layer and in the via. 12. The semiconductor device of claim 8, wherein the first insulating layer has a tensile strength at room temperature of greater than 1 MPa, an elongation at room temperature of between 20 and 150%, and 2~ 3 〇 micron thickness characteristics. Eight, the pattern: (such as the next page) 59