201239203 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉友一種風扇控制系統及方法。 【先前技術】 [0002] 在通訊及電腦領域中，隨著技術的發展，設備的功耗愈 來愈高，因此，對散熱系統的散熱性能及其可靠性提出 了更高的要求。目前’該領域主要的散熱方法主要是利 用散熱風扇進行主動式風冷散熱。其中散熱風扇都是使 用基板管理控制器（Baseboard Management Control， BMC)的脈衝調製訊號（Pulse Width Modulation, PWM)對其進行控制。在滿足系統散熱要求的情況下，使 用BMC的PWM訊號控制散熱風扇可以達到降低系統的功耗 和噪音的目的。然，若BMC在控制風扇時突然停止工作， 此時風扇就會以BMC停止工作前的速度運轉，其轉速將不 再隨系統溫度的改變而變化，如此將可能降低系统的散 熱性能。 — 【發明内容】 [0003] 鑒於以上情況’本發明提供了 一種在BMC停止工作的情況 下仍能保證系統的散熱性能的風扇控制系統及方法。 [0004] 一種風扇控制系統，包括一基本輸入輸出系統（Bi〇s)、 一基板管理控制器（BMC)、一脈衝發生器及—訊號選擇器 ，該BIOS識別該BMC標钱位元的變化並根據該標諸位元 的變化輸出不同的訊號給該訊號選擇器，該訊號選擇器 根據該BIOS的輸出訊號來選擇該BMC所輸出的pwM訊號或 者該脈衝發生器所輸出的PWM訊號傳遞給風扇。 1002020291-0 100112157 表單編號A0101 第3頁/共12頁 201239203 [0005] 一種風扇控制方法，該方法包括步驟： [0006] [0007] [0008] [0009] [0010] [0011] [0012] [0013] [0014] 該脈衝發生器產生PWM訊號使風扇全速轉動； 該B M C定時設置其標諸位元的值； 該BIOS定時讀取並存儲該BMC内部標誌位元的值； 比較該B10S内存儲空間的值是否一致； 若該存儲空間的值不一致，該訊號選擇器選擇該BMC的 PWM訊號傳遞給風扇，即使得該BMC的PWM訊號控制該風 扇轉動，之後執行步驟“該BIOS定時讀取並存儲該BMC内 部標誌位元的值”； 若該存儲空間的值一致，該訊號選擇器選擇該脈衝發生 器的PWM訊號傳遞給風扇，即使得該脈衝發生器的PWM訊 號控制該外部風扇轉動，之後執行步驟“該BIOS定時讀 取並存儲該BMC内部標誌位元的值”。 相較於習知技術，該風扇控制系統及方法透過判斷該BMC 標誌位元的變化來選擇不同的PWM訊號，就可以在該BMC 停止工作後克服系統的散熱性及運行不穩定的不足。 【實施方式】 請參閱圖1，本發明風扇控制系統用於控制一風扇20，該 風扇控制系統的較佳實施方式包括一基本輸入輸出系統 (BIOS)IO、一基板管理控制器（BMC)12、一脈衝發生器 14及一訊號選擇器16。 該BMC 12在其配置資料存儲區内設有一標誌位元。該 BMC 12定時設置其標誌位元的值，例如以一秒為週期來 100112157 表單編號A0101 第4頁/共12頁 1002020291-0 201239203 [0015]201239203 VI. Description of the Invention: [Technical Field of the Invention] [0001] The present invention relates to a fan control system and method. [Prior Art] [0002] In the field of communication and computer, with the development of technology, the power consumption of the device is getting higher and higher. Therefore, higher requirements are placed on the heat dissipation performance and reliability of the heat dissipation system. At present, the main heat dissipation method in this field is mainly to use the cooling fan for active air cooling. The cooling fan is controlled by the Pulse Width Modulation (PWM) of the Baseboard Management Control (BMC). Using the BMC's PWM signal to control the cooling fan can reduce the power consumption and noise of the system when the system's thermal requirements are met. However, if the BMC suddenly stops working while controlling the fan, the fan will run at the speed before the BMC stops working, and its speed will no longer change with the system temperature change, which may reduce the system's heat dissipation performance. - SUMMARY OF THE INVENTION [0003] In view of the above, the present invention provides a fan control system and method that can ensure the heat dissipation performance of the system even when the BMC is stopped. [0004] A fan control system includes a basic input/output system (Bi〇s), a substrate management controller (BMC), a pulse generator, and a signal selector, and the BIOS identifies changes in the BMC standard bit position. And outputting different signals to the signal selector according to the change of the target bit. The signal selector selects the pwM signal output by the BMC or the PWM signal output by the pulse generator to be transmitted to the fan according to the output signal of the BIOS. . 1002020291-0 100112157 Form No. A0101 Page 3 of 12 201239203 [0005] A fan control method, the method comprising the steps: [0006] [0009] [0010] [0012] [0014] The pulse generator generates a PWM signal to cause the fan to rotate at full speed; the BMC timing sets the value of the marked bit; the BIOS periodically reads and stores the value of the BMC internal flag bit; compares the storage space in the B10S If the value of the storage space is inconsistent, the signal selector selects the PWM signal of the BMC to be transmitted to the fan, that is, the PWM signal of the BMC controls the fan to rotate, and then performs the step “The BIOS periodically reads and stores. The value of the internal flag of the BMC is ""; if the value of the storage space is consistent, the signal selector selects the PWM signal of the pulse generator to be transmitted to the fan, so that the PWM signal of the pulse generator controls the external fan to rotate, after which The step "This BIOS periodically reads and stores the value of the BMC internal flag bit" is executed. Compared with the prior art, the fan control system and method can select different PWM signals by judging the change of the BMC flag bit, thereby overcoming the system's heat dissipation and unstable operation after the BMC stops working. Embodiment 1 Referring to FIG. 1 , a fan control system of the present invention is used to control a fan 20 . The preferred embodiment of the fan control system includes a basic input/output system (BIOS) 10 and a baseboard management controller (BMC) 12 . A pulse generator 14 and a signal selector 16. The BMC 12 is provided with a flag bit in its configuration data storage area. The BMC 12 periodically sets the value of its flag bit, for example, in a one second period. 100112157 Form number A0101 Page 4 / Total 12 pages 1002020291-0 201239203 [0015]
[0016] ❹ 定時設置其標誌位元的值。若該BMC 12正常工作，則在 第一個週期内該BMC 12將其標誌位元的值設置為“0” ， 在第二個週期内將其標誌位元的值設置為“Γ ，在第三 個週期内將其標誌位元的值設置為“0” ，在第四個週 期内將其標誌位元的值設置為“Γ ，如此交替設置，使 其標誌位元的值為“0” 、“Γ交替出現；若該BMC 12 停止工作，其標誌位元的值將不再發生變化。 該BIOS 10識別該BMC 12標誌位元的變化並根據該標誌 位元的變化輸出不同的訊號給該訊號選擇器16，該訊號 選擇器16根據該BIOS 10的輸出訊號來選擇將該BMC 12 所輸出的PWM訊號或者該脈衝發生器14所輸出的PWM訊號 傳遞給風扇2 0。 該BIOS 10以與該BMC 12設置該標誌位元值相同的週期 來定時讀取並存儲該BMC 12内標誌位元的值，並將前後 兩個相鄰週期内所讀取的標誌位元的值進行比較。若兩 個相鄰週期内所讀取的標誌位元的值一致，該BIOS 10產 生一高電平訊號；否則，產生一低電平訊號。本實施方 式中，該BIOS 10僅存儲前後兩個相鄰週期内所讀取的標 誌位元的值，即，當該BIOS 10比較完成兩個相鄰週期内 所讀取的標誌位元的值之後即刪除前一週期内所讀取的 標誌位元的值，之後才存儲下一週期内所讀取的標誌位 元的值。 [㈤ 17] 該脈衝發送器14產生的PWM訊號為連續的高電平訊號（即 該脈衝發生器14產生工作週期為1的PWM訊號）。 100112157 表單編號A0101 第5頁/共12頁 1002020291-0 201239203 _]本實施方式中，該訊號選擇器16可為—多路類比開關 (MUX)。該訊號選擇器16透過讀取該M〇s ι〇產生的電平 訊號來確定導通該BMC 12與風扇2G或該脈衝發生器㈣ 風扇2〇，以將該BMC 12所輸出的PWM訊號或該脈衝發生、 器14所輸出的pwm訊號傳遞給該風扇2〇。 [_若該BMC 12處於正常工作狀態，其將會以—定的週期設 置其内部資料存儲區内標誌位元的值，即該Bl〇s在兩 個相鄰週期内所讀取的B M C 12内部資料存儲區内標誌位 元的值將會變化，此時，該BIOS 10則產生低電平的電平 訊號，該訊號選擇器16則將該BMC 1〇所輸出的pwM訊號 傳遞給该風扇2 0 ;若該B M C 12處於非工作狀雖，其將不 改變内部標誌位元的值，此時，該BI〇s丨〇將產生高電平 的電平訊號，該訊號選擇器16則將該脈衝發生器14所輸 出的PWMsfl说傳遞給该風扇20。由於該脈衝發生写Μ所_ 出的PWM訊號為連續的高電平訊號，因此，該風扇2〇將會 —直以其最高速度工作。如此即可保證當該BMC處於非工 作狀態時，該風扇20任能滿足系統的散熱需求。 [0020] 請參閱圖2 ’本發明風扇控制方法較佳實施例包括以下步 驟： [0021] 步驟S1，該脈衝發生器14產生PWM訊號使風扇2〇全速轉 動。系統開機後’ s玄脈衝發生器14產生連續高電平的ρψΜ 訊號，如此使得該風扇2 0以其最高速度工作。 [0022] 步驟S2，該BMC 12定時設置其標該位元的值，例如以一 秒為週期來定時設置其標該位元的值。若該BMC 12正常 100112157 表單編號A0101 第6頁/共12頁 1002020291-0 201239203 工作，則在第一個週期内該BMC 12將其標誌位元的值設 置為’在第二個週期内將其標誌位元的值設置為“ 1” ’在第三個週期内將其標誌位元的值設置為“0” ， 在第四個週期内將其標誌位元的值設置為“Γ ，如此交 替設置’使其標誌位元的值為“〇” 、“丨，，交替出現； 若該BMC 12停止工作，其標誌位元的值將不再發生變化 〇 [0023] Ο 步驟S3’該BIOS 1〇定時讀取並存儲該BMC 12内部標誌 位元的值°本實施方式中，該BIOS 10以與該BMC 12設 置其標諸位元值的週期來定時讀取該BMC 12内標誌位元 的值且該BIOS 1〇僅存儲前後兩個相鄰週期内所讀取的 標钱位兀的值，即，當該BIOS 10比較完成兩個相鄰週期 内所靖取的標喊位元的值之後即刪除前一週期内所讀取 的標〜位元的值’之後才存儲下-週期内所讀取的標該 位元的值。 [0024] G . 步驟S4 ’比較該BI〇s 1〇内存儲空間的值是否一致；該 存儲空^於存儲該狐12内部資料存儲區内標諸位元 的值’當該存儲區内的標钱位元的值-致時，該BIOS 10 產生一高電平訊號給該訊號選擇器16，並進入步驟s6 ; 當該存儲區内的㈣位元的值不—致時，該BIGS 10產生 〆低電平訊號給該訊號選擇器16，並進入步驟Μ。 步驟S5’該訊號選擇器16選擇該BMC 12的削訊號傳遞 給風扇20，即使得賴e 12的酬訊馳制風扇2〇轉 動，之後執行步驟S3。 100112157 表單編號Α〇ι〇ι 第7頁/共12頁 1002020291-0 [0025] 201239203 [0026] 步驟S6，該訊號選擇器16選擇該脈衝發生器14的PWM訊 號傳遞給風扇20，即使得該脈衝發生器14的PWM訊號控 制該外部風扇20轉動，之後執行步驟S3。 [0027] 綜上所述，本發明確已符合發明專利的要件，爰依法提 出專利申請。惟，以上該者僅為本發明的較佳實施方式 ，本發明的範圍並不以上述實施方式為限，舉凡熟悉本 案技藝的人士援依本發明的精神所作的等效修飾或變化 ，皆應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 [0028] 圖1為本發明風扇控制、統與風扇的方框圖。 [0029] 圖2為本發明風扇控制方法較佳實施例的流程圖。 【主要元件符號說明】 [0030] BIOS: 10 [0031] BMC: 12 [0032] 脉衝發生器：14 [0033] 訊號選擇器：16 [0034] 風扇：20 1002020291-0 100112157 表單編號A0101 第8頁/共12頁[0016] 定时 Set the value of its flag bit periodically. If the BMC 12 is working normally, the BMC 12 sets the value of its flag bit to "0" in the first cycle, and sets the value of its flag bit to "Γ" in the second cycle. Set the value of its flag bit to "0" in three cycles, and set the value of its flag bit to "Γ in the fourth cycle, so alternately set its flag bit value to "0". "Γ alternately appears; if the BMC 12 stops working, the value of the flag bit will not change. The BIOS 10 identifies the change of the BMC 12 flag bit and outputs a different signal according to the change of the flag bit. The signal selector 16 selects, according to the output signal of the BIOS 10, the PWM signal output by the BMC 12 or the PWM signal output by the pulse generator 14 to the fan 20. The BIOS 10 A period of the same flag bit value is set as the BMC 12 to periodically read and store the value of the flag bit in the BMC 12, and compare the values of the flag bits read in the two adjacent periods. If the flag bit is read in two adjacent cycles Consistently, the BIOS 10 generates a high level signal; otherwise, generates a low level signal. In this embodiment, the BIOS 10 only stores the value of the flag bit read in two adjacent periods before and after, ie, When the BIOS 10 compares the value of the flag bit read in two adjacent periods, the value of the flag bit read in the previous period is deleted, and then the flag read in the next period is stored. The value of the bit. [(5) 17] The PWM signal generated by the pulse transmitter 14 is a continuous high level signal (ie, the pulse generator 14 generates a PWM signal with a duty cycle of 1.) 100112157 Form No. A0101 Page 5 / A total of 12 pages 1002020291-0 201239203 _] In this embodiment, the signal selector 16 can be a multi-channel analog switch (MUX). The signal selector 16 reads the level signal generated by the M〇s ι〇 Determining to turn on the BMC 12 and the fan 2G or the pulse generator (4) fan 2〇 to transmit the PWM signal output by the BMC 12 or the pwm signal output by the pulse generator 14 to the fan 2〇. The BMC 12 is in normal working condition and it will be set to The period sets the value of the flag bit in the internal data storage area, that is, the value of the flag bit in the internal data storage area of the BMC 12 read by the B1 〇s in two adjacent periods will change. The BIOS 10 generates a low level signal, and the signal selector 16 transmits the pwM signal outputted by the BMC 1 to the fan 2 0; if the BMC 12 is in a non-operational state, it will not change the internal The value of the flag bit, at this time, the BI〇s丨〇 will generate a high level signal, and the signal selector 16 transmits the PWMsfl output from the pulse generator 14 to the fan 20. Since the PWM signal generated by the pulse is a continuous high level signal, the fan 2 will operate at its maximum speed. This ensures that the fan 20 can meet the cooling requirements of the system when the BMC is in a non-working state. Referring to FIG. 2, a preferred embodiment of the fan control method of the present invention includes the following steps: [0021] In step S1, the pulse generator 14 generates a PWM signal to cause the fan 2 to rotate at full speed. After the system is turned on, the s 脉冲 pulse generator 14 generates a continuous high level ρ 讯 signal, so that the fan 20 operates at its highest speed. [0022] Step S2, the BMC 12 periodically sets the value of the bit, for example, periodically sets the value of the bit in a cycle of one second. If the BMC 12 is normal 100112157 Form No. A0101 Page 6 / Total 12 Page 1002020291-0 201239203, the BMC 12 sets the value of its flag bit to 'in the second cycle' during the first cycle. The value of the flag bit is set to "1" 'The value of its flag bit is set to "0" in the third cycle, and the value of its flag bit is set to "Γ, so alternate in the fourth cycle. Set 'The value of its flag bit is "〇", "丨," alternately; if the BMC 12 stops working, the value of its flag bit will not change again [0023] Ο Step S3' The BIOS 1 〇 Reading and storing the value of the BMC 12 internal flag bit periodically. In this embodiment, the BIOS 10 periodically reads the value of the flag bit in the BMC 12 with a period in which the BMC 12 sets its target bit value. And the BIOS 1 〇 only stores the value of the standard money bit 读取 read in two adjacent periods, that is, after the BIOS 10 compares the values of the spoofed bits in the two adjacent periods. That is, the value of the target-bit read in the previous week is deleted, and then the next-cycle is stored. The bit value of the read standard. [0024] G. Step S4 'Compare whether the value of the storage space in the BI〇s 1〇 is consistent; the storage space is used to store the value of the marked bit in the internal data storage area of the Fox 12' when the standard in the storage area The value of the money bit is such that the BIOS 10 generates a high level signal to the signal selector 16 and proceeds to step s6; when the value of the (four) bit in the storage area is not true, the BIGS 10 is generated. The low level signal is given to the signal selector 16, and the process proceeds to step Μ. In step S5', the signal selector 16 selects the clipping number of the BMC 12 to be transmitted to the fan 20, that is, the reciprocating fan 2 of the Lai 12 is rotated, and then step S3 is performed. 100112157 Form No. Α〇ι〇ι Page 7 / Total 12 Page 1002020291-0 [0025] 201239203 [0026] Step S6, the signal selector 16 selects the PWM signal of the pulse generator 14 to be transmitted to the fan 20, that is, The PWM signal of the pulse generator 14 controls the rotation of the external fan 20, and then step S3 is performed. [0027] In summary, the present invention has indeed met the requirements of the invention patent, and the patent application is filed according to law. However, the above is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiments, and those skilled in the art will be able to make equivalent modifications or changes in accordance with the spirit of the present invention. It is covered by the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS [0028] FIG. 1 is a block diagram of a fan control, system and fan of the present invention. 2 is a flow chart of a preferred embodiment of a fan control method of the present invention. [Main component symbol description] [0030] BIOS: 10 [0031] BMC: 12 [0032] Pulse generator: 14 [0033] Signal selector: 16 [0034] Fan: 20 1002020291-0 100112157 Form number A0101 8 Page / Total 12 pages