TW201236140A - Semiconductor structure and manufacturing method of the same - Google Patents

Abstract

A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, a second stacked structure, a dielectric element, and a conductive line. The first stacked structure and the second stacked structure are disposed on the substrate. Each of the first stacked structure and the second stacked structure includes conductive strips and insulating strips stacked alternately. The conductive strips are separated from each other by the insulating strips. The dielectric element is disposed on the first stacked structure and the second stacked structure and includes a second dielectric portion. The first stacked structure and the second stacked structure are separated from each other by only the second dielectric portion. The conductive line is disposed on the stack sidewalls of the first stacked structure and the second stacked structure far from the second dielectric portion. The dielectric element is between the conductive line and the first stacked structure and is between the conductive line and the second stacked structure.

Description

201236140

TW7164PA VI. Description of the Invention: </ RTI> The present invention relates to a semiconductor structure and a method of manufacturing the same, and more particularly to a memory device and a method of fabricating the same. [Prior Art] Memory devices are used in many products, such as MP3 players, digital cameras, computer files, and the like. As applications increase, so does the demand for memory devices toward smaller sizes and larger memory capacities. In response to this demand, it is required to manufacture a memory device having a high component density. Designers have developed a way to increase the density of memory devices by using a three-dimensional stacked memory device to achieve higher memory capacity while reducing the cost per bit. However, at present, the memory unit size limit of such a memory device is still greater than 50 nm, and it is difficult to make a major breakthrough. SUMMARY OF THE INVENTION The present invention is directed to a semiconductor structure and a method of fabricating the same. The semiconductor structure has a very small miniature size. A semiconductor structure is provided. The semiconductor structure includes a substrate, a first stacked structure, a second stacked structure, dielectric elements, and conductive lines. The first stack structure and the second stack structure are disposed on the substrate. Each of the first stack structure and the second stack structure includes staggered stacked conductive stripes and insulating stripes. The conductive stripes are separated by insulating stripes. The dielectric element is disposed on the first stacked structure and the second stacked structure and includes a second dielectric portion. The first stacked structure and the second stacked structure are separated from each other only by the second dielectric portion. Conductive wire 201236140

, 1W / 104PA = = a stack structure and the second stack structure away from the second dielectric stack: on the sidewall. The dielectric component is interposed between the conductive line and the first stack and between the conductive line and the second stacked structure. = manufacturing method of two semiconductor structures. The method includes the steps of forming a first stacked structure and a second stacked structure on a substrate. Each of the 'th structure and the second stacked structure includes staggered stacked stripes and insulation. The conductive strips (4) are separated by a domain edge stripe. Form the interface. The dielectric component includes a second dielectric portion. The first stack structure and the second stack structure are separated from each other only by the second dielectric portion. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments will be described in detail with reference to the accompanying drawings. [Embodiment] Fig. 1 (d) is a perspective view of a semiconductor structure of an embodiment. Fig. 2 is a cross-sectional view of the semiconductor structure of Fig. 1 taken along a meander line. In the embodiment, the "semiconductor structure is a three-dimensional vertical interlayer memory device, that is, a gate memory device", for example, includes a nand type flash memory or an anti-fuse memory. ~ Please refer to the 1st, the semiconductor structure includes the substrate 2. The f-stack structure 4, the second stack structure 6, the third stack structure 8, and the fourth stack structure 10 are disposed on the substrate 2. Each of the first stacked structure 4, the second stacked structure 6, the f-three stacked structure 8 and the fourth stacked structure 1A includes staggered stacked conductive stripes 12 and insulating stripes 14. The conductive stripes 12 are separated from each other by the insulating stripes 14. The insulating stripes 14 may include an oxide such as ruthenium oxide. The conductive strips 12 may comprise a metal or semiconductor material such as p_type polycrystal 201236140

TW7164PA 矽. In one embodiment, the different levels of conductive stripes 12 are respectively used as bit lines (BL) of different memory planes. A first gap 16 is formed between the first stacked structure 4 and the second stacked structure 6. An ith gap 18 is formed between the second stack structure 6 and the third stack structure 8. A third gap 20 is formed between the third stack structure 8 and the fourth stack structure 1A. The first stack structure 4 includes opposing first stack sidewalls 22 and second stack sidewalls 24. The second stack structure 6 includes opposing third stack sidewalls 26 and fourth stack sidewalls 28. The third stack structure 8 includes: a pair of fifth stack sidewalls 30 and a sixth stack sidewall 32. The fourth stack 10 includes a seventh stacking sidewall 34 and an eighth stacking side, and a stacking sidewall 22 and a fourth stacking sidewall 28 are away from the first stacking sidewall 24 and the third stack _26 are adjacent to the first stack Gap: 1 : Stack (4) 28贞 The fifth stack sidewall 3 is adjacent to the nth third stack sidewall 26 and the sixth stack sidewall 32 away from the second _! The six sidewalls 32 and the seventh stack sidewall 34 are adjacent to the third gap 2〇. The first side wall 30 and the eighth stack side wall 36 are away from the third gap. 4, ^ 1 ^ ' dielectric member 38 can be (d) in the first - stack structure, the mouth structure 8 and the fourth stack structure 1 〇丨 electrical components 38 include, for example, the first dielectric portion 40, The second dielectric portion 42, the third dielectric portion 44, the fourth portion 48, the Yasaka Hachiman*, the '丨电邛46, the fifth dielectric knife 48, the sixth dielectric portion 5〇, the seventh Points 54. The ^人^, 丨 邛 邛 52 and the eighth dielectric portion are disposed on the first stack sidewall 22 . The first &quot;electrical portion 42 is disposed in the first gap rA ^ ^ ^ ^. The third dielectric portion 44 is disposed on the fourth stack sidewall 28 . The fifth stack is on the side wall 30. The fifth dielectric portion 46 is disposed in the third power gap.

1W7164PA \ &gt; 2 in the middle. The sixth dielectric portion 50 is disposed on the eighth stack sidewall 36. The seventh dielectric portion 52 is disposed on the upper surfaces of the first stacked structure 4 and the second stacked structure 6. The eighth dielectric portion 54 is disposed on the upper surfaces of the third stacked structure 8 and the fourth stacked structure 10. In other words, the conductive line 56 is disposed in the second gap 18 between the second dielectric portion 44 and the fourth dielectric portion 46. The first dielectric portion is interposed between the first stacked structure 4 and the conductive line 56. The third dielectric portion 44 is interposed between the second stacked structure 6 and the conductive line brother. The fourth dielectric portion 46 is between the third stacked structure 8 and the conductive line brother. The sixth dielectric portion 50 is interposed between the fourth stacked structure 1G and the conductive line %. In one embodiment, the conductive, line 56 is used as a word line (w L). Conductive wire $6 can include a metal or semiconductor material such as P+ type polycrystalline. Furthermore, the first stacked structure 4 and the second stacked structure 6 of the Yanzhao 1st diagram are only opened by the second dielectric. The second stack structure 8 and the fourth stack structure 10 are only symmetrical by the fifth dielectric portion 48, and the fresh elements are not reduced. Please refer to "2 B, step by step, half of the Moco 2, 7 vertical axis (χ direction) structure has a very high component density. Below nm. Therefore, the + conductor is in the embodiment, for example, the stacking sidewall 24 and the first stack of the second stacking community 4

The distance from F is about the first stack wall 26 is about W. The thickness of the first-stacked conductive strip 12 is the thickness K of the dielectric portion 40: the first stack sidewall 22 of 15 is about 15 nm. . 201236140 on the first dielectric part 40

TW7164PA

The thickness I of the I I conductive line 56 is about 10 nm. In other embodiments, for example, the distance F between the second stack sidewalls 24 and the third stack sidewalls 26 may be less than the distance N between the fourth stack sidewalls 28 and the fifth stack sidewalls 30. The distance F may be less than twice the thickness Q of the third dielectric portion 44 (i.e., F &lt; 2*Q). The distance F can be greater than one-half times the thickness Q (i.e., F&gt; Q/2). The distance F can be less than or equal to 30 nm. The distance N can be greater than or equal to 30 nm. The thickness Q can be greater than 12 nm. In some embodiments, the distance F is 16 nm. The distance N is 24 nm. The thickness Q is 14 nm. In one embodiment, the drain side of the three-dimensional vertical gate memory device has a diode design with a stack side of each layer on the source side. In other embodiments, the source side has a diode design and the drain side has a stacked layer for each layer. Referring to Figure 1, dielectric component 38 can have a single dielectric material. In other words, the first dielectric portion 40, the second dielectric portion 42, the third dielectric portion 44, the fourth dielectric portion 46, the fifth dielectric portion 48, the sixth dielectric portion 50, and the seventh dielectric Each of the portions 52 and the eighth dielectric portion 54 has a single dielectric material. In one embodiment, dielectric element 38 is used as an anti-fuse memory layer and is comprised of an anti-fuse material, for example, an oxide such as oxidized granules, or a nitride such as nitrite. FIG. 3 illustrates a semiconductor structure of another embodiment. The semiconductor structure of FIG. 3 differs from the semiconductor structure of FIG. 1 in that, in dielectric element 138, second dielectric portion 142 and fifth dielectric portion 148 have a single dielectric material, including an oxide such as hafnium oxide. And each of the first dielectric portion 140, the third dielectric portion 144, the fourth dielectric portion 146, the sixth dielectric portion 150, the seventh dielectric portion 152, and the eighth dielectric portion 154 has a plurality of 201236140

TW7164FA t = a number of different dielectric materials (including, for example, oxides such as oxidized ♦, Å, such as tantalum nitride), such as dielectric layer 135, germanium 7, 139. In one embodiment, the dielectric layers 135 and 139 have an oxide layer. The electrical layer 137 has a multilayer structure of tantalum nitride and dielectric layers 135, 137 and 13'. For example, the thick layer of the dielectric layer 135. In the range of 5nm-10nm. The thickness of the dielectric layer 137 may be 5 nm to 1 〇 nm. The dielectric = thickness can be from 5 nm to 12 nm. . In one embodiment, the dielectric sound 1 ^ ^ is used as a charge storage layer. FIG. 4 illustrates a semiconductor structure of an embodiment. The semiconductor structure of FIG. 4 differs from the semiconductor structure of FIG. 3 in that the first dielectric portion 540, the third dielectric portion 544, the fourth dielectric portion 546, and the sixth dielectric portion are in the dielectric member. Each of the 550, seventh dielectric portion 552 and the eighth dielectric portion 554 has a germanium structure, wherein the dielectric layers 521, 525, and 529 may be tantalum oxide, and the dielectric layers 523 and 527 may be tantalum nitride. In addition, the thickness of the dielectric layers 521, 523, 525 is smaller than the dielectric layer 527,

529. For example, the dielectric layers 521, 523, 525 may each have a thickness of from 1 nm to 3 nm. The dielectric layer 527 may have a thickness of 5 nm to 1 〇 nm. The dielectric layer 529 may have a thickness of 5 nm to 12 nm. In one embodiment, dielectric layers 521, 523, and 525 are used as hole tunneling structures. Dielectric layer 527 is used as the charge storage layer. Dielectric layer 523 is used as a tunneling dielectric layer. Referring to FIG. 4, for example, the distance between the first stacked structure .504 and the conductive strip 512 of the second stacked structure 506 (as a bit line) (in this example, the second dielectric portion 542) The thickness is at least equal to the thickness of the second dielectric portion 544 or the seventh dielectric portion 552 (having an ONONO structure) to avoid too high coupling between adjacent conductive stripes 512 201236140

1 W/104 corpse A capacitor. Figure 5 illustrates a semiconductor structure of an embodiment. The semiconductor structure of Fig. $ differs from the semiconductor structure of Fig. 1 in that dielectric element 238 is composed of a plurality of different dielectric materials. For example, each of the first dielectric portion 240, the third dielectric portion 244, the fourth dielectric portion 246, the sixth dielectric=the file 25〇, the seventh dielectric portion 252, and the eighth dielectric portion 254 It is a multilayer structure composed of dielectric layers 235, 237, and 239. In one embodiment, dielectric layers 235 and 239 have hafnium oxide, dielectric layer 237 has tantalum nitride, and dielectric layers 235, 237, and 239 form a multi-layer structure of tantalum. The second dielectric portion 242 and the fifth dielectric portion 248 are also comprised of different dielectric materials included in the dielectric layers 235, 237, and 239. 6 to 12 illustrate the fabrication of a semiconductor structure in an embodiment. Referring to FIG. 6, a conductive layer 403 and an insulating layer 405 are alternately stacked on a substrate 402. The conductive layers 403 are separated from each other by the insulating layer 405. The conductive layer 403 is insulated from the substrate 4〇2. The substrate 4〇2 may include an oxide gasification. The substrate 402 may also include a stone substrate and is insulated from the conductive layer 403 by a dielectric layer (not shown). Referring to FIG. 7, the patterned mask layer 4〇7 is formed on the stacked conductive layer 403 and the insulating layer 405. The portion of the conductive layer 403 and the insulating layer 405 that is not shielded by the mask layer 407 is removed to form the first stack acoustic structure 404, the second stack structure 406, the third stack structure 4〇8, and the fourth as shown in FIG. The stack structure 41 is. Each of the first stack structure 4〇4, the second stack structure 4〇6, the first stack structure 408, and the fourth stack structure 410 includes alternating strips of conductive strips 412 and insulating strips 414. Referring to Figure 9, a dielectric element 438 is formed on the first stacked structure 404, the second build-up structure 201236140 1 W/164FA » » 406, the third stacked structure 408, and the fourth stacked structure 410. Referring to Fig. 10, a conductive material 439 is formed on the dielectric member 438. Contact material 441 can be formed on conductive material 439. In one embodiment, conductive material 439 includes, for example, a P+ type polysilicon, and contact material 441 includes a metal halide such as tungsten telluride. Referring to Fig. 11, a patterned mask layer 443 is formed on the contact material 441. The portion of conductive material 439 and contact material 441 that is not obscured by mask layer 443 is removed to form conductive lines 456 and contact structures 458 as shown in FIG. The present invention has been described above by way of a preferred embodiment, and is not intended to limit the invention, and it is intended that the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a perspective view showing a semiconductor structure of an embodiment. Fig. 2 is a cross-sectional view of the semiconductor structure of Fig. 1 taken along line AA. FIG. 3 illustrates a semiconductor structure of an embodiment. Figure 4 illustrates a semiconductor structure of an embodiment. Figure 5 illustrates a semiconductor structure of an embodiment. 6 to 12 illustrate a method of fabricating a semiconductor structure in an embodiment. [Main component symbol description] 2. 402: Base 201236140

1 W7I64FA 4, 404, 504: first stack structure 6, 406, 506: second stack structure 8, 408: third stack structure 10, 410: fourth stack structure 12, 412, 512: conductive strips 14, 414: Insulation stripe 16: first gap 18: second gap

20: third gap 22: first stack side wall 24: second stack side wall 26: third stack side wall 28: fourth stack side wall 30: fifth stack side wall 32: sixth stack side wall 34: seventh stack side wall

36: eighth stack sidewalls 38, 138, 238, 438, 538: dielectric elements 40, 140, 240, 540: first dielectric portions 42, 142, 242, 542: second dielectric portions 44, 144, 244 544: third dielectric portion 46, 146, 246, 546: fourth dielectric portion 48, 148, 248: fifth dielectric portion 50, 150, 250, 550: sixth dielectric portion 52, 152, 252 552: seventh dielectric portion 12 201236140 IW / 164HA « » 54, 154, 254, 554: eighth dielectric portion 56, 456: conductive lines 135 ' 137 , 139 ' 235 ' 237 , 239 ' 521 ' 523 , 525, 527, 529: dielectric layer 403: conductive layer 405: insulating layer 4〇7, 443: mask layer 439: conductive material • 441: contact material 458: contact structure E: half pitch F, N: distance G, K, Μ, Q: thickness 13

Claims (1)

201236140 TW7164PA • r VII. Patent Application Range: 1. A semiconductor structure comprising: a substrate; a first stacked structure and a second stacked structure disposed on the substrate, wherein the first stacked structure and the second stacked Each of the structures includes staggered stacked conductive stripes and insulating stripes, the conductive stripes being separated by the insulating stripes; a dielectric element disposed on the first stacked structure and the second stacked structure and including a second dielectric An electrical portion, wherein the first stacked structure and the second stacked structure are separated from each other only by the second dielectric portion; and a conductive line disposed away from the first stacked structure and the second stacked structure a stacked sidewall of the second dielectric portion, wherein the dielectric component is interposed between the conductive line and the first stacked structure and between the conductive line and the second stacked structure. 2. The semiconductor structure of claim 1, wherein the conductive line is used as a word line, and the conductive strip of the first stacked structure and the second stacked structure is used as a bit line. 3. The semiconductor structure of claim 1, wherein the first stacked structure and the second stacked structure have a first gap, the first stacked structure comprising an opposite first stacked sidewall and a second stacking sidewall, the second stacking structure includes an opposite third stacking sidewall and a fourth stacking sidewall, the first stacking sidewall and the fourth stacking sidewall being away from the first compartment 201236140 1 W/164FA % 间隙, 'the second stack sidewall and the third stack sidewall are adjacent to the first gap, the dielectric component further comprises: a first dielectric portion disposed on the first stack sidewall; First, &quot; is called and hard four piles on the side of the 丄 丄 八 八 " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " The semiconductor structure of claim 3, wherein the dielectric portion and the third dielectric portion have a dielectric material earlier. The invention relates to a semiconductor structure according to item 3 of the patent scope, a single dielectric material in the basin, the first dielectric portion and the: multi-layer, 纟I: system having a plurality of different dielectric materials 6 into the semiconductor structure as described in claim 3, the first electrical portion of the basin (four) is composed of a plurality of different dielectric materials, and each of the dielectric portion and the third dielectric portion has The multilayer structure of the dielectric material is the same as that of the semiconductor structure of the third aspect of the invention, wherein the semiconductor structure is between the first stacked structure and the conductive line The semiconductor structure of the seventh aspect of the present invention, wherein the conductive line is used as a sub-line, and the conductive strip is used as a bit line. The first stack structure 9. The semiconductor structure described in claim 3, further comprising 15 201236140 TW7164PA a third stack structure, wherein ' ' the second stack structure and the third There is a second gap between the stacked structures, The second stack structure includes an opposite fifth stack sidewall and a six stack sidewall, and the fourth stack sidewall and the fifth stack sidewall are adjacent to the second gap. The sidewall and the sixth stack sidewall further comprise a fourth dielectric portion away from the second spacer, and the fourth dielectric portion is disposed on the fifth stack sidewall of the Shai, the conductive line configuration In the second gap and between the third dielectric portion and the fourth dielectric portion. 10. The semiconductor according to item 9 (4) includes a fourth stack structure, wherein the tan 匕 gap 5 Between the second stack structure and the fourth stack structure, a third=fourth stack structure includes opposite eight stack sidewalls, and the squeak is adjacent to the third stack sidewall. a gap, and the sidewall and the eighth stack sidewall are further away from the third dielectric component, further comprising a fifth dielectric portion - a knife portion, and a fifth dielectric portion is disposed on the third layer: the portion is disposed in the first portion Eight stacking sidewalls. The first...&quot; lh as described in claim 1G a conductor structure, y 201236140 1W7164PA I » 5Hai = 介 ^ ^ hand 'between the fourth stack structure and the conductive line. The first dielectric portion of the semiconductor structure, wherein the fourth dielectric portion , the current part;; = part of the third dielectric part, the - dielectric material. &quot; the electrical part and the sixth dielectric part have a single please turn 1 please 帛 1G Gu semiconductor structure, 1 in the Each of the fifth dielectric portions has /, an electrical material, the first dielectric portion, the third dielectric portion, and the second dielectric device, as described in the second section of the electric power application department. The semiconductor structure is composed of a dielectric material of Yintong, a multilayer structure composed of the first dielectric portion, the fourth dielectric portion and the sixth dielectric material. The system 'has a semi-conducting structure as described in the first item of the eight-eighth item, 1; the electric 7-piece includes an oxide or a nitride. /, 16. A method of fabricating a semiconductor structure, comprising: forming a first stacked structure and a second stack in C, the towel-stacking structure and the second stack comprising staggered stacks The conductive stripe and the insulating layer are separated by the insulating stripe; the conductive strip forms a dielectric element on the first stacked structure, wherein the dielectric element includes a second dielectric structure and the second dielectric structure The structure is only by the second dielectric part 结= junction 17 201236140 TW7164PA 造==================================================================================== a conductive line and the /, W dielectric conductive line and the second stacked structure.隹 "Between the structure and between the method of the method 1",: the gap between the semiconductor structure described in claim 16 of the patent application, the first stack 4 structure and the second (four) structure have - - two stacks =; the stack structure includes opposing - first stack sidewalls and - fourth stack sidewall structure including opposite "third stack 4 sidewalls" and a first gap, the sidewalls and the fourth stack sidewall being remote from the first - between The second stack sidewall and the third stack sidewall are adjacent to the first 1; the dielectric component further includes: and a first-dielectric portion disposed on the first stack sidewall, in the middle=three ί section, configured On the fourth stack sidewall, a second intermediate dielectric portion is disposed in the first gap. The semiconductor structure of the invention is formed by the first stacked structure and the conductive portion, and a dielectric portion is interposed between the second stacked structure and the conductive line. The third dielectric portion is connected to the second dielectric portion 201236140. The semiconductor structure manufacturing method of claim 18, further comprising: forming a third stack structure; and forming a conductive line, wherein the second stack structure and the third stack structure have a first a gap, the third stack structure includes a fifth stack side and a sixth stack side wall, and the fourth stack side wall and the fifth stack side wall are adjacent to the second gap 'the third stack side wall and the first The sixth stacking sidewall is separated from the second gap, and the dielectric component further includes a fourth portion f, the fourth dielectric blade is disposed on the fifth stack sidewall, and the conductive wire is disposed in the second gap And between the third dielectric portion and the fourth dielectric portion. The third stack structure and the fourth three gaps, (4) the method and method of the semiconductor structure described in the scope of claim 2G, further comprising forming a fourth stack structure, wherein the fourth stack structure has a - The fourth initial crystal β sister akh. gap, gap, The dielectric component further includes a fifth dielectric layer and a sixth dielectric portion I, 201236140 TW7164PA, the fifth dielectric portion is disposed in the third gap, and the sixth dielectric portion is configured On the eighth stack sidewall. 22. The method of fabricating a semiconductor structure according to claim 21, wherein the sixth dielectric portion is interposed between the fourth stacked structure and the conductive line. 20