201234767 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明係有關一種轉換率（Slew rate)增強電路’特 別是關於一種適用於運算放大器的轉換率增強電路。 【先前技術】 [〇〇〇2] 運算放大器為差動放大器的一種，普遍使用來建構各種 電子系統。一般會使用米勒（Miller)電容於運算放大 器中進行頻率補償以增進穩定度。然而，大電容量的米 _ 勒電容會降低運算放大器的轉換率，因而限制了運算放 〇 大器的操作速度。si此’於設計運算放大器時，必需於 . ;;.. : 穩定度和轉換率之間作一取捨。 [0003] 鑑於傳統運算放大器受限於轉換率或穩定度，因此亟需 提出一種新穎的轉換率增強電路，用以增造放大器的操 作速度，可強化轉換率但不會影響其穩定度。 【發明内容】 [0004] 鑑於上述，本發明實施例的:且的之一在於提出一種轉換 〇 率增強電路，用以增加放大器的轉換率，但不會犧牲其 穩定度。 [0005] 根據本發明實施例，轉換率增強電路包含電流源、電流 鏡電路及切換電路。電流源用以提供或汲取電流。電流 鏡電路根據電流源以產生鏡射電流而適應性地提供給放 100104689 大器**亥放大器接收非反相輸入電壓及反相輸入電壓。 切換電路電性耦接至電流源及電流鏡電路。切換電路包 含並聯之第一分支及第二分支，其中第一分支及第二分 支的路徑根據非反相輸入電壓及反相輸入電壓而分別受 表單編號A0101 第3 1/共15頁 1002008142-0 201234767 控於第一開關及第二開關。 【實施方式】 [0006] 第一圖顯示本發明實施例之轉換率增強電路1的方塊圖。 本實施例之轉換率增強電路1可用以增加放大器2的轉換 率，該放大器2可為運算放大器，但不限定於此。放大器 2接收一對差動輸入電壓，亦即非反相輸入電壓V +及反相 輸入電壓V-，因而產生輸出電MV 。放大器2可包含至少 0 一米勒電容，用以補償放大器2的頻率。 [0007] 在本實施例中，轉換率增強電路1包含電流源10、切換電 路12及電流鏡電路14。其中，切換電路12電性耦接於電 流源1 0及電流鏡電路1 4。在一例子中，切換電路1 2係電 性耦接於電流源10與電流鏡電路14之間。電流源10用以 提供或汲取電流。切換電路12包含二並聯之分支：第一 分支及第二分支，其電性耦接於電流源10與電流鏡電路 14之間，且二分支之路徑分別受控於第一開關SW1及第二 開關SW2。當非反相輸入電壓V +與反相輸入電壓V-的壓差 (V + )-(V-)大於第一預設值時，則第一開關SW1會閉合， 否則該第一開關SW1會斷開。當反相輸入電壓V-與非反相 輸入電壓V+的壓差（V-)-(V + )，或稱為反壓差（reverse voltage difference) ， 大於第二預設值時， 則第二開關SW2會閉合，否則該第二開關SW2會斷開。上 述第一預設值與第二預設值不一定要相同。當任一分支 閉合時，電流鏡電路14會根據電流源10以產生鏡射電流 給放大器2。該鏡射電流可同於電流源10的電流，也可以 是電流源1 0之電流的適當倍數。 100104689 表單編號A0101 第4頁/共15頁 1002008142-0 201234767 [0008]在本實施例中，當非反相輪入電壓v+與反相輸入電壓V-之間的壓差處於變換狀態（例如升緣或降緣）時，轉換 率增強電路1適應性地提供額外電流，亦即鏡射電流，給 放大器2。由於轉換率係與流經放大器2的電流成正比例 ，因此，當壓差處於變換狀態時，會因該額外電流而增 加其轉換率。相反地，當壓差處於穩定狀態時，轉換率 增強電路1停止提供該額外電流至放大器2，因而維持放 大器2的穩定度。 〇 剛帛二圖顯示第—圖之轉換率增強電路〗的詳細電路。本實 施例的放大器2包含差動對（differentiM pair) 20 ，電性耦接於主動電流負栽22與電流源24之間。差動對 20包含二N型金屬氧化物半導體（NM〇s)電晶體…和犯 ，其分別接收非反相輸入電壓¥+與反相輸入電壓^。放 大器2還包含輸出級26，其包含串聯之p型金屬氧化物半 導體（PMOS)電晶體pi及霄流源26〇。輸與節點v。位於 PMOS電晶體P1及電流源260之間。標註c者為米勒電容 ' …"Μ:.ί [_]切換電路12的第-分支包含串聯之_5第一電晶想们及 PMOS第二電晶體ο ^ NMOS第一電晶體M1的源極連接至 PMOS第二電晶體M2的源極。NM__電晶體_没極連 接至電流源10，且PMOS第二電晶體M2的汲極連接至電流 鏡電路14。_S第-電晶舰的閑極接收非反相輸入電 壓V+，而PMOS第二電晶體M2的閘極接收反相輸入電壓v_ 〇 表單編號A0101 _類似的情形，切換電路12的第二分支包含串聯之麵§第 100104689 1002008142-0 第5頁/共15頁 201234767 二電晶體M3及PM0S第四電晶體M4。NMOS第三電晶體[^3的 源極連接至PM〇s第四電晶體M4的源極。NM0S第三電晶體 M3的汲極連接至電流源1〇，且pM〇s第四電晶體M4的汲極 連接至電流鏡電路14。NM0S第三電晶體M3的閘極接收反 相輸入電壓V-，而PM0S第四電晶體M4的閘極接收非反相 輸入電壓V+。 [0012] 詳而言之，對於第一分支而言，當以下條件符合時， NM0S第一電晶體Ml及PM0S第二電晶體M2會導通：201234767 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a slew rate enhancement circuit', particularly to a conversion rate enhancement circuit suitable for an operational amplifier. [Prior Art] [〇〇〇2] An operational amplifier is a type of differential amplifier that is commonly used to construct various electronic systems. Miller capacitors are typically used in the op amp for frequency compensation to improve stability. However, a large capacitance of the mega-capacitor reduces the conversion rate of the operational amplifier, thus limiting the operating speed of the operational amplifier. When designing an operational amplifier, it is necessary to make a trade-off between stability and conversion rate. [0003] In view of the fact that conventional op amps are limited by slew rate or stability, it is desirable to propose a novel slew rate enhancement circuit that increases the operating speed of the amplifier and enhances the slew rate without compromising its stability. SUMMARY OF THE INVENTION In view of the above, one of the embodiments of the present invention is to provide a conversion rate enhancement circuit for increasing the conversion rate of an amplifier without sacrificing its stability. According to an embodiment of the invention, the conversion rate enhancement circuit includes a current source, a current mirror circuit, and a switching circuit. A current source is used to provide or draw current. The current mirror circuit is adaptively supplied to the amplifier according to the current source to generate a mirror current, and the non-inverting input voltage and the inverting input voltage are received by the amplifier. The switching circuit is electrically coupled to the current source and the current mirror circuit. The switching circuit includes a first branch and a second branch connected in parallel, wherein the paths of the first branch and the second branch are respectively subjected to the form number A0101 according to the non-inverting input voltage and the inverted input voltage, respectively, 3 1 / 15 pages 1002008142-0 201234767 is controlled by the first switch and the second switch. [Embodiment] The first figure shows a block diagram of a conversion rate enhancement circuit 1 of an embodiment of the present invention. The conversion rate enhancement circuit 1 of the present embodiment can be used to increase the conversion ratio of the amplifier 2, which can be an operational amplifier, but is not limited thereto. Amplifier 2 receives a pair of differential input voltages, i.e., a non-inverting input voltage V+ and an inverting input voltage V-, thereby producing an output electrical MV. Amplifier 2 can include at least a one Miller capacitance to compensate for the frequency of amplifier 2. In the present embodiment, the conversion rate enhancement circuit 1 includes a current source 10, a switching circuit 12, and a current mirror circuit 14. The switching circuit 12 is electrically coupled to the current source 10 and the current mirror circuit 14. In one example, the switching circuit 12 is electrically coupled between the current source 10 and the current mirror circuit 14. Current source 10 is used to provide or draw current. The switching circuit 12 includes two parallel branches: a first branch and a second branch electrically coupled between the current source 10 and the current mirror circuit 14, and the paths of the two branches are respectively controlled by the first switch SW1 and the second Switch SW2. When the voltage difference (V + ) - (V -) between the non-inverting input voltage V + and the inverting input voltage V - is greater than the first preset value, the first switch SW1 will be closed, otherwise the first switch SW1 will disconnect. When the voltage difference (V−)−(V + ) between the inverting input voltage V− and the non-inverting input voltage V+, or the reverse voltage difference, is greater than the second preset value, then the second Switch SW2 will close, otherwise the second switch SW2 will open. The first preset value and the second preset value are not necessarily the same. When either branch is closed, current mirror circuit 14 produces a mirror current to amplifier 2 based on current source 10. The mirror current can be the same as the current of the current source 10 or an appropriate multiple of the current of the current source 10. 100104689 Form No. A0101 Page 4 of 15 1002008142-0 201234767 [0008] In the present embodiment, when the voltage difference between the non-inverted wheeling voltage v+ and the inverting input voltage V- is in a transformed state (for example, liter The conversion rate enhancement circuit 1 adaptively provides an additional current, that is, a mirror current, to the amplifier 2 when it is edged or lowered. Since the slew rate is proportional to the current flowing through the amplifier 2, when the voltage difference is in the transition state, the slew rate is increased by the extra current. Conversely, when the differential pressure is in a steady state, the slew rate enhancement circuit 1 stops supplying the additional current to the amplifier 2, thus maintaining the stability of the amplifier 2. 〇 The second diagram shows the detailed circuit of the conversion rate enhancement circuit of the first figure. The amplifier 2 of the present embodiment includes a differential pair (20) that is electrically coupled between the active current source 22 and the current source 24. The differential pair 20 includes two N-type metal oxide semiconductor (NM〇s) transistors... and it receives a non-inverting input voltage ¥+ and an inverting input voltage ^, respectively. The amplifier 2 also includes an output stage 26 comprising a p-type metal oxide semiconductor (PMOS) transistor pi and a turbulent source 26A connected in series. Lose with node v. Located between the PMOS transistor P1 and the current source 260. The label c is the Miller capacitance '..."Μ:. ί [_] The first branch of the switching circuit 12 includes the _5 first electric crystal and the PMOS second crystal ο ^ NMOS first transistor M1 The source is connected to the source of the PMOS second transistor M2. The NM__Crystal_ is not connected to the current source 10, and the drain of the PMOS second transistor M2 is connected to the current mirror circuit 14. The idle pole of the _S first-electrocrynic ship receives the non-inverting input voltage V+, and the gate of the PMOS second transistor M2 receives the inverted input voltage v_ 〇 form number A0101 _ similarly, the second branch of the switching circuit 12 contains Tandem surface § 100104689 1002008142-0 Page 5 of 15201234767 Two transistors M3 and PM0S fourth transistor M4. The source of the NMOS third transistor [^3 is connected to the source of the PM〇s fourth transistor M4. The drain of the NM0S third transistor M3 is connected to the current source 1A, and the drain of the pM〇s fourth transistor M4 is connected to the current mirror circuit 14. The gate of the NM0S third transistor M3 receives the inverting input voltage V-, and the gate of the PM0S fourth transistor M4 receives the non-inverting input voltage V+. [0012] In detail, for the first branch, when the following conditions are met, the NMOS first transistor M1 and the PMOS second transistor M2 are turned on:
(V+)>(V-)+V + I V I tn tp 其中，Vtn為NM0S第一電晶體Ml的臨界電壓，而V為 t P ' PM0S第二電晶體M2的臨界電壓。換句話說，上述的第一 預設值為V 絕對值和V 之和。 tp tn [0013] 對於第二分支而言，當以下條件符合時，NM0S第三電晶 體M3及PM0S第四電晶體M4會導通：(V+)>(V-)+V + I V I tn tp where Vtn is the threshold voltage of the NM0S first transistor M1, and V is the threshold voltage of the t P 'PM0S second transistor M2. In other words, the first preset value described above is the sum of the absolute value of V and V. Tp tn [0013] For the second branch, the NM0S third transistor M3 and the PMOS fourth transistor M4 are turned on when the following conditions are met:
(V-)XV+)+V+ + | V I tn tp 其中，V 為NM0S第三電晶MM3的臨界電壓，而V 為 tn tp PM0S第四電晶體M4的臨界電壓。換句話說，上述的第二 預設值為V 絕對值之和。 tp tn [0014] 電流鏡電路14包含二同型M0S電晶體：第一 M0S電晶體M5 及第二M0S電晶體M6 (如第二圖所示同為NM0S電晶體） ，其電流的方向同於電流源1 〇的電流方向。第一 M0S電晶 體M5連接成二極體型態，且第一M0S電晶體M5和第二M0S 電晶體M6的閘極連接在一起。第一M0S電晶體M5電性耦接 至切換電路12，特別是連接至PM0S第二電晶體M2和PM0S 第四電晶體M4的汲極；第二M0S電晶體M6電性耦接至放大 100104689 表單編號A0101 第6頁/共15頁 1002008142-0 201234767 器2，特別是連接至差動對2〇。根據第二圖所示架構，除 了錢源24所提供U之外，第：_電痛6還適應性 地提供額外電流，亦g卩倍如啦 丌即鏡射電流，給差動對20。藉此， 得以增進放大器2的轉換率但不會影響其穩定度。 [0015] Ο 、"員示第一圖之轉換率增強電路〗的另一詳細 電路。本實施例之轉換率增強電路丨係用以增強軌對轨（ rail to rail)運异放大器的轉換率。第三圖所示的轉 換率增強電路1類似於第二圏所示的轉換率增強電路】， 不同的地方在於’第三圖的轉換率增強電路】包含二轉換 率增強電路：N型轉換率增強電路1N及P型轉換率增強電 路1P。其巾，N型轉換率增強電路1N使則型電流鏡電路 14N (亦即’第二圖的第一M0S電晶體Jf5及第二M0S電晶 體材6白為N型）以提供鏡射電流給N型差動對20N，而P型 轉換率增強電路1P使用p型電流鏡電路14p (亦即，第二 圖的第一M0S電晶體M5及第二M0S電晶體M6皆為P型）以 &供鏡射電流給p型差動對2〇p ^ 〇 [0016] 軌對軌運算放大器的：N型差動對;2〇Ν相應一主動電流負載 22N，而P型差動對2〇p相應另一主動電流負載22p。標註(V-)XV+)+V+ + | V I tn tp where V is the threshold voltage of the NM0S third transistor MM3, and V is the threshold voltage of the tn tp PM0S fourth transistor M4. In other words, the second preset value described above is the sum of the absolute values of V. Tp tn [0014] The current mirror circuit 14 comprises a two-type MOS transistor: a first MOS transistor M5 and a second MOS transistor M6 (as shown in the second figure are NM0S transistors), the direction of the current is the same as the current Source 1 〇 current direction. The first MOS transistor M5 is connected in a diode form, and the gates of the first MOS transistor M5 and the second MOS transistor M6 are connected together. The first MOS transistor M5 is electrically coupled to the switching circuit 12, in particular to the drains of the PMOS second transistor M2 and the PMOS fourth transistor M4; the second MOS transistor M6 is electrically coupled to the amplification 100104689 form No. A0101 Page 6 of 15 1002008142-0 201234767 2, especially connected to the differential pair 2〇. According to the architecture shown in Figure 2, in addition to the U provided by Qianyuan 24, the first:_Electric Pain 6 also adaptively provides additional current, which is also the same as the mirror current, giving the differential pair 20. Thereby, the conversion rate of the amplifier 2 can be improved without affecting its stability. [0015] 详细 , " Member of the first graph of the conversion rate enhancement circuit〗 of another detailed circuit. The conversion rate enhancement circuit of the present embodiment is used to enhance the conversion rate of a rail to rail transmission amplifier. The conversion rate enhancement circuit 1 shown in the third figure is similar to the conversion rate enhancement circuit shown in FIG. 2, and the difference is that the conversion rate enhancement circuit of the third diagram includes two conversion rate enhancement circuits: N-type conversion rate. The enhancement circuit 1N and the P-type conversion rate enhancement circuit 1P. The towel, the N-type conversion rate enhancement circuit 1N makes the current type current mirror circuit 14N (that is, the first MOS transistor Jf5 of the second figure and the second MOS transistor material 6 are N-type) to provide a mirror current. The N-type differential pair 20N, and the P-type conversion rate enhancement circuit 1P uses the p-type current mirror circuit 14p (that is, the first MOS transistor M5 and the second MOS transistor M6 of the second figure are both P-type) to & For mirror current to p-type differential pair 2〇p ^ 〇[0016] Rail-to-rail operational amplifier: N-type differential pair; 2〇Ν corresponding one active current load 22N, and P-type differential pair 2〇 p corresponds to another active current load 22p. Label
Cml及Cm2者為米勒電容。根據第三圖所示架構，除了電流 源24N及24P所提供電流之外，N型電流鏡電路14N和p型 電流鏡電路14P還適應性地分別提供額外電流，亦即鏡射 電流’給N型差動對20N和P型差動對20P。藉此，得以增 進軌對軌運算放大器的轉換率但不會影響其穩定度。 以上所述僅為本發明之較佳實施例而已，並非用以限定 本發明之申請專利範圍；凡其它未脫離發明所揭示之精 100104689 表單編號A0101 第7頁/共15頁 1002008142-0 [0017] 201234767 神下所完成之等效改變或修飾，均應包含在下述之申請 專利範圍内。 【圖式簡單說明】 [0018] 第一圖顯示本發明實施例之轉換率增強電路的方塊圖。 第二圖顯示第一圖之轉換率增強電路的詳細電路。 第三圖顯示第一圖之轉換率增強電路的另一詳細電路。 【主要元件符號說明】 [0019] 1 轉換率增強電路 1N N型轉換率增強電路 1P P型轉換率增強電路 10 電流源 12 切換電路 14 電流鏡電路 14N N型電流鏡電路 14P P型電流鏡電路 2 放大Is 20 差動對 20N N型差動對 20P P型差動對 22 主動電流負載 22N 主動電流負載 22P 主動電流負載 24 電流源 24N N型電流源 24P P型電流源 表單編號A0101 第8頁/共15頁 100104689 1002008142-0 201234767Cml and Cm2 are Miller capacitors. According to the architecture shown in the third figure, in addition to the currents supplied by the current sources 24N and 24P, the N-type current mirror circuit 14N and the p-type current mirror circuit 14P also adaptively provide additional current, that is, the mirror current 'to N Type differential pair 20N and P type differential pair 20P. This allows the conversion rate of the rail-to-rail op amp to be increased without compromising its stability. The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention; the other is not departing from the disclosure of the invention 100104689 Form No. A0101 Page 7 / Total 15 Page 1002008142-0 [0017 201234767 Equivalent changes or modifications made by God shall be included in the scope of the patent application below. BRIEF DESCRIPTION OF THE DRAWINGS [0018] The first figure shows a block diagram of a conversion rate enhancement circuit of an embodiment of the present invention. The second figure shows the detailed circuit of the conversion rate enhancement circuit of the first figure. The third figure shows another detailed circuit of the conversion rate enhancement circuit of the first figure. [Main component symbol description] [0019] 1 Conversion rate enhancement circuit 1N N-type conversion rate enhancement circuit 1P P-type conversion rate enhancement circuit 10 Current source 12 Switching circuit 14 Current mirror circuit 14N N-type current mirror circuit 14P P-type current mirror circuit 2 Amplification Is 20 Differential Pair 20N N Type Differential Pair 20P P Type Differential Pair 22 Active Current Load 22N Active Current Load 22P Active Current Load 24 Current Source 24N N Type Current Source 24P P Type Current Source Form No. A0101 Page 8 / Total 15 pages 100104689 1002008142-0 201234767
26 輸出級 260 電流源 SW1 第一開關 SW2 第二開關 V + 非反相輸入電壓 V- 反相輸入電壓 V 0 輸出電壓 C Ω1 米勒電容 米勒電容 米勒電容 N1、N2 NM0S電晶體 PI PM0S電晶體 Ml NM0S第一電晶體 M2 PM0S第二電晶體 M3 NM0S第三電晶體 M4 PM0S第四電晶體 M5 第一 M0S電晶體 M6 第二M0S電晶體 100104689 表單編號A0101 第9頁/共15頁 1002008142-026 Output stage 260 Current source SW1 First switch SW2 Second switch V + Non-inverting input voltage V- Inverting input voltage V 0 Output voltage C Ω1 Miller capacitance Miller capacitance Miller capacitance N1, N2 NM0S transistor PI PM0S Transistor M1 NM0S First transistor M2 PM0S Second transistor M3 NM0S Third transistor M4 PM0S Fourth transistor M5 First MOS transistor M6 Second MOS transistor 100104689 Form number A0101 Page 9 / Total 15 pages 1002008142 -0