201230638 六、發明說明： 【發明所屬之技術領域】 本發明係關於升壓型之電源裝置。 【先前技術】 作為將由交流電源產生之交流電壓整流成直流電壓之整 流電路，或將從直流電源等輸入之直流低電壓升壓，從而 作為直流之高電壓輸出之電源裝置之方式，已知有升壓型 (或亦稱為 Boost Style)。 例如，如圖11所示，若將非專利文獻1之第40頁圖3.1記 載之升壓型電源電路在必要之範圍内予以簡略化而示例， 則電源電路50係將由電源51產生之低電壓之輸入電壓Vcc 升壓，作為輸出電壓Vo供給至負載R50者，且其包含電感 器L50、二極體D50、N通道型MOSFET Q50、控制電路 52 '及電容器C50。（再者，該非專利文獻之圖3.1之題名 雖為「降壓型轉換器之原理電路」，但其顯然為誤植，應 為「升壓型轉換器之原理電路」）。 電感器L50其一端連接於電源51之正側。二極體D50其 陰極與電感器L50之另一端連接，而陽極連接於負載R50之 正側（輸出電壓Vo之輸出端之正側）。MOSFET ()50其汲極 連接於二極體D50之陰極，而源極連接於接地GND。控制 電路52連接於MOSFET Q50之閘極。電容器C50連接於二 極體D50之陽極與接地GND之間。 且，控制電路52係控制輸入至MOSFET Q50之閘極之電 壓，控制MOSFET Q50之ΟΝ/OFF動作，以使輸出電壓Vo成 156365.doc 201230638 為較輸入電壓Vcc更為升壓之特定值的方式，對MOSFET Q50進行重複ΟΝ/OFF動作之開關動作。 要進行利用該電源電路50之升壓動作，係在假設電容器 C50之兩端電壓為0 V、且於電感器L50中流動之電流為0A 之狀態（即，無論是電荷、磁通之任一種形態皆為無能量 蓄積之狀態）下，首先，在將電源51連接於電源電路50之 狀態下，藉由控制電路52開啟MOSFET Q50，使電流從電 源51依序流向電感器L50、MOSFET Q50，並將電源51之 電能作為磁能蓄積於電感器L50。 其後，若藉由控制電路52關閉MOSFET Q50，則由於電 感器L50於即將關閉MOSFET Q50之前之方向繼續流動電 流，故於電感器L50之電源5 1側產生具有負極性之電壓， 而於二極體D50側產生具有正極性之電壓。該電壓與電源 51之輸入電壓Vcc之和會經由二極體D50作為輸出電壓Vo 而被供給至電容器C50與負載R50。 電容器C50對負載R50供給在MOSFET Q50開啟期間蓄積 之電荷，即電能，另一方面，蓄積在MOSFET Q50關閉期 間經由二極體D50供給之電能，使輸出電壓Vo平滑化。 如此，由於從電源電路50供給至電容器C50與負載R50 之輸出電壓Vo係在MOSFET Q50關閉期間由電感器L50產 生之電壓加上電源51之輸入電壓Vcc者，故該電源電路50 可將輸入電壓Vcc經升壓後之輸出電壓Vo供給至電容器 C50與負載R50。 然而，在上述之電源電路50中，因升壓動作開始前之暫 156365.doc 201230638 態現象，會導致產生超過預期之特定值之高電壓作為輸出 電壓Vo。例如，一般的情形為，在升壓動作開始前， MOSFET Q50為關閉，如此sM〇SFET Q5〇在關閉之狀態 下，將電源5 1連接於電源電路5〇，從電源5丨對電源電路5〇 施加輸入電壓Vcc。 如此，在將電容器C5〇充電至與輸入電壓Vcc相等為 止，使電流依序流向電源51、電感器L5〇、二極體£)5〇、 電容器C50。而若輸出電壓乂〇與二極體D5〇之順向電壓下 降量之和之電壓與電源51的輸入電壓Vcc相等，則電流之 流動停止，輸出電壓Vo成為電源51之輸入電壓Vcc之初始 狀態，且從該狀態開始利用電源電路5〇進行升壓動作，此 乃理想之升壓動作之開始狀態。 然而，在包源電路5〇中，在從電源5丨向電容器C5〇之充 電路徑之中途插入有電感器L50。因此，會導致在電容器 C50與電感器L50產生正弦波狀之振動，即所謂的 振，從而導S需對t容器C5〇充電超過電源51之輸入電壓 Vcc之電壓。 作為一例，使用P〇Wer SIM公司製之模擬軟體psiM進行 模擬，以證實在電容器C5〇與電感器L5〇產生如上所述之 LC共振。 如圖12所示，進行模擬之第4模擬電路在利用電源電路 50之升塵動作開始前經除去不必要之元件而予以簡略化。 具體而S，在利用t源電路5〇之升I動作開始前，由於 MOSFET Q50為關閉狀態，故作為不必要之元件予以除 156365.doc 201230638 去。又’控制MOSFET Q50之控制〇N/〇FF動作之控制電路 52亦作為不必要之元件而予以除去。且，負載R5〇假設其 相當輕且為無負載狀態。此外，將各元件之電路常數設 為’電感器L50之電感值：22[μΗ]、電容器C50之靜電電 谷.1〇〇〇F]、二極體D50之順向電壓下降：〇 5[ν]、電源 51之輸入電壓Vcc : 10[ν] ’將進行模擬之結果之波形顯示 於圖13。 圖1 3之上段顯示於二極體D5 0中流動之電流11之波形， 下段顯示輸出電壓Vo(電容器C5〇之兩端電壓）之波形、電 源51之輸入電壓Vcc之波形、電感器乙5〇之兩端電壓％之 波形。再者，電感器1^50之電壓在二極體D5〇側成為正的 時候作為正電壓表示。如圖13所示，可知輸出電壓v〇明 顯超過輸入電壓Vcc，且上升至接近電感器L5〇之兩端電壓 V1之最向電壓值與電源51之輸入電壓Vcc的和之電壓。 該輸出電壓ν〇之上升被認為是電感器L5〇與電容器c5〇 之LC共振引起者，且在輸出電壓Vo上升至最高之時點， 藉由一極體D50之作用，使輸出電壓v〇維持在上升至最高 、门電c，以阻止電流從電容器C5〇向電感器逆流。若 j為如此高之輸出電壓V〇，則會導致負載R50在消耗電容 态C50中蓄積之電能之前，無法降低至期望之值。再者， 右電感器L50之電感值為〇[μΗ],則該輸出電壓％之最高電 值食/、會上升至輸入電壓Vcc為止，但如此會對升壓動 作造成障礙。X，若電容器C50之靜電電容為較小之 則會成為相當高之值。 156365.doc 201230638 其次’以圖14所示之從圖12所示之第4模擬電路中除去 二極體D50之第5模擬電路進行模擬，將該模擬之結果之波 形顯示於圖15。再者，在圖14所示之電路中，由於除去了 二極體D50，故於圖15之上段顯示於電感器L5〇中流動之 電流13之波形。 如圖15所示，觀察該等之波形，在除去二極體〇5〇之狀態 下產生1^0共振，若計鼻該共振頻率，為^=1/(2冗也〇)=3393[1^；]。 且該週期1為t=295[ps] ’與圖13所示之電流或電壓之升 高時之週期大致一致。因此可知，因LC共振導致對輸入電 壓Vcc加上電感器L5〇之兩端電壓V1時之最初遭遇到正側 峰值之瞬間電壓、即大約20[v]被蓄積於電容器C5〇，成為 輸出電壓Vo。再者，圖15所示之輸出電壓v〇略微大於圖13 所不之輸出電壓Vo ’係由於除去了二極體d50，使二極體 D 5 0之順向電壓不會降低所導致。 其次’如圖16所示，以在圖14所示之第5模擬電路中將 二極體D50復原且連接^[^^作為負載R5〇之第6模擬電路進 行模擬’將該模擬之結果之波形顯示於圖17。再者，由於 將電源51之輸入電壓vcc設為ι〇[ν]，故ι〇[ω]之負載r5〇即 使在不進行升壓動作之情形下，仍會流動1[Α]之電流，消 耗10 [W]之電力。因此，輸出電壓Vo在不產生LC共振之情 形時’應會低於輸入電壓Vcc。然而，如圖17之下段所 示’輸出電壓Vo因LC共振而在大約〇.7[ps]左右期間，超 過輸入電壓Vcc。 因此’例如若設電源51之輸入電壓Vcc=10[V]，負載R50 156365.doc 201230638 所必須或所預期之特定之輸出電壓V〇=l2[v]，則即使在附 加相當於1〇[Ω]之負載R50之狀態下，在數百[叩]期間仍 會對負載R50施加過電壓。此時，若負載R5〇僅為電阻 體，則有時雖可能容許該過電壓，但若為對過大之電壓/ 電流之感度較高之半導體，例如LED(發光二極體）等，則 可能有因該過電壓而遭破壞之危險性。又，亦會使電容器 C50或二極體D50曝露於該[〇共振引起之高電壓從 須使用耐電壓高之高價者。 對此，作為抑制該LC共振之電路構成，係例如在專利 文獻1記載之電容器充電裝置中，於直流電源與共振用電 感之間，以使該半導體開關與共振用電感之連接點連接於 與接地GND相反驗方向的方式，將半導體_以所謂的 續流（或飛輪）二極體連接。且，該電容器充電裝置預測/運 舁能量蓄積電容器之充電量，控制半導體開關之〇n/〇ff 動作，從而抑制LC共振。又，電容器充電裝置具有另―個 升壓動作用之半導體開關，以控制電路進行各個半導體開 關之控制。 [先行技術文獻] [專利文獻] [專利文獻1]曰本特開2003-143875號公報（圖〇 [非專利文獻]岡山務著，「切換轉換器電路入門」、曰 刊工業新聞社，2006年9月20日初版第1刷發行，第39頁至 49頁、及第51頁至63頁 【發明内容】 156365.doc 201230638 [發明所欲解決之問題] 然而，如該專利文獻！記載之電容器充電裝置所示，若 使用半導體開關來抑制LC共振，會產生各種問題。例如， - '必須預先預測/運算電容器之充電量，且必須高速處理， • 彳疋而導致耗電里增大。又，由於必須控制2個半導體開 • 關，而難以使用通用之電源1C等作為可實現此之電路構 成，必須為例如DSP(Digital Signa丨Pr〇cess〇r，數位信號 處理器）或MPU(Micr〇 Processing Unit，微處理單元）等之 高性能之電源1C，從而導致成本增大。 又，為用於升壓而於電感器中蓄積磁能時，必須開啟半 導體開關，每次進行該蓄積就會導致半導體開關之電壓下 降程度之電力損失，使電力轉換效率降低。再者，若電容 器之充電量之預測/運算之精度低，於電感器中過度流動 電流而過度蓄積磁能，則會使該過度之磁能無謂地消耗， 導致電力轉換效率降低。 因此，本發明之目的在於提供一種降低成本且提高電力 轉換效率之電源裝置。 [解決問題之技術手段] • 本發明之電源裝置為升壓型之電源裝置，且具備：斬波 • 電路，其包含：一端連接於輸入直流輸入電壓之輸入端之 电感器；連接於前述電感器之另一端與輸出直流輸出電壓 之輸出端之間，直僅可於從前述電感器之另一端向前述輸 出端之方向導通之第1逆流防止元件；連接於前述第1逆流 防止元件之上游端與基準電位之間之第1開關元件；及控 156365.doc 201230638 制前述第1開關元件之控制電路；電容器，其連接於前述 第1逆流防止元件之下游端與基準電位之間；及旁=電 路，其包含未經由前述斬波電路之前述電感器而將前述輸 入端與削述輸出端分路連接，並僅可於從前述輸入 述輸出端之方向導通之第2逆流防止元件，且不包含電: 器。 ？ 根據本發明之電源裝置，由於在升壓動作開始前被施加 直流輸入電壓時，使電容器經由旁通電路充電，故抑制電 流於斬波電路中之流動’從而在斬波電路之電感器與電容 器難以產生LC共振。因此，對於構成電源裝置之零件，無 需使用對應於LC共振引起之過電壓之高耐壓之零件，可使 用通用性之價廉之零件，從而可降低成本。又，不會因[。 共振引起之過電壓導致連接於輸出端之負載損傷，從而可 提高安全性及可靠性。 又’若假設未於旁通電路連接第2逆流防止元件，當第i 開關7L件之開關動作開始、升壓動作開始，且直流輸出電 壓超過直流輸入電壓時，電流會經由旁通電路從輸出端之 電谷器逆流至輸入端側，導致輸入端與輸出端短路，而對 升左動作4成障礙。因此，藉由於旁通電路設置第2逆流 防止元件，可防止經由旁通電路之逆流，從而確實進行升 壓動作。 如此’可抑制成為於斬波電路產生LC共振之起因之電 ’ I·之々a動’防止因l C共振導致之過電廢被輪出至輸出端。 此時，由於旁通電路可由價廉之零件構成，故可降低成 156365.doc 201230638 本又’為使LC共振難以產生，不於斬波電路之怪常之電 流路徑串聯地連接例如電阻等之電流限制元件，而是構成 始終為升壓動作開始前僅暫時通電之旁通電路。因此，由 於设置於該旁通f路之元件之電壓下降造成之電力損失僅 於該短暫期間產生，而非怪常產生者，故可大致忽略設置 旁通電路所引起之電力轉換效率之降低…由於可藉由 旁通電路將在升壓動作開始前於電感器中流動之電流抑制 至最小限度，故不會於電感器中過度蓄積磁能，亦不會無 謂地消耗該過度之磁能’從而可提高電力轉換效率。 另方面’沈另一觀點而言，本發明之電源裝置為升壓 型之電源裝置’且具備：斬波電路、電容器及旁通電路， 該斬波電路包含：— _ 蜢連接於輸入直流輸入電壓之輸入端 之電感器；連接於前述電感器之另—端與輸出直流輸出電 壓之輸出端之間’且僅可於從前述電感器之另—端向前述 輸出端之方向導通之第！逆流防止元件；連接於前述第1逆 流防止元件之上游端與基準電位之間之糾開關元件；及 元件Μ制電路；豸電容器係連接於前 边幻逆流防止it件之下游端與基準電位之間；且該旁通 含未經由前述斬波電路之前述電感器而將前述輸入 别述輸出端分路連接’並由前述控制電料以控制之 A幵1關7L件’且不包含電感器。前述控制電路係在未使 ^第1開關元件進行開關動作期間，開啟前述第2開關元 j吏月』述第1開關70件進行開關動作期間，關閉前 述第2開關元件。 156365.doc 201230638 根據本發明之電源裝置，由於在進行第丨開關元件之開 關動作之前、即升壓動作開始前施加直流輸入電壓時，係 開啟旁通電路之第2開關元件，使電容器經由旁通電路充 電’故抑制電流於斬波電路中之流動，從而在斬波電路之 電感器與電容器難以產生Lc共振。因此，對於構成電源裝 置之零件，無需使用對應MLC共振引起之過電壓之高耐壓 之零件’可使用通用性之價廉之零件，從而可降低成本。 又’不會因LC共振引起之過電塵導致連接於輪出端之負載 才貝傷，從而可提肉安全性及可靠性。 又，假設當進行第1開關元件之開關動作，在升壓動作 開始期間’使旁通電路之第2開關元件開启欠，則在直流輸 出電壓超過直流輸入電壓時，電流會經由旁通電路從輸出 端之電容器逆流至輸人端側，導致輸人端與輸出端短路， 而對升壓動作造成障礙。對此，#由進行第旧關元件之 開關動作，在升壓動作開始期間，關閉旁通電路之第㈣ 關几件，可防止經由旁通電路之逆流，從而確實進行升壓 動作。 如此，可抑制成為於斬波電路產生1〇共振之起因之電 流之流動’防止因LC共振導致之過電壓輸出至輸出端。此 時，由於旁通電路可由價廉之零件構成，故可降低成本。 又’為使LC共振難以產生’不於斬波電路之恆常之電流路 徑串聯連接例如電阻箄之雪法 _ 寻之電限制兀件，而是構成始終為 升壓動作開始前僅暫時通電之旁通電路。因此，由於設置 於該旁通電路之元件之雪廒tan , _ 开之電廢下降造成之電力損失僅於該短 156365.doc -12- 201230638 暫期間產生’而非恆常產生者，故可大致忽略設置旁通電 路引起之電力轉換效率之降低。又，由於可藉由旁通電 路，將在升壓動作開始前於電感器中流動之電流抑制至最 小限度，故不會於電感器中過度蓄積磁能，亦不會無謂地 消耗該過度之磁能，從而可提高電力轉換效率。 再者，第2開關元件與二極體不同，.為開啟時於雙向流 動電流之7〇件。因此，在停止第丨開關元件之開關動作、 升壓動作停止後，開啟第2開關元件，藉此可經由旁通電 路使電容器之電能回流至輸入端，在輸入端連接有其他負 載之情形時，可有效活用從電容器回流之電能。 又’前述第2開關元件較佳為包含僅可於從前述輸入端 向前述輸出端之方向導通之第2逆流防止元件之 MOSFET。藉此，由於m〇SFEt與雙極電晶體不同，為電 壓控制’故驅動所需之電力較少。又，由於M〇sfet包含 第2逆流防止元件，故假設在進行第1開關元件之開關動作 之前、即升壓動作開始前被施加直流輸入電壓時，即使旁 通電路之MOSFET因某些理由未開啟而為關閉，但由於電 容器經由第2逆流防止元件充電，故仍可抑制於斬波電路 中流動電流’使得斬波電路之電感器與電容器難以產生LC 共振。如此，藉由於旁通電路設置包含第2逆流防止元件 之MOSFET’可基於防止伴隨著LC共振而產生無法控制之 高電壓之觀點，構成故障防護之電源裝置。 又，前述第2開關元件為雙極電晶體’且前述旁通電路 亦可進一步包含與前述第2開關元件並聯連接、且僅可於 156365.doc 13 201230638 從前述輸入端向前述輸出端之方向導通之第2逆流防止元 件。藉此，由於在旁通電路並聯連接有雙極電晶體與第2 逆流防止元件，故假設在進行第丨開關元件之開關動作之 刖、即升壓動作開始前被施加直流輸入電壓時，即使旁通 電路之雙極電晶體因某些理由未開啟而為關閉，但由於電 容器經由第2逆流防止元件充電，故仍可抑制在斬波電路 中流動電流，使得斬波電路之電感器與電容器難以產生LC 共振。如此，藉由於旁通電路並聯設置雙極電晶體與第2 逆流防止元件，仍可基於防止伴隨著[〇共振而產生無法控 制之高電壓之觀點，構成故障防護之電源裝置。 再者，較佳為於前述旁通電路進一步串聯連接電流限制 元件。藉此，可防止經由旁通電路充電電容器時流動之電 流過大而造成連接於第2逆流防止元件或輸入端之電源損 傷。 π除此之外，前述旁通電路所具有之電阻成份與前述電容 器之月f電電4之時間常數，較佳為藉由前述控制電路使前 述第1開關元件進行開關動作之狀態下的前述斬波電路所 八有之電阻成份與前述電容器之靜電電容之時間常數（具 體’係、以構成斬波電路之電感器及第i逆流防止元件 之等價之電阻與電容器求得之時間常數）以下。藉此，可 里由旁通電路充電電容器之速度較經由斬波電路充電電 容器為快，從而可更難以產生LC共振。 [發明之效果] 本發明可抑制成為於斬波電路產生叫振之起因之電 156365.doc 201230638 流之流動，從而防止因Lc共振導致過電壓向輸出端輸出。 此時，由於旁通電路可由價廉之零件構成，故可降低成 本。又，為使LC共振難以產生，並非串聯連接例如電阻等 之電流限制70件’而是構成旁通電路。因此，由於設置於 該旁通電路之元件之電壓下降所造成之電力損失僅暫時產 生而非隍吊產生，故可大致忽略設置旁通電路所引起之 ^力轉換效率之降低。X ’由於可藉由旁通電路，將在升 壓動作開始前於電感器中流動之電流抑制至最小限度，故 不會於電感器中過度蓄積磁能，亦不會無謂地消耗該過度 之磁能，從而可提高電力轉換效率。 【實施方式】 <第1實施形態> 八人說明本發明之第1實施形態《本實施形態係將本 發明應用於將與直流電源連接、將從直流電源輸人之低電 壓之輸入電壓升壓並作為高電壓之輸出電壓而供給至負載 之升壓.型切換電源電路之一例。圖i係本發明之第i實施形 態之電源電路之電路圖。 如圖1所示，電源電路10(電源裝置）係將由電源u產生之 低電壓之輸入電壓Vcc升壓，作為高電壓之輸出電壓供 給至負載R10’且具有電感器L1〇、2個二極體Di〇(第^ 流防止70件）、D11(第2逆流防止元件）、N通道型 Q10(第1開關元件）、控制電路12、電容器⑽、及電阻 Rll(電流限制元件）。 電感器L10其—端連接於電利之正側。 156365.doc •15· 201230638 陰極與電感器L1G之另-端連接’而陽極連接於負載㈣之 正側（輸出電壓Vo之輸出端之正側）e M〇SFET qi〇其汲極 連接於二極體D1〇之陰極，源極與接地gnd(基準電位）連 接。控制電路12連接於M0SFET Q1〇之閘極。電容器〇1〇 連接於二極體D10之陽極與接地GND之間。二極體Du其 陰極連接於電感器L10之一端，電阻RU連接於二極體〇1; 之陽極與負载R 1 〇之正側。 如此，連結電源Π之正側與負載R1〇之正側之路徑包含 串聯連接電感器L10與二極體D〗〇之主路徑15，與串聯連 接相對於該主路徑15分支之二極體DU與電阻Rn之旁通 路在1 6之兩條路從。再者，本實施形態之旁通路徑16與設 置於該旁通路徑16之二極體Du及電阻川相冑於本發明 之旁通電路。 且，控制電路12控制輸入至M〇SFET Q1〇之閘極之電 壓’並控制MOSFET Q10之〇N/〇FF動作，且以使輸出電壓 v〇成為特定值的方式，對M〇SFETQl〇進行重複〇〜〇卯動 作之開關動作。 利用該電源電路10之升壓動作係以如下之方式進行。 (1) 首先’從電源u對電源電路1〇施加輸入電壓Vcc。 對省電源電路1 〇之輸入電壓Vec之施加，包含將常開式之 電源11連接於電源電路1〇之情形，及將〇ff之電源11連接 於電源電路10後再0N之情形。此時，未利用控制電路12 對MOSFET Q1 0之閘極施加電麗，mosfet Q10為OFF。 (2) 然後’若對電源電路1〇施加輸入電壓Vcc，則經由 I56365.doc 201230638 主路徑15之電感器L1〇及二極體m〇開始電容器。◦之充 電。又，除此之外，經由旁通電路16之二極體du及及電 阻Rllitfr電容new之充電。即’經由2條路徑進行電容 器C10之充電此時，藉由相對於主路徑15之時間常數較 小地設定旁通路徑16之時間常數，使較多之電流流動於旁 通路仅16，從而經由旁通路徑16較主路徑^更急速地充電 電容器C10。 (3)如此，藉由經由旁通路徑16之電容器Ci〇之充電， 使電今HC1G之兩端電麗急速地接近電源u之輸入電壓 Vec且由於串聯連接有電感器L10及二極體d1〇之主路 粍15之兩編之電壓均大致成為輸入電壓，且與電容器 C10之兩端電壓之差變小，故來自電感器⑽及二極體⑽ ，充電變小’從而於電感器L1〇中流動之電流(磁通之變化 里）亦變小。結果，在電感器L10與電容器C10處未產生lc 共振，或僅止於極微弱者。 (4)因此，控制電路12切換控制m〇sfet 直至開始 升C動作為止’抑制電源電路1G之輸出電塵V。成為輸入電 壓Vcc以上之過電壓，並抑制在與輸入電壓同等或附近 之值’而不致於產生LC共振。 如此，本實施形態在電源11之電壓施加之初始狀態等之 暫二a應時’在電源電路丨〇中產生電感器Li〇與電容器c1〇 引起之LC共振前，利用旁通路徑16將電容器CIO先行急速 充電而壓抑成為LC原因之流向主路徑15之電流，藉此使 輸出電壓Vo不會成為電源11之輸入電壓Vcc以上之過電 156365.doc 17 201230638 壓。 再者，如上所述若在將電容器cl〇充電後，使控制電路 12及MOSFET Ql〇驅動，開始升壓動作，則電容器ci〇之 兩端電壓即輸出電壓Vo會超過電壓u之輸入電壓Vc(^該 情形下，於旁通路徑16設置二極體Du乃為了防止電流從 電容器C10向電源11逆流。 假設於旁通路徑16上未設置該二極體Du之情形，輸出 電壓Vo係經由電源11之輸入電壓Vcc與電阻RU而連接，但 若鑑於電阻R11如後所述較佳為採用必要最小限度之值， 則由於輸出電壓Vo與輸入電壓Vcc實質為大致短路之形 態，故會對升壓動作造成障礙。如此，使用二極體1作 為逆流防止元件，藉此可價廉且容易地防止經由旁通路徑 1 6之電流之逆流，並防止對升壓動作之障礙。 又，電阻R11係限制電流，以免充電電容器c丨〇時之電 流過大，使得二極體D11或電源Π損傷。再者，藉由增大 電阻Rl 1之電阻值，假設於旁通路徑16上未設置二極體 D11之情形下，雖可防止如上所述輸出電壓％與電源丨1之 輸入電壓Vcc短路，但卻背離旁通路徑16之本來之目的， 亦即使電流快速地流向電容器C10而快速地進行充電之觀 點。即，電阻R11較佳為採用可防止二極體Du或電源^損 傷之最小之電阻值。 其次，作為一例，使用P〇wer SIM公司製之模擬軟體 PSIM進行模擬，以證實如上所述之Lc共振之抑制。以下 說明之模擬為進行升壓動作前之狀態。圖2係本發明之第1 -J 8 - 156365.doc 201230638 實施形態之電源電路之第丨模擬電路圖。圖3係圖2之第^莫 擬電路圖之波形圖。 如圖2所示，進行模擬之第丨模擬電路除去了在利用電源 電路10之升壓動作開始前不必要之元件，具體而言，在利 用電源電路1 0之升壓動作開始前，M〇SFET Q 1 〇為關閉狀 嘘，故作為不必要者而予以除去。又，控制M0SFET Qi0 之控制電路12亦為不必要者故而除去。且，負载Rl 〇假設 其相Μ輕且為無負載狀態。此外，將各元件之電路常數設 為，電感器L10之電感值：22[μΗ]、電容器cl〇之靜電電 谷.100[pF]、二極體D10之順向電壓下降：〇 5[v]、電源 11之輸入電壓Vcc : 10[V]，二極體D11之順向電壓下降： 〇.5[V]，電阻R11之電阻值：〇.1[Ω]，將進行模擬之結果之 波形顯示於圖3。 圖3之上段顯示主路徑1 5之二極體d 1 〇中流動之電流11之 波形，與旁通路徑16之二極體D11中流動之電流12之波 ^ 下知顯示電源11之輸入電壓Vcc之波形、電感器li〇之 兩端電壓VI之波形，及輸出電壓ν〇(電容器C10之兩端電 壓）之波形。如圖3所示，在源自電源1 i之輸入電壓Vcc剛 施加後（時間=〇)附近經由旁通路徑16於二極體D11中流動 大量電流12 ’伴隨於此’輸出電壓乂0即電容器cl〇之兩端 電壓亦急劇增大。 此時’於電感器L10中亦流動電流’伴隨於此，在電感 器L10與電容器C10雖會產生些許Lc共振，但電感器L10之 兩端電壓止於2[V]左右之較小值《其原因如上所述，即電 156365.doc -19· 201230638 合器C1〇藉由旁通路徑16之二極體Dll及電阻R11予以急速 充電之、、表故。其結果’輸出電壓Vo止於大約11 [V]，不及 在未&置配置有二極體D11及電阻R11之旁通路徑16之先 則技術之電源電路所產生的電源丨丨之輸入電壓vcc之近2倍 之20 [ V]左右（參照圖丨丨〜丨3)。 再者’在上述之模擬電路中於二極體D丨丨中流動之電流 在時間=0附近達及8〇[A]以上，但如此之大電流之流動僅 為又電源11施加輸入電壓Vcc之瞬間。通常，二極體等之 電力元件係定義短時間（暫態）之額定值。其容許值例如通 電電流之額定值係定義為較連續之額定值為大之值。因 此，無需將該暫態之電流作為恆常流動者而選擇二極體 D11或電阻RU，只要是能夠暫態之特性上容許者即可選 定’可使用通用之零件，從而可降低成本。 或者’電容器C10之兩端電壓即輸出電壓¥〇，只要可容 许略微大之暫態電壓，則藉由增大旁通路徑i 6之電阻J 之電阻值，可抑制二極體Dll中流動之暫態之電流。 再者，在上述之第1模擬電路中，在使負載R1〇成為無負 載狀態’即在因LC共振使得輸出電壓Vo最容易上升之條 件下之電路中進行模擬，其次，進行對圖2之第丨模擬電路 連接1〇[Ω]之負載Ri〇的情形之第2模擬電路之模擬。圖斗係 本發明之第1實施形態之電源電路之第2模擬電路圖。圖5 係圖4之第2模擬電路圖之波形圖。 如圖5所不，在圖4所示之第2模擬電路中，由於輸出電 壓V〇有負載R10引起之電力消耗’故比電源U之輸入電壓 156365.doc -20- 201230638201230638 VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a boost type power supply device. [Prior Art] As a power supply device that rectifies an AC voltage generated by an AC power source into a DC voltage or a DC voltage that is input from a DC power source or the like as a DC power supply device, it is known that Boost type (or Boost Style). For example, as shown in FIG. 11, the boost type power supply circuit described in FIG. 3.1 on page 40 of Non-Patent Document 1 is exemplified by a simplified range, and the power supply circuit 50 is a low voltage generated by the power supply 51. The input voltage Vcc is boosted and supplied as an output voltage Vo to the load R50, and includes an inductor L50, a diode D50, an N-channel MOSFET Q50, a control circuit 52', and a capacitor C50. (Further, the title of Figure 3.1 of this non-patent document is "the principle circuit of the buck converter", but it is obviously a mis-plantation and should be the "principle circuit of the boost converter"). The inductor L50 has one end connected to the positive side of the power source 51. The diode D50 has its cathode connected to the other end of the inductor L50 and the anode connected to the positive side of the load R50 (the positive side of the output terminal of the output voltage Vo). The MOSFET () 50 has its drain connected to the cathode of the diode D50 and its source connected to the ground GND. Control circuit 52 is coupled to the gate of MOSFET Q50. The capacitor C50 is connected between the anode of the diode D50 and the ground GND. Moreover, the control circuit 52 controls the voltage input to the gate of the MOSFET Q50 to control the ΟΝ/OFF action of the MOSFET Q50 so that the output voltage Vo is 156365.doc 201230638 is a specific value that is more boosted than the input voltage Vcc. The MOSFET Q50 is repeatedly turned on/off. The boosting operation by the power supply circuit 50 is performed in a state where the voltage across the capacitor C50 is 0 V and the current flowing in the inductor L50 is 0 A (that is, either charge or magnetic flux) In the state in which the mode is no energy accumulation, first, in a state where the power source 51 is connected to the power supply circuit 50, the MOSFET Q50 is turned on by the control circuit 52, and the current flows from the power source 51 to the inductor L50 and the MOSFET Q50 in sequence. The electric energy of the power source 51 is stored as magnetic energy in the inductor L50. Thereafter, if the MOSFET Q50 is turned off by the control circuit 52, since the inductor L50 continues to flow in the direction immediately before the MOSFET Q50 is turned off, a voltage having a negative polarity is generated on the power source 5 1 side of the inductor L50, and A voltage having a positive polarity is generated on the side of the pole body D50. The sum of this voltage and the input voltage Vcc of the power source 51 is supplied to the capacitor C50 and the load R50 via the diode D50 as the output voltage Vo. The capacitor C50 supplies the load R50 with electric charge accumulated during the turn-on of the MOSFET Q50, that is, electric energy, and on the other hand, accumulates electric energy supplied via the diode D50 during the off period of the MOSFET Q50, and smoothes the output voltage Vo. Thus, since the output voltage Vo supplied from the power supply circuit 50 to the capacitor C50 and the load R50 is the voltage generated by the inductor L50 during the turn-off of the MOSFET Q50 plus the input voltage Vcc of the power supply 51, the power supply circuit 50 can input the input voltage. The boosted output voltage Vo of Vcc is supplied to the capacitor C50 and the load R50. However, in the power supply circuit 50 described above, a high voltage exceeding a predetermined specific value is generated as the output voltage Vo due to the phenomenon of the 156365.doc 201230638 state before the start of the boosting operation. For example, in general, before the start of the boosting operation, the MOSFET Q50 is turned off, so that the sM〇SFET Q5〇 is turned off, the power supply 51 is connected to the power supply circuit 5〇, and the power supply 5 is connected to the power supply circuit 5输入 Apply the input voltage Vcc. In this manner, when the capacitor C5 is charged to be equal to the input voltage Vcc, the current flows sequentially to the power source 51, the inductor L5, the diode, and the capacitor C50. On the other hand, if the voltage of the sum of the output voltage 乂〇 and the forward voltage drop of the diode D5 is equal to the input voltage Vcc of the power source 51, the flow of the current stops, and the output voltage Vo becomes the initial state of the input voltage Vcc of the power source 51. From this state, the boosting operation is performed by the power supply circuit 5, which is an ideal starting state of the boosting operation. However, in the packet source circuit 5A, the inductor L50 is inserted in the middle of the charging path from the power source 5 to the capacitor C5. Therefore, a sinusoidal vibration, that is, a so-called vibration, is generated in the capacitor C50 and the inductor L50, so that the conduction S needs to charge the t-tank C5 to exceed the voltage of the input voltage Vcc of the power source 51. As an example, simulation was performed using a pseudo-software psiM manufactured by P〇Wer SIM Co., Ltd. to confirm that LC resonance as described above was generated in the capacitor C5 〇 and the inductor L5 。. As shown in Fig. 12, the fourth analog circuit for simulation is simplified by removing unnecessary components before the start of the dust lifting operation of the power supply circuit 50. Specifically, before the start of the I operation by the t source circuit 5, since the MOSFET Q50 is turned off, it is removed as an unnecessary component. 156365.doc 201230638. Further, the control circuit 52 for controlling the operation of the MOSFET Q50, 〇N/〇FF, is also removed as an unnecessary component. Also, the load R5 is assumed to be fairly light and in an unloaded state. In addition, the circuit constant of each component is set to 'inductance value of inductor L50: 22 [μΗ], electrostatic battery of capacitor C50. 1〇〇〇F], and forward voltage drop of diode D50: 〇5[ ν], the input voltage of the power source 51 Vcc : 10 [ν] ' The waveform of the result of the simulation is shown in FIG. The upper part of Fig. 1 shows the waveform of the current 11 flowing in the diode D50, and the lower part shows the waveform of the output voltage Vo (the voltage across the capacitor C5〇), the waveform of the input voltage Vcc of the power supply 51, and the inductor B5. The waveform of the voltage % at both ends of the crucible. Further, the voltage of the inductor 1^50 is expressed as a positive voltage when the side of the diode D5 is positive. As shown in Fig. 13, it can be seen that the output voltage v 〇 clearly exceeds the input voltage Vcc and rises to a voltage close to the sum of the most extreme voltage value of the voltage V1 across the inductor L5 与 and the input voltage Vcc of the power source 51. The rise of the output voltage ν〇 is considered to be caused by the LC resonance of the inductor L5〇 and the capacitor c5〇, and the output voltage v〇 is maintained by the action of the one-pole body D50 at the point when the output voltage Vo rises to the highest. At the highest rise, the gate is energized c to prevent current from flowing back from capacitor C5 to the inductor. If j is such a high output voltage V〇, the load R50 cannot be lowered to the desired value until the power stored in the capacitive state C50 is consumed. Furthermore, if the inductance value of the right inductor L50 is 〇 [μΗ], the highest voltage value of the output voltage % will rise to the input voltage Vcc, but this will hinder the boosting operation. X, if the capacitance of the capacitor C50 is small, it will become a relatively high value. 156365.doc 201230638 Next, the fifth analog circuit of the diode D50 is removed from the fourth analog circuit shown in Fig. 12 as shown in Fig. 14 and simulated, and the waveform of the result of the simulation is shown in Fig. 15. Further, in the circuit shown in Fig. 14, since the diode D50 is removed, the waveform of the current 13 flowing in the inductor L5 is shown in the upper portion of Fig. 15. As shown in Fig. 15, the waveforms are observed, and 1^0 resonance is generated in a state where the diode 〇5〇 is removed. If the resonance frequency is measured, it is ^=1/(2 redundancy)=3393 [ 1^;]. And the period 1 is such that t = 295 [ps] ' substantially coincides with the period when the current or voltage shown in Fig. 13 rises. Therefore, it is understood that the instantaneous voltage at which the positive side peak is encountered when the voltage V1 across the inductor L5 is applied to the input voltage Vcc due to the LC resonance, that is, approximately 20 [v] is accumulated in the capacitor C5 〇, and becomes the output voltage. Vo. Further, the output voltage v 图 shown in Fig. 15 is slightly larger than the output voltage Vo ′ shown in Fig. 13 because the diode d50 is removed, so that the forward voltage of the diode D 5 0 is not lowered. Next, as shown in FIG. 16, the diode D50 is restored in the fifth analog circuit shown in FIG. 14 and connected to ^6^ as the sixth analog circuit of the load R5〇, and the result of the simulation is performed. The waveform is shown in Figure 17. Furthermore, since the input voltage vcc of the power source 51 is set to ι〇[ν], the load r5〇 of ι〇[ω] flows a current of 1 [Α] even when the boosting operation is not performed. Consumes 10 [W] of electricity. Therefore, the output voltage Vo should be lower than the input voltage Vcc when the LC resonance is not generated. However, as shown in the lower part of Fig. 17, the output voltage Vo exceeds the input voltage Vcc during about 〇7 [ps] due to LC resonance. Therefore, for example, if the input voltage Vcc=10[V] of the power supply 51 is set, the specific output voltage V〇=l2[v] which is required or expected by the load R50 156365.doc 201230638, even if it is equivalent to 1〇[ In the state of the load R50 of Ω], an overvoltage is applied to the load R50 during several hundred [叩] periods. In this case, if the load R5 〇 is only a resistor, the overvoltage may be tolerated. However, if the semiconductor is sensitive to an excessive voltage/current, for example, an LED (light emitting diode), There is a danger of being destroyed by this overvoltage. In addition, the capacitor C50 or the diode D50 is also exposed to the high voltage caused by the resonance of the high voltage. In the capacitor charging device described in Patent Document 1, for example, in the capacitor charging device described in Patent Document 1, the connection point between the semiconductor power source and the resonance inductor is connected between the DC power source and the resonance inductor. The ground GND is connected in the opposite direction to connect the semiconductor _ in a so-called freewheeling (or flywheel) diode. Further, the capacitor charging device predicts/operates the amount of charge of the energy storage capacitor, and controls the 〇n/〇ff operation of the semiconductor switch to suppress LC resonance. Further, the capacitor charging device has another semiconductor switch for boosting operation, and the control circuit controls the respective semiconductor switches. [PRIOR ART DOCUMENT] [Patent Document 1] [Patent Document 1] Unexamined Patent Publication No. 2003-143875 (Fig. 〇 [Non-patent literature] Okayama, "Introduction to Switching Converter Circuits", 曰刊工业新闻社, 2006 The first brush release on September 20th, the first print release, pages 39 to 49, and pages 51 to 63 [invention content] 156365.doc 201230638 [Problems to be solved by the invention] However, as described in the patent document! As shown in the capacitor charging device, if a semiconductor switch is used to suppress LC resonance, various problems occur. For example, - 'The amount of charge of the capacitor must be predicted/calculated in advance, and high-speed processing must be performed, and 耗 causes an increase in power consumption. Further, since it is necessary to control two semiconductor on/offs, it is difficult to use a general-purpose power supply 1C or the like as a circuit configuration that can be realized, and it is necessary to be, for example, a DSP (Digital Signa丨Pr〇cess〇r, digital signal processor) or an MPU ( The high-performance power supply 1C such as the Micr〇Processing Unit (micro-processing unit) leads to an increase in cost. In addition, when accumulating magnetic energy in the inductor for boosting, the semiconductor switch must be turned on every time. This accumulation causes a power loss of the voltage drop of the semiconductor switch, and the power conversion efficiency is lowered. Further, if the accuracy of the prediction/calculation of the charge amount of the capacitor is low, excessive current flows in the inductor to excessively accumulate magnetic energy. Therefore, the excessive magnetic energy is consumed unnecessarily, resulting in a decrease in power conversion efficiency. Therefore, an object of the present invention is to provide a power supply device that reduces cost and improves power conversion efficiency. [Technical means for solving the problem] • Power supply device of the present invention The boost type power supply device includes: a chopper circuit including: an inductor having one end connected to an input end of the input DC input voltage; and an output end connected to the other end of the inductor and the output DC output voltage a first backflow prevention element that is electrically connected to the output end from the other end of the inductor; and a first switching element that is connected between the upstream end of the first backflow prevention element and a reference potential; Control 156365.doc 201230638 The control circuit of the first switching element described above; a capacitor connected to the foregoing a downstream end of the first backflow preventing element and a reference potential; and a bypass circuit including the inductor connected to the thinned output terminal without passing through the inductor of the chopper circuit, and only The second backflow prevention element that is turned on in the direction of the output terminal does not include an electric device. According to the power supply device of the present invention, the capacitor is passed through the bypass circuit when a DC input voltage is applied before the start of the boosting operation. Charging, so suppressing the flow of current in the chopper circuit', it is difficult for LC inductors to be generated in the inductor and capacitor of the chopper circuit. Therefore, it is not necessary to use a high resistance to the overvoltage caused by LC resonance for the components constituting the power supply device. Pressed parts can be used with versatile and inexpensive parts to reduce costs. Again, not because of [. The overvoltage caused by resonance causes damage to the load connected to the output, which improves safety and reliability. Further, if it is assumed that the second backflow prevention element is not connected to the bypass circuit, when the switching operation of the i-th switch 7L starts, the boosting operation starts, and the DC output voltage exceeds the DC input voltage, the current is output from the bypass circuit. The end of the electric grid device flows back to the input end side, causing the input end to be short-circuited with the output end, and the left-hand action 4 becomes an obstacle. Therefore, by providing the second backflow preventing element by the bypass circuit, the backflow through the bypass circuit can be prevented, and the boosting operation can be surely performed. Thus, the electric power that causes the LC resonance to occur in the chopper circuit can be suppressed, and the electric power waste caused by the l C resonance is prevented from being taken to the output end. At this time, since the bypass circuit can be composed of inexpensive components, it can be reduced to 156365.doc 201230638. In order to make the LC resonance difficult to generate, the current path of the chopper circuit is not connected in series, for example, a resistor or the like. The current limiting element constitutes a bypass circuit that is always energized only temporarily before the start of the boosting operation. Therefore, since the power loss caused by the voltage drop of the component disposed in the bypass path is generated only during the short period of time, rather than the stranger, the power conversion efficiency caused by setting the bypass circuit can be largely ignored... Since the current flowing in the inductor before the start of the boosting operation can be minimized by the bypass circuit, the magnetic energy is not excessively accumulated in the inductor, and the excessive magnetic energy is not unnecessarily consumed. Improve power conversion efficiency. In another aspect, the power supply device of the present invention is a boost type power supply device and includes: a chopper circuit, a capacitor, and a bypass circuit, the chopper circuit including: - _ 蜢 connected to the input DC input The inductor at the input end of the voltage; connected between the other end of the inductor and the output end of the output DC output voltage' and can only be turned on from the other end of the inductor to the output end! a backflow prevention element; an error correction element connected between the upstream end of the first backflow prevention element and a reference potential; and a component clamping circuit; the tantalum capacitor is connected between the downstream end of the front side reverse current prevention element and the reference potential And the bypass includes the inductors that are not passed through the aforementioned chopper circuit, and the input terminals are connected to the output terminal and are controlled by the aforementioned control material to turn off the 7L piece and do not include the inductor. The control circuit turns off the second switching element while the first switching element is turned on and the first switching unit 70 is turned on during the switching operation without turning on the first switching element. 156365.doc 201230638 According to the power supply device of the present invention, since the DC input voltage is applied before the switching operation of the second switching element, that is, before the start of the boosting operation, the second switching element of the bypass circuit is turned on, and the capacitor is passed through the side. By charging the circuit, the current in the chopper circuit is suppressed, so that it is difficult for the inductor and the capacitor of the chopper circuit to generate Lc resonance. Therefore, it is not necessary to use a component having a high withstand voltage corresponding to the overvoltage caused by the MLC resonance for the components constituting the power source device, and it is possible to use a versatile and inexpensive component, thereby reducing the cost. Moreover, the electric shock caused by the LC resonance will not cause the load connected to the wheel end to be damaged, thereby improving the safety and reliability of the meat. Further, when the switching operation of the first switching element is performed, and the second switching element of the bypass circuit is turned on during the start of the boosting operation, when the DC output voltage exceeds the DC input voltage, the current is passed from the bypass circuit. The capacitor at the output end flows back to the input end side, causing the input end and the output end to be short-circuited, which causes an obstacle to the boosting action. In this regard, by performing the switching operation of the old off-gate element, the fourth (4) off of the bypass circuit is turned off during the start of the boosting operation, and the reverse flow through the bypass circuit can be prevented, so that the boosting operation can be surely performed. In this way, it is possible to suppress the flow of current which is caused by the resonance of the chopper circuit, and to prevent the overvoltage from being output to the output terminal due to the LC resonance. At this time, since the bypass circuit can be composed of inexpensive parts, the cost can be reduced. In addition, in order to make the LC resonance difficult to generate, the constant current path of the chopper circuit is connected in series, for example, the snow method of the resistor _, the electric limiting device, but the configuration is always only temporarily energized before the start of the boosting operation. Bypass circuit. Therefore, due to the snowfall tan, the power loss caused by the falling of the components of the bypass circuit is only generated during the temporary period of the short 156365.doc -12-201230638, rather than the constant generator. The reduction in power conversion efficiency caused by setting the bypass circuit is largely ignored. Moreover, since the current flowing in the inductor before the start of the boosting operation can be minimized by the bypass circuit, the magnetic energy is not excessively accumulated in the inductor, and the excessive magnetic energy is not unnecessarily consumed. , thereby improving power conversion efficiency. Furthermore, the second switching element is different from the diode, and is a 7-turn current flowing in both directions when turned on. Therefore, after the switching operation of the second switching element is stopped and the boosting operation is stopped, the second switching element is turned on, whereby the power of the capacitor can be returned to the input terminal via the bypass circuit, and when other loads are connected to the input terminal. , can effectively use the electrical energy returned from the capacitor. Further, the second switching element preferably includes a MOSFET which is only capable of conducting the second backflow prevention element in the direction from the input terminal to the output terminal. Thereby, since m〇SFEt is different from the bipolar transistor, the power required for driving is less. Further, since M〇sfet includes the second backflow prevention element, it is assumed that the MOSFET of the bypass circuit is not used for some reason until the DC input voltage is applied before the switching operation of the first switching element, that is, before the start of the boosting operation. Turning on is off, but since the capacitor is charged via the second backflow prevention element, the current flowing in the chopper circuit can be suppressed, making it difficult for the inductor and the capacitor of the chopper circuit to generate LC resonance. As described above, the MOSFET' including the second backflow prevention element is provided in the bypass circuit, and the power supply device for fail-safe can be constructed from the viewpoint of preventing an uncontrollable high voltage from accompanying the LC resonance. Further, the second switching element is a bipolar transistor ′ and the bypass circuit may further include a parallel connection with the second switching element, and may only be in a direction from the input end to the output end of 156365.doc 13 201230638 The second backflow prevention element that is turned on. Therefore, since the bipolar transistor and the second backflow prevention element are connected in parallel to the bypass circuit, it is assumed that even after the switching operation of the second switching element is performed, that is, when the DC input voltage is applied before the start of the boosting operation, even The bipolar transistor of the bypass circuit is turned off for some reason, but since the capacitor is charged by the second backflow preventing component, the current flowing in the chopper circuit can be suppressed, so that the inductor and the capacitor of the chopper circuit are prevented. It is difficult to generate LC resonance. In this way, by providing the bipolar transistor and the second backflow prevention element in parallel by the bypass circuit, it is possible to constitute a power supply device for fail-safe prevention from the viewpoint of preventing a high voltage that cannot be controlled due to [〇 resonance. Furthermore, it is preferable that the current limiting element is further connected in series to the bypass circuit. Thereby, it is possible to prevent the current flowing through the charging capacitor when passing through the bypass circuit from being excessively large, thereby causing damage to the power supply connected to the second backflow prevention element or the input terminal. In addition to π, the time constant of the resistance component of the bypass circuit and the month f of the capacitor is preferably the state in which the first switching element is switched by the control circuit. The time constant of the resistance component of the wave circuit and the capacitance of the capacitor (specifically, the time constant obtained by the equivalent resistance and capacitance of the inductor constituting the chopper circuit and the ith anti-flow prevention component) . Thereby, the speed of charging the capacitor by the bypass circuit is faster than that of the charging capacitor via the chopper circuit, so that LC resonance can be more difficult to occur. [Effect of the Invention] According to the present invention, it is possible to suppress the flow of the electric current which is caused by the chopper circuit, thereby preventing the overvoltage from being output to the output terminal due to the Lc resonance. At this time, since the bypass circuit can be constituted by inexpensive parts, the cost can be reduced. Further, in order to make LC resonance difficult to generate, a series current connection of, for example, a resistor or the like is limited to 70 pieces, and a bypass circuit is formed. Therefore, since the power loss caused by the voltage drop of the components provided in the bypass circuit is only temporarily generated instead of the sling, the reduction in the force conversion efficiency caused by the setting of the bypass circuit can be largely ignored. Since X' can bypass the current flowing in the inductor before the start of the boosting operation by the bypass circuit, the magnetic energy is not excessively accumulated in the inductor, and the excessive magnetic energy is not unnecessarily consumed. , thereby improving power conversion efficiency. [Embodiment] <First Embodiment> Eight persons will explain the first embodiment of the present invention. This embodiment applies the present invention to an input voltage for connecting a DC power source to a low voltage input from a DC power source. An example of a step-up switching power supply circuit that boosts and supplies a high voltage output voltage to a load. Figure i is a circuit diagram of a power supply circuit of an ith embodiment of the present invention. As shown in FIG. 1, the power supply circuit 10 (power supply device) boosts the input voltage Vcc of the low voltage generated by the power supply u, and supplies it as a high voltage output voltage to the load R10' and has the inductor L1 〇 and two diodes. The body is Di (the 70th flow prevention), the D11 (the second backflow prevention element), the N-channel type Q10 (the first switching element), the control circuit 12, the capacitor (10), and the resistor R11 (current limiting element). The inductor L10 has its end connected to the positive side of the battery. 156365.doc •15· 201230638 The cathode is connected to the other end of the inductor L1G' and the anode is connected to the positive side of the load (4) (the positive side of the output end of the output voltage Vo) e M〇SFET qi〇 its drain is connected to the second The cathode of the polar body D1 is connected to the ground gnd (reference potential). The control circuit 12 is connected to the gate of the MOSFET Q1. The capacitor 〇1〇 is connected between the anode of the diode D10 and the ground GND. The diode Du has its cathode connected to one end of the inductor L10, and the resistor RU is connected to the anode 〇1; the anode and the positive side of the load R 1 〇. Thus, the path connecting the positive side of the power supply 与 and the positive side of the load R1 包含 includes a main path 15 connecting the inductor L10 and the diode D 串联 in series, and a diode DU branched in series with respect to the main path 15 The bypass path with the resistor Rn is taken in two paths of 16. Further, the bypass path 16 of the present embodiment is in contact with the diodes Du and the resistors provided in the bypass path 16 in the bypass circuit of the present invention. Further, the control circuit 12 controls the voltage input to the gate of the M〇SFET Q1〇 and controls the 〇N/〇FF operation of the MOSFET Q10, and performs M〇SFETQ1〇 in such a manner that the output voltage v〇 becomes a specific value. Repeat the switch action of 〇~〇卯 action. The boosting operation by the power supply circuit 10 is performed as follows. (1) First, the input voltage Vcc is applied to the power supply circuit 1 from the power source u. The application of the input voltage Vec to the power supply circuit 1 includes a case where the normally open type power supply 11 is connected to the power supply circuit 1A, and a case where the power supply 11 of the 〇ff is connected to the power supply circuit 10 and then 0N. At this time, the control circuit 12 is not applied to the gate of the MOSFET Q1 0, and the mosfet Q10 is turned OFF. (2) Then, when the input voltage Vcc is applied to the power supply circuit 1〇, the capacitor is started via the inductor L1〇 and the diode m〇 of the main path 15 of I56365.doc 201230638. Charge the battery. Further, in addition to this, charging is performed via the diode di of the bypass circuit 16 and the resistor Rllitfr capacitor new. That is, the charging of the capacitor C10 is performed via two paths. At this time, by setting the time constant of the bypass path 16 with respect to the time constant of the main path 15, a large amount of current flows through the bypass path, and only 16 is passed. The bypass path 16 charges the capacitor C10 more rapidly than the main path ^. (3) In this way, by charging through the capacitor Ci of the bypass path 16, the two ends of the current HC1G are rapidly approaching the input voltage Vec of the power supply u and the inductor L10 and the diode d1 are connected in series. The voltages of the two main circuits of the main circuit 15 are roughly the input voltage, and the difference between the voltages of the two ends of the capacitor C10 becomes smaller, so that the inductor (10) and the diode (10) are charged less, and thus the inductor L1 The current flowing in the sputum (in the change of the magnetic flux) also becomes smaller. As a result, no lc resonance occurs at the inductor L10 and the capacitor C10, or only at a very weak level. (4) Therefore, the control circuit 12 switches the control m〇sfet until the start of the C operation, and suppresses the output of the electric dust V of the power supply circuit 1G. It becomes an overvoltage of the input voltage Vcc or more and suppresses the value at or near the input voltage without causing LC resonance. As described above, in the present embodiment, when the initial state of the voltage application of the power source 11 is applied, the capacitor is used in the power supply circuit 丨〇 before the LC resonance of the inductor Li 〇 and the capacitor c1 产生 is generated, and the capacitor is bypassed by the bypass path 16 . The CIO first charges rapidly and suppresses the current flowing to the main path 15 due to the LC, so that the output voltage Vo does not become the overvoltage of the input voltage Vcc of the power supply 11 156365.doc 17 201230638. Further, as described above, after the capacitor c1 is charged, the control circuit 12 and the MOSFET Q10 are driven to start the boosting operation, and the voltage across the capacitor ci〇, that is, the output voltage Vo exceeds the input voltage Vc of the voltage u. (In this case, the diode Du is provided in the bypass path 16 in order to prevent current from flowing back from the capacitor C10 to the power source 11. Assuming that the diode Du is not provided on the bypass path 16, the output voltage Vo is via The input voltage Vcc of the power supply 11 is connected to the resistor RU. However, in view of the fact that the resistor R11 is preferably a minimum necessary value as will be described later, since the output voltage Vo and the input voltage Vcc are substantially short-circuited, The boosting operation causes an obstacle. Thus, the diode 1 is used as the backflow preventing element, whereby the backflow of the current through the bypass path 16 can be prevented inexpensively and easily, and the obstacle to the boosting operation can be prevented. R11 is used to limit the current so as not to overcharge the capacitor C丨〇, so that the diode D11 or the power supply is damaged. Further, by increasing the resistance of the resistor R11, it is assumed that the bypass path 16 is not provided. In the case of the diode D11, although the output voltage % is prevented from being short-circuited with the input voltage Vcc of the power supply 如上1 as described above, the original purpose of the bypass path 16 is deviated, and even if the current flows rapidly to the capacitor C10, the current is fast. The charging R11 is preferably a resistor having a minimum resistance that prevents the diode Du or the power source from being damaged. Next, as an example, a simulation software PSIM manufactured by P〇wer SIM is used for simulation. The suppression of the Lc resonance as described above is confirmed. The simulation described below is the state before the boosting operation. Fig. 2 is a ninth analog circuit diagram of the power supply circuit of the first embodiment of the present invention. 3 is a waveform diagram of the second schematic circuit diagram of FIG. 2. As shown in FIG. 2, the analog second analog circuit removes unnecessary components before the start of the boosting operation by the power supply circuit 10, specifically, Before the start of the boosting operation of the power supply circuit 10, the M〇SFET Q 1 〇 is turned off, so it is removed as unnecessary. Further, the control circuit 12 for controlling the MOSFET Qi0 is also unnecessary. And the load Rl 〇 is assumed to be relatively light and unloaded. In addition, the circuit constant of each component is set to the inductance value of the inductor L10: 22 [μΗ], the electrostatic electricity valley of the capacitor cl〇. 100[pF], the forward voltage drop of the diode D10: 〇5[v], the input voltage Vcc of the power supply 11: 10[V], the forward voltage of the diode D11 drops: 〇.5[V], The resistance value of the resistor R11: 〇.1 [Ω], the waveform of the result of the simulation is shown in Fig. 3. The upper section of Fig. 3 shows the waveform of the current 11 flowing in the dipole d 1 主 of the main path 1 5 , and The wave of the current 12 flowing in the diode D11 of the bypass path 16 is shown to show the waveform of the input voltage Vcc of the power source 11, the waveform of the voltage VI across the inductor li, and the output voltage ν〇 (capacitor C10) The waveform of the voltage at both ends. As shown in FIG. 3, a large amount of current 12' flows in the diode D11 via the bypass path 16 immediately after the application of the input voltage Vcc from the power source 1i (time = 〇) is accompanied by the 'output voltage 乂 0 The voltage across the capacitor cl〇 also increases sharply. At this time, 'the current flows in the inductor L10' is accompanied by this, although some Lc resonance occurs in the inductor L10 and the capacitor C10, but the voltage across the inductor L10 stops at a small value of about 2 [V]. The reason is as described above, that is, the electric 156365.doc -19· 201230638 combiner C1 急 is rapidly charged by the diode D11 of the bypass path 16 and the resistor R11, and is decelerated. As a result, the output voltage Vo stops at about 11 [V], which is less than the input voltage of the power supply generated by the power supply circuit of the prior art in which the bypass path 16 of the diode D11 and the resistor R11 is disposed. Nearly 2 times the vcc is about [V] (see Figure 丨丨~丨3). Furthermore, the current flowing in the diode D丨丨 in the above analog circuit reaches 8 〇 [A] or more in the vicinity of time = 0, but the flow of such a large current is only the input voltage Vcc applied to the power source 11 again. The moment. Usually, a power component such as a diode is defined as a short-time (transient) rating. The allowable value, such as the rated value of the current, is defined as a value that is greater than the continuous rating. Therefore, it is not necessary to select the diode D11 or the resistor RU as the constant current, and it is possible to use a general-purpose component as long as it is capable of transient characteristics, thereby reducing the cost. Or 'the voltage across the capacitor C10, that is, the output voltage 〇, as long as a slightly large transient voltage can be tolerated, by increasing the resistance value of the resistance J of the bypass path i 6 , the flow in the diode D11 can be suppressed. Transient current. Further, in the first analog circuit described above, the simulation is performed in a circuit in which the load R1 〇 is in a no-load state, that is, the output voltage Vo is most likely to rise due to LC resonance, and secondly, FIG. 2 is performed. The simulation of the second analog circuit in the case where the second analog circuit is connected to the load Ri of [〇]. Fig. 2 is a second analog circuit diagram of the power supply circuit according to the first embodiment of the present invention. Figure 5 is a waveform diagram of the second analog circuit diagram of Figure 4. As shown in Fig. 5, in the second analog circuit shown in Fig. 4, since the output voltage V 〇 has the power consumption caused by the load R10', the input voltage is higher than the power source U 156365.doc -20- 201230638
Vcc超過大約^…左右，但迅速衰減收斂至輸入電壓以 下。因此，在具有負載R10之情形中’ Lc*振引起之過度 之輸出電壓V〇之供給亦被抑制為較小，旁通路徑16對電容 器C10之充電引起之LC共振之抑制效果仍大。 再者，如上所述，在第1實施形態中，就構成旁通路徑 16之70件之特性，係將從電源丨丨至電容器Ci〇之旁通路徑 16之二極體D11或電阻R11所具有之電阻成份，與以電容 器C10決定之時間常數之值，設為小於主路徑15之電感器 L10之感應常數及二極體Dl〇之導通電阻值，與以電容器 1 〇决疋之時間g數。藉此，只要以經由旁通路徑16充^ 之電容器cio之速度快於經由主路徑15充電電容器之 速度之方式設定即可。 然而，即使無法完全滿足該條件，則不依據分別經由旁 通路徑16與主路徑15之充電速度之差異，而至少經由旁通 路徑16對電容器C10進行充電，則至少LC共振引起之對電 容器C10之過剩之電壓之充電可抑制在最低限度，從而防 止負載R10之損傷等。 ^例如，假設於電路丨〇中未設置旁通路徑i 6之情形，需對 電容器C10充電最大為輸入電壓Vcc 2倍之電壓。相對於 此，若設置旁通路徑16，則即使產生Lc共振，只要其峰值 電壓止於高出輸入電壓之Vcc之數十百分點至數百分點， 則可防止防止負載R1 〇等之損傷。 再者，以本實施形態之旁通路徑16能夠有效地抑制IX 共振’其原因為於旁通路徑16上未設置電感器，自旁通路 156365.doc -21 · 201230638 徑16之充電係以所謂的CR(電容器與電阻）電路之充電，為 非振動者之緣故。利用LC共振（本來振動）之充電電流會因 電感器U0之影響使得壓之上升更為延遲。相 對於此，以旁通路徑16之充電在來自電源u之輸入電壓Vcc is more than about ^..., but the fast decay converges below the input voltage. Therefore, in the case where the load R10 is present, the supply of the excessive output voltage V? caused by the 'Lc* oscillation is also suppressed to be small, and the effect of suppressing the LC resonance caused by the charging of the capacitor C10 by the bypass path 16 is still large. Further, as described above, in the first embodiment, the characteristics of the 70 members constituting the bypass path 16 are from the power supply 丨丨 to the diode D11 of the bypass path 16 of the capacitor Ci 或 or the resistor R11. The resistance component and the time constant determined by the capacitor C10 are set to be smaller than the inductance constant of the inductor L10 of the main path 15 and the on-resistance value of the diode D1, and the time of the capacitor 1 g number. Therefore, it suffices that the speed of the capacitor cio charged via the bypass path 16 is faster than the speed of charging the capacitor via the main path 15. However, even if the condition cannot be fully satisfied, the capacitor C10 is not charged via at least the bypass path 16 according to the difference in charging speeds of the bypass path 16 and the main path 15, respectively, and at least the LC resonance causes the capacitor C10. The charging of the excess voltage can be suppressed to a minimum, thereby preventing damage to the load R10 and the like. For example, assuming that the bypass path i 6 is not provided in the circuit ,, the capacitor C10 is charged up to a voltage twice the input voltage Vcc. On the other hand, if the bypass path 16 is provided, even if the Lc resonance occurs, as long as the peak voltage thereof is tens of percentage points to several percentage points higher than the Vcc of the input voltage, it is possible to prevent the damage of the load R1 or the like from being prevented. Furthermore, the bypass path 16 of the present embodiment can effectively suppress the IX resonance. The reason is that the inductor is not provided on the bypass path 16, and the charging of the path 156365.doc -21 · 201230638 is 16 The charging of the CR (capacitor and resistor) circuit is for the non-vibrator. The charging current using LC resonance (original vibration) causes the voltage rise to be delayed due to the influence of the inductor U0. In contrast, the charging of the bypass path 16 is at the input voltage from the power supply u.
Vcc施加之際毫無延遲地開始’電容itcio未充電之 '即與 電源11之電壓差越大則充電電流越大，從而迅速將電容器 C10充電。 ° 另一方面，為產生LC共振所需之對電感器^⑺之磁能係 電感器L10之兩端電壓越大及時間越長則越大。然而，根 據本實施形態，由於預先將電容器C10充電至大致輸入電 壓Vcc為止，故電感器L丨〇之兩端電壓變小。因此，可在施 加輸入電壓Vcc後立即亦將電感器L1〇所保有之磁能抑制為 較小，從而對電容器C10之充電電壓被抑制為較低。 如此，可抑制成為產生LC共振之起因之電流於主路徑 15中流動，防止LC共振產生而對負載R1〇輸出過電壓。因 此’不會使負載R10因過電壓而損傷，從而可提高安全性 及可罪性。又，對構成電源電路丨〇之零件，無需使用對應 於伴著LC共振之過電壓之高耐壓之零件，可使用有通用 性之價廉之零件，再者，由於包含二極體D11或電阻R11 之旁通路徑16自身亦可以價廉之零件之構成，故可降低成 本〇 具體而言，例如，在有因LC共振而上升至輸出電壓 Vo=24V等之情況時，需要最低限度耐壓25V之製品，實用 上需要耐壓3 5 V以上之製品。且越是耐壓高之製品，則成 156365.doc •22· 201230638 本越增加。然而’若能防止LC共振，設輸入電壓 Vcc=i2V、輸出電壓v〇=15V，則電容器cl〇只要最低限度 耐麗16V之製品，實用上只要耐壓25v之製品即已足夠， 故可降低成本。 再者’為使LC共振難以產生，並非於主路徑丨5 _聯連 接例如電阻等之電流限制元件，而是構成旁通路徑16。因 此，由於設置於該旁通路徑16之元件之電壓下降所造成之 電力知失為暫時產生而非恆常產生者，故可大致忽略設置 旁通路徑16所引起之電力轉換效率之降低。又，由於可藉 由旁通路徑16將升壓動作開始前於電感器中流動之電流抑 制至最小限度，故不會於電感器L10中過度蓄積磁能，亦 不會無謂地消耗該過度之磁能，從而可提高電力轉換效 率。 再者，在本實施形態中，構成電源電路10之元件中，除 了配置於旁通路徑16之二極體D11與電阻R11及電容器Cl0 之外，升壓動作相關之元件，即電感器L1〇、二極體 DIO、N通道sM〇SFET Q1〇、及控制電路12相當於本發明 之斬波電路。 <第2實施形態> 其次，說明本發明之第2實施形態。再者，對具有與第工 實施形態相同之功能之構成要素省略說明，並附註相同之 符號。圖6係本發明之第2實施形態之電源電路之電路圖。 如圖6所示，在第2實施形態之電源電路20之旁通路徑％ 中，僅第1實施形態之旁通路徑16之二極體Du變成 156365.doc -23· 201230638 MOSFETQ20以外，其他構成相同。 該電源電路20之MOSFET Q20(第2開關元件）為P通道型 MOSFET，且在從圖6之旁通路徑26之左方向右方之方 向，具有源自於元件構造之本體二極體（第2逆流防止元 件）。且，MOSFET Q20其閘極連接於控制電路22，與 MOSFET Q10雖然動作時序不同，但同樣作為開關元件發 揮功能。具體而言，控制電路22在未對MOSFET Q10進行 開關動作期間，以開啟MOSFET Q20的方式進行控制’而 在對MOSFET Q10進行開關動作期間，以關閉MOSFET Q20的方式進行控制。 其次，說明配置於該旁通路徑之MOSFET Q20之周邊 電路。圖7係配置於圖6之旁通路徑之MOSFET之周邊電路 圖。如圖7所示，MOSFET Q20為P通道型，且來自控制電 路22之ΟΝ/OFF控制信號係經由電阻R21被施加於閘極，另 一方面，同一閘極係經由電阻R20而連接於電源21。電阻 R22係在自控制電路22被賦予OFF控制信號（接近電容器 C10側之電壓值之方向之信號）之情形時，用於關閉 MOSFET Q20之偏壓電阻。 該等各元件之常數在驅動控制電路22並開始升壓動作 時，相對於MOSFET Q20呈OFF狀態，且無需在升壓動作 之停止、控制電路22之重設中或之後等進行升壓動作，或 在無法進行時設定為ON狀態。電源21之電壓可為正、 負、或O(GND)之任意之值，只要滿足上述之條件，且在 不損傷MOSFET Q20之範圍内可任意選擇。電阻R20、 156365.doc •24· 201230638 R21、R22亦相同，只要包含電源21且滿足MOSFET Q20之 ΟΝ/OFF條件，且在不損傷MOSFET Q20之範圍内可任意選 擇，亦可視必要性隨意設計。 又，若相對於來自控制電路22之ΟΝ/OFF控制信號之位 準低於數[V]，電源11或升壓動作後之電容器C10之電壓成 為數十[V]以上之高電壓之情形，MOSFET Q20之閘極電壓 相對於源極電壓會變得過低，而有可能超過MOSFET Q20 之閘極與汲極或源極之耐壓，或相反的即使控制電路22欲 關閉MOSFET Q20，亦有可能因閘極之電壓未充分上升而 無法關閉。該情形，亦可於以圖7之虛線顯示之位置插入 齊納二極體D20以獲得定電壓。 如圖6及圖7所示，P通道型MOSFET Q20之源自於 MOSFET Q20構造之二極體（本體二極體）存在於從汲極向 源極之方向。藉此，假設因伴隨著控制電路22之故障而發 生動作異常，導致在從電源11施加輸入電壓Vcc之時點， 從控制電路22對MOSFET Q20傳來OFF控制信號之情形 時’與上述之第1實施形態相同，由於構成為從電源11向 電容器C10之經由本體二極體之旁通路徑26，故可防止LC 共振引起之過電壓之產生。再者，除MOSFET Q20以外， 亦可另行將二極體連接於與該本體二極體相同之方向。 此時，由於旁通路徑26中之電壓下降通常較通過 MOSFET Q20之情形為大，故在二極體或本體二極體之電 力損失略微增大。然而，由於對電容器C10之充電係瞬間 完成，故無較大之差異。如此，藉由於旁通路徑26設置包 156365.doc -25- 201230638 含本體二極體之M0SFET Q20，可構成即使在m〇sfet Q20未正常動作之情形下亦可實現之、能夠壓抑旁通路徑 26之動作即對電容器cl〇之快速充電所引起之共振之故 障防護之電源電路2 〇。 再者，若從電源11施加輸入電壓Vcc，則與第丨實施形態 相同，經由旁通路徑26對電容器C10進行充電。然而，在 該第2實施形態中，並非於旁通路徑26上設置僅於一方向When Vcc is applied without any delay, the 'capacitance itcio is not charged', that is, the larger the voltage difference from the power source 11 is, the larger the charging current is, and the capacitor C10 is quickly charged. ° On the other hand, the higher the voltage across the magnetic energy inductor L10 of the inductor (7) required to generate the LC resonance, the longer the voltage and the longer the time. However, according to the present embodiment, since the capacitor C10 is charged to the approximate input voltage Vcc in advance, the voltage across the inductor L? becomes small. Therefore, the magnetic energy held by the inductor L1 〇 can be suppressed to be small immediately after the application of the input voltage Vcc, so that the charging voltage of the capacitor C10 is suppressed to be low. In this way, it is possible to suppress the current which is the cause of the LC resonance from flowing in the main path 15, and to prevent the LC resonance from being generated and to output the overvoltage to the load R1. Therefore, the load R10 is not damaged by overvoltage, which improves safety and sin. Further, it is not necessary to use a component having a high withstand voltage corresponding to an overvoltage accompanying LC resonance for a component constituting the power supply circuit, and it is possible to use a versatile and inexpensive component, and further, because it includes the diode D11 or The bypass path 16 of the resistor R11 itself can also be configured as an inexpensive component, so that the cost can be reduced. Specifically, for example, when there is a case where the LC voltage rises to the output voltage Vo=24V, the minimum resistance is required. Products with a pressure of 25V, practically require products with a pressure of 35 V or more. The more the product with high pressure resistance, the more it becomes 156365.doc •22· 201230638. However, if LC resonance can be prevented and the input voltage Vcc=i2V and the output voltage v〇=15V, the capacitor c1 should be a product with a minimum resistance of 16V, and it is sufficient if the product with a withstand voltage of 25V is sufficient. cost. Further, in order to make the LC resonance difficult to generate, the bypass path 16 is formed instead of the main path 丨5_ in connection with a current limiting element such as a resistor. Therefore, since the power loss caused by the voltage drop of the element provided in the bypass path 16 is temporarily generated rather than constantly generated, the power conversion efficiency caused by the bypass path 16 can be largely ignored. Moreover, since the current flowing in the inductor before the start of the boosting operation can be minimized by the bypass path 16, the magnetic energy is not excessively accumulated in the inductor L10, and the excessive magnetic energy is not unnecessarily consumed. , thereby improving power conversion efficiency. Further, in the present embodiment, among the elements constituting the power supply circuit 10, in addition to the diode D11 disposed in the bypass path 16 and the resistor R11 and the capacitor C10, the element related to the boosting operation, that is, the inductor L1〇 The diode DIO, the N-channel sM〇SFET Q1〇, and the control circuit 12 correspond to the chopper circuit of the present invention. <Second Embodiment> Next, a second embodiment of the present invention will be described. In addition, the description of the components having the same functions as those of the first embodiment will be omitted, and the same reference numerals will be given. Fig. 6 is a circuit diagram of a power supply circuit according to a second embodiment of the present invention. As shown in Fig. 6, in the bypass path % of the power supply circuit 20 of the second embodiment, only the diode Du of the bypass path 16 of the first embodiment is 156365.doc -23· 201230638 MOSFETQ20, and other components the same. The MOSFET Q20 (second switching element) of the power supply circuit 20 is a P-channel MOSFET, and has a body diode derived from the element structure in the direction from the left to the right of the bypass path 26 of FIG. 2 backflow prevention component). Further, the gate of the MOSFET Q20 is connected to the control circuit 22, and the MOSFET Q10 has a different operation timing, but functions as a switching element. Specifically, the control circuit 22 performs control to turn on the MOSFET Q20 while the MOSFET Q10 is not being turned on. When the MOSFET Q10 is turned on and off, the MOSFET Q20 is turned off. Next, the peripheral circuit of the MOSFET Q20 disposed in the bypass path will be described. Figure 7 is a peripheral circuit diagram of a MOSFET disposed in the bypass path of Figure 6. As shown in FIG. 7, the MOSFET Q20 is of a P-channel type, and the ΟΝ/OFF control signal from the control circuit 22 is applied to the gate via the resistor R21, and the same gate is connected to the power source 21 via the resistor R20. . The resistor R22 is used to turn off the bias resistor of the MOSFET Q20 when the control circuit 22 is given an OFF control signal (a signal in the direction of the voltage value on the side of the capacitor C10). The constants of the respective elements are turned off with respect to the MOSFET Q20 when the drive control circuit 22 starts the boosting operation, and it is not necessary to perform the boosting operation such as the stop of the boosting operation or the resetting of the control circuit 22, or the like. Or set to ON when it is not possible. The voltage of the power source 21 can be any value of positive, negative, or O (GND) as long as the above conditions are satisfied and can be arbitrarily selected within a range that does not damage the MOSFET Q20. Resistor R20, 156365.doc •24· 201230638 R21 and R22 are the same. As long as the power supply 21 is included and the MOSFET/OFF condition of the MOSFET Q20 is satisfied, and the MOSFET Q20 is not damaged, it can be arbitrarily selected. Further, when the level of the ΟΝ/OFF control signal from the control circuit 22 is lower than the number [V], the voltage of the capacitor 11 after the power supply 11 or the boosting operation is a high voltage of several tens [V] or more. The gate voltage of MOSFET Q20 may become too low relative to the source voltage, and may exceed the withstand voltage of the gate and drain or source of MOSFET Q20, or vice versa, even if control circuit 22 wants to turn off MOSFET Q20, It may not be possible to turn off due to the gate voltage not rising sufficiently. In this case, the Zener diode D20 can also be inserted at a position shown by a broken line in Fig. 7 to obtain a constant voltage. As shown in Fig. 6 and Fig. 7, the diode of the P-channel type MOSFET Q20 originating from the MOSFET Q20 structure (body diode) exists in the direction from the drain to the source. Therefore, it is assumed that an operation abnormality occurs due to a failure of the control circuit 22, and when the input control voltage is applied from the power supply 11 to the MOSFET Q20 from the control circuit 22, the first control signal is transmitted. Similarly to the embodiment, since the bypass path 26 is formed from the power source 11 to the capacitor C10 via the body diode, the occurrence of overvoltage due to LC resonance can be prevented. Furthermore, in addition to the MOSFET Q20, the diode may be separately connected in the same direction as the body diode. At this time, since the voltage drop in the bypass path 26 is generally larger than in the case of the MOSFET Q20, the power loss in the diode or the body diode is slightly increased. However, since the charging of the capacitor C10 is instantaneously completed, there is no significant difference. In this way, by setting the 156365.doc -25-201230638 MOSFET Q20 including the body diode by the bypass path 26, it can be configured to suppress the bypass path even if the m〇sfet Q20 is not operating normally. The action of 26 is the power supply circuit 2 for the fault protection of the resonance caused by the rapid charging of the capacitor c1. Further, when the input voltage Vcc is applied from the power source 11, the capacitor C10 is charged via the bypass path 26 in the same manner as in the third embodiment. However, in the second embodiment, the bypass path 26 is not provided in only one direction.
導通電流之二極體，而是設置於雙向導通電流之MOSFET Q20，藉此較第！實施形態展現更優良之特性。具體說明如 下。 圖8係本發明之第2實施形態之電源電路之第3模擬電路 圖。圖9係圖8之第3模擬電路圖之波形圖。第3模擬電路為 與第1實施形態之第1模擬電路相同之模擬電路。各元件之 數值與上述之第1實施形態相同。再者，MOSFET Q2〇之導 通電阻係考慮為電阻R11中所含者，且MOSFET Q20之本 體一極體之順向電壓設為0.5 [V]。 ^圖9所示，無論在無負載下容易產生LC共振引起之過 電壓之條件，輸出電壓在由電源11施加輸入電壓Vcc(時 間〇)後仍大致與輸入電壓Vcc一致且過電壓極小。其原 因在於藉由旁通路徑26將電容器C10快速充電，且使過電 =產生之電能回流至電源11之緣故。即，在該第2實施形 態中，亦可進-步壓抑在暫態狀態下些微產生之LC共振所 引起之過電壓。 ' 再者，當然，在控制電路22檢測來自電源丨丨之輸入電壓 156365.doc -26- 201230638The diode of the current is turned on, but the MOSFET Q20 is set in the double-conducting current, which is better than the first! The embodiment exhibits better characteristics. The details are as follows. Fig. 8 is a third analog circuit diagram of the power supply circuit of the second embodiment of the present invention. Figure 9 is a waveform diagram of the third analog circuit diagram of Figure 8. The third analog circuit is the same analog circuit as the first analog circuit of the first embodiment. The numerical values of the respective elements are the same as those of the first embodiment described above. Furthermore, the on-resistance of the MOSFET Q2 is considered to be included in the resistor R11, and the forward voltage of the body of the MOSFET Q20 is set to 0.5 [V]. As shown in Fig. 9, the output voltage is substantially equal to the input voltage Vcc and the overvoltage is extremely small after the input voltage Vcc (time 〇) is applied from the power supply 11 regardless of the condition of the overvoltage caused by the LC resonance. The reason for this is that the capacitor C10 is quickly charged by the bypass path 26, and the over-current = generated electrical energy is returned to the power source 11. That is, in the second embodiment, it is possible to further suppress the overvoltage caused by the LC resonance which is slightly generated in the transient state. Again, of course, the control circuit 22 detects the input voltage from the power supply 156365.doc -26- 201230638
Vcc之施加而開始升壓動作前，控制電路22係以將該旁通 路徑26之M〇SFET Q20關閉，使升壓後之輸出不會與電源 11短路，且電流不會經由旁通路徑26逆流的方式進行控 制。如此，使用MOSFET Q20，MOSFET Q20之開關動作 為關閉MOSFET Q20，即可容易地防止經由旁通路徑％之 逆流。 再者，在該第2實施形態中會產生其他之優點。該優點 為可在進行升壓動作而對負載R1 〇供給電力後，使對負載 R10施加之電壓快速回流至電源i。 例如，即使負載R1 〇並非單純之電阻，而具有特定之臨 限值電壓用於如LED(發光二極體）等之發光，且若為臨限 值以下之電壓則電流幾乎不會流動者，在該第2實施形態 中，仍可將連接於負載R10之電容器cl〇之電能回流至電 源11。 因此，在於電源11連接有與負載R1〇不同之其他負載 時，可使電容器C10之電能回流至該負載，而有效地活 用。或即使在因任何要因導致在升壓動作停止時產生過電 塵’仍可通過相同之路徑回流至電源丨i。 為活用該等之優點，在無需升壓動作之時點，控制電路 22只要關閉升壓用之M〇SFET Q1 〇並使該旁通用m〇sfet Q20開啟即可。 其次，說明對前述實施形態加上各種變更之變更形熊。 惟針對具有與前述實施形態相同之構成者附註相同之符 號，適宜省略其說明。 156365.doc •27- 201230638 在第2實施形態中，雖以MOSFET Q20舉例作為配置於 旁通路徑26之開關元件，但亦可使用雙極電晶體來取代 MOSFET Q20。又，雙極電晶體只要為對應之電路構成即 可，可使用PNP型或NPN型。圖10係取代配置於圖7之旁通 路徑之MOSFET而改以電晶體構成時之電晶體之周邊電路 圖。 本變形例於旁通路徑26配置PNP型雙極電晶體Q2 1來取 代圖6及圖7所示之第2實施形態之MOSFET Q20。再者，在 從雙極電晶體Q21(第2開關元件）之集極朝向射極之方向並 聯連接有二極體D21(第2逆流防止元件）。藉此，與第2實 施形態之MOSFET Q20相同，在雙極電晶體Q21開啟時， 可在汲極與源極間於雙向流動電流，從而可獲得與第2實 施形態相同之效果。惟由於MOSFET與雙極電晶體不同， 為電壓控制，故驅動所需之電力較小，從而可降低耗電 量° 又，在上述之實施形態及變形例中，雖將從電源產生之 直流低電壓升壓，而將直流高電壓供給至負載，但輸入至 電源電路之直流電壓並不限於從電源直接產生之電壓，亦 可藉由整流電路將從交流電源產生之交流電壓整流，並將 經整流之直流電壓輸入至電源電路。 再者，在上述之實施形態及變形例中，雖於旁通路徑設 置有電流限制用之電阻R11，但只要為具有電流限制功能 之元件，則亦可為定電流二極體等任何之元件。又，該電 流限制元件在二極體Dl 1或電源11具有相對於該充電時之 156365.doc -28- 201230638 電流之容量之情形時亦可省略。 又’在上述之第2實施形態及變形例中，作為設置於旁 通路徑之開關元件，雖以MOSFET或雙極電晶體為例進行 . 說月但只要為可在未對升壓用之MOSFET Qi〇進行開關 動作期間使旁通路徑導通，而在對MOSFET Q1 〇進行開關 動作期間使旁通路徑遮斷之開關元件，則亦可為任何之元 件。 再者’在上述之第1實施形態中，雖以將主路徑15之電 感器L10與二極體dio分路的方式構成旁通路徑16，但旁 通路徑16只要構成為至少將作為LC共振之原因之主路徑15 之電感器L10分路即可。因此，例如在圖丨所示之電源電路 中’旁通路徑16之下游端並非連接於二極體Di〇之陰 極’亦可連接於電感器L10與二極體D10之陽極之連接 點。 【圖式簡單說明】 圖1係本發明之第1實施形態之電源裝置之電路圖。 圖2係本發明之第1實施形態之電源裝置之第1模擬電路 圖。 • 圖3係圖2之第1模擬電路圖之波形圖。 • 圖4係本發明之第1實施形態之電源裝置之第2模擬電路 圖。 圖5係圖4之第2模擬電路圖之波形圖。 圖6係本發明之第2實施形態之電源裝置之電路圖。 圖7係配置於圖6之旁通路徑2M〇SF]Et之周邊電路圖。 156365.doc -29- 201230638 圖8係本發明之第2實施形態之電源裝置之第3模擬電路 圖。 圖9係圖8之第3模擬電路圖之波形圖。 圖1 0係取代配置於圖7之旁通路徑之m〇sfeT，而以電 晶體構成時之電晶體之周邊電路圖。 圖11係先前例之電源電路之電路圖。 圖12係先前例之電源電路之第4模擬電路圖。 圖13係圖12之第4模擬電路圖之波形圖。 圖14係先前例之電源電路之第5模擬電路圖。 圖15係圖14之第5模擬電路圖之波形圖。 圖16係先前例之電源電路之第6模擬電路圖。 圖17係圖16之第6模擬電路圖之波形圖。 【主要元件符號說明】 10、20 電源電路 11 電源 12 控制電路 15 主路徑 16 ' 26 旁通路徑 C10 電容器 D10、Dll、D21 二極體 GND 接地 L10 電感器 Q10 、 Q20 MOSFET RIO 負載 156365.doc -30- 201230638Before the voltage boosting operation is started by the application of Vcc, the control circuit 22 turns off the M〇SFET Q20 of the bypass path 26 so that the boosted output does not short-circuit with the power source 11 and the current does not pass through the bypass path 26. Control in a countercurrent manner. Thus, by using the MOSFET Q20, the switching operation of the MOSFET Q20 is to turn off the MOSFET Q20, and the backflow through the bypass path % can be easily prevented. Furthermore, other advantages are obtained in the second embodiment. This advantage is that the voltage applied to the load R10 can be quickly reflowed to the power source i after the power supply to the load R1 〇 is supplied during the boosting operation. For example, even if the load R1 〇 is not a simple resistor, but has a specific threshold voltage for illumination such as an LED (Light Emitting Diode), and if the voltage is less than the threshold value, the current will hardly flow, In the second embodiment, the electric energy of the capacitor c1 connected to the load R10 can be returned to the power source 11. Therefore, when the power source 11 is connected to another load different from the load R1, the electric energy of the capacitor C10 can be returned to the load to be effectively utilized. Or even if excessive dust is generated when the boosting action is stopped due to any cause, it can be returned to the power source 丨i through the same path. To take advantage of these advantages, the control circuit 22 simply turns off the boosting M〇SFET Q1 〇 and turns the bypass m〇sfet Q20 on when the boosting operation is not required. Next, a modified bear in which various modifications are added to the above embodiment will be described. The same components as those of the above-described embodiments are denoted by the same reference numerals, and their descriptions are omitted as appropriate. 156365.doc • 27-201230638 In the second embodiment, the MOSFET Q20 is exemplified as a switching element disposed on the bypass path 26. However, a bipolar transistor may be used instead of the MOSFET Q20. Further, the bipolar transistor may be of a PNP type or an NPN type as long as it is a corresponding circuit configuration. Fig. 10 is a circuit diagram of a peripheral circuit of a transistor in which a MOSFET disposed in the bypass path of Fig. 7 is replaced by a transistor. In the present modification, the PNP-type bipolar transistor Q2 1 is disposed in the bypass path 26 to replace the MOSFET Q20 of the second embodiment shown in Figs. 6 and 7 . Further, a diode D21 (second backflow prevention element) is connected in parallel from the collector of the bipolar transistor Q21 (second switching element) toward the emitter. As a result, similarly to the MOSFET Q20 of the second embodiment, when the bipolar transistor Q21 is turned on, a current can be bidirectionally flowed between the drain and the source, and the same effect as in the second embodiment can be obtained. However, since the MOSFET is different from the bipolar transistor and is controlled by voltage, the power required for driving is small, and the power consumption can be reduced. Further, in the above-described embodiments and modifications, the DC generated from the power source is low. The voltage is boosted, and the DC high voltage is supplied to the load, but the DC voltage input to the power circuit is not limited to the voltage directly generated from the power source, and the AC voltage generated by the AC power source can be rectified by the rectifier circuit, and the The rectified DC voltage is input to the power supply circuit. Further, in the above-described embodiments and modifications, the current limiting resistor R11 is provided in the bypass path. However, any component such as a constant current diode may be used as long as it has a current limiting function. . Further, the current limiting element may be omitted when the diode D11 or the power source 11 has a capacity of 156365.doc -28 - 201230638 current at the time of charging. Further, in the second embodiment and the modification described above, the switching element provided in the bypass path is exemplified by a MOSFET or a bipolar transistor. However, as long as it is a MOSFET that can be used for boosting The bypass path is turned on during Qi's switching operation, and the switching element that blocks the bypass path during the switching operation of the MOSFET Q1 〇 may be any element. Further, in the first embodiment described above, the bypass path 16 is configured such that the inductor L10 of the main path 15 and the diode dio are branched, but the bypass path 16 is configured to be at least LC resonance. The cause of the main path 15 of the inductor L10 can be shunted. Therefore, for example, in the power supply circuit shown in Fig. ’, the downstream end of the bypass path 16 is not connected to the cathode of the diode Di〇, and may be connected to the junction of the inductor L10 and the anode of the diode D10. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram of a power supply device according to a first embodiment of the present invention. Fig. 2 is a first analog circuit diagram of the power supply device according to the first embodiment of the present invention. • Figure 3 is a waveform diagram of the first analog circuit diagram of Figure 2. Fig. 4 is a second analog circuit diagram of the power supply device according to the first embodiment of the present invention. Figure 5 is a waveform diagram of the second analog circuit diagram of Figure 4. Fig. 6 is a circuit diagram of a power supply device according to a second embodiment of the present invention. Fig. 7 is a peripheral circuit diagram of the bypass path 2M〇SF]Et arranged in Fig. 6. 156365.doc -29-201230638 Fig. 8 is a third analog circuit diagram of the power supply device according to the second embodiment of the present invention. Figure 9 is a waveform diagram of the third analog circuit diagram of Figure 8. Fig. 10 is a circuit diagram of a peripheral circuit of a transistor in which a m配置sfeT disposed in the bypass path of Fig. 7 is replaced by a transistor. Figure 11 is a circuit diagram of a power supply circuit of the prior art. Fig. 12 is a fourth analog circuit diagram of the power supply circuit of the prior art. Figure 13 is a waveform diagram of the fourth analog circuit diagram of Figure 12. Fig. 14 is a fifth analog circuit diagram of the power supply circuit of the prior art. Figure 15 is a waveform diagram of the fifth analog circuit diagram of Figure 14. Fig. 16 is a sixth analog circuit diagram of the power supply circuit of the prior art. Figure 17 is a waveform diagram of the sixth analog circuit diagram of Figure 16. [Main component symbol description] 10, 20 Power circuit 11 Power supply 12 Control circuit 15 Main path 16 ' 26 Bypass path C10 Capacitor D10, Dll, D21 Diode GND Ground L10 Inductor Q10, Q20 MOSFET RIO Load 156365.doc - 30- 201230638
Rll 電阻 Vcc 輸入電壓 Vo 輸出電壓 156365.doc •31 ·Rll resistance Vcc input voltage Vo output voltage 156365.doc •31 ·