201227703 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種驅動方法及其裝置，且特別是有 關於一種閘極驅動方法及其裝置。 【先前技術】 液晶顯示器（Liquid Crystal Display，LCD )具有外型 輕薄、耗電量少以及無輻射污染等特性，已被廣泛地應用 在各式電腦系統、行動電話、個人數位助理（PDA)等資 訊產品上。液晶顯示器的工作原理係利用液晶分子在不同 排列狀態下，對光線具有不同的偏振或折射效果，因此可 經由不同排列狀態的液晶分子來控制光線的穿透量，進一 步產生不同強度的輸出光線，及不同灰階強度的紅、綠、 藍光。 請參考圖1’圖1為先前技術一薄膜電晶體（ThinFilm Transistor ’ TFT)液晶顯示器1〇之示意圖。液晶顯示器 10包含一液晶顯示面板（LCD Panel) 100、一源極驅動器 102、一閘極驅動器1〇4以及一電壓產生器1〇6。液晶顯示 面板100係由兩基板（Substrate)構成，而於兩基板間填 充有液晶材料（LCD layer)。一基板上設置有複數條資料 線（Data Line) 108、複數條垂直於資料線1〇8的掃描線 (Scan Line ’或稱閘線，Gate Line) 110以及複數個薄膜 電晶體112,而於另一基板上設置有一共用電極（c〇mm〇n Electrode )用來經由電壓產生器106提供一共用訊號 4 201227703201227703 VI. Description of the Invention: [Technical Field] The present invention relates to a driving method and apparatus therefor, and more particularly to a gate driving method and apparatus therefor. [Prior Art] Liquid crystal display (LCD) has characteristics such as thinness, low power consumption and no radiation pollution, and has been widely used in various computer systems, mobile phones, personal digital assistants (PDAs), etc. Information products. The working principle of the liquid crystal display is that the liquid crystal molecules have different polarization or refraction effects on the light in different arrangement states, so that the liquid crystal molecules of different alignment states can be used to control the amount of light penetration, and further generate output light of different intensity. And red, green, and blue light of different gray levels. Please refer to FIG. 1'. FIG. 1 is a schematic diagram of a prior art thin film transistor (Thin Film Transistor 'TFT) liquid crystal display. The liquid crystal display 10 includes a liquid crystal display panel (LCD panel) 100, a source driver 102, a gate driver 1〇4, and a voltage generator 1〇6. The liquid crystal display panel 100 is composed of two substrates, and a liquid crystal material (LCD layer) is filled between the substrates. A substrate is provided with a plurality of data lines 108, a plurality of scanning lines (Scan Line ' or Gate Lines) 110 perpendicular to the data lines 1 and 8 and a plurality of thin film transistors 112, and A common electrode (c〇mm〇n Electrode) is disposed on the other substrate for providing a common signal through the voltage generator 106. 201227703
Vcom。薄膜電晶體112係以矩陣的方式分佈於液晶顯示面 板100上’每一資料線108對應於液晶顯示面板100上之 一行（Column)，而掃描線ι1〇對應於液晶顯示面板1〇〇 上之一列（Row)’且每一薄膜電晶體112係對應於一晝素 (Pixel)。此外，液晶顯示面板1〇〇之兩基板所構成的電 路特性可視為一等效電容114。 在圖1中，閘極驅動器104依序產生閘極驅動訊號 VG—1〜VGJV[，以逐列開啟薄膜電晶體112，進而更新等 效電容114中儲存之晝素資料。詳細來說，請參考圖2， 圖2為閘極驅動器104之示意圖。閘極驅動器1〇4包含有 一邏輯電路105及緩衝器i〇7_i〜i〇7JV[。負載模組1〇9 1 二109—Μ為各負載之等效電路。邏輯電路1〇5透過控制緩 衝器107—1〜107—Μ中電晶體之開關，輪流接通負載模組 1 〇9_1〜109—Μ至一高電壓VGG及一低電壓VEE，作為問 極驅動訊號VG一 1〜VG__M中的方波。 然而，由於等效電容114與薄膜電晶體112之閘極間 存在寄生電容，當閘極驅動訊號VGj〜VG—M中的方波 位於後緣時’閘極驅動訊號VG—1〜VG—M之電壓變化透 過寄生電谷耦合至專效電谷114 ’使得等效電容η*儲存 偏差的影像内容。為了改善後緣之耦合效應，閘極驅動器 104可透過波形重整’調整閘極驅動訊號vG—丨〜¥(} Μ中 方波的波形，如圖3所示。在圖3中，閘極驅動訊號—VGj 〜VG—Μ中方波之後緣被調變，以避免閘極驅動訊號 〜VG_M之急遽變化影響儲存的晝素内容。當然，欲產i 201227703 圖3之s周變波形’閘極驅動芎 另一方面，旧夕二 額外的控制電路。 另万面圖1之閘極驅動器1〇4 關液晶顯示器1〇上晝素的充電路徑。然而，在 來^有的不需正t極驅動器1〇4有可能會導致液晶顯示 器10有不正爷之晝面產生。因此’為了避免此一現象，許 多的=計因應而生。最常見者為利用系統電路動態地控制 與調整閘極驅動器刚輸出。然而，此作法會導致系統有 許多的耗電，再者額外的電路㈣統成本來制此目標也 是不可避免的。 因此，如何以經濟省電的方法重整閘極驅動訊號的波 形’已成為業界的努力目標之一。 【發明内容】 本發明提供一種閘極驅動器及閘極驅動方法，可以經 濟省電的方法重整閘極驅動訊號的波形。 本發明提供一種閘極驅動器，適於控制一顯示器。閘 極驅動器包括一邏輯電路、多個緩衝器以及一電荷分享模 組。邏輯電路產生多個開關訊號。緩衝器耦接於邏輯電路。 每一緩衝器包括一第一端搞接於邏輯電路，一第二端躺接 於一第一電壓源，一第三端耦接於一第二電壓源，以及一 輸出端耦接於一負載模組。每一緩衝器根據開關訊號中之 一開關訊號’決定供應一第一電麗或一第二電壓，以產生 一閘極驅動訊號。電荷分享模組耦接於缓衝器之輸出端， 並根據多個分享訊號，於每一閘極驅動訊號之一方波之一 6 201227703 别緣及一後緣，使緩衝器之輸出端彼此分享電荷。 ，本發明之一實施例中，上述之閘極驅動器更包括一 ，關模組。開關模組耗接於緩衝器與第一電壓源及第二電 壓源，間。開_組_至少—斷電訊號，於每—閘極驅 號之方波之&緣及後緣，t刀斷第__電麈電源及第二電 壓電源至緩衝器的電連接。 在本發明之—實施例中，上述之開關模組於每一閘極 驅動訊號之方波之前緣及後緣，根據至少—斷電訊號斷 路H _轉訊鶴應之分享訊號指示電荷分享模 連接閘極驅動訊號對應之緩衝器，使緩衝器之輸出端 彼此分旱電荷。 門μ在ί發明之—實施例中，上述之開關模組包括一第一 :抱姑—開關輕接於緩衝器及第—電壓源之間。第一開 第一斷電訊號’於每一閘極驅動訊號之方波之前 緣及後緣’靖第—電壓源至緩衝H之電連接。 Η Μ在ί發明之—實施例中，上述之開關模組包括一第二 播[開_接於緩衝器及第二電壓源之間。第二開 =:第二斷電訊號，於每一閉極驅動訊號之方波之前 、，後緣刀斷第二電壓源至緩衝器之電連接。 在本發明之—實施例中，上述之每一 及—N型場效應電晶體。p型場效應電 一、 θ極耦接於第一端，一源極耦接於第二端，及 決出端。p型場效應電晶體根據開關訊號， 至名—電壓源之電連接。Ν型場效應電晶體包 201227703 括一閘極耦接於第一端，一源極耦接於第三端，B 一、、 耦接於輸出端。N型場效應電晶體根據開關訊號，決— 出端至第二電壓源之電連接。 'z、疋輸 在本發明之-實施例中’上述之電荷分享模組包 個第三開關以及多個第四開關。第三接於對 衝器之輸出端之間。第三開關根據1-分享訊號嗜問 極驅動訊號之方波之前緣及後緣’依序電性連接緩衝器; 的多個對應的缓衝器。第四開關耦接於對應的緩衝<器: 出端之間。第四開關根據一第二分享訊號，於閘極 = 號之方波之前緣及後緣，依序電性連接緩衝器中的多& 應的緩衝器。 在本發明之-實施例中，當第三開關根據第_分享$ 號電性連接對應第三開關的緩衝器時，第四開關根據第二 分享訊號，切斷對應第四開關的緩衝器之電連接。合第: 開關根據第二分享訊號電性連接對應第四開關的^衝= 時’第三開關根據第-分享訊號’ W斷對應第三開關的緩 衝器之電連接。 在本發明之-實施例中’上述之第三開關及第四開斯 分別根㈣-分享訊號及第二分享訊號，交錯地電性連海 對應第二開關的緩衝器及對應第四開關的緩衝P。 在本發明之—實施射，上述之邏輯電^產生 一斷電訊號及分享訊號。 本發明提供—種閘極驅動方法，適於控制—顯示器 閘極驅動方法包括如下步驟。提供一第一電壓及一第二 8 201227703 壓至多個缓衝器。根據多個開關訊號，決定緩衝器輸出一 第一電壓或一第二電壓，以產生多個閘極驅動訊號。根據 多個分旱訊號，於母一閘極驅動訊號之—方波之一前緣及 一後緣，使緩衝器之輸出端彼此分享電荷。 在本發明之一實施例中，上述之閘極驅動方法更包括 如下步驟。根據至少一斷電訊號，於每一閘極驅動訊號之 方波之前緣及後緣，切斷第一電壓及第二電壓至緩衝器的 電連接。 在本發明之一實施例中，上述之切斷第一電壓及第二 電壓至緩衝器的電連接的步驟包括如下步驟。根據一第一 斷電訊號，於每一閘極驅動訊號之方波之前緣及後緣，切 斷第一電壓至緩衝器之電連接。 在本發明之一貫施例中，上述之切斷第一電壓及第二 電壓至緩衝器的電連接的步驟包括如下步驟。根據一第二 斷電訊號，於每一閘極驅動訊號之方波之前緣及後緣，切 斷第二電壓至緩衝器之電連接。 在本發明之一實施例中，上述之使緩衝器之輸出端彼 此分享電荷的步驟包括如下步驟。根據一第一分享訊號， 於閘極驅動訊號之方波之前緣及後緣’依序電性連接緩衝 器中的多個對應的緩衝器。根據一第二分享訊號，於閘極 驅動訊號之方波之前緣及後緣，依序電性連接緩衝器中的 多個對應的緩衝器。 在本發明之一實施例中，當根據第一分享訊號電性連 接對應第一分享訊號的緩衝器時，根據第二分享訊號，切 201227703 斷對應第二分享訊號的緩衝器之電連接。當根據第二分古 ，號電性連接對應第二分享訊號的緩衝器時，根據 旱訊號，切斷對應第一分享訊號的緩衝器之電連接。刀 ，本發明之一實施例中，上述之使緩衝器之輪出端彼 此分享電荷的步驟更包括如下轉。分職據第―分享訊 虎，交錯地電性連接對應第-分享:號的 緩衝益及對應第二分享訊號的緩衝器。 如下ίί發ΓίΓ實施例巾，上述之閘極轉方法更包括 士下步驟。產生至少—斷電訊號及分享訊號。 基於上述，在本發明之範例實施例中，顯示器利用上 述之閘極_方法能㈣與輕鶴_ ^统，夕卜電路的成本，也能分時控制各個閘極驅動器的輸 出’大為降低系統的耗電。 為讓本發明之上述特徵和優點能更鶴錄，下 舉貫施例’並配合所_式作詳細說明如下。 · 【實施方式】 =參考圖4，圖4為本發明實施例 4〇 y a isp ay LCD)中晝素的更新時序 中以矩陣方式排列之薄膜電曰俨丌P控制圖1 TFT) ΤΛ5 ’i〜4l2Ft_ρ2包含有—邏輯電路 收模組430。邏輯電路4〇 ^生，420及一電荷回 υυ用來產生開關訊號SW1〜 201227703 SWM、一斷電訊號BK及分享訊號SS1〜SSM。緩衝器 412_1~412一Μ用來根據開關訊號§wi〜SWM，決定輸出 一第一電壓VI或一第二電壓V2，以產生閘極驅動訊號 VG_1〜VG_M，閘極驅動訊號VG_1〜VG-M分別用來掃 描一列（row)的薄膜電晶體。開關模組42〇用來根據斷 電訊號BK，切斷輸出第一電壓V1至負載模組416j〜 416—M之供電路徑。負載模組M係各負载之 等效電路。最後，電荷回收模組430根據分享訊號SS1〜 SSM ’與負載模組416—1〜416_M分享電荷，以調整閘極 驅動訊號VG_1〜VG_M的波形。須注意的是，有鑑於閘 極驅動_减VG_1〜VG—M細讀的型式指定薄膜電晶 體112的開啟時序’開關模組42〇特別於方波之前緣及後 緣斷路，同時，電荷回收模組430連接至正接收方波之一 負載杈組=6一X’使得電荷回收模組43〇與負載模組 獨立地分旱儲存之電荷，以調整閘極驅動訊號vg」〜 VG_M於前、後緣之波形。 一 簡單來σ兒為了調變閘極驅動訊號VG—1〜VG—M的 波形H極轉g 4Q新增電荷时模組·，其用來調節 負載模組训」〜4〗6—%中儲存之電荷。於閘極驅動訊號 VG_1 VG_M中方波之前緣與後緣，電荷回收模組柳 與負賴組416—1〜416—M分享儲存之電荷，以透過「回 收」及「重複利用」貞載模、组416—卜仙―M +之電荷， 減少產生閘極驅動訊號VG—〗〜VG_M中方波所需的電 能。由於電何分享係—漸進過程，閘極驅動訊號⑽—卜 11 201227703 VG_M中方波之前緣及後緣呈和緩變化狀，因此可達到降 低躺合現象的目的。相較於先前技術在產生方波的過程 中，外接的電壓源須對負載模組416_1〜416JVI反覆地執 行充電和放電操作，造成電能浪費’電荷回收模組430「回 收」閘極驅動訊號VG_1〜VGJV[為第一電壓vi時之電 荷，以達到調變之目的，並於產生下一個方波時，「重複利 用」該電4 ’將閘極驅動訊號VG—1〜VG Μ預充至一第 一預設電壓，以降低閘極驅動器40之功率消耗。 詳細來說’電荷回收模組430包含有一調節電容Cr 及開關432—1〜432_M。開關432一1〜432_M用來根據分享 訊號SS1〜SSM’決定調節電容Cr是否與負載模組416工 〜416—Μ分享電荷。調節電容Cr之―端減於一參考] 壓源，電路設計者可透過選擇參考電壓源提供之一參 壓VREF值，控制從負載模組41〇〜416 μ^ 「重複·」之電荷# ’進錢定第1設電壓及調㈣Vcom. The thin film transistors 112 are distributed on the liquid crystal display panel 100 in a matrix manner. 'Each data line 108 corresponds to one column on the liquid crystal display panel 100, and the scan line ι1 〇 corresponds to the liquid crystal display panel 1 One column (Row) and each of the thin film transistors 112 corresponds to a single pixel (Pixel). Further, the circuit characteristics of the two substrates of the liquid crystal display panel 1 can be regarded as an equivalent capacitor 114. In FIG. 1, the gate driver 104 sequentially generates the gate driving signals VG-1 to VGJV [to open the thin film transistor 112 column by column, thereby updating the pixel data stored in the equivalent capacitor 114. In detail, please refer to FIG. 2, which is a schematic diagram of the gate driver 104. The gate driver 1〇4 includes a logic circuit 105 and buffers i〇7_i to i〇7JV[. The load module 1〇9 1 2 109—Μ is the equivalent circuit of each load. The logic circuit 1〇5 turns on the load modules 1 〇9_1~109_Μ to a high voltage VGG and a low voltage VEE through the control buffers 107-1~107-the switch of the transistor in the middle, as a question mark drive The square wave in the signal VG-1~VG__M. However, since there is a parasitic capacitance between the equivalent capacitor 114 and the gate of the thin film transistor 112, when the square wave in the gate driving signals VGj to VG-M is located at the trailing edge, the gate driving signals VG-1 to VG-M The voltage change is coupled to the dedicated electric valley 114' through the parasitic electric valley so that the equivalent capacitance η* stores the deviation of the image content. In order to improve the coupling effect of the trailing edge, the gate driver 104 can adjust the waveform of the square wave in the gate drive signal vG_丨~¥(} 透过 through the waveform reforming, as shown in FIG. 3. In FIG. 3, the gate Drive signal - VGj ~ VG - 之后 Μ 方 方 被 被 , , , , , , 以避免 以避免 以避免 以避免 以避免 〜 VG VG VG VG VG VG VG VG VG VG VG VG VG VG VG VG VG VG VG VG VG VG VG VG VG VG VG VG VG VG VG VG VG VG VG The pole drive is on the other hand, the second control circuit of the old eve. In addition, the gate driver of Fig. 1 is 1〇4, and the charging path of the liquid crystal display 1 is on the top. However, there is no need for positive The pole driver 1〇4 may cause the LCD panel 10 to be unfair. Therefore, in order to avoid this phenomenon, many of the counts are generated. The most common one is to dynamically control and adjust the gate using the system circuit. The driver just outputs. However, this method will cause the system to have a lot of power consumption, and it is inevitable that the additional circuit (4) system cost to achieve this goal. Therefore, how to reconfigure the gate drive signal by economical power saving method Waveform 'has become SUMMARY OF THE INVENTION The present invention provides a gate driver and a gate driving method for reforming a waveform of a gate driving signal in an economical and power-saving manner. The present invention provides a gate driver suitable for control A display device includes a logic circuit, a plurality of buffers, and a charge sharing module. The logic circuit generates a plurality of switching signals. The buffer is coupled to the logic circuit. Each of the buffers includes a first end a logic circuit, a second end is connected to a first voltage source, a third end is coupled to a second voltage source, and an output end is coupled to a load module. Each buffer is based on the switching signal A switching signal 'determines to supply a first voltage or a second voltage to generate a gate driving signal. The charge sharing module is coupled to the output of the buffer, and according to the plurality of sharing signals, at each gate One of the square wave signals 6 201227703 has a margin and a trailing edge, so that the output ends of the buffer share electric charge with each other. In an embodiment of the invention, the gate driver further includes First, the module is closed. The switch module is connected between the buffer and the first voltage source and the second voltage source, and the open_group_at least-power-off signal is applied to the square wave of each gate drive. The edge and the trailing edge, t-cut the electrical connection between the first power source and the second voltage source to the buffer. In the embodiment of the invention, the above-mentioned switch module is square wave of each gate driving signal The leading edge and the trailing edge, according to at least the power-off signal breaking H _ relaying crane should share the signal indicating that the charge sharing mode is connected to the buffer corresponding to the gate driving signal, so that the output ends of the buffer are separated from each other by the dry charge. In an embodiment, the switch module includes a first: a gu-switch is lightly connected between the buffer and the first voltage source. The first open first power-off signal is driven at each gate The front and back edges of the square wave of the signal 'Jingdi—the voltage source to the electrical connection of the buffer H. In the embodiment of the invention, the switch module includes a second broadcast [open_connected between the buffer and the second voltage source. The second open =: the second power-off signal, before the square wave of each of the closed-circuit driving signals, the trailing edge cuts the electrical connection of the second voltage source to the buffer. In the embodiment of the present invention, each of the above-mentioned -N type field effect transistors. The p-type field effect power is 1. The θ pole is coupled to the first end, the source is coupled to the second end, and the output end. The p-type field effect transistor is connected to the name-voltage source according to the switching signal. The 场-type field effect transistor package 201227703 includes a gate coupled to the first end, a source coupled to the third end, and a first coupling coupled to the output end. The N-type field effect transistor is connected to the electrical connection of the second voltage source according to the switching signal. 'z, 疋 在 In the embodiment of the invention', the charge sharing module described above includes a third switch and a plurality of fourth switches. The third is connected between the outputs of the buffer. The third switch electrically connects the buffers to the plurality of corresponding buffers according to the first wave and the trailing edge of the square wave of the 1-shared signal. The fourth switch is coupled between the corresponding buffer < The fourth switch electrically connects the multiple & buffers in the buffer according to a second shared signal at the leading edge and the trailing edge of the square wave of the gate = number. In the embodiment of the present invention, when the third switch is electrically connected to the buffer corresponding to the third switch according to the _share $, the fourth switch cuts off the buffer corresponding to the fourth switch according to the second shared signal. Electrical connection. In combination, the switch electrically connects the corresponding switch of the fourth switch according to the second share signal. The third switch disconnects the electrical connection of the buffer corresponding to the third switch according to the first share signal. In the embodiment of the present invention, the third switch and the fourth singular root (four)-shared signal and the second shared signal are interleaved electrically connected to the buffer of the second switch and the corresponding fourth switch. Buffer P. In the present invention, the above-mentioned logic generates a power-off signal and a shared signal. The present invention provides a gate driving method suitable for a control-display gate driving method comprising the following steps. A first voltage is applied and a second 8 201227703 is applied to the plurality of buffers. Based on the plurality of switching signals, the buffer outputs a first voltage or a second voltage to generate a plurality of gate driving signals. According to the plurality of drought signals, one of the front and the trailing edge of the square wave of the driving signal of the mother causes the output terminals of the buffer to share the electric charge with each other. In an embodiment of the invention, the gate driving method further includes the following steps. And electrically disconnecting the first voltage and the second voltage to the buffer according to the at least one power-off signal at the leading edge and the trailing edge of the square wave of each gate driving signal. In an embodiment of the invention, the step of cutting off the electrical connection of the first voltage and the second voltage to the buffer comprises the following steps. According to a first power-off signal, the electrical connection of the first voltage to the buffer is cut off at the leading and trailing edges of the square wave of each gate driving signal. In a consistent embodiment of the invention, the step of cutting off the electrical connection of the first voltage and the second voltage to the buffer comprises the following steps. According to a second power-off signal, the electrical connection of the second voltage to the buffer is cut off at the leading and trailing edges of the square wave of each gate drive signal. In one embodiment of the invention, the step of causing the outputs of the buffers to share charge with each other includes the following steps. According to a first shared signal, a plurality of corresponding buffers in the buffer are electrically connected to the front and rear edges of the square wave of the gate driving signal. According to a second shared signal, a plurality of corresponding buffers in the buffer are electrically connected to the front edge and the trailing edge of the square wave of the gate driving signal. In an embodiment of the present invention, when the buffer corresponding to the first shared signal is electrically connected according to the first shared signal, according to the second shared signal, the electrical connection of the buffer corresponding to the second shared signal is cut off. When the buffer corresponding to the second shared signal is electrically connected according to the second division, the electrical connection of the buffer corresponding to the first shared signal is cut off according to the dry signal. Knife, in an embodiment of the present invention, the step of causing the rounds of the buffer to share the charge with each other further includes the following. According to the first-shared newsletter, the inter-connected electrical connection corresponds to the buffer of the first-shared number and the buffer corresponding to the second shared signal. As described in the following example, the above-described gate turning method further includes the steps below. Generate at least - power off signals and share signals. Based on the above, in an exemplary embodiment of the present invention, the display utilizes the above-described gate _ method can (4) and the light crane _ ^ system, the cost of the circuit, can also control the output of each gate driver to be greatly reduced The power consumption of the system. In order to make the above-mentioned features and advantages of the present invention more versatile, the following embodiments will be described in detail as follows. [Embodiment] = Referring to FIG. 4, FIG. 4 is a thin film electronic 曰俨丌 P control arranged in a matrix manner in the update timing of 昼 is is is is is 为本 为本 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ~4l2Ft_ρ2 includes a logic circuit receiving module 430. The logic circuit 4, 420 and a charge return are used to generate the switching signals SW1~201227703 SWM, a power down signal BK and the sharing signals SS1~SSM. The buffers 412_1~412 are used to determine whether to output a first voltage VI or a second voltage V2 according to the switching signals §wi~SWM to generate the gate driving signals VG_1~VG_M, and the gate driving signals VG_1~VG-M They are used to scan a row of thin film transistors, respectively. The switch module 42 is configured to cut off the power supply path for outputting the first voltage V1 to the load modules 416j to 416-M according to the power-off signal BK. The load module M is the equivalent circuit of each load. Finally, the charge recovery module 430 shares the charge with the load modules 416-1 to 416_M according to the shared signals SS1 S SSM ' to adjust the waveforms of the gate drive signals VG_1 VG VG_M. It should be noted that, in view of the gate drive_decrease VG_1~VG-M fine read type, the opening timing of the thin film transistor 112 is specified. The switch module 42 is particularly open to the front and rear edges of the square wave, and at the same time, charge recovery. The module 430 is connected to one of the positive receiving waves, the load group=6-X', so that the charge recovery module 43〇 and the load module independently divide the stored charge to adjust the gate driving signal vg”~ VG_M before The waveform of the trailing edge. A simple sigma to adjust the gate drive signal VG-1~ VG-M waveform H pole turn g 4Q new charge when the module, which is used to adjust the load module training" ~ 4〗 6-% The stored charge. In the front and rear edges of the square wave drive signal VG_1 VG_M, the charge recovery module will share the stored charge with the negative recovery group 416-1~416-M to pass the "recycling" and "reuse" load mode. , group 416 - Buxian - M + charge, reduce the electric energy required to generate the square wave of the gate drive signal VG - 〗 ~ VG_M. Due to the electrical sharing system—progressive process, the gate drive signal (10)—b 11 201227703 VG_M has a gentle change in the front and rear edges of the square wave, so the purpose of reducing the lying phenomenon can be achieved. Compared with the prior art, in the process of generating a square wave, the external voltage source must perform charging and discharging operations on the load modules 416_1~416JVI repeatedly, resulting in waste of power. 'Charge recovery module 430 "Recycling" gate drive signal VG_1 ~VGJV[ is the charge at the first voltage vi for the purpose of modulation, and when the next square wave is generated, "reuse" the electric 4' to precharge the gate drive signals VG-1~VG Μ to A first predetermined voltage is used to reduce the power consumption of the gate driver 40. In detail, the charge recovery module 430 includes an adjustment capacitor Cr and switches 432-1 to 432_M. The switches 432-1 to 432_M are used to determine whether the adjustment capacitor Cr shares the charge with the load module 416 according to the shared signals SS1 to SSM'. Adjusting the capacitance of the capacitor Cr to a reference voltage source, the circuit designer can provide a reference voltage VREF value by selecting a reference voltage source to control the charge from the load module 41〇4161^“repeating·" Qian Ding first set voltage and adjustment (four)
度。緩衝器412」〜412-Μ包含有Ρ型場效應電晶, (field-effect transistor，FET) QP1^QpM ^ N 電晶體QN1〜QNM，用來根據對應㈣關訊號 SW一Μ，決定供應第-電壓V1或第二電壓v2至負載勸 416一1〜416—M。負載模組416—卜％ 含、 電阻R1〜RMf^電容ci,，___/= ;;12γ二Γ切VG^l作,存或輸出電荷，以產生閘極《 訊唬VG一1〜VG—M。另外，為眚 ^ 细420齡㈣句a古一曰曰為現電何分旱操作，開_ 有一開關422，開關422根據斷電訊受 12 201227703 BK，於閘極驅動訊號VGj〜VG_M中方波之前緣及後 緣，切斷第一電壓VI之供電路徑，使得負載電容C1〜CM 與調節電容Cr獨立地分享儲存之電荷。 舉例來說，請參考圖5，圖5為開關訊號SW_1〜 SW_M、斷電訊號BK、分享訊號SS1〜SSM及閘極驅動 訊號VG_1〜VG_3之時序圖。在圖5中，以閘極驅動訊號 VG_1的產生過程為例，於閘極驅動訊號VG_i中方波之 前緣（時間點tl、t2之間），斷電訊號BK指示開關422 切斷第一電壓VI之供電路徑；開關訊號SW_1〜8”_]^1指 示緩衝器412_1〜412_M切斷負載模組416_1〜416__M間 之電連接；分享訊號SS1指示開關432J導通調節電容 Cr及負載電容(^，使得調節電容Cr中儲存之電荷輸出至 負載電容C1，以將閘極驅動訊號VG_1預充至準致能位 準。於閘極驅動訊號VG_1中方波的中段（時間點t2、t3 之間），斷電訊號BK指示開關422恢復輸出第一電壓VI 至負載模組416_1 ;開關訊號SW_1指示缓衝器412_1〜 412_M傳遞第一電壓VI ;分享訊號SS1指示開關432_1 隔離調節電容Cr及負載電容C1，以致能閘極驅動訊號 VG_1。最後，於閘極驅動訊號VG_1中方波之後緣（時間 點t3、t4之間），斷電訊號BK再度指示開關422切斷第一 電壓VI之供電路徑；開關訊號SW_1〜SW_M指示緩衝 器412j〜412_M切斷負載模組416_1〜416_M間之電連 接；分享訊號SS1指示開關432_1導通調節電容Cr及負 載電容C1，使得負載電容C1中儲存之電荷回收至調節電 13 201227703 容Cr’作為產生下一個閘極驅動訊號（VG_2)之方波時， 預充負載電容C1之儲備電荷。閘極驅動訊號vg_2〜 VG-M產生過程之操作與閘極驅動訊號VG_1相同，在此 不贅述。因此，透過於閘極驅動訊號VG—1〜VG—M前緣 及後緣之電荷分享操作’閘極驅動器4〇可回收並重複利用 驅動所需之電荷，以用經濟、省電的方法實現波形調整。 須注意的是，調節電容Cr於閘極驅動訊號VG_l〜 VG_M之前緣與負載電容C1〜CM分享電荷後，仍存有部 份電荷，導致調節電容〇於下次r回收」負載電容C1〜 CM電荷時之效率降低，進而影響調變之幅度。為了確保 閘極驅動訊號VG一1〜VGJV[調變之幅度一致，請參考圖 6 ’圖6為電荷回收模組430之變化實施例一電荷回收模組 630之示意圖。電荷回收模組63〇新增一開關幻4，開關 634耦接於調節電容Cr之兩端，用來根據邏輯電路4〇〇產 生之一清除訊號CLN，於閘極驅動訊號VG一1〜VG Μ之 中段導通，以清除負載電容C1〜CM儲存之電荷，進而確 保閘極驅動訊號VG一1〜VG_M調變之幅度一致。 須注意的是，閘極驅動器40係假設液晶顯示器中之 薄膜電晶體為N型場效應電晶體，其於閘極驅動訊號ye」 〜VG一Μ為第-電壓VI時導通’以更新儲存的晝素内容。 當然，液晶顯示器中之薄膜電晶體亦可能為ρ型場效應電 晶體，在此情況下’請參考冑7，目7為閘極驅動器牝之 變化貫施例一閘極驅動器70之示意圖。閘極驅動器用 來掃描薄膜電晶體為Ρ型場效應電晶體之液晶顯示器。在 201227703 I二7〇中，開關模組420由一開關模組720取代， 一二 _ 722 ’開關722根據斷電訊號BK，切斷第 二之供電路徑。閘極驅動器70中開關訊號SWJ 、斷電訊號BK、分享訊號如〜⑽、清除訊號 =閘極__ 〜VG_3之時序，可參考圖8。 丄VrT圖5類似，差別僅在於欲製造閘極驅動訊號VG_1 極性相反，相關說明可參考前述，在此不贅述。 〜V間極H 4〇、7〇產生方波作為間極_減 一 G—M之操作可歸納為一閘極驅動流程9〇,如第9圖所 不。閘極驅動流程90包含有下列步驟： 步驟900 :開始。 —步驟902 :緩衝器412一X根據開關訊號SW_X，輸出 非致能電壓’作為閘極驅動訊號VG_x。 步驟904 :開關模組420、720根據斷電訊號BK，停 1輪出非致能電壓；電荷回收模組430、630與負載模組degree. The buffers 412"-412-Μ include a field-effect transistor (FET) QP1^QpM^N transistors QN1~QNM, which are used to determine the supply according to the corresponding (4) signal SW. - Voltage V1 or second voltage v2 to load 416 -1 to 416 -M. Load module 416—b%, resistor R1~RMf^capacitor ci,,___/=;;12γ2Γcut VG^l, store or output charge to generate gate “Signal VG-1~VG— M. In addition, for the 420^ fine 420-year-old (four) sentence a ancient one for the current electricity and what is the dry operation, open _ has a switch 422, switch 422 according to the broken telecommunications received 12 201227703 BK, in the gate drive signal VGj ~ VG_M Chinese The leading edge and the trailing edge of the wave cut off the power supply path of the first voltage VI, so that the load capacitances C1 CMCM and the regulating capacitor Cr independently share the stored charge. For example, please refer to FIG. 5. FIG. 5 is a timing diagram of the switching signals SW_1~SW_M, the power-off signal BK, the shared signals SS1~SSM, and the gate driving signals VG_1~VG_3. In FIG. 5, taking the generation process of the gate driving signal VG_1 as an example, in the front edge of the square wave in the gate driving signal VG_i (between time points t1 and t2), the power-off signal BK instructs the switch 422 to cut off the first voltage. The power supply path of the VI; the switching signals SW_1~8"_]^1 indicate that the buffers 412_1~412_M cut off the electrical connection between the load modules 416_1~416__M; the sharing signal SS1 indicates that the switch 432J turns on the adjustment capacitor Cr and the load capacitance (^, The charge stored in the adjustment capacitor Cr is output to the load capacitor C1 to precharge the gate drive signal VG_1 to the quasi-enable level. In the middle of the square wave in the gate drive signal VG_1 (between time points t2 and t3) The power-off signal BK indicates that the switch 422 resumes outputting the first voltage VI to the load module 416_1; the switch signal SW_1 indicates that the buffers 412_1 412 412_M transmit the first voltage VI; the sharing signal SS1 indicates that the switch 432_1 isolates the adjustment capacitor Cr and the load capacitor C1 So that the gate drive signal VG_1 can be turned on. Finally, at the trailing edge of the square wave in the gate drive signal VG_1 (between the time points t3 and t4), the power-off signal BK again instructs the switch 422 to cut off the power supply path of the first voltage VI; switch The numbers SW_1 to SW_M indicate that the buffers 412j to 412_M cut off the electrical connection between the load modules 416_1 to 416_M; the sharing signal SS1 instructs the switch 432_1 to turn on the adjustment capacitor Cr and the load capacitance C1, so that the charge stored in the load capacitor C1 is recovered to the regulated power. 13 201227703 When Cr is used as the square wave of the next gate drive signal (VG_2), the reserve charge of the load capacitor C1 is precharged. The operation of the gate drive signal vg_2~ VG-M is the same as that of the gate drive signal VG_1. Therefore, the charge sharing operation of the gate drive signals VG-1 to VG-M at the leading and trailing edges of the gate drive driver can recover and reuse the charge required for driving to economically. The power-saving method realizes the waveform adjustment. It should be noted that the adjustment capacitor Cr has a partial charge after the charge of the gate drive signals VG_l~ VG_M and the load capacitors C1~CM share, and the adjustment capacitor is still under the control. The efficiency of the secondary load "recovery" of the load capacitance C1~CM is reduced, which in turn affects the amplitude of the modulation. To ensure that the gate drive signals VG-1 to VGJV are the same, please refer to Figure 6. 6 is a schematic diagram of a charge recovery module 630 according to a variation of the charge recovery module 430. The charge recovery module 63 〇 adds a switch phantom 4, and the switch 634 is coupled to the two ends of the adjustment capacitor Cr for The logic circuit 4 generates a clear signal CLN, which is turned on in the middle of the gate drive signal VG-1~VG, to remove the charge stored in the load capacitor C1~CM, thereby ensuring the gate drive signal VG-1~VG_M The magnitude of the change is the same. It should be noted that the gate driver 40 assumes that the thin film transistor in the liquid crystal display is an N-type field effect transistor, which is turned on when the gate driving signal ye"~VG is turned into the first voltage VI" to update the storage.昼素 content. Of course, the thin film transistor in the liquid crystal display may also be a p-type field effect transistor. In this case, please refer to 胄7, and the seventh is a schematic diagram of the gate driver 变化. The gate driver is used to scan a thin film transistor as a liquid crystal display of a 场 field effect transistor. In 201227703 I, the switch module 420 is replaced by a switch module 720, and the switch 722 switches off the second power supply path according to the power-off signal BK. For the timing of the switching signal SWJ, the power-off signal BK, the shared signal such as ~(10), and the clear signal = gate__ to VG_3 in the gate driver 70, refer to FIG.丄VrT Figure 5 is similar, the only difference is that the polarity of the gate driving signal VG_1 is opposite. For the related description, refer to the foregoing, and no further details are provided herein. ~V-pole H 4 〇, 7 〇 produces a square wave as the interpole _ minus one G-M operation can be summarized as a gate drive process 9 〇, as shown in Figure 9. The gate drive process 90 includes the following steps: Step 900: Start. - Step 902: The buffer 412_X outputs the non-enabling voltage ' as the gate driving signal VG_x according to the switching signal SW_X. Step 904: The switch modules 420 and 720 stop the non-enable voltage according to the power-off signal BK; the charge recovery modules 430, 630 and the load module
4 ] N 八二Λ为別根據分享訊號SSx及開關訊號sw_x，獨立地 刀享储存之電荷，以預先調整閘極驅動訊號VG_x至第一 預設電壓。 步驟906 :開關模組420、720及緩衝器412_x分別根 ，斷電訊號BK及開關訊號sw_x導通，以輸出一致能電 壓，作為閘極驅動訊號VG_X。 :»步驟908 :開關634根據清除訊號CLN導通，以清除 調節電容Cr中儲存之電荷。 步驟910 :開關模組420、720根據斷電訊號BK，停 15 201227703 止輸出致能電壓；電荷回收模組430、630與負載模組416_χ 分別根據分享訊號SSx及開關訊號SW_x，獨立地分享儲 存之電荷’以調變閘極驅動訊號VG_x。 步驟912 :開關模組420、720及緩衝器412_x分別根 據斷電訊號BK及開關訊號sw_x，輸出非致能電壓，作 為閘極驅動訊號VG_x。 步驟914 :結束。 在閘極驅動流程90中，若薄膜電晶體為n型場效應 電晶體，非致能電壓為一低電壓，致能電壓為一高電壓。 相反地，若薄膜電晶體為P型場效應電晶體，非致能電壓 為高電壓，致能電壓為低電壓。 在先前技術中，閘極驅動訊號VG_1〜VG Μ之電壓 變化透過寄生電容耗合至等效電容114,使得等效電容114 儲存偏差的影像内容，因此亟欲透過波形重整減輕耦合現 象。因此，本發明透過開關操作，於閘極驅動訊號VG」 〜VG一Μ之前緣及後緣，切斷電源供應，並獨立地分享負 載模組416_1〜416一Μ與電荷回收模組430、630儲存之電 荷。由於電荷分享係一漸進過程，閘極驅動訊號VG 1〜 VGJV[可以緩和的速率下降，可減輕耗合現象。另外，透 過回收負載模組416_1〜416一Μ之電荷，電荷回收模組 430、630預先提升閘極驅動訊號VG_1〜VG Μ至準致能 位準’以降低閘極驅動器40、70之電能消耗。 圖10繪示本發明實施例一閘極驅動器5〇之示意圖。 圖11為斷電訊號ΒΚ卜ΒΚ2、分享訊號sT、Sp&閘極驅 201227703 動訊號VG_1〜VG_4之時序圖。請參考圖10及圖11，閘 極驅動器50用來控制一液晶顯不器（Liquid Crystal Display，LCD)中晝素的更新時序，亦即控制圖1中以矩 陣方式排列之薄膜電晶體（Thin Film Transistor，TFT ) 112 的閘極電壓。在本實施例中，閘極驅動器5〇包括閘極驅動 器包括一邏輯電路500、多個緩衝器512_1〜512_M、一開 關模組520以及一電荷分享模組530。 須注意的是，在本實施例中，有鑑於閘極驅動訊號 VG一1〜VG_M係以方波的型式指定薄膜電晶體112的開 啟時序，開關模組520特別於方波之前緣及後緣斷路。同 時，電荷分享模組530依序連接至負載模組516_1〜 516-M，使緩衝器之輸出端彼此分享電荷，以調整閘極驅 動訊號VG_1〜VGJV[於前、後緣之波形。 進一步而言’邏輯電路5〇〇用來產生開關訊號SW1 〜SWM。緩衝器512—1〜512_M用來根據開關訊號SW1 〜SWM’決定輪出一第一電壓或一第二電壓v2，以產 生閘極驅動訊號VG—1〜VG_M，閘極驅動訊號VG_1〜 VGJVT分別用來掃描一列（r〇w)的薄膜電晶體。 開關模組520根據第一斷電訊號BK1、第二斷電訊號 BK2 ’切斷輸出第-電壓V1或第二電壓V2至負載模組 516 j〜516—M之供電路徑。負載模組M係各 負載之等效電路。在本實施例巾，開賴組包括開關522、 524。開_ 522輕接於各緩衝器與第一電壓源¥1之間，其 根據第-斷電訊號BKl，於每—閘極驅動訊號之方波之前 17 201227703 緣及後緣，切斷第一電壓源V1至各缓銜器之電連接。另 一方面，開關524耦接於各緩衝器與第二電壓源V2之間， 其根據第一斷電訊號BK2，於每一閘極驅動訊號之方波之 前緣及後緣’切斷第二電壓源V2至各缓衝器之電連接。 電荷分享模組53〇根據第一分享訊號ST、第二分享訊 號SP，使緩衝器之輸出端彼此分享電荷，以調整閘極驅動 訊號VG一1〜VGJV[的波形。在本實施例中’電荷分享模 組530包括多個開關m_1〜MjVt-Ι。在此，依據各開關的 控制訊號’可將其分類為兩個群組：其一為受第一分享訊 號ST所控制的第奇數個開關（即複數個第三開關、 M_3、…、及Μ_Μ·2(未繪示）；其二為受第二分享訊號sp 所控制的第偶數個開關（即複數個第四開關)M__2、M_4(未 繪示）、…、及Μ—M-1。第一分享訊號ST與第二分享訊號 SP交替地將第三開關m_1、M_3、…及M_M-2與第四開 關Μ一2、M_4、...、及m_M-1開啟，使顯示器10上一級 的晝素充電路徑與下一級的晝素充電路徑做波形調整。 舉例而言，在閘極驅動訊號VG_1之後緣及閘極驅動 訊號VG—2之前緣，開關522、524分別根據斷電訊號BK1、 BK2而斷路。此時，開關m_1根據第一分享訊號ST導通， 電性連接緩衝器512 j與512_2之輸出端，使兩者彼此分 享電荷，以調整閘極驅動訊號VG_1及VG_2於前、後緣 之波形。接著，在閘極驅動訊號VG_2之後緣及閘極驅動 訊號VG_3之前緣，開關522、524分別根據斷電訊號BK1、 BK2而斷路。此時，開關M2根據第二分享訊號Sp導通， 201227703 接緩衝11 512-2與512_3之輸出端，㈣者彼此分 子:何’以凋整閘極驅動訊號VG—2及vg_3於前、後緣 之波形。其餘的緩衝器之電荷分享，#可以上述操作原理 以此類推，在此便不再贅述。 一值传注意的是，在本實施例中，當開關Μ」根據第一 分旱訊號sT電性連接緩衝器512J、512_2時，開關m、2 根據第二分享訊號Sp，切斷緩衝器5i2_2、512」之電^ ί二ί反地’當開關M-2根據第二分享訊號〜電性連接 緩衝益512—2 ' 512—3日夺，開關M—卜M—3根據第一分享 訊號ST，切斷緩衝器512J、512_2及缓衝器512—3、512 4 之電連接。 — — 換句活說’隨著時序的進行，閘極驅動訊號 的波升>5周整會搭配閘極驅動訊號VG_N來實現，此時第— 分享訊號ST開啟第三開關Μ_Ν·1(未繪示），以使緩衝器 512—Ν-1、512_Ν(未繪示）進行電荷分享。閘極驅動訊號 VG_N的波形調整會搭配閘極驅動訊號vG_N+1來實現， 此時第二分享訊號SP開啟第四開關m_N(未繪示）。極驅動 訊號VG—N+1的波形調整會搭配極驅動訊號vG—N+2來實 現，此時第一分享訊號ST開啟第三開關μ__Ν+1(未繪示）， 以此類推。 在本實施例中，利用第一分享訊號ST控制第三開關 M—卜M_3、…及M—M-2，並利用第二分享訊號Sp控制第 四開關Μ一2、M—4、…、及M—M-1，使各緩衝器之輸出端 可以透過該等開闕將部份的電荷釋出，讓輪出電位達到所. 19 201227703 / 4。如此—來，顯示器⑺不會有不正常的畫面產 ^而緩衝n之輸出顧釋出的電荷會提供釘―級的輸 ^，減少下—級的輸出端開啟所需之電荷，達到省電的 結果。 w咬以 八^在此，本貫施例係以緩衝器之輸出端為單位利用兩個 分享訊號ST、Sp依序傳遞地作控制。在其他實施例中，亦 可以二個以上之緩衝器的輸出端為單位，搭配三個以上之 分享訊號依序傳遞地作控制，相同或相似之處在此便不再 贅述。另外，在本實施例中，斷電訊號BK1、BK2及分享 訊號ST、SP可選擇性地由邏輯電路5〇〇產生，或由閘極驅 動器50外之控制電路產生。在另一實施例中，開關522、 524亦可僅由同一個斷電訊號來控制。 圖12為本發明另一實施例之閘極驅動方法的步驟流 程圖。請同時參照圖1〇至圖12，本實施例之閘極驅動方 法適於控制一顯示器，其包括如下步驟。首先’在步驟 S600,提供一第一電壓vi及一第二電壓V2至多個缓衝器 512_1〜512_M。接著，在步驟S602，根據多個開關訊號 SW1〜SWM，決定緩衝器512_1〜512JV[輸出第一電壓 VI或第二電壓V2，以產生多個閘極驅動訊號VG-1〜 VG_M。之後，在步驟S604，根據第一分享訊號&及苐二 分享訊號SP，於每一閘極驅動訊號之前緣及後緣，使多個 緩衝器之輸出端彼此分享電荷。 另外，本實施例的閘極驅動方法可以由圖1〇〜圖11 實施例之敘述中獲致足夠的教示、建議與實施說明’因此 201227703 不再贅述。 =_動方法二二：利= 出統耗 常的書面產决，此來，顯不器不會有不正 下-級:2端=輪出端所釋出的電荷會提供給 達到減少下-級的輸出端開啟所需之電荷， 雖然本發明已以實施例揭露如上， 本發明，任何所屬技術領域中且有.甫限定 ，精神和範圍内，當可；些二:二:不= 發明之保護範圍當視後附之申請專利範以^ 【圖式簡單說明】 圖1為先前技術-液晶顯示器之示意圖。 圖2為圖1之液晶顯示器中—問極驅動器之示 圖3為一閘極驅動訊號之時序圖。 心· 圖4為本發明實施例一閘極驅動器之示咅圖。 圖5為圖4之閘極驅動器中開關訊 分享訊號及閘極驅動訊號之時序圖。胃W ―斷電訊號、 圖6為圖4之閘極驅動器中—電荷 實施例之示意圖。 吹棋、、且之-變化 圖7為本發明實施例一閘極驅動器之示音圖 圖8為圖7之閘極驅動器中開關訊號、、:斷電訊號、 21 201227703 分享訊號、一清除訊號及閘極驅動訊號之時序圖。 圖9為本發明實施例一閘極驅動流程之示意圖。 圖10繪示本發明實施例一閘極驅動器50之示意圖。 圖11為斷電訊號BK1、BK2、分享訊號ST、SP及閘 極驅動訊號VG_1〜VG__4之時序圖。 圖12為本發明另一實施例之閘極驅動方法的步驟流 程圖。 【主要元件符號說明】 BK :斷電訊號 BK1 :第一斷電訊號 BK2 :第二斷電訊號 VI :第一電壓 V2 :第二電壓 VG 1、VG 2、VG 3、VG4、VG N-1、VG-N、 *— — __ VG一N+1、VG一N+2、VG_M-1、VG_M、VG一X :閘極驅動 訊號 VS_1、VS_2、VS_N-1、VS_N :源極驅動訊號 Vcom :共用訊號 VREF :參考電壓 SW1、SW2、SW3、SWM-1、SWM :開關訊號 SSI、SS2、SS3、SSM :分享訊號 ST :第一分享訊號 Sp :第二分享訊號 22 201227703 QP卜QP2、QP3、QPM-卜QPM : P型場效應電晶體 QN1、QN2、QN3、QNM-1、QNM : N 型場效應電晶 體 IU、R2、R3、RM-卜RM :負載電阻4 ] N 82 Λ 别 根据 根据 根据 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享 分享Step 906: The switch modules 420, 720 and the buffer 412_x are respectively turned on, and the power-off signal BK and the switch signal sw_x are turned on to output a uniform energy voltage as the gate driving signal VG_X. :»Step 908: The switch 634 is turned on according to the clear signal CLN to clear the charge stored in the adjustment capacitor Cr. Step 910: The switch modules 420 and 720 stop the output enable voltage according to the power-off signal BK, and the charge recovery modules 430 and 630 and the load module 416_χ independently share and store according to the shared signal SSx and the switch signal SW_x. The charge 'drives the gate drive signal VG_x. Step 912: The switch modules 420, 720 and the buffer 412_x output a non-enabling voltage according to the power-off signal BK and the switch signal sw_x, respectively, as the gate drive signal VG_x. Step 914: End. In the gate driving process 90, if the thin film transistor is an n-type field effect transistor, the non-energizing voltage is a low voltage, and the enabling voltage is a high voltage. Conversely, if the thin film transistor is a P-type field effect transistor, the non-enabling voltage is a high voltage and the enabling voltage is a low voltage. In the prior art, the voltage change of the gate drive signals VG_1 VG VG 耗 is absorbed by the parasitic capacitance to the equivalent capacitance 114, so that the equivalent capacitance 114 stores the image content of the deviation, and thus the coupling phenomenon is reduced by the waveform reforming. Therefore, the present invention cuts off the power supply through the switching operation at the leading and trailing edges of the gate driving signals VG" to VG, and independently shares the load modules 416_1 to 416 and the charge recovery modules 430 and 630. The stored charge. Since the charge sharing is a gradual process, the gate drive signals VG 1 to VGJV [the rate of relaxation can be reduced, which can alleviate the consumption phenomenon. In addition, by recovering the charge of the load modules 416_1 416 416, the charge recovery modules 430 and 630 pre-elevate the gate drive signals VG_1 VGVG Μ to the quasi-enable level to reduce the power consumption of the gate drivers 40 and 70. . FIG. 10 is a schematic diagram of a gate driver 5 实施 according to an embodiment of the present invention. Figure 11 is a timing diagram of the power-off signal, the shared signal sT, the Sp& gate, and the 201227703 motion signal VG_1 to VG_4. Referring to FIG. 10 and FIG. 11, the gate driver 50 is used to control the update timing of the pixels in a liquid crystal display (LCD), that is, to control the thin film transistors arranged in a matrix in FIG. Film Transistor, TFT ) 112 gate voltage. In this embodiment, the gate driver 5 includes a gate driver including a logic circuit 500, a plurality of buffers 512_1 512 512_M, a switch module 520, and a charge sharing module 530. It should be noted that, in this embodiment, in view of the gate driving signals VG_1 to VG_M, the opening timing of the thin film transistor 112 is specified in a square wave pattern, and the switch module 520 is particularly suitable for the front and rear edges of the square wave. Open circuit. At the same time, the charge sharing module 530 is sequentially connected to the load modules 516_1 516 516-M, so that the outputs of the buffers share electric charges with each other to adjust the waveforms of the gate driving signals VG_1 VG VGJV. Further, the logic circuit 5 is used to generate the switching signals SW1 to SWM. The buffers 512-1 to 512_M are used to determine a first voltage or a second voltage v2 according to the switching signals SW1 to SWM' to generate the gate driving signals VG-1 to VG_M, and the gate driving signals VG_1 to VGJVT respectively Used to scan a column of (r〇w) thin film transistors. The switch module 520 cuts off the power supply path of the output voltage-voltage V1 or the second voltage V2 to the load modules 516 j 516 516-M according to the first power-off signal BK1 and the second power-off signal BK2 ′. The load module M is the equivalent circuit of each load. In the present embodiment, the set of switches includes switches 522, 524. The open _ 522 is lightly connected between each buffer and the first voltage source ¥1, and is cut off according to the first-breaking signal BK1 before the square wave of each gate drive signal 17 201227703 edge and trailing edge The voltage source V1 is electrically connected to each of the terminators. On the other hand, the switch 524 is coupled between each of the buffers and the second voltage source V2, and is cut off according to the first power-off signal BK2 at the leading edge and the trailing edge of each of the gate driving signals. The voltage source V2 is electrically connected to each of the buffers. The charge sharing module 53 causes the output terminals of the buffers to share electric charges with each other according to the first shared signal ST and the second shared signal SP to adjust the waveforms of the gate driving signals VG-1 to VGJV. In the present embodiment, the 'charge sharing module 530' includes a plurality of switches m_1 to MjVt-Ι. Here, according to the control signal ' of each switch, it can be classified into two groups: one is the odd number of switches controlled by the first shared signal ST (ie, the plurality of third switches, M_3, ..., and Μ_Μ) 2 (not shown); the second is the even number of switches (ie, the plurality of fourth switches) M__2, M_4 (not shown), ..., and Μ-M-1 controlled by the second shared signal sp. The first sharing signal ST and the second sharing signal SP alternately turn on the third switches m_1, M_3, ..., and M_M-2 and the fourth switches Μ 2, M_4, ..., and m_M-1 to make the display 10 The first-level halogen charging path and the next-level halogen charging path are waveform-adjusted. For example, at the trailing edge of the gate driving signal VG_1 and the leading edge of the gate driving signal VG-2, the switches 522 and 524 are respectively based on the power-off signal. BK1 and BK2 are disconnected. At this time, the switch m_1 is turned on according to the first shared signal ST, and is electrically connected to the output ends of the buffers 512 j and 512_2 to share the charges with each other to adjust the gate driving signals VG_1 and VG_2. Waveform of the trailing edge. Then, at the trailing edge and gate drive of the gate drive signal VG_2 At the front edge of the VG_3, the switches 522 and 524 are respectively disconnected according to the power-off signals BK1 and BK2. At this time, the switch M2 is turned on according to the second shared signal Sp, and the 201227703 is connected to the output terminals of the buffers 11 512-2 and 512_3, and (4) are mutually molecular. :He's the waveform of the front and rear edges of the gate drive signals VG-2 and vg_3. The charge sharing of the remaining buffers, # can be the same as the above operation principle, and will not be described here. It is noted that, in this embodiment, when the switch 电 is electrically connected to the buffers 512J, 512_2 according to the first drought signal sT, the switches m, 2 cut off the buffers 5i2_2, 512 according to the second shared signal Sp" The electric ^ ί 二ί反地' when the switch M-2 according to the second share signal ~ electrical connection buffer benefit 512-2 '512-3 days, the switch M-Bu M-3 according to the first share signal ST, cut The electrical connection of the buffers 512J, 512_2 and the buffers 512-3, 512 4 is carried out. — — In other words, as the timing progresses, the wave of the gate driving signal rises > 5 weeks will be matched with the gate drive The signal VG_N is implemented. At this time, the first sharing signal ST turns on the third switch Μ_Ν·1 (not shown). In order to make the buffer 512-Ν-1, 512_Ν (not shown) for charge sharing, the waveform adjustment of the gate driving signal VG_N is realized by the gate driving signal vG_N+1, and the second shared signal SP is turned on. Four switches m_N (not shown). The waveform adjustment of the pole drive signal VG-N+1 is implemented with the pole drive signal vG-N+2, at which time the first shared signal ST turns on the third switch μ__Ν+1 (unpainted Show), and so on. In this embodiment, the third switch M-B, M_3, ..., and M-M-2 are controlled by the first shared signal ST, and the fourth switch Μ2, M-4, ... is controlled by the second shared signal Sp. And M-M-1, so that the output of each buffer can release part of the electric charge through the openings, so that the wheel potential reaches the end. 19 201227703 / 4. In this way, the display (7) will not have an abnormal picture production, and the output of the buffer n will provide a pin-level output, reducing the charge required to turn on the output of the lower stage, saving power. the result of. w bite to eight ^ here, the present embodiment is based on the output of the buffer in units of two shared signals ST, Sp in order to control. In other embodiments, the output of more than two buffers may be used as a unit, and more than three shared signals are sequentially transmitted for control. The same or similar points will not be described herein. In addition, in the present embodiment, the power-off signals BK1, BK2 and the shared signals ST, SP can be selectively generated by the logic circuit 5 or by a control circuit external to the gate driver 50. In another embodiment, the switches 522, 524 can also be controlled by only the same power down signal. Figure 12 is a flow chart showing the steps of a gate driving method according to another embodiment of the present invention. Referring to Figures 1A through 12 together, the gate driving method of the present embodiment is adapted to control a display including the following steps. First, at step S600, a first voltage vi and a second voltage V2 are supplied to the plurality of buffers 512_1 ～ 512_M. Next, in step S602, the buffers 512_1 to 512JV are determined based on the plurality of switching signals SW1 to SWM [the first voltage VI or the second voltage V2 is outputted to generate a plurality of gate driving signals VG-1 to VG_M. Then, in step S604, according to the first shared signal & and the second shared signal SP, the outputs of the plurality of buffers share the charge with each other at the leading edge and the trailing edge of each of the gate driving signals. In addition, the gate driving method of the present embodiment can obtain sufficient teachings, suggestions, and implementation instructions from the description of the embodiment of FIGS. 1A to 11th. Therefore, 201227703 will not be described again. =_Motion method 22: Profit = Out of the usual written production decision, this will not have the wrong side - level: 2 end = the charge released by the wheel will be provided to achieve the reduction - The output of the stage turns on the required charge, although the invention has been disclosed in the above embodiments, the invention, any one of the technical fields, and the scope and spirit of the invention, may be; two: two: no = invention The scope of protection is described in the attached patent application. [FIG. 1 is a schematic diagram of a prior art-liquid crystal display. 2 is a timing diagram of a gate driving signal in the liquid crystal display of FIG. 1. FIG. 3 is a timing diagram of a gate driving signal. Figure 4 is a schematic view of a gate driver according to an embodiment of the present invention. FIG. 5 is a timing diagram of the switching signal sharing signal and the gate driving signal in the gate driver of FIG. Stomach W - Power Down Signal, Figure 6 is a schematic diagram of a charge embodiment in the gate driver of Figure 4. FIG. 8 is a schematic diagram of a gate driver of the embodiment of the present invention. FIG. 8 is a switching signal of the gate driver of FIG. 7 , : a power-off signal, 21 201227703 sharing a signal, and a clear signal. And the timing diagram of the gate drive signal. FIG. 9 is a schematic diagram of a gate driving process according to an embodiment of the present invention. FIG. 10 is a schematic diagram of a gate driver 50 according to an embodiment of the present invention. Figure 11 is a timing diagram of the power down signals BK1, BK2, the shared signal ST, SP, and the gate drive signals VG_1 VG VG__4. Figure 12 is a flow chart showing the steps of a gate driving method according to another embodiment of the present invention. [Main component symbol description] BK: power-off signal BK1: first power-off signal BK2: second power-off signal VI: first voltage V2: second voltage VG 1, VG 2, VG 3, VG4, VG N-1 VG-N, *-- __ VG-N+1, VG-N+2, VG_M-1, VG_M, VG-X: gate drive signals VS_1, VS_2, VS_N-1, VS_N: source drive signal Vcom : shared signal VREF: reference voltage SW1, SW2, SW3, SWM-1, SWM: switching signal SSI, SS2, SS3, SSM: shared signal ST: first shared signal Sp: second shared signal 22 201227703 QP BU QP2, QP3 QPM-Bu QPM: P-type field effect transistors QN1, QN2, QN3, QNM-1, QNM: N-type field effect transistors IU, R2, R3, RM-b: RM: load resistance
Cl、C2、C3、CM-1、CM :負載電容Cl, C2, C3, CM-1, CM: load capacitance
Cr :調節電容 CLN :清除訊號 tl、t2、t3、t4 :時間點 10 .液晶顯不裔 100 .液晶顯不面板 102 :源極驅動器 105 :邏輯電路 107一 1、107—2、107M-1、107_M、412—1、412_2、 412—M-卜 412—Μ、512—1、512—2、512_3、512_M :緩衝 器 106 :電壓產生器 108 :資料線 109—1、109—2、109M-1、109_M :負載模組 110 ·掃描線 112 :薄膜電晶體 114 :等效電容 40、50、70、104 :閘極驅動器 400、500 :邏輯電路 416 1、416 2、416 M-1、416 Μ、516 1、516 2、 23 201227703 516_3、516_M :負載模組 420、520、720 :開關模組 422、432_1、432一2、432_M-1、432_M、634、722、 522、524、M_1、M_2、M_3、M_M-1 :開關 430、630 :電荷回收模組 530 :電荷分享模組 90 :閘極驅動流程 900、902、904、906、908、910、912、914、S600、 S602、S604 :步驟 24Cr: adjustment capacitor CLN: clear signal tl, t2, t3, t4: time point 10. liquid crystal display 100. liquid crystal display panel 102: source driver 105: logic circuit 107-1, 107-2, 107M-1 , 107_M, 412-1, 412_2, 412-M-Bu 412-Μ, 512-1, 512-2, 512_3, 512_M: buffer 106: voltage generator 108: data lines 109-1, 109-2, 109M -1, 109_M: load module 110 · scan line 112: thin film transistor 114: equivalent capacitance 40, 50, 70, 104: gate driver 400, 500: logic circuit 416 1, 416 2, 416 M-1, 416 Μ, 516 1, 516 2, 23 201227703 516_3, 516_M: load modules 420, 520, 720: switch modules 422, 432_1, 432-2, 432_M-1, 432_M, 634, 722, 522, 524, M_1 M_2, M_3, M_M-1: switches 430, 630: charge recovery module 530: charge sharing module 90: gate drive flow 900, 902, 904, 906, 908, 910, 912, 914, S600, S602, S604: Step 24