TW201220468A - A package structure for DC-DC converter - Google Patents

A package structure for DC-DC converter Download PDF

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Publication number
TW201220468A
TW201220468A TW099137604A TW99137604A TW201220468A TW 201220468 A TW201220468 A TW 201220468A TW 099137604 A TW099137604 A TW 099137604A TW 99137604 A TW99137604 A TW 99137604A TW 201220468 A TW201220468 A TW 201220468A
Authority
TW
Taiwan
Prior art keywords
low
stage
controller
side mosfet
mosfet chip
Prior art date
Application number
TW099137604A
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Chinese (zh)
Other versions
TWI433297B (en
Inventor
Yueh-Se Ho
Yanxun Xue
Jun Lu
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Alpha & Omega Semiconductor
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Publication date
Application filed by Alpha & Omega Semiconductor filed Critical Alpha & Omega Semiconductor
Priority to TW099137604A priority Critical patent/TWI433297B/en
Publication of TW201220468A publication Critical patent/TW201220468A/en
Application granted granted Critical
Publication of TWI433297B publication Critical patent/TWI433297B/en

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    • H—ELECTRICITY
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    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package.

Description

201220468 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明是有關於一種半導體封裝體結構，特別是有關於 一種能將多個晶片等元件封裝在同一個封裝體中的應用 於直流-直流轉換器的封裝體結構。 【先前技術】 [0002] 在直流-直流轉換器中通常設有兩個MOSFET (金屬氧化物 半導體場效電晶體）作為切換開關。如第1圖所示，是由 2個N型MOSFET連接形成的直流-直流（DC-DC)轉換器的 電路圖。 [0003] 其中高端MOSFET的閘極G1及低端MOSFET的閘極G2均與 一控制器連接；高端MOSFET (HS)的汲極D1連接電源端 Vin，其源極S1連接低端MOSFET (LS)的汲極1)2，而低 端MOSFET的源極S2連接接地端Gnd，則形成所述直流-直 流轉換器。一般在直流-直流轉換器的Vin-Gnd兩端之間 還設置有電容、電感等元件。 [0004] 如第2圖所示，現有一種直流-直流ί轉換器的封裝結構， 使高端MOSFET晶片和低端MOSFET晶片以及控制器封裝在 同一個封裝體中，以減少週邊元件數量，同時提高電源 等的利用效率。 [〇〇〇5] 然而對於具體的封裝體來說，上述高端MOSFET晶片和低 端MOSFET晶片以及控制器只能在引線框架的同一個平面 上平行佈置，那麼封裝體的安裝空間很大程度上限制了 高端MOSFET、低端MOSFET以及控制器的尺寸，這對直流 -直流轉換器的性能提高具有很大的影響。 099137604 表單編號A0101 第4頁/共38頁 0993434508-0 201220468 【發明内容】 [0006] [0007] Ο [0008] [0009] [0010] Ο [0011] [0012] [0013] [0014] 099137604 有鑑於上述習知技藝之問題，本發明的目的在於提供一 種用於直流-直流轉換器的封裝體結構，能夠將多個半導 體晶片#元件封裝在同-個半導體封裝中，以減少直流_ 直流轉換器組裝時元件的數量，也減小整個半導體封裝 的尺寸；進一步地由於封裝空間的節省，能夠在同樣大 小的封裝體内增大ΒΒ片或控制器的尺寸，來有效提高半 導體元件的產品性能。 為了達到上述目的，本發明的技術方案是提供一種用於 直流-直流轉換器的封裝體結構，其中，包含： 分別具有底部汲極、頂部閘極和頂部源極的高端MOSFET 晶片和低端MOSFET晶片； 引線框架，其設置有第一載片台和第二栽片台； 尚端MOSFET晶片設置在第一載片台上，使其底部没極與 第一載片台形成電性連接；二* 控制器’也設置在第一載片台上，其與高端MOSFET晶片 的頂部閘極電性連接； 導電的中間聯結件，其設置在第二載片台及高端M〇SFET 晶片上，並與高端MOSFET晶片的頂部源極電性連接； 低端MOSFET晶片設置在中間聯結件上，其頂部閘極與控 制器電性連接；其底部汲極與中間聯結件的頂面電性連 接’即與高端MOSFET晶片的頂部源極也電性連接； 中間聯結件不覆蓋控制器，使在控制器上方、與低端 表單編號A0101 第5頁/共38頁 0993434508-0 201220468 M0SFET晶片之間存在空隙。 [0015] 在本發明之一實施例中，第二載片台的厚度大於第一載 片台的厚度。 [0016] 其中，第二載片台的厚度與第一載片台上堆疊了高端 M0SFET晶片後的厚度一致。 [0017] 在本發明的另一實施例中，導電的中間聯結件包含一體 設置的第一聯結部，以及厚於第一聯結部的第二聯結部 〇 [0018] 其中，第二聯結部設置在第二載片台上。 [0019] 其中，第一聯結部設置在第一載片台的高端M0SFET晶片 上，使在高端M0SFET晶片的頂部源極通過該第一聯結部 ，與低端M0SFET晶片的底部汲極之間形成電性連接。 [0020] 其中，第一聯結部設置在第一載片台的高端M0SFET晶片 頂面之後的厚度，與第二聯結部設置在第二載片台頂面 之後的厚度一致。 [0021] 在上述兩個實施例中，引線框架上還設置有與第一載片 台、第二載片台分隔且無電性連接的複數個引腳，包含 複數個低端源極引腳、低端閘極引腳、高端源極引腳、 高端閘極引腳以及控制引腳。 [0022] 其中，高端M0SFET晶片通過複數個連接引線鍵合，分別 在其頂部閘極與高端閘極引腳之間、頂部源極與高端源 極引腳之間分別形成電性連接。 [0023] 其中，控制器通過複數個連接引線鍵合，分別與第一載 099137604 表單編號A0101 第6頁/共38頁 0993434508-0 201220468 [0024] [0025] Ο [0026] [0027] ❹ [0028] 片台、複數個控制引腳、低端閘極引腳，以及高端 MOSFΕΤ晶片的頂部閘極形成電性連接。 其中，低端MOSFET晶片通過複數個連接引線鍵合，使其 頂部閘極與低端閘極極引腳之間形成電性連接，即與控 制之間也形成電性連接。 其中，低端MOSFET晶片，覆蓋中間聯結件和控制器頂部 的部分或全部區域。 其中，控制器上方、與低端M0SFET晶片之間的空隙中， 容納鍵合連接控制器與餐端M0SFET晶片或控制引腳的複 數個連接引線。 其中，低端MOSFET晶片通過複數個連接引線鍵合，使其 頂部源極與低端源極引腳之間形成電性連接。 其中，用於直流-直流轉換器的封裝體結構，還包含複數 個金屬連接板，來電性連接低端M0SFET晶片的頂部源極 與低端源極引腳，使金屬連接板得以暴露在封裝體結構 的表面之外。 * ·; " _y - E| * ^ ^ . 本發明用於直流-直流轉換器的封裝體結構，與現有技術 相比，其優點在於： [0029] 本發明通過設置厚薄不同的第一、第二載片台，或是通 過設置含不同厚薄聯結部的中間聯結件，使低端M〇SFET 晶片放置到中間聯結件頂面後，能夠堆疊在第一載片台 的高端MOSFET晶片上，並通過中間聯結件連接高端 MOSFET晶片的頂部源極與低端M〇SFET晶片的底部汲極， 以減少直流-直流轉換器組裝時元件的數量。同時在第一 099137604 表單編號A0101 第7頁/共38頁 0993434508-0 201220468 載片台的控制器上方、與低端MOSFET晶片之間的空隙中 ’能夠容納鍵合連接控制器與高端M0SFET晶片或複數個 引腳的複數個連接引線，以進一步減小整個半導體封裝 的尺寸。 [0030] [0031] [0032] 本發明由於採用低端M0SFET晶片通過中間聯結件堆疊至 尚端M0SFET晶片和控制器上方的封裝體結構，與現有技 術在引線框架上平鋪設置高、低端M0SFET晶片和控制器 的結構相比，本發明在同樣大的引線框架上，可以充分 擴展各元件的尺寸，如將低端M〇SFET晶片面積增大至覆 蓋整個兩端M0SFET晶片和控:制器上'方，能夠有效提高半 導體元件的產品性能。 本發明還通過金屬連接板、金屬連接帶等金屬連接體， 來實現低端M0SFET晶片的頂部源極與低端源極引腳之間 的電性連接，使該金屬連接板能夠在直流_直流轉換器塑 封封裝後外露，以改善半導體封裝的熱性能，同時有效 降低該半導體封裝的厚度。 由本發明通過設置厚薄不同的載片台，或是設置含不同 厚薄聯結部的巾間聯料來承载並祕連接複數個元件 的結構’可以方便地將各種半導體晶片、控制器、電感 或電容等元件堆疊，使魏被封裝在同—個半導體封裝 中，以擴展本發明形成各種其他半導體元件。 、 【實施方式】 以下根據第3圖〜第18圖，詳細說明本發明的—些較佳實 施例，以更好的理解本發明的技術手段和效果。 099137604 表單編號A0101 第8買/共38頁 0993434508-0 [0033] 201220468 [0034] - [0035] Ο [0036] ❹ [0037] [0038] 如第1圖所示’本發明中所提供的直流-直流轉換器，是 由2個相同類型的MOSFET晶片分別作為高端MOSFET晶片 和低端MOSFET晶片，與控制器或其他元件連接後，封裝 在同一個封裝體内，形成獨立的半導體元件。 該2個MOSFET晶片可以是2個Ν型或Ρ型的MOSFET晶片。 但是由於N型MOSFET晶片相比於P型MOSFET晶片，體積較 小，電阻也較小，故在以下所述的實施例中，均以2個N 型MOSFET晶片為例說明。但應當注意的是，這些具體描 述及實例並非用來限制本發觸的範圍β 所述高端MOSFET晶片相比於低端MOSFET晶片尺寸較小。 高端和低端MOSFET晶片均具有底部汲極、頂部源極和頂 部閘極，其中高端MOSFET的閘極G1及低端MOSFET的閘極 G2均與一控制器連接；高端MOSFET (HS)的汲極01連接 電源端Vin，其源極S1連接低端MOSFET (LS)的汲極D2 ，而低端MOSFET的源極S2速接接地端（Gnd)，形成所述 直流-直流轉換器。.在羞流-直流轉換器的Vin-Gnd兩端 之間還可以設置電容、電感等元件。 實施例1 如第3圖所示是本實施例所述用於直流-直流轉換器的封 裝體結構的示意圖，其包含一引線框架，該引線框架上 在同一平面設置有厚度不同的第一載片台11和第二載片 台12，假設第二載片台12的厚度大於第一載片台11厚度 。在本實施例中第一載片台11還包括相互分離的第一部 分和第二部分。當然，也可選用第一部分和第二部分相 099137604 表單編號A0101 第9頁/共38頁 0993434508-0 201220468 互連接的第一載片台。 [0039] 該引線框架上還設置有與第一、第二載片台分隔且無電 性連接的複數個引腳，包含低端源極引腳133、低端閘極 引腳134、高端源極引腳131、高端閘極引腳132以及控 制引腳1 3 5。 [0040] 請參見第3圖所示，並配合參見第4圖所示俯視圖；第5圖 所示是第4圖在A-A’向的剖面圖，第6圖所示是第4圖在 B - B ’向的剖面圖。 [0041] 將所述尺寸較小的高端MOSFET晶片21黏接貼附至第一載 片台11第一部分上，使其底部汲極（圖中未示）與第一 載片台11第一部分形成電性連接；而其頂部源極211和頂 部閘極212通過複數個連接引線51鍵合（bond)，分別與 上述高端源極引腳131、高端閘極引腳132形成電性連接 〇 [0042] 將控制器40黏接貼附至第一載片台11第二部分上，使控 制器40通過複數個連接引線51键合，分別與第一載片台 11、複數個控制引腳135、低端閘極引腳134，以及高端 MOSFET晶片21的頂部閘極21 2形成電性連接。 [0043] 請參見第3圖所示，並配合參見第7圖所示俯視圖；第8圖 所示是第7圖在A-A’向的剖面圖，第9圖所示是第7圖在 B - B ’向的剖面圖。 [0044] 所述第二載片台12的厚度與第一載片台11上堆疊了高端 MOSFET晶片21後的厚度一致。在該第二載片台12及高端 MOSFET晶片21上固定設置一導電的中間聯結件30，使該 099137604 表單編號A0101 第10頁/共38頁 0993434508-0 201220468 [0045]201220468 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a semiconductor package structure, and more particularly to a method for packaging a plurality of wafers and the like in the same package for DC - The package structure of the DC converter. [Prior Art] [0002] Two MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are usually provided as switching switches in a DC-DC converter. As shown in Fig. 1, it is a circuit diagram of a DC-DC converter formed by connecting two N-type MOSFETs. [0003] The gate G1 of the high-side MOSFET and the gate G2 of the low-side MOSFET are all connected to a controller; the drain D1 of the high-side MOSFET (HS) is connected to the power supply terminal Vin, and the source S1 is connected to the low-side MOSFET (LS). The drain 1) 2 and the source S2 of the low side MOSFET are connected to the ground terminal Gnd to form the DC-DC converter. Generally, a capacitor, an inductor, and the like are disposed between the two ends of the DC-DC converter of the DC-DC converter. [0004] As shown in FIG. 2, a conventional DC-DC converter package structure encloses a high-side MOSFET chip and a low-side MOSFET chip and a controller in the same package to reduce the number of peripheral components and improve Utilization efficiency of power supply, etc. [〇〇〇5] However, for a specific package, the above high-end MOSFET chip and low-side MOSFET chip and controller can only be arranged in parallel on the same plane of the lead frame, so the installation space of the package is largely The size of the high-side MOSFET, low-side MOSFET, and controller is limited, which has a large impact on the performance improvement of the DC-DC converter. 099137604 Form No. A0101 Page 4 / Total 38 Page 0993434508-0 201220468 [Invention] [0006] [0007] [0009] [0010] [0014] [0014] [9914] 099137604 In view of the above problems of the prior art, it is an object of the present invention to provide a package structure for a DC-DC converter capable of packaging a plurality of semiconductor wafer # components in the same semiconductor package to reduce DC-DC conversion. The number of components in the assembly of the device also reduces the size of the entire semiconductor package; further, due to the saving of the package space, the size of the chip or the controller can be increased in the same size of the package body, thereby effectively improving the product performance of the semiconductor component. . In order to achieve the above object, the technical solution of the present invention provides a package structure for a DC-DC converter, comprising: a high-side MOSFET chip and a low-side MOSFET having a bottom drain, a top gate, and a top source, respectively. a lead frame, which is provided with a first stage and a second stage; the MOSFET is disposed on the first stage, such that the bottom of the bottom is electrically connected to the first stage; * The controller 'is also disposed on the first stage, which is electrically connected to the top gate of the high-side MOSFET chip; the conductive intermediate junction is disposed on the second stage and the high-end M〇SFET chip, and The top source of the high-side MOSFET is electrically connected; the low-side MOSFET is disposed on the intermediate junction, and the top gate is electrically connected to the controller; and the bottom drain is electrically connected to the top surface of the intermediate junction. The top source of the high-side MOSFET chip is also electrically connected; the intermediate link does not cover the controller, so that the upper part of the controller, and the low-end form number A0101 page 5 / 38 pages 0993434508-0 201220468 M0SFET chip Between the presence of voids. [0015] In one embodiment of the invention, the thickness of the second stage is greater than the thickness of the first stage. [0016] wherein the thickness of the second stage is the same as the thickness after stacking the high-end MOSFET chip on the first stage. [0017] In another embodiment of the present invention, the electrically conductive intermediate coupling member includes a first coupling portion integrally provided, and a second coupling portion thicker than the first coupling portion [0018] wherein the second coupling portion is disposed On the second stage. [0019] wherein the first junction is disposed on the high-side MOSFET of the first stage, such that a top source of the high-side MOSFET wafer passes between the first junction and the bottom drain of the low-side MOSFET wafer Electrical connection. [0020] wherein the thickness of the first connecting portion after the top surface of the high-end MOSFET of the first stage is the same as the thickness of the second connecting portion after the top surface of the second stage. [0021] In the above two embodiments, the lead frame is further provided with a plurality of pins separated from the first stage and the second stage and electrically connected, and includes a plurality of low-end source pins, Low-side gate pin, high-side source pin, high-side gate pin, and control pin. [0022] wherein, the high-end MOSFET chip is electrically connected through a plurality of connection wires, respectively, between the top gate and the high-side gate pin, and between the top source and the high-side source pin. [0023] wherein, the controller is connected by a plurality of connection wires, respectively, and the first carrier 099137604 Form No. A0101 Page 6 / Total 38 Pages 0993434508-0 201220468 [0024] [0025] 0026 [0026] [0027] ❹ [ 0028] The chip, the plurality of control pins, the low-side gate pins, and the top gate of the high-side MOSF germanium wafer are electrically connected. The low-side MOSFET chip is electrically connected through a plurality of connection wires to form an electrical connection between the top gate and the low-side gate pin, that is, an electrical connection is also formed between the control and the control. Among them, the low-end MOSFET chip covers part or all of the middle junction and the top of the controller. Wherein, a gap between the controller and the low-side MOSFET chip accommodates a plurality of connection leads of the bond connection controller and the MOSFET or control pin of the meal terminal. The low-side MOSFET chip is electrically connected through a plurality of connection wires to electrically connect the top source and the low-side source pin. The package structure for the DC-DC converter further includes a plurality of metal connection plates, and the top source and the low-end source pins of the low-side MOSFET are electrically connected to expose the metal connection plate to the package. Outside the surface of the structure. * ·; " _y - E| * ^ ^ . The package structure of the present invention for a DC-DC converter has advantages over the prior art in that: [0029] The present invention provides a first, The second stage can be stacked on the high-end MOSFET of the first stage after the low-side M〇SFET chip is placed on the top surface of the intermediate coupling by providing intermediate couplings having different thick and thin joints. The bottom source of the high-side MOSFET chip and the bottom drain of the low-side M〇SFET chip are connected through an intermediate junction to reduce the number of components in the DC-DC converter assembly. At the same time, in the first 099137604 Form No. A0101, page 7 / 38 pages 0993434508-0 201220468, the gap between the controller of the stage and the low-end MOSFET chip can accommodate the bond connection controller and the high-end MOSFET chip or A plurality of connection leads of a plurality of pins to further reduce the size of the entire semiconductor package. [0032] The present invention uses a low-end MOSFET wafer to be stacked through an intermediate bond to a package structure above the MOSFET and the controller, and the prior art is tiled on the lead frame to set the high and low ends. Compared with the structure of the MOSFET and the controller, the present invention can fully expand the size of each component on the same large lead frame, such as increasing the low-side M〇SFET wafer area to cover the entire two ends of the MOSFET chip and control system. On the 'square side, can effectively improve the performance of semiconductor components. The invention also realizes the electrical connection between the top source and the low-end source pin of the low-end MOSFET chip through a metal connecting body such as a metal connecting plate and a metal connecting strip, so that the metal connecting plate can be in a DC_DC The converter is packaged and exposed to improve the thermal performance of the semiconductor package while effectively reducing the thickness of the semiconductor package. According to the present invention, various semiconductor wafers, controllers, inductors, capacitors, etc. can be conveniently disposed by providing a different thickness of the stage, or by providing an inter-cloth material having different thick and thin joints to carry the structure of connecting a plurality of components. The components are stacked such that they are packaged in the same semiconductor package to expand the present invention to form various other semiconductor components. [Embodiment] Hereinafter, some preferred embodiments of the present invention will be described in detail with reference to FIGS. 3 to 18 to better understand the technical means and effects of the present invention. 099137604 Form No. A0101 8th Buy/Total 38 Page 0993434508-0 [0033] 201200468 [0034] [0036] [0038] [0038] As shown in FIG. 1 'DC provided in the present invention The DC converter is composed of two MOSFET chips of the same type as high-side MOSFET chips and low-side MOSFET chips. After being connected to a controller or other components, they are packaged in the same package to form separate semiconductor components. The two MOSFET chips can be two MOSFETs of the Ν or Ρ type. However, since the N-type MOSFET wafer is smaller in size and smaller in resistance than the P-type MOSFET wafer, in the following embodiments, two N-type MOSFET wafers are exemplified. It should be noted, however, that these specific descriptions and examples are not intended to limit the scope of the present touch. The high side MOSFET die is smaller in size than the low side MOSFET die. Both the high-side and low-side MOSFETs have a bottom drain, a top source, and a top gate. The gate G1 of the high-side MOSFET and the gate G2 of the low-side MOSFET are all connected to a controller; the drain of the high-side MOSFET (HS) 01 is connected to the power terminal Vin, the source S1 is connected to the drain D2 of the low-side MOSFET (LS), and the source S2 of the low-side MOSFET is connected to the ground (Gnd) to form the DC-DC converter. Capacitors, inductors, etc. can also be placed between the Vin-Gnd terminals of the shimmer-DC converter. Embodiment 1 FIG. 3 is a schematic view showing a structure of a package for a DC-DC converter according to the embodiment, which includes a lead frame on which the first load having different thicknesses is disposed on the same plane. The stage 11 and the second stage 12 assume that the thickness of the second stage 12 is greater than the thickness of the first stage 11. In the present embodiment, the first stage 11 further includes a first portion and a second portion which are separated from each other. Of course, the first part and the second part phase can also be selected. 099137604 Form No. A0101 Page 9 of 38 0993434508-0 201220468 The first stage of the interconnection. [0039] The lead frame is further provided with a plurality of pins separated from the first and second stage and electrically connected, including a low-end source pin 133, a low-side gate pin 134, and a high-end source. Pin 131, high-side gate pin 132, and control pin 1 3 5 . [0040] Please refer to FIG. 3, and see the top view shown in FIG. 4; FIG. 5 is a cross-sectional view of FIG. 4 in the direction of A-A', and FIG. 6 is the fourth drawing. A cross-sectional view of the B-B' direction. [0041] attaching the small-sized high-end MOSFET chip 21 to the first portion of the first stage 11, and forming a bottom drain (not shown) with the first portion of the first stage 11 The top source 211 and the top gate 212 are bonded through a plurality of connection leads 51 to form an electrical connection with the high side source pin 131 and the high side gate pin 132 respectively [0042 The controller 40 is adhesively attached to the second portion of the first stage 11, and the controller 40 is bonded through a plurality of connecting leads 51, respectively, to the first stage 11, a plurality of control pins 135, The low side gate pin 134 and the top gate 21 2 of the high side MOSFET wafer 21 form an electrical connection. [0043] Please refer to FIG. 3, and with reference to the top view shown in FIG. 7; FIG. 8 is a sectional view of FIG. 7 in the direction of A-A', and FIG. 9 is the seventh drawing. A cross-sectional view of the B-B' direction. [0044] The thickness of the second stage 12 coincides with the thickness of the first stage 11 on which the high-end MOSFET wafer 21 is stacked. A conductive intermediate connecting member 30 is fixedly disposed on the second stage 12 and the high side MOSFET chip 21, so that the 099137604 form number A0101 is 10 pages/38 pages 0993434508-0 201220468 [0045]

[0046] D[0046] D

[0047] ❹ [0048] 中間聯結件30底部僅覆蓋高端MOSFET晶片21頂部的—部 分’且與所述面端M0SFET晶片21的頂部源極211電性連 接（第8圖）。 請參見第3圖所示，並配合參見第1〇圖所示俯視圖；第11 圖所示是第10圖在A-A’向的剖面圖，第12圖所示是第 10圖在B-B’向的剖面圖。 在中間聯結件3 0頂面黏接貼附所述面積較大的低端 M0SFET晶片22，並與其底部汲極電性連接，因而形成第 1圖中所示高端M0SFET晶片21的源極與低端M0SFET晶片 22的汲極的電性連接。 該低端M0SFET晶片22放置在中間聯結件3〇上.，並覆蓋高 端M0SFET晶片21和控制器40上方的部:分麗.蜂（第1 〇圖） ，低端M0SFET晶片22超出中間聯結件3〇的至少一個邊沿 延伸到控制器40上方的分區域，由於中間聯結件3〇並不 覆蓋控制器40頂部，也不與其有任何連接（第8圖），使 在控制器40上方與低端M0SFET.晶片22之間的空隙中，能 夠容納上述鍵善連接控制器40與高端M〇SFET晶片21或控 制引腳135的複數個連接引線51(第11@)。 該低i^MOSFET晶片22上分別通過複數個連接引線51鍵合 ，將頂部閘極222 ’與所述引線框架上低端閘極引腳134 之間形成電性連接。配合參見第4圖、第7圖及第1〇圖所 不，由於所述低端M0SFET晶片22與控制器4〇分別與低端 間極引腳134電性連接’實現了第1圖中所示，低端 M0SFET晶片22的閘極與控制器4〇的連接。 099137604 表單編號A0101 第11頁/共38頁 0993434508-0 201220468 _]請參見第3圖所示，並配合參見第_所示俯視圖；第μ 圖所示是第13圖在A-A’向的剖面圖，第15圖所示是第 13圖在B-B’向的剖面圖。 _] i用金屬連接板52 (或者也可以是金屬連接帶之類的金 屬連接體）實現低端M0SFET晶片22的頂部源極221與^ 端源極引腳133之間的電性連接（第13圖），使在塑封_封 裝上述整個堆疊的封裝體結構後，不僅可以外露該封裝封 體結構的底部與Vin端連接，還可以外露所述金屬連接板 52的頂部表面與Gnd端連接，以改善|導體封裝的熱性能 ，同時有效降低該半導體封襞的厚度 b [0051] 實施例2 _2]配合參見俯視圖（第16圖）、A_A，向的剖面圖（第^圖 )和B-B’向的剖面圖（圖18)所示，本實施例所述用 於直流-直流轉換器的封裝體結構，具有與實施例丨中類 似的堆疊結構，在引線框架頂部的第一載片台n的第— 部分和第二部分上，分別黏接貼附高端M〇SFET晶片2^及 控制器40。在本實施例中第一载片台丨丨的第—部分和第 二部分相互分離。當然，也可選用第一部分和第二部分 相互連接的第一載片台。 [0053]南端MOSFET晶片21通過複數個連接引線51鍵合，在其頂 部閘極212與咼端閘極引腳13 2之間、頂部源極211與高 端源極引腳131之間分別形成電性連接。控制器4〇通過複 數個連接引線51鍵合，分別與第—載片台n、複數個控 制引腳135、低端閘極引腳134，以及高端m〇SFET晶片21 099137604 表單編號A0101 第12頁/共38頁 0993434508-0 201220468 的頂部閘極21 2形成電性連接。 [0054]在引線框架的第二載片台12及高端MOSFET晶片21的頂部 設置導電的中間聯結件3〇，並在中間聯結件3〇上設置低 端MOSFET晶片22，通過中間聯結件3〇電性連接高端 MOSFET晶片21的頂部源極211與低端mosfeT晶片22的底 部汲極。 [0055]與上述實施例1的不同點在於，本實施例中所述引線框架 上第一載片台11與第二載片台12厚度一致。 [0〇56]所述中間聯結件30包含一體設置的第一聯結部31和第二 聯結部32 ’使第一聯結部31黏接貼附到第一載片台11的 高端MOSFET晶片21頂面之後的厚度，與第二聯結部32黏 接貼附在第二載片台12頂面之後的厚度^致。具體通過 該第一聯結部31實現高端MOSFET晶片21的頂部源極211 與低端MOSFET晶片22的底部汲極的電，連接。 [0057] 對比第1 〇圖與第1 6圖.所示，本實施例中固定設置在中間 聯結件3 0上的低端Μ 0 S F E T晶Ά.2 2面積增大至覆蓋或超出 高端MOSFET晶片21及控制器40上方的整個區域，使在同 樣大的引線框架上，低端MOSFET晶片22的尺寸能夠充分 擴展，因而有效提高半導體元件的產品性能。 [0058] 如第17圖所示，低端MOSFET晶片22超出中間聯結件31的 至少一個邊沿延伸到控制器40上方的分區域，由於所述 第一聯結部31不覆蓋控制器40，使控制器40上方與低端 MOSFET晶片22的空隙中，能夠容納上述控制器40與高端 MOSFET晶片21或其他複數個引腳的連接引線51 » 099137604 表單编號 A0101 第 13 頁/共 38 頁 0993434508-0 201220468 [0059] 本實施例中，低端MOSFET晶片22通過複數個連接引線51 鍵合，分別實現頂部閘極222與低端閘極引腳134之間、 頂部源極221與低端源極引腳133之間的電性連接。 [0060] 在一些較佳的實施例中，所述低端MOSFET晶片22的頂部 源極221與低端源極引腳133之間的電性連接，也可以通 過如第1 3圖所述的金屬連接板52、金屬連接帶等金屬連 接體實現，使其能夠在封裝後外露，以改善半導體封裝 的熱性能，同時有效降低該半導體封裝的厚度。 [0061] 综上所述，本發明通過設置厚薄不同的第一載片台u、 第二載片台12，或是通過辱置含不同厚薄聯結部的中間 聯結件30，使低端MOSFET晶片22放置到中間聯結件3〇頂 面後’能夠堆疊在第一載片台11的高端MOSFET晶片21上 ’並通過中間聯結件30連接高端MOSFET晶片21的頂部源 極211與低端MOSFET晶片22的底部汲極，以減少直流-直 流轉換器組裝時元件的數量。同時在第一载片台11的控 制器40上方、與低端MOSFET晶片22之間的空隙中，能夠 容納鍵合連接控制器40與高端MOSFET晶片21或複數個引 腳的複數個連接引線51，以進一步減小整個半導體封裝 的尺寸。 [0062] 本發明由於採用低端MOSFET晶片22通過中間聯結件30堆 疊至高端MOSFET晶片21和控制器40上方的封裝體結構， 與第2圖所示現有技術在引線框架上平鋪設置高、低端 MOSFET晶片22和控制器40的結構相比，本實施例在同樣 大的引線框架上，可以充分擴展各元件的尺寸，如將低 端MOSFET晶片22面積增大至覆蓋整個高端MOSFET晶片 099137604 表單編號A0101 第14頁/共38頁 0993434508-0 201220468 21和控制器40上方，能夠有效提高半導體元件的產品性 [0063] 本發明還通過金屬連接板52、金屬連接帶等金屬連接體 ’來實現低端MOSFET晶片22的頂部源極與低端源極引腳 133之間的電性連接，使該金屬連接板52能夠在直流—直 流轉換器塑封封裝後外露，以改善半導體封裝的熱性能 ’同時有效降低該半導體封裝的厚度。 [0064] Ο 由本發明所述通過設置厚薄不同的載片台，或是設置含 不同厚第一聯結部31的中間聯結件來承載並電性連接複 數個元件的結構，寸以方便地將各種半導體晶片、控制 器、電感或電料元件堆疊’使其能朗裝在同一個半 導體封裝中，以擴展本發明形成4種其他半導體元件。 [0065] 以上所述僅為舉例性’而㈣限難者。任何未脫離本 發明之精神與範4 ’而對其進行之等效修改或變更，均 應包含於後附之申請專利範圍中。 ❹ [0066] 【圖式簡單說明】 " 、 第1圖是直流-直流轉換器的電路原理框圖. 第2圖是現有直流-錢轉換㈣封裝結和音圖· 第3圖是本發明用於直流—直流轉換器的封裝龍構在實 施例1中的總體結構示意圖； Λ 第4圖〜第15圖是本發明用於直流— 直他轉換器的封裝體結 構在實施例1中的分層結構示意圖； 其中，第4圖、第7圖、第1〇圖、第 圖是實施例1中封裝 體結構的俯視圖； 099137604 第5圖 表單編號A0101 圖 0993434508-0 201220468 、第10圖、第13圖中A-A’方向的刳面圖； 第6圖、第9圖、第12圖、第15圖分別是沿第4圖、第7圖 、第10圖、第13圖中B-B’方向的剖面圖； 第16圖是本發明用於直流-直流轉換器的封裝體結構在實 施例2中的結構俯視圖； 第17圖是沿第16圖中A-A’方向的剖面圖； 第18圖是沿第16圖中B-B’方向的剖面圖。 【主要元件符號說明】 [0067] 11 :第一載片台 12 :第二載片台 21 :高端MOSFET晶片 211 :高端MOSFET晶片的頂部源極 21 2 :高端MOSFET晶片的頂部閘極 22 :低端MOSFET晶片 221 :低端MOSFET晶片的頂部源極 222 :低端MOSFET晶片的頂部閘極 131 :高端源極引腳._ 132 :高端閘極引腳 133 :低端源極引腳 134 :低端閘極引腳 1 3 5 .控制引腳 30 :中間聯結件 31 :第一聯結部 32 :第二聯結部 4 0 :控制器 51 :連接引線 099137604 表單編號A0101 第16頁/共38頁 0993434508-0 201220468 52 :金屬連接板 HS :高端M0SFET LS :低端M0SFET G1、G 2 :間極 Dl、D2 :汲極 SI、S2 :源極 Vin :電壓源 Gnd :接地端 〇 099137604 表單編號A0101 第17頁/共38頁 0993434508-0[0048] The bottom of the intermediate junction member 30 covers only the portion of the top of the high-side MOSFET wafer 21 and is electrically connected to the top source 211 of the surface-side MOSFET wafer 21 (Fig. 8). See Figure 3 for a top view, see Figure 1 for a top view; Figure 11 is a cross-sectional view of Figure 10 in the A-A' direction, and Figure 12 is a 10th view at B- A cross-sectional view of B' direction. The upper-side low-side MOSFET wafer 22 is attached to the top surface of the intermediate bonding member 30, and is electrically connected to the bottom thereof, thereby forming the source and the low side of the high-side MOSFET wafer 21 shown in FIG. The electrical connection of the drain of the terminal MOSFET 22 is performed. The low-side MOSFET wafer 22 is placed on the intermediate junction 3 and overlies the upper MOSFET chip 21 and the upper portion of the controller 40: the bis. bee (Fig. 1), and the low-side MOSFET wafer 22 extends beyond the intermediate junction At least one edge of the 3 延伸 extends to a sub-area above the controller 40, since the intermediate link 3 〇 does not cover the top of the controller 40 and does not have any connection thereto (Fig. 8), so that it is above the controller 40 and low In the gap between the terminal MOSFETs and the wafers 22, a plurality of connection leads 51 (11@) of the above-described key connection controller 40 and the high-side M〇SFET chip 21 or the control pin 135 can be accommodated. The low-voltage MOSFET wafer 22 is respectively bonded by a plurality of connection leads 51 to electrically connect the top gate 222' with the lower-end gate pin 134 of the lead frame. Referring to FIG. 4, FIG. 7 and FIG. 1 , the low-end MOSFET wafer 22 and the controller 4 are electrically connected to the low-end interpole pins 134 respectively. The gate of the low side MOSFET wafer 22 is connected to the controller 4A. 099137604 Form No. A0101 Page 11 of 38 0993434508-0 201220468 _] See Figure 3, and see the top view shown in Figure _; Figure 19 shows Figure 13 in A-A' In the cross-sectional view, Fig. 15 is a cross-sectional view taken along line BB' of Fig. 13. _] i is electrically connected between the top source 221 and the source pin 133 of the low-side MOSFET wafer 22 by a metal connecting plate 52 (or a metal connecting body such as a metal connecting strip). 13)), after the package_structure of the entire package is encapsulated, not only the bottom of the package sealing structure is exposed to the Vin end, but also the top surface of the metal connecting plate 52 is exposed to the Gnd end. To improve the thermal performance of the |conductor package while effectively reducing the thickness of the semiconductor package b [0051] Example 2 _2] See the top view (Fig. 16), A_A, the cross-sectional view (Fig. 2) and B- As shown in the cross-sectional view of the B' direction (Fig. 18), the package structure for the DC-DC converter of this embodiment has a stack structure similar to that of the embodiment, and the first slide on the top of the lead frame On the first part and the second part of the stage n, the high-end M〇SFET chip 2 and the controller 40 are attached and attached, respectively. In the present embodiment, the first portion and the second portion of the first stage stage are separated from each other. Of course, a first stage in which the first portion and the second portion are connected to each other can also be selected. [0053] The south end MOSFET chip 21 is bonded by a plurality of connection leads 51, and is electrically formed between the top gate 212 and the second gate pin 132, and between the top source 211 and the high side source pin 131, respectively. Sexual connection. The controller 4 is bonded through a plurality of connection leads 51, respectively, to the first stage n, the plurality of control pins 135, the low side gate pins 134, and the high end m〇SFET chip 21 099137604 Form No. A0101 No. 12 The top gate 21 2 of page 20 of 0993434508-0 201220468 forms an electrical connection. [0054] A conductive intermediate connecting member 3 is disposed on the top of the second stage 12 and the high-side MOSFET wafer 21 of the lead frame, and a low-end MOSFET wafer 22 is disposed on the intermediate connecting member 3A through the intermediate connecting member 3〇. The top source 211 of the high side MOSFET wafer 21 and the bottom drain of the low side mosfeT wafer 22 are electrically connected. The difference from the first embodiment is that the thickness of the first stage 11 and the second stage 12 on the lead frame in the embodiment are the same. The intermediate coupling member 30 includes a first coupling portion 31 and a second coupling portion 32 ′ that are integrally disposed to adhere the first coupling portion 31 to the top of the high-end MOSFET wafer 21 of the first stage 11 The thickness after the surface is adhered to the thickness of the second joint portion 32 after being attached to the top surface of the second stage 12 . Specifically, the first connection portion 31 realizes electric connection and connection between the top source 211 of the high side MOSFET wafer 21 and the bottom drain of the low side MOSFET wafer 22. [0057] In comparison with the first and sixth figures, in the present embodiment, the low-side S 0 SFET transistor fixed in the intermediate junction 30 is increased in area to cover or exceed the high-side MOSFET. The entire area above the wafer 21 and the controller 40 enables the size of the low-side MOSFET wafer 22 to be sufficiently expanded on the same large lead frame, thereby effectively improving the product performance of the semiconductor element. [0058] As shown in FIG. 17, the low-end MOSFET wafer 22 extends beyond the at least one edge of the intermediate link 31 to a sub-region above the controller 40, since the first junction 31 does not cover the controller 40, enabling control In the gap between the upper part of the device 40 and the low-end MOSFET chip 22, the connection lead of the controller 40 and the high-side MOSFET chip 21 or other plurality of pins can be accommodated. 51 » 099137604 Form No. A0101 Page 13 of 38 0993434508-0 [0059] In this embodiment, the low-side MOSFET chip 22 is bonded through a plurality of connection leads 51, respectively, between the top gate 222 and the low-side gate pin 134, the top source 221 and the low-end source. Electrical connection between the feet 133. [0060] In some preferred embodiments, the electrical connection between the top source 221 and the low-side source pin 133 of the low-side MOSFET wafer 22 can also be as described in FIG. A metal connector such as a metal connecting plate 52 or a metal connecting tape is realized to be exposed after packaging to improve the thermal performance of the semiconductor package while effectively reducing the thickness of the semiconductor package. [0061] In summary, the present invention enables the low-end MOSFET chip by setting the first stage u, the second stage 12 having different thicknesses, or by insulting the intermediate coupling 30 having different thick and thin joints. 22 is placed on the top side of the intermediate junction 3 and can be stacked on the high side MOSFET wafer 21 of the first stage 11 and connected to the top source 211 and the low side MOSFET wafer 22 of the high side MOSFET wafer 21 via the intermediate junction 30. The bottom of the bungee is to reduce the number of components when the DC-DC converter is assembled. At the same time, in the gap between the controller 40 of the first stage 11 and the low-end MOSFET wafer 22, a plurality of connection leads 51 capable of accommodating the bond connection controller 40 and the high-side MOSFET chip 21 or a plurality of pins 51 can be accommodated. To further reduce the size of the entire semiconductor package. [0062] The present invention uses a low-end MOSFET wafer 22 to be stacked on the high-side MOSFET wafer 21 and the package structure over the controller 40 through the intermediate junction 30, and the prior art shown in FIG. 2 is tiled on the lead frame. Compared with the structure of the low-side MOSFET wafer 22 and the controller 40, the present embodiment can sufficiently expand the size of each component on the same large lead frame, such as increasing the area of the low-side MOSFET wafer 22 to cover the entire high-side MOSFET wafer 099137604. Form No. A0101, page 14 / 38 pages 0993434508-0 201220468 21 and above the controller 40, can effectively improve the product properties of the semiconductor component [0063] The present invention also passes through the metal connector 52, metal connecting tape and the like The electrical connection between the top source and the low-side source pin 133 of the low-side MOSFET chip 22 is realized, so that the metal connecting plate 52 can be exposed after the DC-DC converter is packaged to improve the thermal performance of the semiconductor package. 'At the same time effectively reducing the thickness of the semiconductor package. [0064] Ο According to the present invention, by providing a different thickness of the stage, or by providing an intermediate coupling member having different thick first coupling portions 31 to carry and electrically connect a plurality of components, in order to conveniently The semiconductor wafer, controller, inductor or electrode component stack can be mounted in the same semiconductor package to extend the invention to form four other semiconductor components. [0065] The above description is only exemplary and (4) limited. Any equivalent modifications or alterations to the invention may be made without departing from the spirit and scope of the invention. ❹ [0066] [Simple diagram of the diagram] ", Figure 1 is a circuit block diagram of the DC-DC converter. Figure 2 is the existing DC-money conversion (four) package junction and sound map · Figure 3 is used in the present invention The overall structure of the package of the DC-DC converter in the first embodiment; Λ 4th to 15th is the package structure of the present invention for the DC-direct converter in the embodiment 1 FIG. 4, FIG. 7, FIG. 1 and FIG. 1 are top views of the package structure in Embodiment 1; 099137604 FIG. 5 Form No. A0101 FIG. 0993434508-0 201220468, FIG. 10, Figure 13 is a side view of the A-A' direction; Figure 6, Figure 9, Figure 12, and Figure 15 are the B-B along the 4th, 7th, 10th, and 13th, respectively. FIG. 16 is a plan view showing a structure of a package structure for a DC-DC converter of the present invention in Embodiment 2; FIG. 17 is a cross-sectional view taken along line A-A' of FIG. 16; Figure 18 is a cross-sectional view taken along line BB' of Figure 16. [Main Component Symbol Description] [0067] 11: First Stage 12: Second Stage 21: High Side MOSFET Chip 211: Top Source of High Side MOSFET Wafer 21 2: Top Gate 22 of High Side MOSFET Wafer: Low Side MOSFET Chip 221: Top Source 222 of Low Side MOSFET Wafer: Top Gate 131 of Low Side MOSFET Chip: High Side Source Pin._132: High Side Gate Pin 133: Low Side Source Pin 134: Low Terminal gate pin 1 3 5 . Control pin 30 : Intermediate link 31 : First link 32 : Second link 4 0 : Controller 51 : Connecting lead 099137604 Form number A0101 Page 16 / 38 page 0993434508 -0 201220468 52 : Metal connection plate HS : High-end M0SFET LS : Low-side M0SFET G1 , G 2 : Dipole D1 , D2 : Deuterium SI, S2 : Source Vin : Voltage source Gnd : Ground 〇 099137604 Form No. A0101 17 pages/total 38 pages 0993434508-0

Claims (1)

201220468 七、申請專利範圍： 1 . 一種用於直流-直流轉換器的封裝體結構，包含： 分別具有一底部没極、一頂部閘極和一頂部源極的一高端 M0SFET晶片和一低端M0SFET晶片； 一引線框架，其設置有一第一載片台和一第二載片台； 該高端M0SFET晶片設置在該第一載片台上，使其底部及 極與該第一載片台形成電性連接； 一控制器，亦設置在該第一載片台上，其與該高端 M0SFET晶片的頂部閘極電性連接； 導電的一中間聯結件，其設置在該第二載片台及該高端 M0SFET晶片上，並與該高端M0SFET晶片的頂部源極電性 連接； 該低端MOSFET晶片設置在該中間聯結件上'，其頂部閘極 與該控制器電性連接；其底部汲極與該中間聯結件的頂面 電性連接，即與該高端M0SFET晶片的頂部源極電性連接 ;以及 該中間聯結件不覆蓋該控制器，使在該％制器上方、與該 低端M0SFET晶片之間存在空隙。 2 ·如申請專利範圍第1項所述之用於直流-直流轉換器的封裝 體結構’其中該第二載片台的厚度大於該第一載片台的厚 度。 3 .如申請專利範圍第2項所述之用於直流-直流轉換器的封裝 體結構，其中該第二載片台的厚度與該第一載片台上堆疊 了該高端M0SFET晶片後的厚度一致。 4 .如申請專利範圍第1項所述之用於直流-直流轉換器的封裝 099137604 表單編號A0101 第18頁/共38頁 0993434508-0 201220468 體結構，其中該導電的中間聯結件包含一體設置的一第-聯結部，以及厚於該第一聯結部的一第二聯結部； 該第二聯結部設置在該第二載片台上；以及 該第一聯結部設置在該第一載片台的該高端M0SFET晶片 上’使在該高端M0SFET晶片的頂部源極通過該第一聯結 部’與該低端M0SFET晶片的底部汲極之間形成電性連接 〇 如申請專利範圍第4項所述之用於直流-直流轉換器的封裝 體結構，其中該第一聯結部設置在該第一載片台的該高端 M0SFET晶片頂面之藤皭厚度，與該第二磁結部設置在該 "；； .； ... ... 第二載片台頂面之後的厚度一致 如申請專利範圍第3或5項所述之用於直流-直流轉換器的 封裝體結構’其中該引線框架上還設置有與該第一載片台 、該第二載片台分隔且無電性連接的複數個引腳，包含複 數個低端源極引腳、低端閘極引腳、高&源極引腳、高端 閘極引腳以及控制引腳。 如申請專利範圍第6項所述之用於直流-直流轉換器的封裝 體結構’其中該高端M0SFET晶片通過複數個連接引線鍵 合’分別在其頂部閘極與高端閘極引腳之間、頂部源極與 高端源極引腳之間分別形成電性連接。 如申請專利範圍第6項所述之用於直流-直流轉換器的封裝 體結構，其中該控制器通過複數個連接引線鍵合，分別與 該第一載片台、該複數個控制引腳、低端閘極引腳，以及 該高端M0SFET晶片的頂部閘極形成電性連接。 如申請專利範圍第8項所述之用於直流-直流轉換器的封裝 體結構，其中該低端M0SFET晶片通過該複數個連接弓卜線 099137604 表單編號A0101 0993434508-0 第19頁/共38頁 201220468 鍵合，使該低端M0SFET晶片的頂部閘極與該低端閉極引 腳之間形成電性連接，即與該控制器之間也形成電性連接 〇 10 .如申請專利範圍第8項所述之用於直流-直流轉換器的封裝 體結構’其中該低端M0SFET晶片，覆蓋該中間聯結件和 控制器頂部的部分或全部區域。 11 .如申請專利範圍第1 0項所述之用於直流-直流轉換器的封 裝體結構，其中該控制器上方、與該低端M0SFET晶片之 間的空隙中，容納鍵合連接該控制器與該高端M〇SFET晶 片或該控制引腳的該複數個連接引線。 12 .如申請專利範圍第6項所述之用於直流-直流轉換器的封裝 體結構，其中該低端M0SFET晶片通過複數個連接引線鍵 合’使該低端M0SFET晶片的頂部源極與該低端源極引腳 之間形成電性連接。 13 ·如申請專利範圍第6項所述之用於直流-直流轉換器的封裝 體結構，其中還包含複數個全屬:連接板電性連接該低端 M0SFET晶片的頂部源極與愈低_源極弓「腳，使該金屬連 接板得以暴露在該封裝體嫌構的表面之外。 099137604 表單編號A0101 第20頁/共38頁 0993434508-0201220468 VII. Patent Application Range: 1. A package structure for a DC-DC converter, comprising: a high-end MOSFET chip and a low-side MOSFET having a bottom, a top, and a top source, respectively; a lead frame, which is provided with a first stage and a second stage; the high-end MOSFET is disposed on the first stage, such that the bottom and the pole form a battery with the first stage a controller is also disposed on the first stage, electrically connected to a top gate of the high-end MOSFET chip; a conductive intermediate connection member disposed on the second stage and the On the high-end MOSFET chip, and electrically connected to the top source of the high-side MOSFET chip; the low-side MOSFET chip is disposed on the intermediate junction member, and the top gate is electrically connected to the controller; the bottom bungee is The top surface of the intermediate connecting member is electrically connected, that is, electrically connected to the top source of the high-side MOSFET chip; and the intermediate connecting member does not cover the controller, and the low-side MOSFET chip is over the % device Between the presence of voids. 2. The package structure for a DC-DC converter according to claim 1, wherein the thickness of the second stage is greater than the thickness of the first stage. 3. The package structure for a DC-DC converter according to claim 2, wherein a thickness of the second stage and a thickness of the high-end MOSFET wafer are stacked on the first stage Consistent. 4. The package for a DC-DC converter according to claim 1 of the scope of claim 1 099137604 Form No. A0101, page 18 / 38 pages 0993434508-0 201220468 body structure, wherein the conductive intermediate link comprises an integrated arrangement a first coupling portion, and a second coupling portion thicker than the first coupling portion; the second coupling portion is disposed on the second stage; and the first coupling portion is disposed on the first carrier Forming an electrical connection between the top source of the high-side MOSFET wafer through the first junction portion and the bottom drain of the low-side MOSFET wafer, as described in claim 4 a package structure for a DC-DC converter, wherein the first junction portion is disposed on a top surface of the high-end MOSFET wafer of the first stage, and the second magnetic junction portion is disposed in the ";;;;; ... The thickness of the top surface of the second stage is the same as that of the package structure for the DC-DC converter according to claim 3 or 5, wherein the lead frame Also set up with the first a plurality of pins separated from the second stage and electrically connected, including a plurality of low-end source pins, low-side gate pins, high & source pins, and high-side gate leads Foot and control pin. A package structure for a DC-DC converter as described in claim 6 wherein the high-side MOSFET chip is bonded between a top gate and a high-side gate pin through a plurality of connection wires, An electrical connection is formed between the top source and the high side source pin, respectively. The package structure for a DC-DC converter according to claim 6, wherein the controller is bonded to the first carrier, the plurality of control pins, and the plurality of control pins, respectively. The low side gate pin and the top gate of the high side MOSFET chip form an electrical connection. The package structure for a DC-DC converter according to claim 8, wherein the low-end MOSFET chip passes the plurality of connection bow lines 099137604 Form No. A0101 0993434508-0 Page 19 of 38 201220468 bonding, so that the top gate of the low-end MOSFET chip and the low-end closed-pole pin are electrically connected, that is, an electrical connection 〇10 is also formed between the controller and the controller. The package structure for a DC-DC converter described in the section wherein the low-side MOSFET wafer covers a portion or all of the intermediate junction and the top of the controller. 11. The package structure for a DC-DC converter according to claim 10, wherein a gap between the controller and the low-end MOSFET chip accommodates the controller The plurality of connection leads with the high side M〇SFET chip or the control pin. 12. The package structure for a DC-DC converter according to claim 6, wherein the low-side MOSFET chip is bonded to a top source of the low-side MOSFET chip by a plurality of connection wires An electrical connection is made between the low side source pins. 13 . The package structure for a DC-DC converter according to claim 6 , further comprising a plurality of full genus: the connection plate is electrically connected to the top source of the low-side MOSFET chip and the lower _ The source bow "foot" exposes the metal connector to the surface of the package. 099137604 Form No. A0101 Page 20 of 38 0993434508-0
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